Multiple operation circuit, multiplication / accumulation operation device, and memory-in processing device

Abstract

The present application relates to a multiple operation circuit, a multiplication / accumulation operation device having the multiple operation circuit, and an in-memory processing device having the multiple operation circuit. The multiple operation circuit includes a multiplier, an adder, a latch circuit, and a plurality of selectors. The multiplier performs a multiplication calculation on first input data and second input data to generate and output multiplication result data. The adder performs an addition calculation on third input data and fourth input data to generate and output addition result data. The latch circuit latches fifth input data input to an input terminal of the latch circuit to generate and output feedback data. The plurality of selectors change a transfer path of the first result data, the first input data, the second input data, the multiplication result data, and the addition result data according to a first operation mode, a second operation mode, or a third operation mode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0052016, filed on April 21, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of this application relate to multiple operational circuits, a multiplication / accumulation (MAC) arithmetic unit having multiple operational circuits, and an in-memory processing (PIM) device having multiple operational circuits. Background Technology

[0004] Recently, interest in artificial intelligence (AI) has been increasing not only in the information technology industry but also in the financial and healthcare sectors. Accordingly, AI, or more precisely, the introduction of deep learning, has been considered and prototyped in various fields. Generally, the technique of learning deep neural networks (DNNs) or deep networks with added layers more efficiently than ordinary neural networks to utilize them in pattern recognition or reasoning is often referred to as deep learning.

[0005] One reason for this widespread attention may be the improved performance of processors performing arithmetic operations. To improve the performance of artificial intelligence (AI), it may be necessary to increase the number of layers in the neural networks that constitute the AI. This trend has continued in recent years, leading to an exponential increase in the computational demands of the hardware actually performing the calculations. Furthermore, if AI employs a general-purpose hardware system that includes separate memory and processors, its performance may degrade due to limitations in the amount of data communication between memory and processor. To address this issue, PIM devices, which integrate the processor and memory into a single semiconductor chip, have been used as neural network computing devices. Because PIM devices perform arithmetic operations directly within the PIM device, the data processing speed in neural networks can be improved. Summary of the Invention

[0006] According to one embodiment, a multiple operation circuit can include a multiplier, an adder, a latch circuit, and a plurality of selectors. The multiplier is configured to perform a multiplication calculation on first input data and second input data to generate and output multiplication result data. The adder is configured to perform an addition calculation on third input data and fourth input data to generate and output addition result data. The latch circuit is configured to latch fifth input data input to an input terminal of the latch circuit to generate and output feedback data. The plurality of selectors is configured to change a transmission path of first result data, the first input data, the second input data, the multiplication result data, and the addition result data according to a first operation mode, a second operation mode, or a third operation mode.

[0007] According to another embodiment, a multiply and accumulate (MAC) operator includes a plurality of multiple operation circuits. A plurality of sets of first input data is transmitted to the plurality of multiple operation circuits, respectively. A plurality of sets of second input data is transmitted to the plurality of multiple operation circuits, respectively. A plurality of sets of operation result data is output from the plurality of multiple operation circuits, respectively. Each of the plurality of multiple operation circuits is configured to perform an arithmetic operation in a first operation mode, a second operation mode, or a third operation mode according to first to third selection signals.

[0008] According to yet another embodiment, an in-memory processing (PIM) device can include a plurality of banks configured to provide a plurality of sets of weight data, a global buffer configured to provide a plurality of sets of vector data, and a plurality of multiply / accumulate (MAC) operators configured to perform MAC operations on the plurality of sets of weight data and the plurality of sets of vector data. Each of the plurality of MAC operators includes a plurality of multiple operation circuits. Each of the plurality of multiple operation circuits is configured to perform an arithmetic operation in a first operation mode, a second operation mode, or a third operation mode according to first to third selection signals.

[0009] According to yet another embodiment, an in-memory processing (PIM) device can include a plurality of banks configured to provide a plurality of sets of weight data, a global buffer configured to provide a plurality of sets of vector data, and a plurality of multiple operation circuits configured to perform MAC operations on the plurality of sets of weight data and the plurality of sets of vector data. Each of the plurality of multiple operation circuits is configured to perform an arithmetic operation in a first operation mode, a second operation mode, or a third operation mode according to first to third selection signals. BRIEF DESCRIPTION OF DRAWINGS

[0010] Certain features of the disclosed technology are illustrated by various embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1Fig. 1 illustrates a configuration of a multiple operation circuit according to an embodiment of the present disclosure;

[0012] Figure 2 Fig. 1 illustrates a configuration of a multiple operation circuit according to an embodiment of the present disclosure; Figure 1 Fig. 2 illustrates an example of a configuration of a multiplier included in the multiple operation circuit illustrated in Fig. 1;

[0013] Figure 3 Fig. 3 illustrates an example of a configuration of an adder included in the multiple operation circuit illustrated in Fig. 1; Figure 1

[0014] Figure 4 Fig. 4 illustrates an example of a matrix-vector multiplication calculation performed by a multiply-accumulate (MAC) operation in a first operation mode of the multiple operation circuit illustrated in Fig. 1; Figure 1

[0015] Figure 5 Fig. 5 illustrates an example of a process of the matrix-vector multiplication calculation illustrated in Fig. 4; Figure 4

[0016] Figure 6 Fig. 6 illustrates a first MAC operation of the process of the matrix-vector multiplication calculation illustrated in Fig. 5; Figure 5

[0017] Figure 7 Fig. 7 illustrates a second MAC operation of the process of the matrix-vector multiplication calculation illustrated in Fig. 5; Figure 5

[0018] Figure 8 Fig. 8 illustrates an example of a matrix-scalar multiplication calculation performed by an element-wise (EW) multiplication calculation in a second operation mode of the multiple operation circuit illustrated in Fig. 1; Figure 1

[0019] Figure 9 Fig. 9 illustrates an example of the EW multiplication calculation illustrated in Fig. 8; Figure 8

[0020] Figure 10 Fig. 10 illustrates an example of a matrix addition calculation performed by an element-wise (EW) addition calculation in the second operation mode of the multiple operation circuit illustrated in Fig. 1; Figure 1

[0021] Figure 11 Fig. 11 illustrates an example of the EW addition calculation illustrated in Fig. 10; Figure 10

[0022] Figure 12 Fig. 12 illustrates an accumulation calculation performed in a third operation mode of the multiple operation circuit illustrated in Fig. 1; Figure 1

[0023] Figure 13 Fig. 13 illustrates a configuration of a multiple operation circuit according to another embodiment of the present disclosure; ​​​​​​​​​​

[0024] Figure 14 An example of a multiplier included in the multiply operation circuit is illustrated. Figure 13 An example of a multiplier included in the multiply operation circuit is illustrated.

[0025] Figure 15 An example of a multiplier included in the multiply operation circuit is illustrated. Figure 13 An example of a multiplier included in the multiply operation circuit is illustrated.

[0026] Figure 16 A MAC operation performed in a first MAC operation mode of the MAC operation circuit is illustrated. A MAC operation performed in a first MAC operation mode of the MAC operation circuit is illustrated.

[0027] A MAC operation performed in a first MAC operation mode of the MAC operation circuit is illustrated. Figure 17 A MAC operation performed in a second MAC operation mode of the MAC operation circuit is illustrated. Figure 16 A MAC operation performed in a second MAC operation mode of the MAC operation circuit is illustrated. A MAC operation performed in a second MAC operation mode of the MAC operation circuit is illustrated.

[0028] A MAC operation performed in a second MAC operation mode of the MAC operation circuit is illustrated. Figure 18 A MAC operation performed in a second MAC operation mode of the MAC operation circuit is illustrated. Figure 16 A MAC operation performed in a second MAC operation mode of the MAC operation circuit is illustrated. A MAC operation performed in a second MAC operation mode of the MAC operation circuit is illustrated.

[0029] A MAC operation performed in a second MAC operation mode of the MAC operation circuit is illustrated. Figure 19 A PIM device according to another embodiment of the disclosure is illustrated. A PIM device according to another embodiment of the disclosure is illustrated.

[0030] An example of a MAC operation performed by the PIM device is illustrated. Figure 20 An example of a MAC operation performed by the PIM device is illustrated. Figure 19 An example of a MAC operation performed by the PIM device is illustrated. An example of a MAC operation performed by the PIM device is illustrated.

[0031] An example of a MAC operation performed by the PIM device is illustrated. Figure 21 A PIM device according to another embodiment of the disclosure is illustrated. A PIM device according to another embodiment of the disclosure is illustrated.

[0032] A PIM device according to another embodiment of the disclosure is illustrated. Figure 22 An example of a MAC operation performed by the PIM device is illustrated. Figure 21 An example of a MAC operation performed by the PIM device is illustrated. DETAILED DESCRIPTION

[0033] In the following description of embodiments, it will be understood that the terms "first" and "second" are intended to identify elements rather than to define a particular number or sequence of elements. In addition, when one element is referred to as being "on", "above", "over", "under", or "below" another element, it is intended to mean that such element is directly in contact with the other element, or that there is an intervening element between such elements. As used herein, terms such as "on", "above", "over", "under", or "below" are used to describe a relative position relationship and are not intended to limit the scope of the disclosure. Furthermore, when one element is referred to as being "connected" or "coupled" to another element, the element can be directly electrically or mechanically connected or coupled to the other element, or can be indirectly electrically or mechanically connected or coupled to the other element with one or more additional elements between the two elements. In addition, when a parameter is referred to as being "predetermined", it can be intended to mean that the value of the parameter is determined in advance when the parameter is used in a process or algorithm. The value of the parameter can be set at the beginning of the process or algorithm, or can be set during the period of executing the process or algorithm. A logic "high" level and a logic "low" level can be used to describe the logic level of an electrical signal. A signal with a logic "high" level can be distinguished from a signal with a logic "low" level. For example, when a signal with a first voltage corresponds to a signal with a logic "high" level, a signal with a second voltage can correspond to a signal with a logic "low" level. In one embodiment, the logic "high" level can be set to a voltage level higher than the voltage level of the logic "low" level. In addition, the logic level of a signal can be set differently or oppositely according to the embodiment. For example, a certain signal with a logic "high" level in one embodiment can be set to have a logic "low" level in another embodiment.

[0034] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0035] Various embodiments relate to a multiple operation circuit, a MAC operator including the multiple operation circuit, and a PIM device including the multiple operation circuit.

[0036] Figure 1 A configuration of a multiple operation circuit 100 according to an embodiment of the present disclosure is illustrated. Referring to FIG. 1, the multiple operation circuit 100 includes a first input terminal 110, a second input terminal 120, a first output terminal 130, a second output terminal 140, a first operation circuit 150, a second operation circuit 160, and a control circuit 170. Figure 1The multiple operation circuit 100 can receive first input data A[15:0] and second input data B[15:0]. Hereinafter, it can be assumed that the first input data A[15:0] corresponds to a 16-bit binary stream, and the second input data B[15:0] also corresponds to a 16-bit binary stream. However, the embodiment in which the first input data A[15:0] is a 16-bit binary stream and the second input data B[15:0] is a 16-bit binary stream is only one example of the present disclosure. Therefore, in some other embodiments, the number of bits included in the first input data or the second input data can be less than or greater than sixteen. In one embodiment, the first input data A[15:0] can be transferred to the multiple operation circuit 100 from a first memory bank, and the second input data B[15:0] can be transferred to the multiple operation circuit 100 from a second memory bank. Alternatively, the first input data A[15:0] can be transferred to the multiple operation circuit 100 from a memory bank, and the second input data B[15:0] can be transferred to the multiple operation circuit 100 from a buffer memory. The multiple operation circuit 100 can receive first result data IY-1 from another multiple operation circuit (not shown). The multiple operation circuit 100 can receive first to third selection signals SS1 to SS3 and an update signal UPDATE as control signals. The multiple operation circuit 100 can output second result data IY[15:0] and operation result data Y[15:0]. As used herein, the tilde "~" indicates a range of components. For example, "SS1 to SS3" indicates Figure 1 the first to third selection signals SS1, SS2, and SS3 shown in FIG. 1.

[0037] The multiple operation circuit 100 can perform various arithmetic operations in multiple operation modes. The multiple operation modes can include a first operation mode to perform a MAC operation, a second operation mode to perform an element-wise (EW) operation, and a third operation mode to perform an accumulation calculation (also referred to as a "cumulative addition calculation"). The EW operation performed in the second operation mode can include an EW multiplication calculation and an EW addition calculation. In one embodiment, the MAC operation can be performed by a matrix-vector multiplication calculation of first matrix data and second matrix data. The EW multiplication calculation can be performed by multiplying the first matrix data by a matrix scalar having a constant value. The EW addition calculation can be performed by an element-to-element addition calculation of the first matrix data and the second matrix data. In addition, the accumulation calculation can be performed by an addition calculation of the first result data IY-1 and the second result data IY[15:0]. In one embodiment, the first selector, the second selector, the third selector, and the fourth selector 121 to 124 can change a signal transfer path of the first result data IY-1, the first input data and the second input data A[15:0] and B[15:0], the multiplication result data AB[15:0], the addition result data DA11[15:0], and the MAC data MAC[15:0] based on the first selection signal SS1 to the third selection signal SS3 according to the first operation mode, the second operation mode, or the third operation mode. For example, the signal transfer path of the first result data IY-1 or the multiplication result data AB[15:0] can be changed or determined according to which signal is output from the output end OUT1 of the first selector 121 based on the first selection signal SS1.

[0038] When the multiple operation circuit 100 performs the MAC operation in the first operation mode, the first matrix data (i.e., the first input data A[15:0]) and the second matrix data (i.e., the second input data B[15:0]) can be input to the multiple operation circuit 100. When the MAC operation is performed on an "M x N" first matrix and an "N x 1" second matrix, the first input data A[15:0] can correspond to an element of the first matrix, and the second input data B[15:0] corresponds to an element of the second matrix. The first input data A[15:0] can have a floating point format composed of a sign part, an exponent part, and a mantissa part, and the second input data B[15:0] can also have a floating point format composed of a sign part, an exponent part, and a mantissa part. However, the embodiment in which the first input data A[15:0] and the second input data B[15:0] have a floating point format can be only an example of the present disclosure. Therefore, in some other embodiments, the first input data A[15:0] and the second input data B[15:0] can have a fixed point format composed of an integer part including sign data and a decimal part.

[0039] When the multiple operation circuit 100 performs the EW multiplication calculation in the second operation mode, matrix data corresponding to the first input data A[15:0] and a constant value corresponding to the second input data B[15:0] can be input to the multiple operation circuit 100. When the EW multiplication calculation is performed using an "M x N" first matrix and a constant value as input data, the first input data A[15:0] can correspond to elements of the first matrix, and the second input data B[15:0] can correspond to the constant value. When the multiple operation circuit 100 performs the EW addition calculation, first matrix data corresponding to the first input data A[15:0] and second matrix data corresponding to the second input data B[15:0] can be input to the multiple operation circuit 100. When the EW addition calculation is performed using an "M x N" first matrix and an "M x N" second matrix as input data, the first input data A[15:0] can correspond to elements of the "M x N" first matrix, and the second input data B[15:0] can correspond to elements of the "M x N" second matrix. In this case, an element "a" in the "M x N" first matrix can be added to an element "b" located in the same position as the element "a" in the "M x N" second matrix.

[0040] When the multiple operation circuit 100 performs the accumulation calculation in the third operation mode, the multiple operation circuit 100 can receive the first result data IY-1. In one embodiment, the first result data IY-1 can be the first multiplication result data transferred from another multiple operation circuit (not shown) to the multiple operation circuit 100. The multiple operation circuit 100 can perform the accumulation calculation on the first multiplication result data and the second multiplication result data stored in the multiple operation circuit 100 through a previous operation, thereby generating and outputting the second result data IY[15:0]. The second result data IY[15:0] output from the multiple operation circuit 100 can be transferred to another multiple operation circuit (not shown) and can be used as the first result data IY-1 of the other multiple operation circuit.

[0041] The multiple operation circuit 100 can include a multiplier 110, first to fourth selectors 121 to 124, an adder 130, and a latch circuit 140.

[0042] The multiplier 110 can have a first input, a second input, and an output. A first input data A[15:0] corresponding to the first matrix data and a second input data B[15:0] corresponding to the second matrix data can be input to the first and second inputs of the multiplier 110. The multiplier 110 can perform a multiplication calculation on the first input data A[15:0] and the second input data B[15:0] to generate a multiplication result data AB[15:0]. The multiplier 110 can output the multiplication result data AB[15:0] through its output. The first input of the multiplier 110 can be coupled to the first input IN21 of the second selector 122. Thus, the first input data A[15:0] transmitted to the first input of the multiplier 110 can also be transmitted to the first input IN21 of the second selector 122. The second input of the multiplier 110 can be coupled to the first input IN31 of the third selector 123. Thus, the second input data B[15:0] transmitted to the second input of the multiplier 110 can also be transmitted to the first input IN31 of the third selector 123. The output of the multiplier 110 can be coupled to the second input IN12 of the first selector 121. Thus, the multiplication result data AB[15:0] output from the multiplier 110 through the output of the multiplier 110 can be transmitted to the second input IN12 of the first selector 121.

[0043] The first selector 121 can have a first input IN11, a second input IN12, a selection terminal S1, and an output OUT1. The first selector 121 can receive the first result data IY-1 through the first input IN11. Since the second input IN12 of the first selector 121 is coupled to the output of the multiplier 110, the first selector 121 can receive the multiplication result data AB[15:0] from the multiplier 110 through the second input IN12. The first selector 121 can also receive the first selection signal SS1 through its selection terminal S1. The output OUT1 of the first selector 121 can be coupled to both the second input IN22 of the second selector 122 and the first input IN41 of the fourth selector 124. The first selector 121 can output the first result data IY-1 input through the first input IN11 through the output OUT1 in response to the first selection signal SS1 having a first logic level. The first selector 121 can output the multiplication result data AB[15:0] input through the second input IN12 through the output OUT1 in response to the first selection signal SS1 having a second logic level. Hereinafter, it can be assumed that the first logic level is a logic "low" level and the second logic level is a logic "high" level. In one embodiment, the first selector 121 can be implemented with a 2-to-l multiplexer having two inputs and one output.

[0044] The second selector 122 can have a first input end IN21, a second input end IN22, a selection end S2, and an output end OUT2. Since the first input end IN21 of the second selector 122 is coupled to the first input end of the multiplier 110, the first input data A[15:0] can also be transmitted to the first input end IN21 of the second selector 122. The second selection signal SS2 can be input to the selection end S2 of the second selector 122. The output end OUT2 of the second selector 122 can be coupled to the first input end of the adder 130. The second selector 122 can output the first input data A[15:0] input via the first input end IN21 through the output end OUT2 in response to the second selection signal SS2 having a logic "low" level. The second selector 122 can output the output data of the first selector 121 input via the second input end IN22 through the output end OUT2 in response to the second selection signal SS2 having a logic "high" level. In one embodiment, the second selector 122 can be implemented with a 2-to-l multiplexer having two input ends and one output end. In one embodiment, the output data of the second selector 122 can be the third input data received by the adder 130.

[0045] The third selector 123 can have a first input end IN31, a second input end IN32, a selection end S3, and an output end OUT3. Since the first input end IN31 of the third selector 123 is coupled to the second input end of the multiplier 110, the second input data B[15:0] can also be transmitted to the first input end IN31 of the third selector 123. The second input end IN32 of the third selector 123 can be coupled to the output end of the latch circuit 140. Thus, the third selector 123 can receive the feedback data DF[15:0] corresponding to the operation result data Y[15:0] output from the latch circuit 140 through the output end of the latch circuit 140. The second selection signal SS2 can also be transmitted to the selection end S3 of the third selector 123. The output end OUT3 of the third selector 123 can be coupled to the second input end of the adder 130. The third selector 123 can output the second input data B[15:0] input via the first input end IN31 through the output end OUT3 in response to the second selection signal SS2 having a logic "low" level. The third selector 123 can output the feedback data DF[15:0] input via the second input end IN32 through the output end OUT3 in response to the second selection signal SS2 having a logic "high" level. In one embodiment, the third selector 123 can be implemented with a 2-to-l multiplexer having two input ends and one output end. In one embodiment, the output data output from the output end OUT3 of the third selector 123 can be the fourth input data received by the adder 130.

[0046] The adder 130 can have a first input, a second input, and an output. The first input of the adder 130 can be coupled to the output OUT2 of the second selector 122. The second input of the adder 130 can be coupled to the output OUT3 of the third selector 123. Thus, the output data of the second selector 122 can be input to the first input of the adder 130, and the output data of the third selector 123 can be input to the second input of the adder 130. When the second selection signal SS2 has a logic "low" level, the first input data A[15:0] and the second input data B[15:0] can be transferred to the respective one of the first input and the second input of the adder 130. When the second selection signal SS2 has a logic "high" level, the output data of the first selector 121 and the feedback data DF[15:0] output from the latch circuit 140 can be transferred to the respective one of the first input and the second input of the adder 130. The output of the adder 130 can be coupled to both the second input IN42 of the fourth selector 124 and the first output line 161. The adder 130 can perform an addition calculation on the two sets of data input through the first input and the second input of the adder 130 to generate MAC data MAC[15:0]. The adder 130 can transfer the MAC data MAC[15:0] to the second input IN42 of the fourth selector 124, and can also output the MAC data MAC[15:0] via the first input line 161 as second result data IY[15:0] (also referred to as "intermediate result data") corresponding to the output data of the multiple operation circuit 100.

[0047] The fourth selector 124 may have a first input IN41, a second input IN42, a selection terminal S4, and an output terminal OUT4. The selection terminal S4 of the fourth selector 124 may be coupled to the output terminal of the inverter 150. The third selection signal SS3 may be transmitted to the input terminal of the inverter 150. In this embodiment, the inverter 150 can be used to more easily distinguish the logic levels of the second selection signal SS2 and the third selection signal SS3. Therefore, in some other embodiments, the multi-operation circuit 100 can be implemented without the inverter 150. The output terminal OUT4 of the fourth selector 124 may be coupled to the input terminal of the latch circuit 140. The fourth selector 124 may output the output data of the first selector 121 input via the first input terminal IN41 through the output terminal OUT4 in response to the third selection signal SS3 having a logic "high" level. The fourth selector 124 can respond to a third select signal SS3 with a logic "low" level by outputting MAC data MAC[15:0] input via the second input IN42 through output OUT4. In one embodiment, the fourth selector 124 can be implemented using a 2-to-1 multiplexer with two inputs and one output. In one embodiment, the output data output from output OUT4 of the fourth selector 124 can be the fifth input data received via latch circuit 140.

[0048] The latch circuit 140 may have an input, a clock input, and an output Q. In one embodiment, the latch circuit 140 may be implemented using a flip-flop with latching functionality. The input of the latch circuit 140 may be coupled to the output OUT4 of the fourth selector 124. The update signal UPDATE may be transmitted to the clock input of the latch circuit 140. The output Q of the latch circuit 140 may be coupled to both the second input IN32 and the second output line 162 of the third selector 123. The latch circuit 140 may be synchronized with the rising edge of the update signal UPDATE to latch the output data of the fourth selector 124 input to the input of the latch circuit 140. The latched data of the latch circuit 140 may be output through the output Q at a time point after a certain period of time elapsed from the rising edge of the update signal UPDATE. The output data of the latch circuit 140 may correspond to the feedback data DF[15:0] transmitted to the second input IN32 of the third selector 123. In addition, the output data of the latch circuit 140 can be output through the second output line 162 as the operation result data Y[15:0] corresponding to the output data of the multi-operation circuit 100.

[0049] Figure 2 The illustration shows the included Figure 1A configuration example of the multiplier 110 in the multiply operation circuit 100 shown is described. In the present embodiment, it can be assumed that the first input data A[15:0] includes first sign data S1[0] having 1 bit, first exponent data E1[7:0] having 8 bits, and first mantissa data M1[6:0] having 7 bits. In addition, it can be assumed that the second input data B[15:0] includes second sign data S2[0] having 1 bit, second exponent data E2[7:0] having 8 bits, and second mantissa data M2[6:0] having 7 bits. Similarly, it can be assumed that the multiplication result data AB[15:0] output from the multiplier 110 includes third sign data S3[0] having 1 bit, third exponent data E3[7:0] having 8 bits, and third mantissa data M3[6:0] having 7 bits.

[0050] Referring to Figure 2 , the multiplier 110 can include a sign processing circuit 110S, an exponent processing circuit 110E, a mantissa processing circuit 110M, and a normalizer 110N. The sign processing circuit 110S can include an exclusive OR (XOR) gate 111. The XOR gate 111 can perform an XOR operation using the first sign data S1[0] of the first input data A[15:0] and the second sign data S2[0] of the second input data B[15:0] as input data. The XOR gate 111 can output the third sign data S3[0] of the multiplication result data.

[0051] The exponent processing circuit 110E can include a first exponent adder 112 and a second exponent adder 113. The first exponent adder 112 can perform an addition calculation of the first exponent data E1[7:0] of the first input data A[15:0] and the second exponent data E2[7:0] of the second input data B[15:0], and can output the result data of the addition calculation. The second exponent adder 113 can perform an addition calculation of the output data of the first exponent adder 112 and a negative exponent bias value corresponding to the decimal number “-127” to subtract the exponent bias value corresponding to the decimal number “127” from the output data of the first exponent adder 112, thereby generating intermediate exponent data EM[7:0]. The intermediate exponent data EM[7:0] output from the second exponent adder 113 can be transferred to the normalizer 110N.

[0052] The mantissa processing circuit 110M can include a mantissa multiplier 114. The mantissa multiplier 114 can receive first mantissa data M1[7:0] having 8 bits and second mantissa data M2[7:0] having 8 bits. The first mantissa data M1[7:0] having 8 bits can be composed of first mantissa data M1[6:0] having 7 bits included in the first input data A[15:0] and implicit data IB having 1 bit. The second mantissa data M2[7:0] having 8 bits can be composed of second mantissa data M2[6:0] having 7 bits included in the second input data B[15:0] and implicit data IB having 1 bit. The implicit data IB represents a binary number "1" before a floating point number. The mantissa multiplier 114 can perform a multiplication calculation of the first mantissa data M1[7:0] having 8 bits and the second mantissa data M2[7:0] having 8 bits to generate first intermediate mantissa data MM13[15:0] having 16 bits as a result of the multiplication calculation. The first intermediate mantissa data MM13[15:0] having 16 bits generated by the mantissa multiplier 114 can be transferred to the normalizer 110N.

[0053] The normalizer 110N can include a floating point shifter 115, a multiplexer 116, a rounding processor 117, and a third exponent adder 118. The floating point shifter 115 of the normalizer 110N can receive the first intermediate mantissa data MM13[15:0] having 16 bits from the mantissa multiplier 114, and can shift the floating point number of the first intermediate mantissa data MM13[15:0] by 1 bit toward the most significant bit (MSB) of the first intermediate mantissa data MM13[15:0] to generate and output second intermediate mantissa data MM23[15:0]. The floating point number of the second intermediate mantissa data MM23[15:0] can be located between the fifteenth bit MM23

[14] and the MSB MM23

[15] of the second intermediate mantissa data MM23[15:0].

[0054] The multiplexer 116 of the normalizer 110N can receive the first intermediate mantissa data MM13[15:0] from the mantissa multiplier 114 through a first input IN1 of the multiplexer 116. The multiplexer 116 can also receive the second intermediate mantissa data MM23[15:0] from the floating point shifter 115 through a second input IN2 of the multiplexer 116. The multiplexer 116 can receive the MSB signal MM13

[15] of the first intermediate mantissa data MM13[15:0] as a selection signal. When the MSB signal MM13[15:0] of the first intermediate mantissa data MM13[15:0] has a binary number "0", the multiplexer 116 can output the first intermediate mantissa data MM13[15:0] input through the first input IN1. In contrast, when the MSB signal MM13

[15] of the first intermediate mantissa data MM13[15:0] has a binary number "1", the multiplexer 116 can output the second intermediate mantissa data MM23[15:0] input through the second input IN2.

[0055] The rounding processor 117 of the normalizer 110N can remove 9 bits including an implicit bit from the 16-bit intermediate mantissa data output from the multiplexer 116 and can perform a rounding operation while removing the 9 bits including the implicit bit from the 16-bit intermediate mantissa data. During the rounding operation, an addition calculation of adding a value "1" can be performed by a round-off operation or a round-up operation. The rounding processor 117 can output the third mantissa data M3[6:0] having 7 bits included in the multiplication result data AB[15:0].

[0056] The third exponent adder 118 of the normalizer 110N can perform an addition calculation to add the MSB data MM13

[15] of the first intermediate mantissa data MM13[15:0] output from the mantissa multiplier 114 to the intermediate exponent data EM[7:0] output from the second exponent adder 113. The third exponent adder 118 can generate and output the third exponent data E3[7:0] having 8 bits included in the multiplication result data AB[15:0]. When the MSB data MM13

[15] of the first intermediate mantissa data MM13[15:0] has a binary number "0", the third exponent data E3[7:0] output from the third exponent adder 118 can have the same value as the intermediate exponent data EM[7:0] output from the second exponent adder 113. When the MSB data MM13

[15] of the first intermediate mantissa data MM13[15:0] has a binary number "1", the third exponent data E3[7:0] output from the third exponent adder 118 can have a value that is 1 greater than the intermediate exponent data EM[7:0] output from the second exponent adder 113.

[0057] Figure 3 FIG. 13 illustrates a configuration example of the adder 130 included in the Figure 1 A configuration example of the adder 130 included in the multiple operation circuit 100 is illustrated. Hereinafter, it can be assumed that the adder 130 receives the multiplication result data AB[15:0] output from the respective one of the second selector 122 and the third selector 123 and the feedback data DF[15:0]. In one embodiment, the multiplication result data AB[15:0] can correspond to the output data of the multiplier 110 described above. In this case, as described above, the multiplication result data AB[15:0] can be composed of the third sign data S3[0] having 1 bit, the third exponent data E3[7:0] having 8 bits, and the third mantissa data M3[6:0] having 7 bits. In the present embodiment, it can be assumed that the feedback data DF[15:0] is composed of the fourth sign data S4[0] having 1 bit, the fourth exponent data E4[7:0] having 8 bits, and the fourth mantissa data M4[6:0] having 7 bits. Similarly, it can be assumed that the MAC data MAC[15:0] is composed of the sign data MAC_S[0] having 1 bit, the exponent data MAC_E[7:0] having 8 bits, and the mantissa data MAC_M[6:0] having 7 bits. Figure 2 The output data of the multiplier 110 described above. In this case, as described above, the multiplication result data AB[15:0] can be composed of the third sign data S3[0] having 1 bit, the third exponent data E3[7:0] having 8 bits, and the third mantissa data M3[6:0] having 7 bits. In the present embodiment, it can be assumed that the feedback data DF[15:0] is composed of the fourth sign data S4[0] having 1 bit, the fourth exponent data E4[7:0] having 8 bits, and the fourth mantissa data M4[6:0] having 7 bits. Similarly, it can be assumed that the MAC data MAC[15:0] is composed of the sign data MAC_S[0] having 1 bit, the exponent data MAC_E[7:0] having 8 bits, and the mantissa data MAC_M[6:0] having 7 bits.

[0058] Referring to Figure 3 The adder 130 can include a difference circuit 130D, a 2's complement processing circuit 130C, a shift circuit 130S, an addition circuit 130A, and a normalizer 130N. The difference circuit 130D can receive the third exponent data E3[7:0] of the multiplication result data AB[15:0] and the fourth exponent data E4[7:0] of the feedback data DF[15:0]. The difference circuit 130D can compare the third exponent data E3[7:0] with the fourth exponent data E4[7:0] to output the maximum exponent data E_MAX corresponding to the data having a larger value among the third exponent data E3[7:0] and the fourth exponent data E4[7:0]. The difference circuit 130D can also output the exponent difference data DE corresponding to the difference between the third exponent data E3[7:0] and the fourth exponent data E4[7:0]. In addition, the difference circuit 130D can output the selection signal SEL determined according to the target data to be shifted among the third exponent data E3[7:0] and the fourth exponent data E4[7:0]. The maximum exponent data E_MAX output from the difference circuit 130D can be transferred to the normalizer 130N. The exponent difference data DE and the selection signal SEL output from the difference circuit 130D can be transferred to the shift circuit 130S.

[0059] The complement-2 processing circuit 130C can include a first complement-2 processor 131C, a second complement-2 processor 132C, a first multiplexer 133C, and a second multiplexer 134C. The first complement-2 processor 131C can receive third mantissa data M3[6:0] of the multiplication result data AB[15:0]. The first complement-2 processor 131C can calculate a complement-2 value of the third mantissa data M3[6:0] to generate and output third complement-2 data 2M3[6:0]. The second complement-2 processor 132C can receive fourth mantissa data M4[6:0] of the feedback data DF[15:0]. The second complement-2 processor 132C can calculate a complement-2 value of the fourth mantissa data M4[6:0] to generate and output fourth complement-2 data 2M4[6:0].

[0060] The first multiplexer 133C can receive the third mantissa data M3[6:0] of the multiplication result data AB[15:0] through a first input terminal of the first multiplexer 133C. The first multiplexer 133C can receive the third complement-2 data 2M3[6:0] from the first complement-2 processor 131C through a second input terminal of the first multiplexer 133C. The first multiplexer 133C can receive third sign data S3[0] of the multiplication result data AB[15:0] through a selection terminal of the first multiplexer 133C. The first multiplexer 133C can output the third mantissa data M3[6:0] input through the first input terminal or the third complement-2 data 2M3[6:0] input through the second input terminal according to the third sign data S3[0]. In an embodiment, when the third sign data S3[0] has a binary number "0" representing a positive number, the first multiplexer 133C can output the third mantissa data M3[6:0]. In contrast, when the third sign data S3[0] has a binary number "1" representing a negative number, the first multiplexer 133C can output the third complement-2 data 2M3[6:0]. Hereinafter, output data of the first multiplexer 133C will be referred to as first intermediate mantissa data MM1[6:0].

[0061] The second multiplexer 134C can receive the fourth mantissa data M4[6:0] of the feedback data DF[15:0] through a first input terminal of the second multiplexer 134C. The second multiplexer 134C can receive the fourth complement-of-two data 2M4[6:0] from the second complement-of-two processor 132C through a second input terminal of the second multiplexer 134C. The second multiplexer 134C can receive the fourth sign data S4[0] of the feedback data DF[15:0] through a selection terminal of the second multiplexer 134C. The second multiplexer 134C can output the fourth mantissa data M4[6:0] input through the first input terminal or the fourth complement-of-two data 2M4[6:0] input through the second input terminal according to the fourth sign data S4[0]. In one embodiment, when the fourth sign data S4[0] has a binary number "0" representing a positive number, the second multiplexer 134C can output the fourth mantissa data M4[6:0]. Conversely, when the fourth sign data S4[0] has a binary number "1" representing a negative number, the second multiplexer 134C can output the fourth complement-of-two data 2M4[6:0]. Hereinafter, the output data of the second multiplexer 134C will be referred to as second intermediate mantissa data MM2[6:0].

[0062] The shift circuit 130S can include a third multiplexer 131S, a fourth multiplexer 132S, and a shifter 133S. The third multiplexer 131S can receive the first intermediate mantissa data MM1[6:0] from the first multiplexer 133C of the complement-of-two processing circuit 130C through a first input terminal of the third multiplexer 131S. The third multiplexer 131S can receive the second intermediate mantissa data MM2[6:0] from the second multiplexer 134C of the complement-of-two processing circuit 130C through a second input terminal of the third multiplexer 131S. The third multiplexer 131S can receive a selection signal SEL from the difference circuit 130D through a selection terminal of the third multiplexer 131S. The third multiplexer 131S can output the first intermediate mantissa data MM1[6:0] or the second intermediate mantissa data MM2[6:0] according to the selection signal SEL. In one embodiment, when the selection signal SEL has a first logic level (e.g., a logic "low" level), the third multiplexer 131S can output the first intermediate mantissa data MM1[6:0]. Conversely, when the selection signal SEL has a second logic level (e.g., a logic "high" level), the third multiplexer 131S can output the second intermediate mantissa data MM2[6:0]. Hereinafter, the output data of the third multiplexer 131S will be referred to as third intermediate mantissa data MM3[6:0].

[0063] The fourth multiplexer 132S can receive the second intermediate mantissa data MM2[6:0] from the second multiplexer 134C of the 2's complement processing circuit 130C through a first input terminal of the fourth multiplexer 132S. The fourth multiplexer 132S can receive the first intermediate mantissa data MM1[6:0] from the first multiplexer 133C of the 2's complement processing circuit 130C through a second input terminal of the fourth multiplexer 132S. The fourth multiplexer 132S can receive the selection signal SEL from the difference circuit 130D through a selection terminal of the fourth multiplexer 132S. The fourth multiplexer 132S can output the second intermediate mantissa data MM2[6:0] or the first intermediate mantissa data MM1[6:0] according to the selection signal SEL. In one embodiment, when the selection signal SEL has a first logic level (e.g., a logic "low" level), the fourth multiplexer 132S can output the second intermediate mantissa data MM2[6:0]. Conversely, when the selection signal SEL has a second logic level (e.g., a logic "high" level), the fourth multiplexer 131S can output the first intermediate mantissa data MM1[6:0]. Hereinafter, the output data of the fourth multiplexer 132S will be referred to as fourth intermediate mantissa data MM4[6:0].

[0064] The shifter 133S can perform a shift operation on the mantissa bits of the multiplication result data AB[15:0] or the feedback data DF[15:0] so that the third exponent data E3[7:0] of the multiplication result data AB[15:0] input to the adder 130 is identical to the fourth exponent data E4[7:0] of the feedback data DF[15:0] input to the adder 130. Specifically, the shifter 133S can receive the fourth intermediate mantissa data MM4[6:0] from the fourth multiplexer 132S. The fourth intermediate mantissa data MM4[6:0] can be the third 2's complement data 2M3[6:0] (or the third mantissa data M3[6:0] of the multiplication result data AB[15:0]) or the fourth 2's complement data 2M4[6:0] (or the fourth mantissa data M4[6:0] of the feedback data DF[15:0]). The shifter 133S can also receive the exponent difference data DE from the difference circuit 130D. The shifter 133S can shift the fourth intermediate mantissa data MM4[6:0] by a number of bits corresponding to the exponent difference data DE to generate shifted mantissa data SM[6:0].

[0065] In the present embodiment, the shifter 133S can be configured to shift the bits included in the fourth intermediate mantissa data MM4[6:0] in the left direction. However, the present embodiment can be merely an example of the present disclosure. Therefore, in some other embodiments, the shifter 133S can be configured to shift the bits included in the fourth intermediate mantissa data MM4[6:0] in the right direction. When the shifter 133S is configured to shift the bits included in the fourth intermediate mantissa data MM4[6:0] in the left direction as in the present embodiment, the mantissa data having a relatively smaller value than the fourth intermediate mantissa data MM4[6:0] can be transferred to the shifter 133S. Alternatively, when the shifter 133S is configured to shift the bits included in the fourth intermediate mantissa data MM4[6:0] in the right direction, the mantissa data having a relatively larger value than the fourth intermediate mantissa data MM4[6:0] can be transferred to the shifter 133S. The mantissa data input to the shifter 133S can be selected by a selection signal SEL, which is transferred from the difference circuit 130D to the selection terminal of the third multiplexer 131S and the fourth multiplexer 132S.

[0066] The addition circuit 130A can include an integer adder 131A, a third two's complement processor 132A, and a fifth multiplexer 133A. The integer adder 131A can receive the third intermediate mantissa data MM3[6:0] and the shifted mantissa data SM[6:0] from a corresponding one of the third multiplexer 131S and the shifter 133S included in the shift circuit 130S. In addition, the integer adder 131A can receive the third sign data S3[0] and the fourth sign data S4[0]. The integer adder 131A can generate and output the sign data MAC_S[0] of the MAC data MAC[15:0] according to a result of an addition calculation of the third sign data S3[0], the fourth sign data S4[0], the third intermediate mantissa data MM3[6:0], and the shifted mantissa data SM[6:0]. Further, the integer adder 131A can perform an addition calculation of the third intermediate mantissa data MM3[6:0] and the shifted mantissa data SM[6:0] to generate and output the added mantissa data AM[6:0]. In one embodiment, when the third sign data S3[0] and the fourth sign data S4[0] both have a binary number "0" representing a positive number, the integer adder 131A can output a binary number "0" as the sign data MAC_S[0] of the MAC data MAC[15:0]. When the third sign data S3[0] and the fourth sign data S4[0] both have a binary number "1" representing a negative number, the integer adder 131A can output a binary number "1" as the sign data MAC_S[0] of the MAC data MAC[15:0]. When one of the third sign data S3[0] and the fourth sign data S4[0] has a binary number "0" and the other of the third sign data S3[0] and the fourth sign data S4[0] has a binary number "1", if a rounding occurs as a result of the addition calculation of the third intermediate mantissa data MM3[6:0] and the shifted mantissa data SM[6:0], the integer adder 131A can output a binary number "0" as the sign data MAC_S[0], and if the addition calculation of the third intermediate mantissa data MM3[6:0] and the shifted mantissa data SM[6:0] does not occur, the integer adder 131A can output a binary number "1" as the sign data MAC_S[0]. The integer adder 131A can output the sign data MAC_S[0] of the MAC data MAC[15:0] through a first output terminal, and can output the added mantissa data AM[6:0] through a second output terminal.

[0067] The third 2's complement processor 132A can receive the added mantissa data AM[6:0] output from the integer adder 131A through the second output terminal of the integer adder 131A. The third 2's complement processor 132A can calculate the 2's complement of the added mantissa data AM[6:0] to output the 2's complement of the added mantissa data AM[6:0] as the 2's complement added mantissa data 2AM[6:0]. The fifth multiplexer 133A can receive the added mantissa data AM[6:0] output from the integer adder 131A through the first input terminal of the fifth multiplexer 133A via the second output terminal of the integer adder 131A. The fifth multiplexer 133A can receive the 2's complement added mantissa data 2AM[6:0] from the third 2's complement processor 132A through the second input terminal of the fifth multiplexer 133A. The fifth multiplexer 133A can receive the sign data MAC_S[0] of the MAC data MAC[15:0] output from the integer adder 131A via the first output terminal of the integer adder 131A through the selection terminal of the fifth multiplexer 133A. The fifth multiplexer 133A can output the added mantissa data AM[6:0] input through the first input terminal of the fifth multiplexer 133A or the 2's complement added mantissa data 2AM[6:0] input through the second input terminal of the fifth multiplexer 133A through the output terminal of the fifth multiplexer 133A according to the sign data MAC_S[0] of the MAC data MAC[15:0]. In one embodiment, when the sign data MAC_S[0] has a binary number "0" representing a positive number, the fifth multiplexer 133A can output the added mantissa data AM[6:0]. Conversely, when the sign data MAC_S[0] has a binary number "1" representing a negative number, the fifth multiplexer 133A can output the 2's complement added mantissa data 2AM[6:0]. Hereinafter, the output data of the fifth multiplexer 133A will be referred to as the fifth intermediate mantissa data MM5[6:0].

[0068] The normalizer 130N may have a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The normalizer 130N can receive the maximum exponent data E_MAX from the difference circuit 130D through its first input terminal. The normalizer 130N can receive the fifth intermediate mantissa data MM5[6:0] from the fifth multiplexer 133A through its second input terminal. The normalizer 130N can output the maximum exponent data E_MAX input through its first input terminal as the exponent data MAC_E[7:0] of the MAC data MAC[15:0] through its first output terminal. Furthermore, the normalizer 130N can perform rounding operations on the fifth intermediate mantissa data MM5[6:0] input through its second input terminal, thereby generating the mantissa data MAC_M[6:0] of the MAC data MAC[15:0], which is then output through the second output terminal of the normalizer 130N.

[0069] Figure 4 The illustration shows that Figure 1 An example of matrix-vector multiplication performed by MAC operation in the first operation mode of the multi-operation circuit 100 shown. See also Figure 4 The multi-operation circuit 100 can perform matrix-vector multiplication calculations of the weight matrix 210 and the vector matrix 220 to perform MAC operations for generating the result matrix 230. The weight matrix 210 can have “M” rows (i.e., the first to the Mth rows RW(1), RW(2), ..., and RW(M)) and “N” columns (i.e., the first to the Nth columns CW(1), CW(2), ..., and CW(N)) (where “M” and “N” are natural numbers equal to or greater than 2). The vector matrix 220 can have “N” rows (i.e., the first to the Nth rows RV(1), RV(2), ..., and RV(N)) and one column CV(1). The result matrix 230 can have “M” rows (i.e., the first to the Mth rows RR(1), RR(2), ..., and RR(M)) and one column CR(1).

[0070] The weight matrix 210 can have "M x N" weight elements, i.e., W(1.1) ~ W(1.N),..., and W(M.1) ~ W(M.N). The vector matrix 220 can have "N" vector elements, i.e., V(1), V(2),..., and V(N). The result matrix 230 can have "M" result elements, i.e., MAC_RST(1), MAC_RST(2),..., and MAC_RST(M). Hereinafter, the term "weight data" can be interpreted to have the same meaning as the term "weight element," and the term "vector data" can be interpreted to have the same meaning as the term "vector element." In addition, the term "MAC result data" can be interpreted to have the same meaning as the term "result element." Hereinafter, it can be assumed that the weight data and the vector data have a 16-bit floating point format, e.g., a 16-bit Brain Floating Point (BF16) format.

[0071] The MAC result data MAC_RST(1) in the first row RR(1) of the result matrix 230 can be generated by a matrix-vector multiplication calculation of the weight data W(1.1) ~ W(1.N) in the first row RW(1) of the weight matrix 210 with the vector data V(1) ~ V(N) of the vector matrix 220. The MAC result data MAC_RST(2) in the second row RR(2) of the result matrix 230 can be generated by a matrix-vector multiplication calculation of the weight data W(2.1) ~ W(2.N) in the second row RW(2) of the weight matrix 210 with the vector data V(1) ~ V(N) of the vector matrix 220. Similarly, the MAC result data MAC_RST(M) in the M-th row RR(M) of the result matrix 230 can be generated by a matrix-vector multiplication calculation of the weight data W(M.1) ~ W(M.N) in the M-th row RW(M) of the weight matrix 210 with the vector data V(1) ~ V(N) of the vector matrix 220.

[0072] Figure 5 An example of an execution process of the matrix-vector multiplication calculation is illustrated. Figure 4 The multiple operation circuit 100 can perform a MAC operation on the weight data (e.g., W(1.1) ~ W(1.N), W(2.1) ~ W(2.N),..., or W(M.1) ~ W(M.N)) arranged in any one of the first to M-th rows RW(1) ~ RW(M) of the weight matrix 210 and the vector data of the vector matrix 220. For example, as illustrated in FIG. 2, the multiple operation circuit 100 can perform a MAC operation on the weight data W(1.1) ~ W(1.N) in the first row RW(1) of the weight matrix 210 and the vector data V(1) ~ V(N) of the vector matrix 220 to generate the MAC result data MAC_RST(1) in the first row RR(1) of the result matrix 230. Figure 5 As illustrated, the multiple operation circuit 100 can perform a MAC operation on the weight data W(1.1) ~ W(1.N) in the first row RW(1) of the weight matrix 210 and the vector data V(1) ~ V(N) of the vector matrix 220 to generate the MAC result data MAC_RST(1) in the first row RR(1) of the result matrix 230.

[0073] Specifically, the multiple operation circuit 100 can perform a first MAC operation using the weight data W(l,l) located at the intersection of the first row RW(l) and the first column CW(l) of the weight matrix 210 and the vector data V(l) located in the first row RV(l) of the vector matrix 220 as input data, thereby generating first MAC data MAC1[15:0]. Next, the multiple operation circuit 100 can perform a second MAC operation on the weight data W(l,2) located at the intersection of the first row RW(l) and the second column CW(2) of the weight matrix 210 and the vector data V(2) located in the second row RV(2) of the vector matrix 220 to generate second MAC data MAC2[15:0]. The second MAC operation can include an accumulation calculation for accumulating the multiplication result of the weight data W(l,2) and the vector data V(2) with the first MAC data MAC1[15:0].

[0074] Subsequently, the multiple operation circuit 100 can perform a third MAC operation on the weight data W(l,3) located at the intersection of the first row RW(l) and the third column CW(3) of the weight matrix 210 and the vector data V(3) located in the third row RV(3) of the vector matrix 220 to generate third MAC data MAC3[15:0]. The third MAC operation can include an accumulation calculation for adding the multiplication result of the weight data W(l,3) and the vector data V(3) to the second MAC data MAC2[15:0]. These MAC operations can be sequentially performed until an Nth MAC operation for multiplying the weight data W(l,N) located at the intersection of the first row RW(l) and the Nth column CW(N) of the weight matrix 210 by the vector data V(N) located in the Nth row RV(N) of the vector matrix 220 is performed. The Nth MAC operation can be an accumulation calculation for adding the multiplication result of the weight data W(l,N) and the vector data V(N) to the result of the (N-l)th MAC operation. The Nth MAC data MAC“N”[15:0] generated by the Nth MAC operation can correspond to the MAC result data MAC_RST(l) in the first row RR(l) of the result matrix 230.

[0075] Figure 6 illustrates a first MAC operation of Figure 1 performed by the multiple operation circuit 100 shown in Figure 5 . In Figure 6 , the same reference numerals or symbols used in Figure 1 indicate the same elements. See Figure 6To perform the first MAC operation of the multi-processor circuit 100, a first selection signal SS1 with a logic "HI" level, a second selection signal SS2 with a logic "HI" level, and a third selection signal SS3 with a logic "LO" level can be sequentially transmitted to the multi-processor circuit 100. The level of the update signal UPDATE can change from a logic "LO" level to a logic "HI" level before the second selection signal SS2 is transmitted to the multi-processor circuit 100 and after the third selection signal SS3 is transmitted to the multi-processor circuit 100. Located in the weight matrix ( Figure 4 The weight data W(1.1)[15:0] at the intersection of the first row RW(1) and the first column CW(1) of multiplier 110 can be input to the first input of multiplier 110. Vector matrix ( Figure 4 The vector data V(1) in the first row RV(1) of 220 can be input to the second input of multiplier 110. (See reference...) Figure 2 As described, multiplier 110 can perform multiplication on weight data W(1.1)[15:0] and vector data V(1) to generate first multiplication result data WV1[15:0] and output it through the output terminal of multiplier 110.

[0076] The first selector 121, which receives the first selection signal SS1 with a logic "HI" level, can output the first multiplication result data WV1[15:0] input via the second input IN12 of the first selector 121 through its output terminal OUT1. The first multiplication result data WV1[15:0] output from the first selector 121 can be transmitted to the second input IN22 of the second selector 122. The first multiplication result data WV1[15:0] output from the first selector 121 can also be transmitted to the first input IN41 of the fourth selector 124. When the level of the update signal UPDATE changes from a logic "LO" level to a logic "HI" level, the latch circuit 140 can output its latched data as the first feedback data DF1[15:0], which is transmitted to the second input IN32 of the third selector 123. In this case, because the latch circuit 140 has an initialization state, the first feedback data DF1[15:0] can have a zero value. After the latch circuit 140 outputs the first feedback data DF1[15:0] with a value of zero, the level of the update signal UPDATE can be changed from the logic "high (HI)" level to the logic "low (LO)" level.

[0077] The second selector 122 receiving the second selection signal SS2 having the logic "high (HI)" level can output the first multiplication result data WV1[15:0] transferred from the first selector 121 to the second input IN22 of the second selector 122 through the output OUT2. The first multiplication result data WV1[15:0] output from the second selector 122 can be transferred to the first input of the adder 130. The third selector 123 receiving the second selection signal SS2 having the logic "high (HI)" level can output the first feedback data DF1[15:0] transferred from the latch circuit 140 to the second input IN32 of the third selector 123 through the output OUT3 of the third selector 123. The first feedback data DF1[15:0] output from the third selector 123 can be transferred to the second input of the adder 130.

[0078] The adder 130 can perform an addition calculation using the first multiplication result data WV1[15:0] input to the first input and the first feedback data DF1[15:0] input to the second input as input data, thereby generating and outputting the first MAC data MAC1[15:0]. Since the first feedback data DF1[15:0] has a zero value, the first MAC data MAC1[15:0] output from the adder 130 can have the same value as the first multiplication result data WV1[15:0] generated by the multiplier 110. The first MAC data MAC1[15:0] output from the adder 130 can be transferred to the second input IN42 of the fourth selector 124 through the output of the adder 130. In addition, the first MAC data MAC1[15:0] output from the adder 130 can be output from the multiple operation circuit 100 through the first output line 161 to provide the intermediate result data IY[15:0]. The inverter 150 can change the level of the third selection signal SS3 from the logic "low (LO)" level to the logic "high (HI)" level, and the third selection signal SS3 having the logic "high (HI)" level can be transferred to the fourth selector 124. The fourth selector 124 receiving the third selection signal SS3 having the logic "high (HI)" level can output the first MAC data MAC1[15:0] transferred from the adder 130 to the second input IN42 through the output OUT4. The first MAC data MAC1[15:0] output from the fourth selector 124 can be transferred to the input of the latch circuit 140.

[0079] When the level of the update signal UPDATE changes from a logic "low (LO)" level to a logic "high (HI)" level, the latch circuit 140 can latch the first MAC data MAC1 [15:0] transferred to the input end of the latch circuit 140. In addition, the latch circuit 140 can output the latched data of the first MAC data MAC1 [15:0] through the output end Q of the latch circuit 140. The first MAC data MAC1 [15:0] output from the latch circuit 140 can be transferred to the second input end IN32 of the third selector 123 to provide feedback data used for the second MAC operation performed in the next step. The first MAC data MAC1 [15:0] output from the latch circuit 140 can also be output from the multiple operation circuit 100 through the second output line 162. After the latch circuit 140 outputs the first MAC data MAC1 [15:0], the level of the update signal UPDATE can change from the logic "high (HI)" level to the logic "low (LO)" level.

[0080] Figure 7 The second MAC operation process of the multiple operation circuit 100 shown in Figure 1 is illustrated. Figure 5 The second MAC operation process of the multiple operation circuit 100 shown in Figure 7 is illustrated. Figure 1 The same reference numerals or symbols as used in the first MAC operation process of the multiple operation circuit 100 shown in Figure 7 are used to represent the same elements. Referring to Figure 4 , to perform the second MAC operation of the multiple operation circuit 100, the first selection signal SS1 having a logic "high (HI)" level, the second selection signal SS2 having a logic "high (HI)" level, and the third selection signal SS3 having a logic "low (LO)" level can be sequentially transferred to the multiple operation circuit 100. The level of the update signal UPDATE can change from the logic "low (LO)" level to the logic "high (HI)" level before the time point at which the second selection signal SS2 is transferred to the multiple operation circuit 100 and after the time point at which the third selection signal SS3 is transferred to the multiple operation circuit 100. The weight data W(1.2) [15:0] at the intersection of the first row RW(1) and the second column CW(2) of the weight matrix (210) of Figure 4 may be input to the first input end of the multiplier 110. The vector data V(2) in the second row RV(2) of the vector matrix (220) of may be input to the second input end of the multiplier 110. The multiplier 110 can perform a multiplication calculation on the weight data W(1.2) [15:0] and the vector data V(2) to generate the second multiplication result data WV2 [15:0] and output through the output end of the multiplier 110.

[0081] The first selector 121, which receives the first selection signal SS1 with a logic "high (HI)" level, can output the second multiplication result data WV2[15:0] input via the second input IN12 of the first selector 121 through its output terminal OUT1. The second multiplication result data WV2[15:0] output from the first selector 121 can be transmitted to the second input IN22 of the second selector 122. The second multiplication result data WV2[15:0] output from the first selector 121 can also be transmitted to the first input IN41 of the fourth selector 124. When the level of the update signal UPDATE transmitted to the clock terminal of the latch circuit 140 changes from a logic "low (LO)" level to a logic "high (HI)" level, the latch circuit 140 can output its latched data as the second feedback data DF2[15:0], which is transmitted to the second input IN32 of the third selector 123. In this case, the second feedback data DF2[15:0] can correspond to the reference... Figure 5 and Figure 6 The first MAC data MAC1[15:0] is latched in latch circuit 140 during the first MAC operation described. After latch circuit 140 outputs second feedback data DF2[15:0], the level of update signal UPDATE can be changed from logic "low (LO)" level to logic "high (HI)" level.

[0082] The second selector 122, which receives the second selection signal SS2 with a logic "HI" level, can output the second multiplication result data WV2[15:0] transmitted from the first selector 121 to the second input IN22 of the second selector 122 via its output terminal OUT2. The second multiplication result data WV2[15:0] output from the second selector 122 can be transmitted to the first input terminal of the adder 130. The third selector 123, which receives the second selection signal SS2 with a logic "HI" level via its selection terminal S3, can output the second feedback data DF2[15:0] (i.e., the first MAC data MAC1[15:0]) transmitted from the latch circuit 140 to the second input terminal IN32 of the third selector 123 via its output terminal OUT3. The first MAC data MAC1[15:0] output from the third selector 123 can be transmitted to the second input terminal of the adder 130.

[0083] Adder 130 can use the second multiplication result data WV2[15:0] input to the first input terminal and the first MAC data MAC1[15:0] input to the second input terminal as input data to perform addition calculation, thereby generating and outputting the second MAC data MAC2[15:0]. Therefore, the second MAC data MAC2[15:0] output from adder 130 can have a value that accumulates the second multiplication result data to the first MAC data MAC1[15:0], as shown in the reference. Figure 5 As described. The second MAC data MAC2[15:0] output from adder 130 can be transmitted to the second input IN42 of fourth selector 124 through the output of adder 130. In addition, the second MAC data MAC2[15:0] output from adder 130 can be output from multi-operation circuit 100 through first output line 161 to provide intermediate result data IY[15:0]. Inverter 150 can change the level of third selection signal SS3 from logic "low (LO)" level to logic "high (HI)" level, and the third selection signal SS3 with logic "high (HI)" level can be transmitted to the selection terminal S4 of fourth selector 124. Fourth selector 124, which receives the third selection signal SS3 with logic "high (HI)" level, can output the second MAC data MAC2[15:0] transmitted from adder 130 to second input IN42 through output terminal OUT4. The second MAC data MAC2[15:0] output from the fourth selector 124 can be transmitted to the input of the latch circuit 140.

[0084] The latch circuit 140 can be synchronized with the rising edge of the update signal UPDATE to latch the second MAC data MAC2[15:0]. Furthermore, the latch circuit 140 can output the latched data of the second MAC data MAC2[15:0] through its output terminal Q. The second MAC data MAC1[15:0] output from the latch circuit 140 can be transmitted to the second input terminal IN32 of the third selector 123 to provide feedback data for the third MAC operation to be performed in the next step. The second MAC data MAC2[15:0] output from the latch circuit 140 can also be output from the multi-operation circuit 100 through the second output line 162. After the latch circuit 140 outputs the second MAC data MAC2[15:0], the level of the update signal UPDATE can be changed from a logic "high (HI)" level to a logic "low (LO)" level.

[0085] Figure 8 The illustration shows that Figure 1 An example of matrix-scalar multiplication performed by EW multiplication in the second operation mode of the multi-operation circuit 100 shown. See also Figure 8The multi-processor circuit 100 can perform matrix-scalar multiplication on the weight matrix 310 and the constant C to perform EW multiplication for generating the result matrix 330. In this embodiment, it can be assumed that the weight matrix 310 and the reference... Figure 5 The weight matrix 310 is the same as described. Therefore, the weight matrix 310 can have “M×N” sets of weight data W(1.1)~W(1.N), ... and W(M.1)~W(MN). Conversely, the constant C can consist of a single data. The result matrix 330 can have EWM result data EWM(1.1)~EWM(1.N), ... and EWM(M.1)~EWM(MN), which are generated by the EW multiplication of the multiple operation circuit 100 and serve as elements of the result matrix 330. Therefore, the result matrix 330 can have the same size as the weight matrix 310. That is, the result matrix 330 can have “M” rows (i.e., the first row to the Mth row R(1)~R(M)) and “N” columns (i.e., the first column to the Nth column C(1)~C(N)). The EWM result data EWM corresponding to the elements of the result matrix 330 can be obtained by multiplying the weight data W(1.1) to W(1.N), ... and W(M.1) to W(MN) by a constant C. Accordingly, the EW multiplication calculation performed in the second operation mode of the multiplication circuit 100 can be implemented using only multiplication calculation without any accumulation calculation.

[0086] Figure 9 The diagram illustrates the process of... Figure 1 The multi-operation circuit 100 shown performs the following operations: Figure 8 EW multiplication calculation. Figure 9 In, and in Figure 1 The same reference numerals or symbols used in the figures denote the same elements. See also Figure 9 To perform EW multiplication calculations in the second operation mode of the multi-operation circuit 100, a first selection signal SS1 with a logic "high (HI)" level and a third selection signal SS3 with a logic "high (HI)" level can be applied to one of the first selector 121 and the fourth selector 124 respectively. In this case, the second selection signal SS2 is deactivated. Therefore, the second selector 122 and the third selector 123 do not operate. The level of the update signal UPDATE can change from a logic "low (LO)" level to a logic "high (HI)" level at a time point after a certain period of time has elapsed since the third selection signal SS3 was applied to the multi-operation circuit 100 (e.g., after the output data of the fourth selector 124 is transmitted to the input of the latch circuit 140). Located in the weight matrix ( Figure 8The weight data W(1.1) [15:0] at the intersection of the first row RW(1) and the first column CW(1) of the weight data W[15:0] of the memory 310) can be input to the first input end of the multiplier 110. The constant data C [15:0] can be input to the second input end of the multiplier 110. The constant data C [15:0] can be provided by converting a constant (C) into the same format (e.g., the BF16 format) as the weight data. The multiplier 110 can perform a multiplication calculation on the weight data W(1.1) [15:0] and the constant data C [15:0] to generate first multiplication result data WC1 [15:0] and output through the output end of the multiplier 110. Figure 8

[0087] The first selector 121 receiving the first selection signal SS1 having the logic "high (HI)" level can output the first multiplication result data WC1 [15:0] input through the second input end IN12 of the first selector 121 through the output end OUT1. The first multiplication result data WC1 [15:0] output from the first selector 121 can be transferred to the second input end IN22 of the second selector 122 and the first input end IN41 of the fourth selector 124. Because the second selection signal SS2 is deactivated, the second selector 122 and the third selector 123 do not operate and the adder 130 does not operate. The inverter 150 can change the level of the third selection signal SS3 from the logic "high (HI)" level to the logic "low (LO)" level, and the third selection signal SS3 having the logic "low (LO)" level can be transferred to the selection end S4 of the fourth selector 124. The fourth selector 124 receiving the third selection signal SS3 having the logic "low (LO)" level can output the first multiplication result data WC1 [15:0] transferred from the output end OUT1 of the first selector 121 to the first input end IN41 of the fourth selector 124 through the output end OUT4. The first multiplication result data WC1 [15:0] output from the fourth selector 124 can be transferred to the input end of the latch circuit 140.

[0088] ​The latch circuit 140 can latch the first multiplication result data WC1[15:0] in synchronization with a rising edge of the update signal UPDATE. In addition, the latch circuit 140 can output the latched data of the first multiplication result data WC1[15:0] through an output terminal Q of the latch circuit 140. After the latch circuit 140 outputs the first multiplication result data WC1[15:0], the level of the update signal UPDATE can change from a logic "high (HI)" level to a logic "low (LO)" level. The first multiplication result data WC1[15:0] output from the latch circuit 140 can be output from the multiple operation circuit 100 through a second output line 162. The first multiplication result data WC1[15:0] output from the multiple operation circuit 100 can correspond to the EWM result data EWM(1.1) at the intersection of the first row R(1) and the first column C(1) of the result matrix 330 shown in FIG. 4. Figure 8

[0089] Figure 10 FIG. 4 illustrates an example of a matrix addition calculation performed by an EW addition calculation in a second operation mode of the multiple operation circuit 100 shown in FIG. 1. Figure 1 Figure 10 Figure 5 ​​​The weight matrix 210 described has the same form. Therefore, the first matrix 410 can have “M×N” first data A(1.1)~A(1.N), ... and A(M.1)~A(MN), and the second matrix 420 can also have “M×N” second data B(1.1)~B(1.N), ... and B(M.1)~B(MN). The result matrix 430 can have EWA result data EWA(1.1)~EWA(1.N), ... and EWA(M.1)~EWA(MN) generated by the EW addition calculation of the multiple operation circuit 100 as elements of the result matrix 430. Therefore, the result matrix 430 can have the same size as each of the first matrix 410 and the second matrix 420. That is, the result matrix 430 can have “M” rows (i.e., the first row to the Mth row R(1)~R(M)) and “N” columns (i.e., the first column to the Nth column C(1)~C(N)). The EWA result data EWM corresponding to the elements of the result matrix 430 can be obtained by adding the first data A(1.1) to A(1.N), ... and A(M.1) to A(MN) of the first matrix 410 to the corresponding data in the second data B(1.1) to B(1.N), ... and B(M.1) to B(MN) of the second matrix 420. In this way, the EW addition calculation performed in the second operation mode of the multiple operation circuit 100 can be implemented using only addition calculation, without utilizing any multiplication calculation or any accumulation calculation performed for MAC operation.

[0090] Figure 11 The diagram illustrates the process of... Figure 1 The multi-operation circuit 100 shown performs the following operations: Figure 10 EW addition calculation. Figure 11 In, and in Figure 1 The same reference numerals or symbols used in the figures denote the same elements. See also Figure 11 To perform EW addition calculations in the second operation mode of the multi-operation circuit 100, a second selection signal SS2 with a logic "low (LO)" level can be applied to the selection terminals S2 of the second selector 122 and S3 of the third selector 123. Additionally, a third selection signal SS3 with a logic "low (LO)" level can be transmitted to the input of an inverter 150 coupled to the selection terminal S4 of the fourth selector 124. The first selection signal SS1 can be deactivated, causing the first selector to not operate. The level of the update signal UPDATE can change from a logic "low (LO)" level to a logic "high (HI)" level at a point in time after a certain period elapses from the time the third selection signal SS3 is applied to the multi-operation circuit 100 (e.g., after the output data of the fourth selector 124 is transmitted to the input of the latch circuit 140).

[0091] Located in the first matrix ( Figure 10 The first data A(1.1)[15:0] at the intersection of the first row R(1) and the first column C(1) of the second matrix 410) can be transmitted to the first input IN21 of the second selector 122. Located in the second matrix ( Figure 10 The second data B(1.1)[15:0] at the intersection of the first row R(1) and the first column C(1) of the 420) can be transmitted to the first input IN31 of the third selector 123. The second selector 122, which receives the second selection signal SS2 with a logic "LO" level, can output the first data A(1.1)[15:0] to the first input IN21 through the output OUT2. The first data A(1.1)[15:0] output from the second selector 122 can be transmitted to the first input of the adder 130. The third selector 123, which receives the second selection signal SS2 with a logic "LO" level, can output the second data B(1.1)[15:0] to the first input IN31 through the output OUT3. The second data B(1.1)[15:0] output from the third selector 123 can be transmitted to the second input of the adder 130.

[0092] Adder 130 can perform addition calculations on first data A (1.1) [15:0] input to the first input terminal and second data B (1.1) [15:0] input to the second input terminal, thereby generating addition result data DA11 [15:0]. The addition result data DA11 [15:0] generated by adder 130 can be transmitted to the second input terminal IN42 of fourth selector 124 through the output terminal of adder 130. In addition, the addition result data DA11 [15:0] generated by adder 130 can be output from multiplex circuit 100 through first output line 161 to provide intermediate result data IY [15:0]. Fourth selector 124, which receives the logic "high (HI)" level output from inverter 150, can output the addition result data DA11 [15:0] transmitted from adder 130 to the second input terminal IN42 of fourth selector 124 through output terminal OUT4. The summation result data DA11[15:0] output from the fourth selector 124 can be transmitted to the input of the latch circuit 140.

[0093] The latch circuit 140 can latch the addition result data DA11[15:0] output from the fourth selector 124 in synchronization with a rising edge of the update signal UPDATE. In addition, the latch circuit 140 can output the latched data of the addition result data DA11[15:0] through an output terminal Q of the latch circuit 140. After the latch circuit 140 outputs the addition result data DA11[15:0], the level of the update signal UPDATE can change from a logic "high (HI)" level to a logic "low (LO)" level. The addition result data DA11[15:0] output from the latch circuit 140 can be output from the multiple operation circuit 100 through the second output line 162. The addition result data DA11[15:0] output from the multiple operation circuit 100 can correspond to the EWA result data EWA(1.1) located at the intersection of the first row R(1) and the first column C(1) of the result matrix 430 shown in FIG. 4B. Figure 10

[0094] Figure 12 FIG. 4B illustrates an accumulation calculation performed in a third operation mode of the multiple operation circuit 100 shown in FIG. 4A. Figure 1 In the third operation mode of the multiple operation circuit 100, the accumulation calculation can be performed when some data is latched in the latch circuit 140. In one embodiment, in order to latch some data by the latch circuit 140, the MAC operation described with reference to Figure 6 Figure 7 The MAC operation described with reference to FIGS. 3A and 3B can be performed in advance in the first operation mode of the multiple operation circuit 100. This embodiment will be described in connection with a case where the MAC operation performed in the first operation mode of the multiple operation circuit 100 generates the weight data W(1.2) located at the intersection of the first row RW(1) and the second column CW(2) of the weight matrix 210 shown in FIG. 4A and the vector data V(2) in the second row RV(2) of the vector matrix 220 shown in FIG. 4A. Figure 5 Figure 5 The MAC operation described with reference to FIGS. 3A and 3B can be performed in advance in the first operation mode of the multiple operation circuit 100. This embodiment will be described in connection with a case where the MAC operation performed in the first operation mode of the multiple operation circuit 100 generates the weight data W(1.2) located at the intersection of the first row RW(1) and the second column CW(2) of the weight matrix 210 shown in FIG. 4A and the vector data V(2) in the second row RV(2) of the vector matrix 220 shown in FIG. 4A.

[0095] Referring to FIG. 4B, the multiple operation circuit 100 can perform the accumulation calculation in the third operation mode. Figure 12 ​​​corresponding to the first result data IY-1 can be transmitted to the first input end IN11 of the first selector 121. The first selector 121 can output the first multiplication result data WV1[15:0] through the output end OUT1 in response to the first selection signal SS1 having the logic "low (LO)" level. The first multiplication result data WV1[15:0] output from the first selector 121 can be transmitted to the second input end IN22 of the second selector 122. The latching circuit 140 can output the second multiplication result data WV2[15:0] latched in the latching circuit 140 through the output end Q in synchronization with the rising edge of the update signal UPDATE. The second multiplication result data WV2[15:0] output from the latching circuit 140 can be fed back to the second input end IN32 of the third selector 123. In addition, the second multiplication result data WV2[15:0] output from the latching circuit 140 can be output from the multiple operation circuit 100 to provide the operation result data Y[15:0].

[0096] corresponding to the first result data IY-1 can be transmitted to the first input end IN11 of the first selector 121. The first selector 121 can output the first multiplication result data WV1[15:0] through the output end OUT1 in response to the first selection signal SS1 having the logic "low (LO)" level. The first multiplication result data WV1[15:0] output from the first selector 121 can be transmitted to the second input end IN22 of the second selector 122. The latching circuit 140 can output the second multiplication result data WV2[15:0] latched in the latching circuit 140 through the output end Q in synchronization with the rising edge of the update signal UPDATE. The second multiplication result data WV2[15:0] output from the latching circuit 140 can be fed back to the second input end IN32 of the third selector 123. In addition, the second multiplication result data WV2[15:0] output from the latching circuit 140 can be output from the multiple operation circuit 100 to provide the operation result data Y[15:0].

[0097] When the second selection signal SS2 having a logic "high (HI)" level is transmitted to the selection terminal S2 of the second selector 122, the second selector 122 can output the first multiplication result data WV1[15:0] input to the second input terminal IN22 of the second selector 122 through the output terminal OUT2. The first multiplication result data WV1[15:0] output from the second selector 122 can be transmitted to the first input terminal of the adder 130. When the second selection signal SS2 having a logic "high (HI)" level is transmitted to the selection terminal S3 of the third selector 123, the third selector 123 can output the second multiplication result data WV2[15:0] input to the second input terminal IN32 of the third selector 123 through the output terminal OUT3. The second multiplication result data WV2[15:0] output from the third selector 123 can be transmitted to the second input terminal of the adder 130.

[0098] The adder 130 can perform an addition calculation for adding the first multiplication result data WV1[15:0] input to the first input terminal of the adder 130 to the second multiplication result data WV2[15:0] input to the second input terminal of the adder 130, thereby generating second MAC data MAC2[15:0]. The second MAC data MAC2[15:0] generated by the adder 130 can be output from the multiple operation circuit 100 through the first output line 161 to provide second result data IY[15:0]. As described with reference to Figure 5 The second MAC data MAC2[15:0] output from the multiple operation circuit 100 through the first output line 161 can have the same value as data generated by the second MAC operation.

[0099] Figure 13 FIG. 1 illustrates a configuration of a multiple operation circuit 100 according to an embodiment of the disclosure. Referring to FIG. 1, the multiple operation circuit 100 can include a multiplier 110, first to fourth selectors 121 to 124, an adder 130, a latch circuit 140, and an inverter 150. Figure 13 The first to fourth selectors 121 to 124, the adder 130, the latch circuit 140, and the inverter 150 of the multiple operation circuit 100 can have substantially the same configurations as those of the first to fourth selectors 121 to 124, the adder 130, the latch circuit 140, and the inverter 150 of the multiple operation circuit 100 described with reference to FIG. 1, respectively. Therefore, the same descriptions as those set forth in the embodiment of FIG. 1 will be omitted hereinafter. Figure 1 Figure 1 The multiplier 110 can be different from the multiplier 110 described with reference to FIG. 1 in that the multiplier 110 does not perform a normalization process.

[0100] The multiplier 110 can be different from the multiplier 110 described with reference to FIG. 1 in that the multiplier 110 does not perform a normalization process. Figure 2 ​The multiplier 110 described above. Specifically, when the first input data A[15:0] and the second input data B[15:0] having the 16-bit floating-point format are input to the multiply-accumulate circuit 500, the multiplier 510 can perform a multiplication calculation on the first input data A[15:0] and the second input data B[15:0]. The multiplier 510 can generate and output the multiplied result data AB[24:0] as a result of the multiplication calculation. Since the multiplier 510 does not perform a normalization process, the multiplied result data AB[24:0] output from the multiplier 510 can have a 25-bit floating-point format. Therefore, all of the multiplied result data AB[24:0], the feedback data DF[24:0] transferred to the second input terminal IN32 of the third selector 523, and the MAC data MAC[24:0] output from the adder 530 and the latch circuit 540 can have a 25-bit floating-point format. The 25-bit MAC data MAC[24:0] can be normalized to have a 16-bit floating-point format by the normalizer 570, and the normalized MAC data MAC[15:0] having the 16-bit floating-point format can be output from the normalizer 570 to provide the 16-bit result data Y[15:0].

[0101] Figure 14 FIG. 13 illustrates a configuration of the multiply-accumulate circuit 500 included in the multiply-accumulate circuit 500 shown in FIG. 12. Figure 13 An example of a configuration of the multiplier 510 included in the multiply-accumulate circuit 500 shown in FIG. 12 is described. In the present embodiment, it can be assumed that the first input data A[15:0] and the second input data B[15:0] both have a 16-bit brain floating-point (BF16) format. Therefore, the first input data A[15:0] can be composed of first sign data S1[0] having 1 bit, first exponent data E1[7:0] having 8 bits, and first mantissa data M1[6:0] having 7 bits. In addition, the second input data B[15:0] can be composed of second sign data S2[0] having 1 bit, second exponent data E2[7:0] having 8 bits, and second mantissa data M2[6:0] having 7 bits. As described with reference to FIG. 11, the multiplied result data AB[24:0] output from the multiplier 510 can have a 25-bit floating-point format. In the following, it can be assumed that the multiplied result data AB[24:0] is composed of fifth sign data S5[0] having 1 bit, fifth exponent data E5[7:0] having 8 bits, and fifth mantissa data M5[15:0] having 16 bits. Figure 13

[0102] Referring to FIG. 13, Figure 14 ​The multiplier 510 can include a sign processing circuit 510S, an exponent processing circuit 510E, and a mantissa processing circuit 510M. The sign processing circuit 510S can include an exclusive OR (XOR) gate 511. The XOR gate 511 can receive first sign data S1[0] of the first input data A[15:0] and second sign data S2[0] of the second input data B[15:0]. When only one of the first sign data S1[0] and the second sign data S2[0] has a binary number "1" representing a negative number, the XOR gate 511 can output the binary number "1" representing the negative number. Conversely, when the first sign data S1[0] and the second sign data S2[0] both have a binary number "0" representing a positive number or a binary number "1" representing a negative number, the XOR gate 511 can output a binary number "0" representing the positive number. The output data of the XOR gate 511 can correspond to fifth sign data S5[0] of the 25-bit multiplication result data AB[24:0].

[0103] The exponent processing circuit 510E can include a first exponent adder 512 and a second exponent adder 513. The first exponent adder 512 can receive first exponent data E1[7:0] of the first input data A[15:0] and second exponent data E2[7:0] of the second input data B[15:0]. The first exponent adder 512 can add the first exponent data E1[7:0] and the second exponent data E2[7:0] to generate and output addition result data. The first exponent data E1[7:0] can have an exponent bias value corresponding to the decimal number "127" and a value of original data of the first exponent data E1[7:0] added, and the second exponent data E2[7:0] can also have an exponent bias value corresponding to the decimal number "127" and a value of original data of the second exponent data E2[7:0] added. Therefore, to obtain an exponent including the exponent bias value, the second exponent adder 513 can perform addition to add a negative exponent bias value corresponding to the decimal number "-127" to the addition result data output from the first exponent adder 512 to subtract the decimal number "127" from the addition result data output from the first exponent adder 512. The addition result data output from the second exponent adder 513 can correspond to fifth exponent data E5[7:0] of the 25-bit multiplication result data AB[24:0].

[0104] The mantissa processing circuit 510M may include a mantissa multiplier 514. The mantissa multiplier 514 may receive first mantissa data M1[7:0] of first input data A[15:0] and second mantissa data M2[7:0] of second input data B[15:0]. The first mantissa data M1[7:0] can be provided in an 8-bit form having "1.M1[6:0]" by adding an implicit bit IB "1" to the first mantissa data M1[6:0], and can be input to the mantissa multiplier 514. Similarly, the second mantissa data M2[7:0] can also be provided in an 8-bit form having "1.M2[6:0]" by adding an implicit bit IB "1" to the second mantissa data M2[6:0], and can be input to the mantissa multiplier 514. The mantissa multiplier 514 can perform a multiplication calculation on the first mantissa data M1[7:0] with 8 bits and the second mantissa data M2[7:0] with 8 bits. The mantissa multiplier 514 can output 16 bits as the result of the multiplication calculation. The 16 bits output from the mantissa multiplier 514 can correspond to the fifth mantissa data M5[15:0], which has 16 bits included in the multiplication result data AB[24:0] with 25-bit floating-point format. Since the multiplier 510 does not perform normalization processing, the floating-point number of the fifth mantissa data M5[15:0] included in the multiplication result data AB[24:0] can be located between the fourteenth bit M5

[13] and the fifteenth bit M5

[14] of the fifth mantissa data M5[15:0].

[0105] Figure 15 The illustration shows the included Figure 13 An example of the normalizer 570 in the multi-operation circuit 500 is shown. See also... Figure 15 Normalizer 570 can receive MAC data MAC[24:0] in 25-bit floating-point format and can normalize the MAC data MAC[24:0]. In the multiplication circuit, the MAC data MAC[24:0] can have the same format as the multiplication result data AB[24:0] output from multiplier 510. Therefore, as referenced... Figure 14As described, the MAC data MAC[24:0] input to the normalizer 570 can consist of a 1-bit sixth symbolic data S6[0], an 8-bit sixth exponentic data E6[7:0], and a 16-bit sixth mantissa data M6[15:0]. The normalizer 570 can normalize the MAC data MAC[24:0] to generate and output result data Y[15:0] in 16-bit Brain Floating-Point (BF16) format. Therefore, the result data Y[15:0] output from the normalizer 570 can consist of a 1-bit seventh symbolic data S7[0], an 8-bit seventh exponentic data E7[7:0], and a 7-bit seventh mantissa data M7[6:0]. In the normalizer 570, the sixth symbolic data S6[0] of the MAC data MAC[24:0] is not normalized. Therefore, the sixth symbol data S6[0] can be output from the normalizer 570 without any data change, to provide the seventh symbol data S7[0] result data Y[15:0].

[0106] The normalizer 570 may include: a floating-point shifter 571, a multiplexer 572, a rounding processor 573, and an adder 574. The floating-point shifter 571 can draw data from a latch circuit (…). Figure 13 540) receives 16 bits of sixth mantissa data M6[15:0]. Floating-point shifter 571 can shift the binary floating-point of the sixth mantissa data M6[15:0] by one bit towards the most significant bit (MSB) of the sixth mantissa data M6[15:0] to generate and output the sixth mantissa data with the shifted binary floating-point number. Specifically, because the MAC data MAC[24:0] has a reference Figure 14The multiplication result data AB[24:0] output from the multiplier 510 is in the same format, so the binary floating point of the sixth mantissa data M6[15:0] can also be located between the fourteenth bit M6

[13] and the fifteenth bit M6

[14] of the sixth mantissa data M6[15:0]. Therefore, the two bits including the MSB of the sixth mantissa data M6[15:0] (i.e., the fifteenth bit M6

[14] and the MSB M6

[15] ) can be located to the left of the binary floating point of the sixth mantissa data M6[15:0]. The floating point shifter 571 can shift the binary floating point of the sixth mantissa data M6[15:0] so that the binary floating point of the sixth mantissa data M6[15:0] is located between the fifteenth bit M6

[14] and the MSB M6

[15] of the sixth mantissa data M6[15:0]. When the MSB M6

[15] of the sixth mantissa data M6[15:0] has a binary number "1", the data generated by the floating point shifter 571 can have the form of "1.M6[14:0]" including an implicit bit. However, when the MSB M6

[15] of the sixth mantissa data M6[15:0] has a binary number "0", the data generated by the floating point shifter 571 can have the form of "0.M6[14:0]" without an implicit bit. The data having the binary floating point shifted by the floating point shifter 571 can be transferred to the first input IN1 of the multiplexer 572.

[0107] The multiplexer 572 can receive data having a binary floating point shifted by the floating point shifter 571 through a first input IN1 of the multiplexer 572. Also, the multiplexer 572 can receive sixth mantissa data M6[15:0] of the MAC data MAC[24:0] through a second input IN2 of the multiplexer 572. Also, the multiplexer 572 can receive MSB data M6

[15] of the sixth mantissa data M6[15:0] through a selection terminal of the multiplexer 572. When the MSB M6

[15] of the sixth mantissa data M6[15:0] has a binary number "1" corresponding to a logical "high" level, the multiplexer 572 can output data input to the first input IN1 (i.e., 16-bit data having a "1.M6[14:0]" format including an implicit bit). When the MSB M6

[15] of the sixth mantissa data M6[15:0] has a binary number "0" corresponding to a logical "low" level, the multiplexer 572 can output the sixth mantissa data M6[15:0] input to the second input IN2. When the MSB M6

[15] of the sixth mantissa data M6[15:0] has a binary number "0", the sixth mantissa data M6[15:0] output from the multiplexer 572 can have a "01.M6[13:0]" format. In this case, data having a "1.M6[14:0]" format including an implicit bit can be obtained by removing the MSB M6

[15] of the sixth mantissa data M6[15:0] having a logical "low (0)" level from the sixth mantissa data M6[15:0] having a "01.M6[13:0]" format.

[0108] The rounding processor 573 can receive 16-bit data from the multiplexer 572. The rounding processor 573 can remove 9 bits including an implicit bit from the 16-bit output of the multiplexer 572 to generate 7-bit data, and can perform a rounding operation while removing the 9 bits including the implicit bit from the 16-bit data. During the rounding operation, an addition calculation of adding a value "1" can be performed by a rounding down operation or a rounding up operation. The rounding processor 573 can generate and output seventh mantissa data M7[6:0] having 7 bits included in the result data Y[15:0] as a result of the operation for adjusting the number of bits and the rounding operation.

[0109] The adder 574 can receive the sixth exponent data E6[7:0] and the MSB data M6

[15] of the sixth mantissa data M6[15:0] having 8 bits of the MAC data MAC[24:0]. The adder 574 can perform an addition calculation on the sixth exponent data E6[7:0] and the MSB data M6

[15] of the sixth mantissa data M6[15:0]. When the MSB data M6

[15] of the sixth mantissa data M6[15:0] has a binary number "0", the adder 574 can output the same data as the sixth exponent data E6[7:0]. When the MSB data M6

[15] of the sixth mantissa data M6[15:0] has a binary number "1", the adder 574 can output data generated by adding 1 to the sixth exponent data E6[7:0]. As described above, when the MSB data M6

[15] of the sixth mantissa data M6[15:0] has a binary number "1", the multiplexer 572 can output data generated by shifting the binary floating point number of the sixth mantissa data M6[15:0] by one bit to the most significant bit (MSB) of the sixth mantissa data M6[15:0]. Accordingly, in this case, the change in the exponent due to the shift of the binary floating point can be compensated for by adding 1 to the sixth exponent data E6[7:0] input to the adder 574. The 8-bit output data of the adder 574 can provide the seventh exponent data E7[7:0] having 8 bits included in the result data Y[15:0].

[0110] Figure 16 FIG. 1 illustrates a MAC operator 600 according to an embodiment of the disclosure. Referring to FIG. 1, Figure 16 The MAC operator 600 can receive "N" first input data A(1) ~ A(N) and "N" second input data B(1) ~ B(N). The MAC operator 600 can also receive various control signals, such as a first selection signal SS1, a second selection signal SS2, a third selection signal SS3, and an update signal UPDATE. The MAC operator 600 can output an Nth second result data IY(N-1) and "N" operation result data (i.e., first operation result data to Nth operation result data Y(0) ~ Y(N-1)).

[0111] The MAC operator 600 can include "N" multiple operation circuits (MOC(0) ~ MOC(N-1)) (i.e., first multiple operation circuit to Nth multiple operation circuit 610(0) ~ 610(N-1)). Each of the first multiple operation circuit to Nth multiple operation circuit 610(0) ~ 610(N-1) constituting the MAC operator 600 can have substantially the same configuration as the multiple operation circuit 100 described with reference to FIG. 1. Accordingly, the first multiple operation circuit to Nth multiple operation circuit 610(0) ~ 610(N-1) will not be described in detail. Figure 1 The MAC operator 600 can include "N" multiple operation circuits (MOC(0) ~ MOC(N-1)) (i.e., first multiple operation circuit to Nth multiple operation circuit 610(0) ~ 610(N-1)). Each of the first multiple operation circuit to Nth multiple operation circuit 610(0) ~ 610(N-1) constituting the MAC operator 600 can have substantially the same configuration as the multiple operation circuit 100 described with reference to FIG. 1. Accordingly, the first multiple operation circuit to Nth multiple operation circuit 610(0) ~ 610(N-1) will not be described in detail. Figure 1The configuration and operation of the described multiple operation circuit 100 can be equally applied to each of the first to Nth multiple operation circuits 610(0)~610(N-1). Therefore, the description of the configuration and operation of each of the first to Nth multiple operation circuits 610(0)~610(N-1) will be omitted below to avoid repetitive explanation.

[0112] The first to third selection signals SS1, SS2, and SS3 and the update signal UPDATE input to the MAC operator 600 can be transferred to each of the first to Nth multiple operation circuits 610(0)~610(N-1). Also, the "N" first input data A(1)~A(N) can be transferred to a corresponding one of the first to Nth multiple operation circuits 610(0)~610(N-1), and the "N" second input data B(1)~B(N) can also be transferred to a corresponding one of the first to Nth multiple operation circuits 610(0)~610(N-1). For example, the first data A(1) of the first input data A(1)~A(N) and the first data B(1) of the second input data B(1)~B(N) can be transferred to the first multiple operation circuit 610(0), and the second data A(2) of the first input data A(1)~A(N) and the second data B(2) of the second input data B(1)~B(N) can be transferred to the second multiple operation circuit 610(1). Similarly, the Nth data A(N) of the first input data A(1)~A(N) and the Nth data B(N) of the second input data B(1)~B(N) can be transferred to the Nth multiple operation circuit 610(N-1). The first input data A(1)~A(N) and the second input data B(1)~B(N) can have different data formats according to the calculation performed with the first input data A(1)~A(N) and the second input data B(1)~B(N) as input data, as described with reference to Figure 1

[0113] ​Each of the first through Nth multiple operation circuits 610(0)-610(N-1) can receive the first result data IY-1 to generate and output second result data IY. For example, the first multiple operation circuit 610(0) can receive a first data IY-1(0) of the first result data IY-1 to generate and output a first data IY(0) of the second result data IY. In one embodiment, the first data IY-1(0) of the first result data IY-1 input to the first multiple operation circuit 610(0) can be fixed to have a value of "0". The first multiple operation circuit 610(0) corresponds to a first one of the first through Nth multiple operation circuits 610(0)-610(N-1). In another embodiment, the first data IY-1(0) of the first result data IY-1 input to the first multiple operation circuit 610(0) can be provided by an external device coupled to the MAC operator 600 each time the first multiple operation circuit 610(0) requests the first data IY-1(0). The second multiple operation circuit 610(1) can receive a second data IY-1(1) of the first result data IY-1 to generate and output a second data IY(1) of the second result data IY. Similarly, the Nth multiple operation circuit 610(N-1) can receive an Nth data IY-1(N-1) of the first result data IY-1 to generate and output an Nth data IY(N-1) of the second result data IY. The Nth data IY(N-1) of the second result data IY output from the Nth multiple operation circuit 610(N-1) can be output from the MAC operator 600. The Nth multiple operation circuit 610(N-1) corresponds to a last one of the first through Nth multiple operation circuits 610(0)-610(N-1).

[0114] The first through Nth operation result data Y(0)-Y(N-1) output from the MAC operator 600 can be output from the first through Nth multiple operation circuits 610(0)-610(N-1), respectively. That is, the operation result data Y generated by the first through Nth multiple operation circuits 610(0)-610(N-1) can be output from the MAC operator 600. The first multiple operation circuit 610(0) can output the first operation result data Y(0), and the second multiple operation circuit 610(1) can output the second operation result data Y(1). Similarly, the Nth multiple operation circuit 610(N-1) can output the Nth operation result data Y(N-1).

[0115] The first to Nth multiple operation circuits 610(0) to 610(N-1) can be connected in series, such that the output line of the (i-1)th multiple operation circuit is coupled to the input line of the i-th multiple operation circuit (where "i" is one of the natural numbers from "1" to "N"). Therefore, the second result data IY output from the (i-1)th multiple operation circuit can be the first result data IY-1 input to the i-th multiple operation circuit. Specifically, the first data IY(0) of the second result data IY output through the output line of the first operation circuit 610(0) can correspond to the second data IY-1(1) of the first result data IY-1 input to the second operation circuit 610(1) via the input line of the second operation circuit 610(1). In addition, the second data IY(1) of the second result data IY output through the output line of the second operation circuit 610(1) can correspond to the second data IY-1(1) input to the third operation circuit via the input line of the third operation circuit. Figure 16 The first result data IY-1 (omitted) is the third data IY-1(2).

[0116] Through the (N-2)th operational circuit ( Figure 16 The (N-2)th data IY(N-3) of the second result data IY output through the output line of the (N-1)th arithmetic circuit 610(N-2) can correspond to the (N-1)th data IY-1(N-2) of the first result data IY-1 input to the (N-1)th arithmetic circuit 610(N-2) through the input line of the (N-1)th arithmetic circuit 610(N-2). Furthermore, the (N-1)th data IY(N-2) of the second result data IY output through the output line of the (N-1)th arithmetic circuit 610(N-2) can correspond to the Nth data IY-1(N-1) of the first result data IY-1 input to the Nth arithmetic circuit 610(N-1) through the input line of the Nth arithmetic circuit 610(N-1). The Nth data IY(N-1) of the second result data IY output through the output line of the Nth arithmetic circuit 610(N-1) can be output from the MAC arithmetic unit 600.

[0117] The MAC arithmetic unit 600 can selectively perform MAC operations in the first operation mode, EW multiplication and EW addition calculations in the second operation mode, or accumulation calculations in the third operation mode. The operation or calculation performed by the MAC arithmetic unit 600 can be selected by the first selection signal SS1, the second selection signal SS2, the third selection signal SS3, and the update signal UPDATE. When the first selection signal SS1 and the second selection signal SS2, which have a logic "high (HI)" level, and the third selection signal SS3, which has a logic "low (LO)" level, are transmitted to the MAC arithmetic unit 600, the MAC arithmetic unit 600 can perform operations as referenced. Figure 6 and Figure 7The MAC operation in the first operation mode is performed as in the described multiple operation circuit 100.

[0118] When the first selection signal SS1 and the third selection signal SS3 having a logic "high (HI)" level are transmitted to the MAC operator 600 and the second selection signal SS2 is deactivated, the MAC operator 600 can perform the EW multiplication calculation in the second operation mode as in the described multiple operation circuit 100. Figure 9 The MAC operation in the first operation mode is performed as in the described multiple operation circuit 100. Figure 11 The MAC operation in the first operation mode is performed as in the described multiple operation circuit 100. Figure 12 The MAC operation in the first operation mode is performed as in the described multiple operation circuit 100.

[0119] When the MAC operator 600 performs the MAC operation in the first operation mode, the MAC operation can be performed in the first MAC operation mode or the second MAC operation mode. The MAC operation in the first MAC operation mode or the MAC operation in the second MAC operation mode can be selected according to a manner in which the weight data and the vector data are input to the first multiple operation circuit to the Nth multiple operation circuit 610(0)~610(N-1). When the MAC operator 600 performs the MAC operation in the first MAC operation mode, the MAC operator 600 can output the MAC result data MAC_RST located in one of the rows of the result matrix 230 as shown in FIG. 7. In this case, the Nth data IY(N-1) of the second result data IY output from the Nth multiple operation circuit 610(N-1) can correspond to the MAC result data MAC_RST. When the MAC operator 600 performs the MAC operation in the second MAC operation mode, the MAC operator 600 can output the MAC result data MAC_RST located in one of the columns of the result matrix 230 as shown in FIG. 7. In this case, the Nth data IY(N-1) of the second result data IY output from the Nth multiple operation circuit 610(N-1) can correspond to the MAC result data MAC_RST. Figure 4 The MAC operation in the first operation mode is performed as in the described multiple operation circuit 100. Figure 4The illustrated result matrix 230 includes a plurality of sets of MAC result data (e.g., first MAC result data to Mth MAC result data MAC_RST(1) ~ MAC_RST(M)). In this case, the first operation result data to the Nth operation result data Y(0) ~ Y(N-1) output from the respective one of the first multiple operation circuit to the Nth multiple operation circuit 610(0) ~ 610(N-1) can correspond to the first MAC result data to the Mth MAC result data MAC_RST(1) ~ MAC_RST(M), respectively. Any one of the first MAC result data to the Mth MAC result data MAC_RST(1) ~ MAC_RST(M) can be data generated by a matrix-vector multiplication calculation performed using the weight data arranged in any one row of the weight matrix and the vector data of the vector matrix as input data.

[0120] Figure 17 The MAC operation performed in the first MAC operation mode of the MAC operator 600 is illustrated. Figure 16 The same reference numerals or symbols used in Figure 17 The same reference numerals or symbols used in Figure 16 The same reference numerals or symbols used in Figure 4 The MAC operation in the matrix-vector multiplication calculation described with reference to

[0121] The MAC operation in the matrix-vector multiplication calculation described with reference to Figure 17The MAC operator 600 can receive the weight data W(1.1) ~ W(1.N) in the first row CR(1) of the weight matrix 210 and the vector data V(1) ~ V(N) of the vector matrix 220. To make the MAC operator 600 perform the MAC operation in the first MAC operation mode, the "N" sets of weight data W(1.1) ~ W(1.N) can be transferred to a corresponding one of the first multiple operation circuit to the Nth multiple operation circuit 610(0) ~ 610(N-1). The "N" sets of vector data V(1) ~ V(N) can also be transferred to the first multiple operation circuit to the Nth multiple operation circuit 610(0) ~ 610(N-1), respectively. For example, the weight data W(1.1) located at the intersection of the first row RW(1) and the first column CW(1) of the weight matrix 210 and the vector data V(1) in the first row RV(1) of the vector matrix 220 can be transferred to the first multiple operation circuit 610(0). In addition, the weight data W(1.2) located at the intersection of the first row RW(1) and the second column CW(2) of the weight matrix 210 and the vector data V(2) in the second row RV(2) of the vector matrix 220 can be transferred to the second multiple operation circuit 610(1). Similarly, the weight data W(1.N) located at the intersection of the first row RW(1) and the Nth column CW(N) of the weight matrix 210 and the vector data V(N) in the Nth row RV of the vector matrix 220 can be transferred to the Nth multiple operation circuit 610(N-1).

[0122] First, the first selection signal SS1 and the second selection signal SS2 having a logic "high (HI)" level, the third selection signal SS3 having a logic "low (LO)" level, and an update signal UPDATE for a latch operation can be transferred to the MAC operator 600, so that the first multiple operation circuit to the Nth multiple operation circuit 610(0) ~ 610(N-1) of the MAC operator 600 performs the MAC operation in the first operation mode. The first multiple operation circuit 610(0) can perform a multiplication calculation on the weight data W(1.1) and the vector data V(1) to generate first multiplication result data WV(1), as described with reference to FIG. 2. Figure 6 The first multiple operation circuit 610(0) can latch the first multiplication result data WV(1) in the latch circuit 140 included in the first multiple operation circuit 610(0). Figure 6

[0123] ​The operation, substantially the same as the MAC operation performed in the first operation mode of the first multi-operation circuit 610(0), can be performed in each of the second to Nth multi-operation circuits 610(1) to 610(N-1). Therefore, the second multi-operation circuit 610(1) can perform a multiplication operation on the weight data W(1,2) and the vector data V(2) to generate a second multiplication result data WV(2), and can latch the second multiplication result data WV(2) into a latch circuit included in the second multi-operation circuit 610(1). Figure 6 In 140). Furthermore, the (N-1)th multiplication circuit 610 (N-2) can perform a multiplication calculation on the weight data W(1.(N-1)) and the vector data V(N-1) to generate the (N-1)th multiplication result data WV(N-1), and can latch the (N-1)th multiplication result data WV(N-1) into a latch circuit included in the (N-1)th multiplication circuit 610 (N-2). Figure 6 In 140). Similarly, the Nth multiple operation circuit 610 (N-1) can perform multiplication calculation on the weight data W (1.N) and the vector data V (N) to generate the Nth multiplication result data WV (N), and can latch the Nth multiplication result data WV (N) in the latch circuit included in the Nth multiple operation circuit 610 (N-1). Figure 6 (of 140).

[0124] Next, the first selection signal SS1 with a logic "low (LO)" level, the second selection signal SS2 with a logic "high (HI)" level, and the update signal UPDATE for latching operations can be transmitted to the MAC arithmetic unit 600, while the third selection signal SS3 is deactivated. As a result, the first multi-operation circuit to the Nth multi-operation circuit 610(0) to 610(N-1) of the MAC arithmetic unit 600 can perform the accumulation calculation in the third operation mode. The first multi-operation circuit 610(0) can receive the first result data IY-1(0) with a zero value. The first multi-operation circuit 610(0) can perform an addition calculation on the first result data IY-1(0) with a zero value and the first multiplication result data WV(1) latched in the first multi-operation circuit 610(0) to generate the first MAC data MAC(1), and can output the first MAC data MAC(1) as the first data IY(0) of the second result data IY.

[0125] The second multiple operation circuit 610(1) can receive the first MAC data MAC(1) output from the first multiple operation circuit 610(0) as the second data IY-1(1) of the first result data IY-1. The second multiple operation circuit 610(1) can perform an addition calculation on the first MAC data MAC(1) and the second multiplication result data WV(2) which is locked in the second multiple operation circuit 610(1) to generate second MAC data MAC(2), and can output the second MAC data MAC(2) as the second data IY(1) of the second result data IY.

[0126] The (N-1)th multiple operation circuit 610(N-2) can receive the (N-2)th MAC data MAC(N-2) output from the (N-2)th multiple operation circuit 610(N-2) (omitted in the middle) as the (N-1)th data IY-1(N-2) of the first result data IY-1. The (N-1)th multiple operation circuit 610(N-2) can perform an addition calculation on the (N-2)th MAC data MAC(N-2) and the (N-1)th multiplication result data WV(N-1) which is locked in the (N-1)th multiple operation circuit 610(N-2) to generate (N-1)th MAC data MAC(N-1), and can output the (N-1)th MAC data MAC(N-1) as the (N-1)th data IY(N-2) of the second result data IY. Figure 17

[0127] The Nth multiple operation circuit 610(N-1) can receive the (N-1)th MAC data MAC(N-1) output from the (N-1)th multiple operation circuit 610(N-2) as the Nth data IY-1(N-1) of the first result data IY-1. The Nth multiple operation circuit 610(N-1) can perform an addition calculation on the (N-1)th MAC data MAC(N-1) and the Nth multiplication result data WV(N) which is locked in the Nth multiple operation circuit 610(N-1) to generate Nth MAC data MAC(N), and can output the Nth MAC data MAC(N) as the Nth data IY(N-1) of the second result data IY. The Nth MAC data MAC(N) output from the Nth multiple operation circuit 610(N-1) corresponding to the Nth data IY(N-1) of the second result data IY can be first MAC result data MAC_RST(1) generated by a matrix-vector multiplication calculation of weight data W(1.1) ~ W(1.N) in the first row RW(1) of the weight matrix 210 and vector data V(1) ~ V(N) of the vector matrix 220, as described with reference to Figure 4 and Figure 5 .

[0128] ​Figure 18 illustrates Figure 16 The MAC operator 600 shown performs a MAC operation in a second MAC operation mode. In Figure 18 In the matrix-vector multiplication calculation described with reference to Figure 16 The same reference numerals or symbols used in Figure 4 This embodiment will be described in connection with the MAC operation in the matrix- vector multiplication calculation described with reference to the first embodiment, which is performed using the weight matrix 210 and the vector matrix 220 as input data to generate the result matrix 230. In this case, it can be assumed that the MAC operator 600 includes the same number of multiple operation circuits 610(0)~610(M-1) as the number of rows RW of the weight matrix 210. That is, the number of the multiple operation circuits 610(0)~610(M-1) can be equal to the number of rows of the weight matrix 210. Each of the first to Mth multiple operation circuits 610(0)~610(M-1) can perform the MAC operation in the first operation mode repeatedly the same number of times as the number of columns CW of the weight matrix 210, which corresponds to the number of rows RV of the vector matrix 220, to thereby perform the MAC operation in the second MAC operation mode of the MAC operator 600.

[0129] Referring to Figure 18In the second MAC operation mode, the MAC operator 600 can sequentially receive the weight data W(l.l)~W(l.N),..., and W(M.l)~W(M.N) arranged in all the rows RW(l)~RW(M) of the weight matrix 210 and the vector data V(l)~V(N) of the vector matrix 220. In order for the MAC operator 600 to perform the MAC operation in the second MAC operation mode, the "N" groups of weight data W arranged in one of the rows of the weight matrix 210 can be sequentially transferred to the first multiple operation circuit to the Mth multiple operation circuit 610(0)~610(M-l), and the "N" groups of vector data V(l)~V(N) of the vector matrix 220 can also be sequentially transferred to the first multiple operation circuit to the Mth multiple operation circuit 610(0)~610(M-l). For example, the weight data W(l.l)~W(l.N) arranged in the first row RW(l) of the weight matrix 210 can be sequentially transferred to the first multiple operation circuit 610(0), and the vector data V(l)~V(N) of the vector matrix 220 can also be sequentially transferred to the first multiple operation circuit 610(0). In addition, the weight data W(2.l)~W(2.N) arranged in the second row RW(2) of the weight matrix 210 can be sequentially transferred to the second multiple operation circuit 610(l), and the vector data V(l)~V(N) of the vector matrix 220 can also be sequentially transferred to the second multiple operation circuit 610(l). Similarly, the weight data W((M-l).l)~W((M-l).N) arranged in the (M-l)th row RW(M-l) of the weight matrix 210 can be sequentially transferred to the (M-l)th multiple operation circuit 610(M-2), and the vector data V(l)~V(N) of the vector matrix 220 can also be sequentially transferred to the (M-l)th multiple operation circuit 610(M-2). Finally, the weight data W(M.l)~W(M.N) arranged in the Mth row RW(M) of the weight matrix 210 can be sequentially transferred to the Mth multiple operation circuit 610(M-l), and the vector data V(l)~V(N) of the vector matrix 220 can also be sequentially transferred to the Mth multiple operation circuit 610(M-l).

[0130] First, the first selection signal SS1 and the second selection signal SS2 having a logic "high (HI)" level, the third selection signal SS3 having a logic "low (LO)" level, and an update signal UPDATE for a latch operation can be transferred to the MAC operator 600 so that the first multiple operation circuits to the Mth multiple operation circuits 610(0) to 610(M-1) of the MAC operator 600 perform a MAC operation in a first operation mode. When the weight data W(1.1), W(2.1), …, W((M-1).1), and W(M.1) arranged in a first column CW(1) of the weight matrix 210 are transferred to a corresponding one of the first multiple operation circuits to the Mth multiple operation circuits 610(0) to 610(M-1), and the vector data V(1) in a first row RV(1) of the vector matrix 220 is transferred to each of the first multiple operation circuits to the Mth multiple operation circuits 610(0) to 610(M-1), each of the first multiple operation circuits to the Mth multiple operation circuits 610(0) to 610(M-1) can perform a first MAC operation in the first operation mode. The first MAC operation performed in the first operation mode can be the same as the first MAC operation described with reference to Figure 5 and Figure 6 Each of the multiple operation circuits 610(0) to 610(M-1) can perform the first MAC operation in the first operation mode to generate first MAC data MAC1[15:0] of one of the rows of the weight matrix 210. The "M" sets of the first MAC data MAC1[15:0] generated by the multiple operation circuits 610(0) to 610(M-1) can be latched in the latch circuits included in the corresponding one of the multiple operation circuits 610(0) to 610(M-1).

[0131] Next, when the weight data W(1.2), W(2.2), …, W((M-1).2), and W(M.2) arranged in a second column CW(2) of the weight matrix 210 are transferred to a corresponding one of the first multiple operation circuits to the Mth multiple operation circuits 610(0) to 610(M-1), and the vector data V(2) in a second row RV(2) of the vector matrix 220 is transferred to each of the first multiple operation circuits to the Mth multiple operation circuits 610(0) to 610(M-1), each of the first multiple operation circuits to the Mth multiple operation circuits 610(0) to 610(M-1) can perform a second MAC operation in the first operation mode. The second MAC operation performed in the first operation mode can be the same as the second MAC operation described with reference to Figure 5 and Figure 7The second MAC operation described is the same. Each of the multiple operation circuits 610(0) ~ 610(M-1) can perform the second MAC operation in the first operation mode to generate the second MAC data MAC2[15:0] of one of the rows of the weight matrix 210. The "M" sets of the second MAC data MAC2[15:0] generated by the multiple operation circuits 610(0) ~ 610(M-1) can be latched in the latching circuits included in the respective ones of the multiple operation circuits 610(0) ~ 610(M-1). Subsequently, when the weight data W(l.3), W(2.3),..., W((M-1).3), and W(M.3) arranged in the third column CW(3) of the weight matrix 210 are transferred to the respective ones of the first multiple operation circuit to the Mth multiple operation circuit 610(0) ~ 610(M-1), and the vector data V(3) in the third row RV(3) of the vector matrix 220 are transferred to each of the first multiple operation circuit to the Mth multiple operation circuit 610(0) ~ 610(M-1), each of the first multiple operation circuit to the Mth multiple operation circuit 610(0) ~ 610(M-1) can perform a third MAC operation in the first operation mode. The third MAC operation in the first operation mode can also be performed in substantially the same manner as described with reference to the first MAC operation and the second MAC operation. Each of the multiple operation circuits 610(0) ~ 610(M-1) can perform the third MAC operation in the first operation mode to generate the third MAC data MAC3[15:0] of one of the rows of the weight matrix 210. The "M" sets of the third MAC data MAC3[15:0] generated by the multiple operation circuits 610(0) ~ 610(M-1) can be latched in the latching circuits included in the respective ones of the multiple operation circuits 610(0) ~ 610(M-1). Figure 5 and Figure 7 The third MAC operation described is the same. Each of the multiple operation circuits 610(0) ~ 610(M-1) can perform the third MAC operation in the first operation mode to generate the third MAC data MAC3[15:0] of one of the rows of the weight matrix 210. The "M" sets of the third MAC data MAC3[15:0] generated by the multiple operation circuits 610(0) ~ 610(M-1) can be latched in the latching circuits included in the respective ones of the multiple operation circuits 610(0) ~ 610(M-1).

[0132] In the same manner as described above, each of the multiple operation circuits 610(0) ~ 610(M-1) can sequentially perform the fourth MAC operation to the Nth MAC operation in the first operation mode to sequentially generate the fourth MAC data to the Nth MAC data MAC4[15:0] ~ MAC(N)[15:0] of one of the rows of the weight matrix 210. The "M" sets of the Nth MAC data MAC(N)[15:0] generated by the respective ones of the first multiple operation circuit to the Mth multiple operation circuit 610(0) ~ 610(M-1) can respectively correspond to Figure 5The first to Mth MAC results MAC_RST(1) to MAC_RST(M) of the result matrix 230 shown in the middle. That is, the first multiple operation circuit 610(0) can output the Nth MAC data MAC(N)[15:0] generated by performing the first to Nth MAC operations on the weight data W(1.1) to W(1.N) arranged in the first row of the weight matrix 210 and the vector data V(1) to V(N) of the vector matrix 220 as the first MAC result data MAC_RST(1). Further, the second multiple operation circuit 610(1) can output the Nth MAC data MAC(N)[15:0] generated by performing the first to Nth MAC operations on the weight data W(2.1) to W(2.N) arranged in the second row of the weight matrix 210 and the vector data V(1) to V(N) of the vector matrix 220 as the second MAC result data MAC_RST(2). Similarly, the (M-1)th multiple operation circuit 610(M-2) can output the Nth MAC data MAC(N)[15:0] generated by performing the first to Nth MAC operations on the weight data W((M-1).1) to W((M-1).N) arranged in the (M-1)th row of the weight matrix 210 and the vector data V(1) to V(N) of the vector matrix 220 as the (M-1)th MAC result data MAC_RST(M-1). Finally, the Mth multiple operation circuit 610(M-1) can output the Nth MAC data MAC(N)[15:0] generated by performing the first to Nth MAC operations on the weight data W(M.1) to W(M.N) arranged in the Mth row of the weight matrix 210 and the vector data V(1) to V(N) of the vector matrix 220 as the Mth MAC result data MAC_RST(M).

[0133] Figure 19 A PIM device 700 according to an embodiment of the present disclosure is illustrated. Referring to Figure 19, the PIM device 700 can include "L" number of banks BK(0)~BK(L-1) (i.e., first bank to Lth bank 710(0)~710(L-1)), "L" number of MAC operators MAC(0)~MAC(L-1) (i.e., first MAC operator to Lth MAC operator 720(0)~720(L-1)), a global buffer (GB) 730, and a command decoder 740 (where "L" is a natural number equal to or greater than two). In an embodiment, each of the banks 710(0)~710(L-1) can constitute a MAC unit with any of the MAC operators 720(0)~720(L-1). The MAC operator MAC of a certain MAC unit can receive weight data from the bank of the certain MAC unit. For example, the first bank 710(0) and the first MAC operator 720(0) can constitute a first MAC unit. In this case, the first MAC operator 720(0) can receive weight data from the first bank 710(0). The configuration and operation of each of the MAC operators 720(0)~720(L-1) can be the same as the configuration and operation of the MAC operator 600 described with reference to Figure 6 and Figure 17 In this case, each of the MAC operators 720(0)~720(L-1) included in the PIM device 700 can perform the same MAC operation in the first MAC operation mode as described with reference to Figure 17

[0134] The global buffer 730 can be configured to transfer vector data for MAC operation to the MAC operators 720(0)~720(L-1). To make the global buffer 730 transfer the vector data to the MAC operators 720(0)~720(L-1), the global buffer 730 can output, in response to a request from a host (not shown), receive vector data from a controller (not shown) to store the vector data therein. In an embodiment, the global buffer 730 can transfer the vector data to the MAC operators 720(0)~720(L-1) through a global input / output (I / O) line GIO. The vector data output from the global buffer 730 can be transferred to each of the MAC operators 720(0)~720(L-1).

[0135] The command decoder 740 can receive a command CMD from an external device such as a controller. The command decoder 740 can decode the command CMD to generate and output control signals such as a first selection signal SS1, a second selection signal SS2, a third selection signal SS3, and an update signal UPDATE. Although in Figure 19 ​The command decoder 740 can also output additional control signals, such as read and write signals for accessing the memory banks 710(0)~710(L-1) and the global buffer 730, which are not shown. As described with reference to Figure 16 to Figure 18 The first to third selection signals SS1~SS3 and the update signal UPDATE can control the multiple arithmetic operations or calculations of the MAC operators 720(0)~720(L-1) in the first MAC operation mode.

[0136] Figure 20 FIG. 7 illustrates an example of a MAC operation performed by the PIM device 700. Figure 19 As described with reference to Figure 19 The MAC operators 720(0)~720(L-1) of the PIM device 700 can perform the MAC operation in the first MAC operation mode described with reference to Figure 17 The following description of the MAC operation according to the present embodiment can equally apply to the MAC operation of each of the second to Lth MAC operators 720(1)~720(L-1).

[0137] Referring to Figure 20 The first MAC operator 720(0) can include “N” multiple operation circuits (i.e., first to Nth multiple operation circuits 610(0)~610(N-1)). The first MAC operator 720(0) can receive the weight data W(1.1)~W(1.N) from the first memory bank 710(0) to perform the MAC operation. In addition, the first MAC operator 720(0) can receive the vector data V(1)~V(N) from the global buffer 730 of the PIM device 700. The “N” sets of weight data W(1.1)~W(1.N) output from the first memory bank 710(0) can be transmitted to the first to Nth multiple operation circuits 610(0)~610(N-1) of the first MAC operator 720(0), respectively. The “N” sets of vector data V(1)~V(N) output from the global buffer 730 of the PIM device 700 can also be transmitted to the first to Nth multiple operation circuits 610(0)~610(N-1) of the first MAC operator 720(0), respectively. The first MAC operator 720(0) can perform the MAC operation in the first MAC operation mode. As reference Figure 19 Figure 19 Figure 17 The first to third selection signals SS1~SS3 and the update signal UPDATE can control the multiple arithmetic operations or calculations of the MAC operators 720(0)~720(L-1) in the first MAC operation mode.

[0136] Figure 20 FIG. 7 illustrates an example of a MAC operation performed by the PIM device 700. Figure 19 As described with reference to Figure 19 The MAC operators 720(0)~720(L-1) of the PIM device 700 can perform the MAC operation in the first MAC operation mode described with reference to Figure 17 The following description of the MAC operation according to the present embodiment can equally apply to the MAC operation of each of the second to Lth MAC operators 720(1)~720(L-1).

[0137] Referring to Figure 20 The first MAC operator 720(0) can include “N” multiple operation circuits (i.e., first to Nth multiple operation circuits 610(0)~610(N-1)). The first MAC operator 720(0) can receive the weight data W(1.1)~W(1.N) from the first memory bank 710(0) to perform the MAC operation. In addition, the first MAC operator 720(0) can receive the vector data V(1)~V(N) from the global buffer 730 of the PIM device 700. The “N” sets of weight data W(1.1)~W(1.N) output from the first memory bank 710(0) can be transmitted to the first to Nth multiple operation circuits 610(0)~610(N-1) of the first MAC operator 720(0), respectively. The “N” sets of vector data V(1)~V(N) output from the global buffer 730 of the PIM device 700 can also be transmitted to the first to Nth multiple operation circuits 610(0)~610(N-1) of the first MAC operator 720(0), respectively. The first MAC operator 720(0) can perform the MAC operation in the first MAC operation mode. As reference Figure 19 Figure 19 Figure 17 The first to third selection signals SS1~SS3 and the update signal UPDATE can control the multiple arithmetic operations or calculations of the MAC operators 720(0)~720(L-1) in the first MAC operation mode.

[0136] Figure 20 FIG. 7 illustrates an example of a MAC operation performed by the PIM device 700. Figure 19 As described with reference to Figure 19 The MAC operators 720(0)~720(L-1) of the PIM device 700 can perform the MAC operation in the first MAC operation mode described with reference to Figure 17 The following description of the MAC operation according to the present embodiment can equally apply to the MAC operation of each of the second to Lth MAC operators 720(1)~720(L-1).

[0137] Referring to Figure 20 The first MAC operator 720(0) can include “N” multiple operation circuits (i.e., first to Nth multiple operation circuits 610(0)~610(N-1)). The first MAC operator 720(0) can receive the weight data W(1.1)~W(1.N) from the first memory bank 710(0) to perform the MAC operation. In addition, the first MAC operator 720(0) can receive the vector data V(1)~V(N) from the global buffer 730 of the PIM device 700. The “N” sets of weight data W(1.1)~W(1.N) output from the first memory bank 710(0) can be transmitted to the first to Nth multiple operation circuits 610(0)~610(N-1) of the first MAC operator 720(0), respectively. The “N” sets of vector data V(1)~V(N) output from the global buffer 730 of the PIM device 700 can also be transmitted to the first to Nth multiple operation circuits 610(0)~610(N-1) of the first MAC operator 720(0), respectively. The first MAC operator 720(0) can perform the MAC operation in the first MAC operation mode. As reference Figure 19 Figure 19 Figure 17 The first to third selection signals SS1~SS3 and the update signal UPDATE can control the multiple arithmetic operations or calculations of the MAC operators 720(0)~720(L-1) in the first MAC operation mode.

[0136] Figure 20 FIG. 7 illustrates an example of a MAC operation performed by the PIM device 700. Figure 19 As described with reference to Figure 19 The MAC operators 720(0)~720(L-1) of the PIM device 700 can perform the MAC operation in the first MAC operation mode described with reference to Figure 17 The following description of the MAC operation according to the present embodiment can equally apply to the MAC operation of each of the second to Lth MAC operators 720(1)~720(L-1).

[0137] Referring to Figure 20 The first MAC operator 720(0) can include “N” multiple operation circuits (i.e., first to Nth multiple operation circuits 610(0)~610(N-1)). The first MAC operator 720(0) can receive the weight data W(1.1)~W(1.N) from the first memory bank 710(0) to perform the MAC operation. In addition, the first MAC operator 720(0) can receive the vector data V(1)~V(N) from the global buffer 730 of the PIM device 700. The “N” sets of weight data W(1.1)~W(1.N) output from the first memory bank 710(0) can be transmitted to the first to Nth multiple operation circuits 610(0)~610(N-1) of the first MAC operator 720(0), respectively. The “N” sets of vector data V(1)~V(N) output from the global buffer 730 of the PIM device 700 can also be transmitted to the first to Nth multiple operation circuits 610(0)~610(N-1) of the first MAC operator 720(0), respectively. The first MAC operator 720(0) can perform the MAC operation in the first MAC operation mode. As reference Figure 19 Figure 19 Figure 17 The first to third selection signals SS1~SS3 and the update signal UPDATE can control the multiple arithmetic operations or calculations of the MAC operators 720(0)~720The first MAC operator 720(0) can perform a MAC operation in the first MAC operation mode to output an Nth MAC data MAC(N) generated by the Nth multiple operation circuit 610(N-1) as an Nth data IY(N-1) of the second result data IY. The Nth MAC data MAC(N) output from the first MAC operator 720(0) can correspond to a first MAC result data MAC_RST(1) of the result matrix.

[0138] Figure 21 FIG. 1 illustrates a PIM device 100 according to an embodiment of the disclosure. Referring to FIG. 1, the PIM device 100 can include an 'L' number of banks BK(0) ~ BK(L-1) (i.e., first to Lth banks 110(0) ~ 110(L-1)), an 'L' number of multiple operation circuits MOC(0) ~ MOC(L-1) (i.e., first to Lth multiple operation circuits 120(0) ~ 120(L-1)), a global buffer (GB) 130, and a command decoder 140 (where 'L' is a natural number equal to or greater than two). Figure 21 The PIM device 800 can include 'L' number of banks BK(0) ~ BK(L-1) (i.e., first to Lth banks 810(0) ~ 810(L-1)), 'L' number of multiple operation circuits MOC(0) ~ MOC(L-1) (i.e., first to Lth multiple operation circuits 820(0) ~ 820(L-1)), a global buffer (GB) 830, and a command decoder 840 (where 'L' is a natural number equal to or greater than two). In the PIM device 800, each of the first to Lth multiple operation circuits 820(0) ~ 820(L-1) can have the same configuration as the multiple operation circuit 100 described with reference to FIG. 1. Accordingly, each of the first to Lth multiple operation circuits 820(0) ~ 820(L-1) can selectively perform a MAC operation, an EW multiplication calculation, an EW addition calculation, or an accumulation calculation. When each of the first to Lth multiple operation circuits 820(0) ~ 820(L-1) performs a MAC operation, each of the first to Lth banks 810(0) ~ 810(L-1) can constitute a MAC unit with any one of the first to Lth multiple operation circuits 820(0) ~ 820(L-1). The multiple operation circuit 820 of a certain MAC unit can receive weight data for a MAC operation from the bank of the certain MAC unit. For example, the first bank 810(0) and the first multiple operation circuit 820(0) can constitute a first MAC unit. In this case, the first multiple operation circuit 820(0) can receive weight data from the first bank 810(0). When the PIM device 800 performs a MAC operation, the first to Lth multiple operation circuits 820(0) ~ 820(L-1) can perform a MAC operation in the second MAC operation mode described with reference to FIG. 2. Figure 1 Figure 18

[0139] ​​The global buffer 830 can be configured to transfer vector data for MAC operations to the first to Lth multiple operation circuits 820(0)-820(L-1). To cause the global buffer 830 to transfer the vector data to the first to Lth multiple operation circuits 820(0)-820(L-1), the global buffer 830 can receive the vector data from a controller (not shown) to store the vector data therein in response to a request output from a host (not shown). In one embodiment, the global buffer 830 can transfer the vector data to the first to Lth multiple operation circuits 820(0)-820(L-1) through global input / output (I / O) lines GIO. The vector data output from the global buffer 830 can be transferred to each of the first to Lth multiple operation circuits 820(0)-820(L-1).

[0140] The command decoder 840 can receive a command CMD from an external device (e.g., a controller). The command decoder 840 can decode the command CMD to generate and output control signals, such as a first selection signal SS1, a second selection signal SS2, a third selection signal SS3, and an update signal UPDATE. Although not shown in FIG. 8A, the command decoder 840 can also output other control signals, such as read and write signals for accessing the banks 810(0)-810(L-1) and the global buffer 830. As described with reference to Figure 21 Figure 16 to Figure 18 The first to third selection signals SS1-SS3 and the update signal UPDATE can control arithmetic operations or calculations of the multiple operation circuits 820(0)-820(L-1), as described with reference to

[0141] Figure 22 FIG. 8B illustrates an example of a MAC operation performed by the PIM device 800 shown in FIG. 8A. As described with reference to Figure 21 Figure 21 The multiple operation circuits 820(0)-820(L-1) of the PIM device 800 can perform MAC operations in the second MAC operation mode described with reference to Figure 18 Figure 22 Referring to FIG. 8B, the first multiple operation circuit 820(0) can sequentially receive weight data W(1.1)-W(1.N) from the first bank 810(0) to perform a MAC operation. In addition, the first multiple operation circuit 820(0) can sequentially receive vector data V(1)-V(N) from the global buffer 830 of the PIM device 800. Figure 21

[0142] ​​​​Specifically, the first multiple operation circuit 820(0) can receive the weight data W(1.1) and the vector data V(1) from respective ones of the first memory bank 810(0) and the global buffer 830 to perform a first MAC operation. Next, the first multiple operation circuit 820(0) can receive the weight data W(1.2) and the vector data V(2) from respective ones of the first memory bank 810(0) and the global buffer 830 to perform a second MAC operation. Subsequently, the first multiple operation circuit 820(0) can receive the weight data W(1.3) and the vector data V(3) from respective ones of the first memory bank 810(0) and the global buffer 830 to perform a third MAC operation. As such, the MAC operations can be iteratively performed until an Nth MAC operation is performed on the weight data W(1.N) located at the intersection of the first row and the Nth column of the weight matrix and the vector data V(N) of the Nth row of the vector matrix. After performing the Nth MAC operation of the first multiply operation circuit 820(0), the first multiply operation circuit 820(0) can output a first MAC data MAC(1) corresponding to the MAC operation results of the weight data W(1.1) ~ W(1.N) and the vector data V(1) ~ V(N) as a first MAC result data MAC_RST(1). In the same manner, the remaining multiple operation circuits (i.e., the second multiple operation circuit to the Lth multiple operation circuit 820(1) ~ 820(L-1)) can also perform the MAC operations to generate and output a second MAC data to an Lth MAC data MAC(2) ~ MAC(L) as a second MAC result data to an Lth MAC result data MAC_RST(2) ~ MAC_RST(L), respectively.

[0143] For purposes of illustration, a limited number of possible embodiments for the present teachings have been set forth above. Persons of ordinary skill in the art will understand that numerous modifications, additions, and substitutions are possible. Although this patent document includes particular embodiments, it is understood that the embodiments are not to be taken as limiting the scope of the present teachings or the potential claims that can be made. Certain features described herein in the context of separate embodiments can also be implemented in combination. Conversely, various features described herein in the context of a single embodiment can also be implemented separately or in any suitable subcombination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be deleted from the combination, and the claimed combination can also be intended to cover each sub-combination.

Claims

1. A multiple operation circuit, comprising: a multiplier configured to perform a multiplication calculation on first input data and second input data to generate and output multiplied result data; an adder configured to perform an addition calculation on third input data and fourth input data to generate and output added result data; a latch circuit configured to latch fifth input data input to an input terminal of the latch circuit to generate and output feedback data; and a plurality of selectors configured to change a transmission path of first result data, the first input data, the second input data, the multiplied result data, and the added result data according to a first operation mode, a second operation mode, or a third operation mode, and wherein the plurality of selectors include: a first selector configured to receive the first result data and the multiplied result data to output one of the first result data and the multiplied result data in response to a first selection signal; a second selector configured to receive the first input data and output data of the first selector to output one of the first input data and the output data of the first selector in response to a second selection signal; a third selector configured to receive the second input data and the feedback data to output one of the second input data and the feedback data in response to the second selection signal; and a fourth selector configured to receive the output data of the first selector and the added result data to output one of the output data of the first selector and the added result data in response to a third selection signal, and wherein the first selector has a first input terminal receiving the first result data, a second input terminal coupled to an output terminal of the multiplier, a selection terminal receiving the first selection signal, and an output terminal, wherein the second selector has a first input terminal receiving the first input data, a second input terminal coupled to the output terminal of the first selector, a selection terminal receiving the second selection signal, and an output terminal coupled to a first input terminal of the adder, wherein the third selector has a first input terminal receiving the second input data, a second input terminal coupled to an output terminal of the latch circuit, a selection terminal receiving the second selection signal, and an output terminal coupled to a second input terminal of the adder, and wherein the fourth selector has a first input terminal coupled to the output terminal of the first selector, a second input terminal coupled to an output terminal of the adder, a selection terminal receiving the third selection signal, and an output terminal coupled to an input terminal of the latch circuit. The plurality of selectors are configured such that, when a multiplication and accumulation operation is performed in the first operation mode, the multiplied result data is transmitted to become the third input data, and the feedback data is transmitted to become the fourth input data.

2. The multiple operation circuit according to claim 1, wherein ​ 3. The multiple operation circuit according to claim 1, wherein The plurality of selectors are configured such that, when performing an element-wise multiplication calculation in the second operation mode, the multiplication result data is transferred to the input terminal of the latch circuit.

4. The multiple operation circuit according to claim 1, wherein The plurality of selectors are configured such that, when performing an element-wise addition calculation in the second operation mode, the first input data is transferred to be the third input data, and the second input data is transferred to be the fourth input data.

5. The multiple operation circuit according to claim 1, wherein The plurality of selectors are configured such that, when performing an accumulation calculation in the third operation mode, the first result data is transferred to be the third input data, and the feedback data is transferred to be the fourth input data.

6. The multiple operation circuit according to claim 1, further comprising an inverter that inverts a level of the third selection signal to transfer an inverted signal of the third selection signal to the fourth selector.

7. The multiple operation circuit according to claim 1, wherein, The first selector is configured to output the first result data when the first selection signal has a first logic level, and is configured to output the multiplication result data when the first selection signal has a second logic level; wherein the second selector is configured to output the first input data when the second selection signal has the first logic level, and is configured to output the output data of the first selector when the second selection signal has the second logic level; wherein the third selector is configured to output the second input data when the second selection signal has the first logic level, and is configured to output the feedback data when the second selection signal has the second logic level; and wherein the fourth selector is configured to output the output data of the first selector when the third selection signal has the second logic level, and is configured to output the addition result data when the third selection signal has the first logic level.

8. The multiple operation circuit according to claim 7, wherein, output data of the second selector corresponds to the third input data; wherein output data of the third selector corresponds to the fourth input data; and wherein output data of the fourth selector corresponds to the fifth input data.

9. The multiple operation circuit according to claim 8, wherein, The latch circuit is synchronized with a logic level transition of an update signal input to a clock terminal of the latch circuit to latch the fifth input data input to the input terminal of the latch circuit, and output latch data of the fifth input data via an output terminal of the latch circuit as the feedback data.

10. The multiple operation circuit according to claim 9, further comprising: a first output line through which the addition result data output from the adder is transferred to provide second result data; and a second output line through which the latch data of the fifth input data output from the latch circuit is transferred to provide operation result data.

11. The multiple operation circuit according to claim 10, wherein In the first operation mode, the multiplication and accumulation operation is performed by a matrix-vector multiplication calculation of the weight data and the vector data; wherein, in the second operation mode, an element-wise multiplication calculation is performed by a matrix-scalar multiplication calculation of the weight data and a constant; wherein, in the second operation mode, an element-wise addition calculation is performed by a matrix addition calculation of a first matrix and a second matrix; and wherein, in the third operation mode, an accumulation calculation is performed by adding the first result data and the latched data.

12. The multiple operation circuit according to claim 11, wherein, The multiplication and accumulation operation is performed in the first operation mode when the first selection signal and the second selection signal have the second logic level and the third selection signal has the first logic level.

13. The multiple operation circuit according to claim 11, wherein, The element-wise multiplication calculation is performed in the second operation mode when the first selection signal and the third selection signal have the second logic level and the second selection signal is deactivated.

14. The multiple operation circuit according to claim 11, wherein, The element-wise addition calculation is performed in the second operation mode when the second selection signal and the third selection signal have the first logic level and the first selection signal is deactivated.

15. The multiply arithmetic circuit of claim 11, wherein, The accumulation calculation is performed in the third operation mode when the first selection signal has the first logic level, the second selection signal has the second logic level and the third selection signal is deactivated.

16. The multiple operation circuit according to claim 1, wherein the first input data has a floating point format including first sign data, first exponent data and first mantissa data; wherein, the second input data has a floating point format including second sign data, second exponent data and second mantissa data; and wherein, the multiplier includes: a sign processing circuit configured to perform a logical exclusive OR operation on the first sign data and the second sign data to generate and output third sign data of the multiplication result data; an exponent processing circuit configured to add the first exponent data and the second exponent data to generate an exponent addition result data, and configured to subtract a bias value from the exponent addition result data; a mantissa processing circuit configured to perform an addition calculation on the first mantissa data and the second mantissa data; and a normalizer configured to convert exponent data output from the exponent processing circuit to normalized third exponent data of the multiplication result data, and configured to convert mantissa data output from the mantissa processing circuit to normalized third mantissa data of the multiplication result data.

17. The multiple operation circuit according to claim 16, wherein, the third input data has a floating point format including third sign data, third exponent data and third mantissa data; wherein, the fourth input data has a floating point format including fourth sign data, fourth exponent data and fourth mantissa data; and wherein, the adder includes: a difference circuit configured to compare the third exponent data and the fourth exponent data to generate and output maximum exponent data, exponent difference data and a selection signal; 2's complement processing circuitry configured to output, as first intermediate mantissa data, either the third mantissa data or 2's complement data of the third mantissa data according to a value of the third sign data, and configured to output, as second intermediate mantissa data, either the fourth mantissa data or 2's complement data of the fourth mantissa data according to a value of the fourth sign data; shift circuitry configured to perform a shift operation on either the first intermediate mantissa data or the second intermediate mantissa data according to a logic level of the selection signal, and output, as third intermediate mantissa data, mantissa data that is not shifted and output, as shifted intermediate mantissa data, mantissa data that is to be shifted; addition circuitry configured to add the third intermediate mantissa data and the shifted intermediate mantissa data to generate sign data and added mantissa data of the addition result data, configured to output, via a first output of the addition circuitry, the sign data of the addition result data, and configured to output, via a second output of the addition circuitry, either the added mantissa data or 2's complement data of the added mantissa data as third intermediate mantissa data according to a value of the sign data of the addition result data; and normalizer configured to normalize the maximum exponent data and the third intermediate mantissa data to generate exponent data and mantissa data of the addition result data.

18. The multiply-accumulate circuit of claim 1, wherein the first input data having a floating point format including first sign data, first exponent data, and first mantissa data; wherein the second input data has a floating point format including second sign data, second exponent data, and second mantissa data; wherein a number of bits included in the multiplication result data output from the multiplier is twice a number of bits included in either the first input data or the second input data; wherein a number of bits included in the addition result data output from the adder is equal to a number of bits included in the multiplication result data; and wherein a number of bits included in the feedback data output from the latch circuitry is equal to a number of bits included in the addition result data.

19. The multiply-accumulate circuit of claim 18, wherein the multiplier including a mantissa multiplier configured to perform a multiplication computation on first data including the first mantissa data of the first input data and implicit bits and second data including the second mantissa data of the second input data and implicit bits to generate and output result data of the multiplication computation; and wherein the result data output from the mantissa multiplier provides mantissa data of the multiplication result data output from the multiplier.

20. The multiply-accumulate circuit of claim 18, further comprising normalizer coupled to an output of the latch circuitry, wherein, the normalizer configured to normalize the feedback data output from the latch circuitry to generate data having a same number of bits as either the first input data or the second input data.

21. The multiply arithmetic circuit of claim 20, wherein, the normalizer including: a floating point shifter configured to receive mantissa data of the output data of the latching circuit to shift a binary floating point of the mantissa data one bit to a most significant bit of the mantissa data to generate and output the mantissa data having the shifted binary floating point; a multiplexer configured to selectively output the mantissa data of the output data of the latching circuit or the output data of the floating point shifter according to a logic level of the most significant bit of the mantissa data of the output data of the latching circuit; a rounding processor configured to remove certain bits including an implicit bit from the output data of the multiplexer and configured to perform a rounding operation to generate and output the mantissa data having a same number of bits as the first input data or the second input data; and an adder configured to add the most significant bit data of the mantissa data of the output data of the latching circuit to the exponent data of the output data of the latching circuit to generate and output the exponent data having a same number of bits as the first input data or the second input data.

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