Storage device, method and system for data processing

Abstract

A storage device, a data processing method and system are provided. The storage device comprises: a plurality of storage units which can be accessed in parallel; a controller configured to: receive a first access command for the plurality of storage units; in response to a number of storage units in an open state in the plurality of storage units being less than a set threshold, generate an activation command corresponding to the first access command; and in response to the number of storage units in the open state in the plurality of storage units being greater than or equal to the set threshold, not generate the activation command corresponding to the first access command. Embodiments of the present application limit the number of storage units that can be opened according to the threshold of the number of storage units in the access state inside the storage device, limit the flow of the activation command corresponding to the access command, and help save power consumption while ensuring efficiency.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of data storage, and more specifically, to a storage device, a data processing method and system. BACKGROUND

[0002] Double Data Rate Synchronous Dynamic Random Access Memory, also known as DDR, is the most widely used memory product at present, and has great advantages in cost, bandwidth, power consumption, etc. In a heavy load scenario, due to the cumulative effect of access commands, the commands on the DDR bus have reached the full load situation, and the activate and pre-power-on commands in the DDR controller will open more rows and pages, which will not bring additional performance benefits, but will waste power consumption. SUMMARY

[0003] Embodiments of the present application provide a storage device, a data processing method and system, and the following describes various aspects of the embodiments of the present application.

[0004] In a first aspect, a storage device is provided, comprising: a plurality of storage units that can be accessed in parallel; a controller configured to: receive a first memory access command for the plurality of storage units; in response to a number of storage units in the plurality of storage units in an open state being less than a set threshold, generate an activate command corresponding to the first memory access command; and in response to the number of storage units in the plurality of storage units in the open state being greater than or equal to the set threshold, not generate the activate command corresponding to the first memory access command.

[0005] In a second aspect, a data processing method is provided, applied to a storage device, the storage device comprising: a plurality of storage units that can be accessed in parallel; a controller; the method comprising: receiving a first memory access command for the plurality of storage units; in response to a number of storage units in the plurality of storage units in an open state being less than a set threshold, generating an activate command corresponding to the first memory access command; and in response to the number of storage units in the plurality of storage units in the open state being greater than or equal to the set threshold, not generating the activate command corresponding to the first memory access command.

[0006] In a third aspect, a data processing system is provided, comprising a processor and a storage device as described in the first aspect.

[0007] Embodiments of the present application limit the number of storage units that can be opened according to the threshold of the number of storage units in the access state inside the storage device, and limit the activate command corresponding to the access command, which helps to save power consumption while ensuring efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1A structural schematic diagram of the storage device provided in the embodiment of the present application.

[0009] Figure 2 is Figure 1 A schematic diagram of one possible implementation of the storage device.

[0010] Figure 3 is Figure 2 A flowchart of state switching of the numbering machine of

[0011] Figure 4 is Figure 2 A schematic diagram of mechanism setting of the numbering machine of

[0012] Figure 5 is a flowchart of the method for data processing provided in the embodiment of the present application.

[0013] Figure 6 is a schematic diagram of the data processing system provided in the embodiment of the present application. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application.

[0015] The storage device is a device for storing information, usually after digitizing the information and then storing it by using media such as electricity, magnetism or optics. According to different uses, it can be divided into memory (main memory) and external storage (auxiliary memory). In the running of a computer or a system on a chip, the CPU will transfer the data needed for operation to the memory for operation, and then the CPU will transmit the result after the operation is completed. The running of the memory determines the stable running of the computer. The memory (Memory) is also called the internal memory or the main memory, which is used to temporarily store the operation data in the CPU and exchange data with the external storage such as a hard disk.

[0016] Memory can be categorized by its working principle into Random Access Memory (RAM), Read Only Memory (ROM), and cache. RAM is the most important type of memory. Based on memory technology standards, it can be divided into Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), and Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), among others. DDRSDRAM, also known simply as DDR, is currently the most widely used memory product, offering significant advantages in cost, bandwidth, and power consumption.

[0017] A typical memory system is logically organized into channels, banks, rows, and columns. Multiple banks share a single channel connected to the processor. A bank is the smallest physical unit that can operate independently and in parallel; that is, multiple banks can simultaneously read / write data independently. However, if the target data for two access requests is in the same bank, the two requests can only be processed serially, not in parallel. A bank can contain a large number of pages, and all pages can be arranged in a two-dimensional matrix consisting of rows and columns.

[0018] Once a data access request arrives at the Bank, completing the data access requires three steps:

[0019] 1) Active: Reads the target row data from the 2D storage array into the row buffer. 2) Read / Write: Reads / writes data in the row buffer. 3) Precharge: Writes the data in the row buffer back to the 2D storage array. This is the last operation on the row. A new row can only be accessed after this operation is completed; this operation is also called closing open rows.

[0020] The DDR controller of the relevant technology sends Active and Precharge commands based on basic commands. That is, once a specific read or write command is cached in the DDR controller, the DDR controller will generate specific Active and Precharge commands according to the state of the DDR.

[0021] The logic for generating Active and Precharge commands in this way does not result in additional power consumption or performance loss under light load conditions or when commands are not accumulated. However, in heavy load scenarios, such as PUBG Gaming and WeChat video chat, due to the cumulative effect of access commands, the commands on the DDR bus have reached full load. The number of access commands exceeds the total number of banks, and opening more rows and pages in more banks will not bring additional performance benefits, but will lead to wasted power consumption.

[0022] It should be noted that the example mentioned above, where opening more banks when the DDR bus is fully loaded leads to wasted power, is just one example. The embodiments of this application can be applied to any type of scenario where there is wasted power in the memory access command control of storage devices.

[0023] Therefore, developing a solution for controlling memory access commands in storage devices to reduce power consumption is a problem that needs to be solved.

[0024] To address the aforementioned problems, this application proposes a storage device, and the embodiments of this application are described in detail below.

[0025] Figure 1 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application. The storage device 100 may include a plurality of storage units 110 and a controller 120.

[0026] The multiple storage units 110 are multiple storage units that can be accessed in parallel, such as multiple banks, from Bank(0) to Bank(n), where n can be, for example, 16, 32, etc. The storage units mentioned below in this application refer to storage units that can be accessed in parallel.

[0027] A Bank is the smallest physical unit that can operate independently and in parallel, meaning that multiple Banks can be read from and written to simultaneously. However, if two data access requests target data in the same Bank, these two requests can only be processed serially, not in parallel. A Bank can contain a large number of pages, and all pages can be arranged in a two-dimensional matrix with rows horizontally and columns vertically.

[0028] In some implementations, the Bank can be based on a Bank sequence architecture. For example, 16 Banks are divided into 4 groups, each group containing 4 Banks, such as Bank(0) to Bank(3) as a group.

[0029] The controller 120 is connected to multiple memory cells 110 and is used to receive first memory access commands for the multiple memory cells 110. The first memory access command may include read / write commands, also known as load / store memory access instructions. Load / store memory access instructions are instructions specifically designed for memory access in the RISC architecture.

[0030] Based on the number of storage units 110 that can be accessed in parallel, the controller 120 can set the number of storage units in the open state, i.e., set a threshold. The set threshold can be any integer greater than 1 and not greater than the total number of storage units. The controller 120 performs rate limiting on the number of storage units in the open state, i.e., rate limiting on the activation commands corresponding to the first memory access commands of the multiple storage units 110. If the total number of banks is 32, the set threshold can be 24, then the maximum number of banks in the open state is 24, i.e., 24 banks can be read / written independently at the same time. In some embodiments, the set threshold can be 18, and the maximum number of banks in the open state is 18.

[0031] After receiving a first memory access command for multiple memory cells 110, if the number of memory cells in the multiple memory cells 110 that are in the open state is less than a set threshold, the controller 120 generates an activation command corresponding to the first memory access command. If the number of memory cells in the multiple memory cells 110 that are in the open state is greater than or equal to the set threshold, the controller 120 does not generate an activation command corresponding to the first memory access command.

[0032] In some implementations, the number of storage units that can be opened can be dynamically limited based on the number of storage units in an access state within the corresponding storage device under the usage scenario. That is, the threshold can be dynamically adjusted according to the usage scenario.

[0033] In some implementations, the controller 120 can adjust the value of the set threshold according to the idle and busy status of the multiple storage units 110. For example, when the storage units in the multiple storage units 110 are idle, the set threshold can be set to a smaller number; when the storage units in the multiple storage units 110 are frequently accessed, the set threshold can be set to a relatively larger number.

[0034] In some implementations, the idle / busy status of multiple storage units 110 can be determined by the time each storage unit 110 is idle and accessed. A threshold can be adjusted based on the idle and access times of the multiple storage units 110.

[0035] In some implementations, a loop time period can be set. Within the loop time period, the time during which a storage unit among the multiple storage units 110 is in an idle state and the time during which it is in an access state are determined.

[0036] In some implementations, the set threshold can be adjusted based on the idle / busy status of the controller 120 receiving the first memory access command. For example, if the controller 120 receives fewer first memory access commands from multiple memory units 110 over a period of time, it indicates that the controller 120 is mostly idle. If the controller 120 receives more first memory access commands from multiple memory units 110, it indicates that the controller 120 is mostly blocked.

[0037] This application embodiment limits the number of memory cells that can be opened based on a determined threshold for the number of memory cells in an access state within the storage device. It also limits the activation commands corresponding to access commands, thus helping to save power while ensuring efficiency. For example, a 16GB memory chip has a total of 256 banks. The active power reserve power of a single bank is 23.915mW, and the idle power reserve power of a single bank is 21.815mW. If, in a specific scenario, the threshold is set to 192, and 64 fewer banks are opened, the power saving is 134.4mW.

[0038] In some implementations, a loop time period can be set. Within the loop time period, the set threshold can be adjusted according to the idle / busy status of the controller 120.

[0039] In some embodiments, the cycle time period can employ a tick-tock timer as a global time wheel, which serves as a time reference. The complete rotation cycle of the time wheel can be measured as 3.2 µsec, where the time unit for each control point of the timer is 0.025 µsec (i.e., 25 GHz). A tick-based 7-bit counter can also be included, capable of counting to 128 increments, i.e., 128 * 0.025 = 3.2 µsec.

[0040] In some use cases, external access to the storage device 100 may be periodic, or intermittently idle and frequently accessed. In some implementations, a first time window can be set within the cycle time. Within the first time window, the controller 120 receives and processes the first memory access commands from multiple storage units 110. Outside the first time window, the controller 120 receives the first memory access commands from multiple storage units 110 but does not process them, waiting until they arrive within the time window before processing them. Within the first time window, the controller 120 can check the open status of multiple storage units 110, receive and process the first memory access commands from multiple storage units 110, thus maximizing power saving while ensuring efficiency.

[0041] Within the loop time period, the time of the first time window can be adjusted, the start time of the first time window can be set or adjusted, and the stop time of the first time window can also be set or adjusted.

[0042] In some embodiments, a pair of periodic time registers can be set for a first time window. One register, the start register, is used for the start time of the first time window, serving as the starting point of timing. The second register, the stop register, is used for the end time of the first time window, serving as the ending point of timing. The time difference between the stop register and the start register is the time period of the first time window. When the global timer's time equals the start register's time, the controller 120 can set the enable bit for the memory cell status category and allow counting from the memory cell's status category. When the global timer's time equals the stop register's time, the controller 120 resets the enable bit for the memory cell status category and stops checking the memory cell status category. If the start register and stop register are configured with the same value, the stop register has priority and does not allow access to the memory cell's status category.

[0043] In some implementations, the controller 120 can divide the first time window into idle time and blocking time to detect the idle / busy status of the controller 120. It should be noted that the idle time includes not only the time when the controller 120 does not receive the first memory access command, but also the time when the number of open memory cells among the multiple memory cells 110 is greater than or equal to a set threshold, during which the controller 120 does not generate the activation command corresponding to the first memory access command. The blocking time is the time when the number of open memory cells among the multiple memory cells 110 is less than the set threshold, after the controller 120 receives the first memory access command and generates the activation command corresponding to the first memory access command.

[0044] In some implementations, an idle time counter can be set to count idle time. A blocking time counter can be set to count blocking time. The sum of idle time and blocking time is the total time of the first time window.

[0045] In some implementations, two thresholds can be set for idle time: a total time threshold and a first threshold, also known as the idle threshold. Similarly, two thresholds can be set for blocking time: a total time threshold and a second threshold, also known as the blocking threshold. Based on the idle and blocking time status of the controller 120, i.e., the idle / busy status of the controller 120, the set thresholds for openable memory units are adjusted. The total time threshold is the total time of the first time window, which is the time difference between the stop register and the start register. The first threshold should be less than the total time threshold, and the second threshold should also be less than the total time threshold.

[0046] For example, in a clock mechanism with a cycle time period of 3.2 microseconds corresponding to 128 scales, the total cycle time threshold can be 100. The first threshold can be initially set to be greater than 30, for example, 40, and the second threshold can be initially set to be greater than 50, for example, 60.

[0047] In some implementations, the controller 120 can adjust the size of the idle threshold and the blocking threshold, as well as the size of the set threshold, based on the busy / idle status of the activation command corresponding to the output first memory access command.

[0048] Optionally, when the controller 120 is idle for a longer period than a first threshold and a first condition is met, the value of the first threshold can be increased based on the adjustment deviation. The first condition, also known as a first critical condition, can include one or more of the following: reaching a set threshold; reaching the start time threshold of a first time window; reaching the stop time threshold of a first time window; or reaching the total number threshold of multiple memory units 110. In this case, it indicates that the controller 120 receives fewer first memory access commands, and the controller 120 is idle for a longer period, allowing for an increase in the value of the first threshold.

[0049] Optionally, if the time the controller 120 is in an idle state is less than a first threshold, the value of the first threshold remains unchanged.

[0050] Optionally, if the time during which the controller 120 is in a blocked state is less than or equal to the second threshold, the value of the set threshold remains unchanged.

[0051] Optionally, if the time the controller 120 is in a blocked state is less than the second threshold in two or more consecutive time cycles, the threshold value can be reduced. In this case, it indicates that the controller 120 receives fewer first memory access commands and the controller 120 is in a blocked state for a shorter period of time, so the value of the threshold value can be reduced.

[0052] Optionally, if the controller 120 is in a blocked state for a longer period than the second threshold, the second threshold can be increased, or the set threshold can be increased.

[0053] In some implementations, the controller 120 may employ a numbering machine to manage the sequence numbers of all waiting-to-be-accessed storage units. The numbering machine can also be called a storage unit numbering machine or a storage unit number manager, simply referred to as a numbering machine. When the storage unit is a Bank, the numbering machine is also called a Bank numbering machine. The Bank numbering machine can store variables of storage units in the open state and queue set variables for storing all waiting-to-be-accessed storage units. After receiving a first memory access command for multiple storage units 110, if the number of open storage units among the multiple storage units 110 is less than a set threshold, the Bank numbering machine generates an activation command corresponding to the first memory access command. If the number of open storage units among the multiple storage units 110 is greater than or equal to the set threshold, the Bank numbering machine does not generate an activation command corresponding to the first memory access command.

[0054] In some implementations, the Bank numbering machine can operate cyclically within a certain time period. This time period can be based on a timer mechanism of the marked microarchitecture, with the timer of the marked microarchitecture serving as a global time wheel and a time reference. The cyclical time period may also include a first time window. Within the first time window, multiple first memory access commands from storage units 110 are received, and the Bank numbering machine processes them accordingly, generating an activation command corresponding to the first memory access command. Outside the first time window, multiple first memory access commands from storage units 110 are received, but the Bank numbering machine does not process them, waiting for them to arrive within the first time window before processing them.

[0055] In some implementations, for time-division multiplexing (TDM), a global time wheel is used as a time reference to allow or disallow checking the set threshold of the Bank numberer. TDM divides the channel into different time slots and interpolates different pulse signals in different time slots to achieve multiplexing of multiple signals in the time domain.

[0056] This application embodiment limits the number of memory cells that can be opened based on a determined threshold number of memory cells in an access state within the storage device, and rate-limits the activation commands corresponding to access commands. Depending on different usage scenarios, the threshold number of memory cells in an access state can be adjusted accordingly, helping to save power consumption while ensuring efficiency.

[0057] Figure 2 yes Figure 1 A schematic diagram of one possible implementation of a storage device. Figure 2 The architecture is based on bank sequences and uses a storage cell numbering machine to manage the sequence numbers of all storage cells waiting to be accessed. For example... Figure 2 As shown, the storage device may include multiple storage units 210 and a numbering machine 220.

[0058] The multiple storage units 210 are multiple storage units that can be accessed in parallel, and can be multiple banks, from Bank(0) to Bank(n), where n can be, for example, 16. The multiple storage units 210 can be based on a bank sequence architecture. For example, 16 banks are divided into 4 groups, each group including 4 banks, such as Bank(0) to Bank(3) as a group.

[0059] The numbering machine 220 is connected to multiple storage units 210 and is used to receive first memory access commands for the multiple storage units 210. The first memory access command may include a read command or a write command.

[0060] The Bank numbering machine 220 can set the number of banks in the open state based on the number of banks that can be accessed in parallel, i.e., set a threshold. The numbering machine 220 limits the number of banks in the open state, that is, it limits the activation commands corresponding to the first memory access commands of multiple banks. If the total number of banks is 16, the threshold can be set to 12, and the maximum number of banks in the open state is 12, that is, 12 banks can independently read / write data at the same time.

[0061] After receiving a first memory access command for multiple banks, the numbering machine 220 generates an activation command corresponding to the first memory access command when the number of banks in the multiple storage units 210 that are in the open state is less than a set threshold. When the number of banks in the multiple storage units 210 that are in the open state is greater than or equal to the set threshold, the numbering machine 220 does not generate an activation command corresponding to the first memory access command.

[0062] In some embodiments, a cycle time period can be set. During the cycle time period, the idle / busy status of the numbering machine 220 is determined, and a set threshold is adjusted.

[0063] The cycle time period can employ a tick-tock timer mechanism, with the global time wheel of the tick-tock microarchitecture serving as a time reference. In some use cases, access to the storage device is periodic, or intermittently idle and frequently accessed. In some embodiments, a first time window can be set within the cycle time period. Within the first time window, the numberer 220 receives and processes the first memory access commands of multiple storage units 210. Outside the first time window, the numberer 220 receives the first memory access commands of multiple storage units 210 but does not process them, waiting for them to arrive within the time window before processing them. Within the first time window, the numberer 220 checks the open status of multiple storage units 210, receives and processes the first memory access commands of multiple storage units 210, maximizing power savings while ensuring efficiency.

[0064] Within the loop time period, the time of the first time window can be adjusted, the start time of the first time window can be set or adjusted, and the stop time of the first time window can also be set or adjusted.

[0065] In some embodiments, a pair of periodic time registers can be set for a first time window. One register is used for the start time of the first time window, serving as the start of timing. The second register is used for the end time of the first time window, serving as the stop register, serving as the end of timing. The time difference between the stop register and the start register is the time period of the first time window. When the global timer's time equals the start register's time, the numberer 220 can set the enable bit for the memory cell status category and allow counting from the memory cell's status category. When the global timer's time equals the stop register's time, the numberer 220 resets the enable bit for the memory cell status category and stops checking the memory cell status category. If the start register and stop register are configured with the same value, the stop register has priority and does not allow access to the memory cell's status category.

[0066] In some embodiments, the numbering machine 220 may be divided into idle time and blocked time in the first time window to reflect the idle and busy status of the numbering machine 220 in the first time window.

[0067] In some implementations, an idle time counter (Idle CNT) can be set to count idle time. For example, when numbering machine 220 is in the Rdy Assert and Vld Deassert states, Idle CNT is incremented. A block time counter (Block CNT) can also be set to count block time. For example, when numbering machine 220 is in the Vld Assert and Rdy Deassert states, Block CNT is incremented. The sum of the idle time and the block time is the total time of the first time window.

[0068] Two thresholds can be set for idle time: a total cycle time threshold and a first threshold, also known as the idle threshold. Similarly, two thresholds can be set for blocking time: a total cycle time threshold and a second threshold, also known as the blocking threshold. For example, in a clock mechanism with a cycle time of 3.2 microseconds corresponding to 128 scales, the total cycle time threshold can be 100 scales, the first threshold can be initially set to 35 scales, and the second threshold can be initially set to 55 scales.

[0069] like Figure 2 As shown, the numbering machine 220 receives the total number of Banks and the set threshold parameters, and calculates the idle time and blocking time. Based on the busy / idle status of the activation command corresponding to the first memory access command, the numbering machine 220 can adjust the size of the idle threshold and the blocking threshold, as well as the size of the set threshold.

[0070] Figure 3 yes Figure 2 A flowchart illustrating the state switching process of numbering machine 220. (See attached diagram.) Figure 3 As shown, the numbering machine 220 has three states: idle state, monitoring state, and active state. In the idle state, when the numbering machine 220 reaches the start time of the first time window, it switches to the monitoring state. In the monitoring state, the numbering machine 220 can check the status of multiple banks. If the number of banks in the multiple storage units 210 that are in the open state is less than a set threshold, when a first memory access command is received, the numbering machine 220 can generate an activation command corresponding to the first memory access command and switch to the active state. In the monitoring state, the numbering machine 220 waits to receive the first memory access command. If the stop time of the first time window is reached, and no first critical condition is met (e.g., reaching the set threshold, or the blocking time reaching the blocking threshold), the numbering machine 220 switches to the idle state. In the active state, when the bank setting threshold changes, for example, when it decreases, the numbering machine 220 can switch to the idle state.

[0071] Figure 4 yes Figure 2 A schematic diagram of the mechanism setup of the numbering machine 220. (See diagram for example.) Figure 4As shown, the initial parameters of the numbering machine 220 can be set. For example, the total number of banks, the threshold parameter, the total cycle time period can be 128 scales, the initial idle threshold is greater than 30 scales, the initial blocking threshold is greater than 50 scales, etc.

[0072] The numbering machine 220 can set a first condition, also known as a first critical condition. The first condition may include one or more of the following: reaching a set threshold; reaching the start time threshold of a first time window; reaching the stop time threshold of a first time window; reaching the total number threshold of multiple banks 210.

[0073] The numbering machine 220 can be configured with a cyclic time period, which can employ a TickTock timer mechanism as a time reference. In some use cases, access to the storage device is periodic, or intermittently idle and frequently accessed. A first time window can be set within the cyclic time period. A pair of periodic time registers can be set for the first time window, namely a start time register and a stop time register. Adjusting the start time register and the stop time register can increase or decrease the first time window.

[0074] Within the first time window, the numbering machine 220 receives and processes the first memory access commands from multiple memory units 210. Outside the first time window, the numbering machine 220 receives the first memory access commands from multiple memory units 210 but does not process them, waiting for them to arrive within the time window before processing them.

[0075] Optionally, when the numbering machine 220 is idle for a longer period than a first threshold and the first condition is met, the value of the first threshold can be increased based on the adjustment deviation. In this case, it indicates that the controller 120 receives fewer first memory access commands and the numbering machine 220 is idle for a longer period, thus the value of the first threshold can be increased.

[0076] Optionally, if the numbering machine 220 is idle for less than a first threshold time, the value of the first threshold remains unchanged.

[0077] Optionally, if the numbering machine 220 is in a blocked state for a period of time that is less than or equal to the second threshold, the value of the set threshold remains unchanged.

[0078] Optionally, if the numbering machine 220 remains in a blocked state for less than the second threshold time across two or more consecutive cycle periods, the threshold value can be reduced. In this case, it indicates that the numbering machine 220 receives fewer first memory access commands and spends less time in a blocked state, thus allowing for a reduction in the threshold value.

[0079] Optionally, if the numbering machine 220 is in a blocked state for a longer period than the second threshold, the second threshold can be increased, or the set threshold can be increased.

[0080] According to the embodiments of this application, the number threshold of the number of storage units in the access state can be adjusted based on the busy / idle status of the storage units inside the storage device in the usage scenario. Based on the number threshold of the number of storage units in the access state, the number of storage units that can be opened is limited, and the activation command corresponding to the access command is rate-limited, which helps to save power consumption while ensuring efficiency.

[0081] The above text combined Figures 1-4 The device embodiments of this application are described in detail below, in conjunction with... Figure 5 The present application describes in detail the method embodiments. It should be understood that the description of the method embodiments corresponds to the description of the apparatus embodiments; therefore, any parts not described in detail can be referred to the preceding apparatus embodiments.

[0082] Figure 5 This is a flowchart illustrating the data processing method provided in the embodiments of this application. Figure 5 The method can be applied to the storage device described in any of the preceding embodiments. The storage device may include multiple storage cells and a controller that can be accessed in parallel. Figure 5 The method includes steps S510 to S540, which are described in detail below.

[0083] In step S510, a first memory access command for multiple memory cells is received.

[0084] In step S520, it is determined whether the number of memory cells in the open state among the multiple memory cells is less than a set threshold. If it is less than the set threshold, proceed to step S530; if it is not less than the set threshold, proceed to step S540.

[0085] In step S530, if the number of memory cells in the open state is less than a set threshold, an activation command corresponding to the first memory access command is generated, and no restrictions are placed on the activation command corresponding to the access command.

[0086] In step S540, no activation command is generated corresponding to the first memory access command, and rate limiting is applied to the activation command corresponding to the access command.

[0087] Figure 6 This is a schematic diagram of the data processing system provided in an embodiment of this application. For example... Figure 6 As shown, the data processing system may include a storage device 610 and a processor 620 as described above.

[0088] The processor 620 is connected to the storage device 610 via a data bus to perform data processing.

[0089] It should be understood that in the various embodiments of this application, "first," "second," etc., are used to distinguish different objects, rather than to describe a specific order. The order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0090] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0091] In the embodiments provided in this application, it should be understood that when a part is referred to as "connected" or "linked" to another part, it means that the part can be "directly connected" and also "electrically connected," with another element involved. Furthermore, the term "connected" also means that the parts are "physically connected" and "wirelessly connected." Additionally, when a part is referred to as "containing" an element, unless otherwise stated, it means that the part may include, but does not exclude, the other element.

[0092] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0093] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0094] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage device, characterized in that, include: Multiple storage units that can be accessed in parallel; The controller is used to perform the following operations: Receive a first memory access command for the plurality of memory units; In response to the fact that the number of memory cells in the plurality of memory cells that are in the open state is less than a set threshold, an activation command corresponding to the first memory access command is generated; If the number of memory cells in the plurality of memory cells that are in the open state is greater than or equal to the set threshold, no activation command corresponding to the first memory access command is generated. The controller is also used to perform the following operations: Determine the duration during which the controller is in a blocked state; The set threshold is adjusted based on the duration the controller is in the blocked state. The blocking state time is the time when the number of open storage units among the plurality of storage units is less than the set threshold, after the controller receives the first memory access command and generates the activation command corresponding to the first memory access command.

2. The storage device according to claim 1, characterized in that, The controller is used to perform the following operations: The set threshold is adjusted according to the idle / busy status of the multiple storage units.

3. The storage device according to claim 1, characterized in that, The controller is used to perform the following operations: If the controller is in a blocked state for a longer period than the second threshold, the value of the set threshold remains unchanged.

4. The storage device according to claim 1, characterized in that, The controller is used to perform the following operations: If the controller remains in a blocked state for two or more times without reaching the second threshold, the value of the set threshold is reduced.

5. A data processing method, characterized in that, Applied to a storage device, the storage device comprising: Multiple storage units that can be accessed in parallel; Controller; The method includes: Receive a first memory access command for the plurality of memory units; In response to the fact that the number of memory cells in the plurality of memory cells that are in the open state is less than a set threshold, an activation command corresponding to the first memory access command is generated; If the number of memory cells in the plurality of memory cells that are in the open state is greater than or equal to the set threshold, no activation command corresponding to the first memory access command is generated. The method further includes: Determine the duration during which the controller is in a blocked state; The set threshold is adjusted based on the duration the controller is in the blocked state. The blocking state time is the time when the number of open storage units among the plurality of storage units is less than the set threshold, after the controller receives the first memory access command and generates the activation command corresponding to the first memory access command.

6. The method according to claim 5, characterized in that, The method includes: The set threshold is adjusted according to the idle / busy status of the multiple storage units.

7. A data processing system, characterized in that, It includes a processor and a storage device as described in any one of claims 1-4.

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