Multiple-level interval sensing circuit and sensing method with multiple hysteresis

Abstract

A multi-level interval sensing circuit and sensing method with multiple hysteresis. The sensing circuit includes: a comparison circuit that compares an input signal with a corresponding limit threshold; and a control circuit that periodically selects the limit threshold and samples the comparison result to perform a judgment step to determine the interval of the input signal. The judgment step includes: S100: when the input signal is higher than the upper limit threshold for m consecutive times, the adjacent higher interval is designated as the next interval, and the judgment step corresponding to the next interval is performed; when the input signal is lower than the corresponding lower limit threshold for m consecutive times, the adjacent lower interval is designated as the next interval, and the judgment step corresponding to the next interval is performed; S200: when no adjacent interval is designated as the next interval, an interval output signal corresponding to the interval is generated, and then the step S100 corresponding to the interval is entered.

Description

Technical Field

[0001] The present invention relates to a sensing circuit with hysteresis, and more particularly to a sensing circuit with multiple hysteresis and multiple level intervals. The present invention also relates to a sensing method with multiple hysteresis and multiple level intervals. Background Art

[0002] See also Figure 1A and Figure 1B , Figure 1A Figure 1 shows a conventional sensing circuit with hysteresis (i.e., a Schmitt trigger comparator 1001) and its time-domain operating waveforms. Schmitt trigger comparator 1001 has a threshold voltage Vth and a hysteresis voltage Vhys, thereby sensing the level of the input signal Vin and determining whether it is in the high or low range. Furthermore, it filters out noise from the input signal Vin, as shown in Figure 1, to obtain a stable output signal Vout. Figure 1B Display corresponds to Figure 1A The output signal of the embodiment corresponds to the characteristic curve of the input signal. The output signal Vout has different characteristics when the input signal Vin is up and down, and there is a hysteresis voltage Vhys between the two characteristic curves.

[0003] Figure 2 A typical circuit diagram of a Schmitt trigger comparator is shown. The hysteresis sensing circuit 1002 is based on an inverter and adds a positive feedback element to achieve the hysteresis function.

[0004] Figure 3 Another conventional sensing circuit (ie, hysteresis sensing circuit 1003 ) is shown. The hysteresis sensing circuit 1003 is configured as a positive feedback operational amplifier circuit to implement a hysteresis function, wherein a reference signal Vref and a feedback resistor determine a hysteresis voltage Vhys.

[0005] Figure 1A 、 Figure 1B 、 Figure 2 and Figure 3 The disadvantage of the prior art hysteresis sensing circuit is that it only has a threshold value and a hysteresis voltage for determining the level range, and the range threshold value and the hysteresis voltage are not easy to set freely.

[0006] Compared to Figure 1A 、 Figures 1B to 3 The advantages of the sensing circuit of the present invention are that it can have multiple hysteresis and multiple interval thresholds, and the levels of the interval thresholds and the multiple hysteresis of the sensing circuit can be freely set. Summary of the Invention

[0007] From one perspective, the present invention provides a multiple-level interval sensing circuit with multiple hysteresis, which is used to sense the level of an input signal and determine whether the level of the input signal is located in one of a plurality of level intervals with hysteresis, wherein each of the level intervals has corresponding multiple limit thresholds and a hysteresis amount, wherein the multiple limit thresholds include a corresponding upper limit threshold and a lower limit threshold; the multiple-level interval sensing circuit with multiple hysteresis includes: a comparison circuit, which generates a comparison result based on the comparison between the input signal and the corresponding limit threshold; and a control circuit, which periodically selects the corresponding limit threshold and samples the comparison result based on a sampling frequency, and performs an interval judgment step to generate an interval output signal indicating the level interval corresponding to the input signal, wherein the corresponding limit threshold is selected from at least one of the limit thresholds corresponding to the interval judgment step, wherein the interval judgment step The method comprises steps S100 and S200, wherein step S100 comprises: step S110: when the input signal is higher than the corresponding upper limit threshold value for a predetermined number of times in a first overdue period, designating an adjacent higher level interval as the next level interval, and performing the interval determination step corresponding to the next level interval; and step S120: when the input signal is lower than the corresponding lower limit threshold value for a predetermined number of times in a second overdue period, designating an adjacent lower level interval as the next level interval, and performing the interval determination step corresponding to the next level interval; wherein when neither step S110 nor step S120 designates any adjacent level interval as the next level interval, performing the corresponding step S200; wherein step S200 comprises: generating the interval output signal corresponding to the level interval, and then entering step S100 corresponding to the level interval.

[0008] In a preferred embodiment, step 110 further includes step S114: determining whether the input signal is lower than the corresponding upper limit threshold for m consecutive times within the first overdue period; step S120 further includes step S124: determining whether the input signal is higher than the corresponding lower limit threshold for m consecutive times within the second overdue period; wherein when neither step S110 nor step S120 specifies any adjacent level interval as the next level interval, and the following conditions are met, the corresponding step S200 is performed: the first overdue period has expired or the judgment result of step S114 is yes, and the second overdue period has expired or the judgment result of step S124 is yes.

[0009] In a preferred embodiment, the interval determination step corresponding to the next level interval is performed in the following order: S200, S100; or S100, S200.

[0010] In a preferred embodiment, the upper lower threshold is equal to the lower upper threshold, so that the hysteresis value is equal to the interval range corresponding to the level interval.

[0011] In a preferred embodiment, when the corresponding level interval is a highest level interval, the upper limit threshold and the lower limit threshold are both empty sets, and the corresponding step S110 is not executed; when the corresponding level interval is a lowest level interval, the upper limit threshold and the lower limit threshold are both empty sets, and the corresponding step S120 is not executed.

[0012] In a preferred embodiment, the input signal corresponds to a voltage form.

[0013] In a preferred embodiment, the control circuit includes a digital filter circuit and an interval determination circuit, wherein the digital filter circuit includes: m flip-flops connected in series, for sampling and transferring the comparison result in a time sequence according to the sampling frequency, wherein the state output signals of the m flip-flops each correspond to m consecutive sampling signals of the comparison result; the interval determination circuit is used to perform the interval determination step based on whether the m consecutive sampling signals are at the same level and / or are overdue.

[0014] In a preferred embodiment, the digital filter circuit further comprises: an AND logic circuit having m input terminals, configured to receive the state output signals of the m flip-flops, determine whether they are all at a high level, and output a filtered positive signal; wherein the interval determination circuit performs the following operations: Step S110 comprises: when the filtered positive signal is enabled within the first overdue period, indicating that the input signal is higher than the corresponding upper threshold for m consecutive times, designating an adjacent higher level interval as the next level interval; Step S120 comprises: when the filtered positive signal is enabled within the second overdue period, indicating that the input signal is lower than the corresponding lower threshold for m consecutive times, designating an adjacent lower level interval as the next level interval; wherein if the corresponding filtered positive signal in Steps S110 and S120 is not enabled within the corresponding first overdue period or the second overdue period, the corresponding Step S200 is performed.

[0015] In a preferred embodiment, the digital filter circuit further includes: another AND logic circuit having m input terminals, for receiving the status output signals of the m flip-flops to determine whether they are all at a low level, and outputting a filtered negation signal; wherein the interval judgment circuit further performs the following operations: step S114 includes: judging whether the input signal is lower than the corresponding upward upper limit threshold for m consecutive times within the first overdue period based on whether the filtered negation signal is enabled within the first overdue period; step S124 includes: judging whether the input signal is higher than the corresponding downward lower limit threshold for m consecutive times within the second overdue period based on whether the filtered negation signal is enabled within the second overdue period.

[0016] In a preferred embodiment, the comparison circuit includes: a comparator for comparing a reference signal with an input-related signal related to the input signal to generate the comparison result; the control circuit also includes: an adjustment circuit for generating a corresponding adjustment signal according to the corresponding limit threshold, for adjusting the input-related signal or the reference signal so that the comparison between the reference signal and the input-related signal corresponds to the comparison between the input signal and the corresponding limit threshold.

[0017] In a preferred embodiment, the interval determination circuit is further configured to time the first overdue period and / or the second overdue period.

[0018] In a preferred embodiment, the interval determination step further includes a reset step S000 , wherein the step S000 includes: resetting the interval output signal, and performing a standard interval step S100 .

[0019] From another perspective, the present invention provides a method for sensing multiple level ranges with multiple hysteresis, for sensing the level of an input signal and determining whether the input signal is within one of multiple level ranges with hysteresis, wherein each level range has corresponding multiple limit thresholds and a hysteresis amount, wherein the multiple limit thresholds include a corresponding upper limit threshold and a corresponding lower limit threshold. The method for sensing multiple level ranges with multiple hysteresis includes: generating a comparison result based on a comparison between the input signal and the corresponding limit threshold; and performing a range determination step based on a sampling frequency, periodically selecting the corresponding limit threshold and sampling the comparison result to generate a range output signal indicating the level range corresponding to the input signal, wherein the corresponding limit threshold is selected from at least one of the limit thresholds corresponding to the range determination step, wherein the range determination step includes step S100. And step S200, wherein step S100 includes: step S110: when the input signal is higher than the corresponding upper limit threshold value for a predetermined number of times in a first overdue period, designate the adjacent higher level interval as the next level interval, and perform the interval judgment step corresponding to the next level interval; and step S120: when the input signal is lower than the corresponding lower limit threshold value for a predetermined number of times in a second overdue period, designate the adjacent lower level interval as the next level interval, and perform the interval judgment step corresponding to the next level interval; wherein when neither step S110 nor step S120 designates any adjacent level interval as the next level interval, perform the corresponding step S200; wherein step S200 includes: generating the interval output signal corresponding to the level interval, and then entering step S100 corresponding to the level interval.

[0020] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1A A conventional sensing circuit with hysteresis and its time-domain operating waveform are shown.

[0022] Figure 1B Display corresponds to Figure 1A The output signal corresponds to the characteristic curve diagram of the input signal.

[0023] Figures 2 and 3 Several prior art hysteresis sensing circuits are shown.

[0024] Figure 4 A characteristic curve diagram showing an embodiment of a sensing circuit according to the present invention.

[0025] Figure 5A characteristic curve diagram showing another embodiment of the sensing circuit according to the present invention.

[0026] Figure 6A A control flow chart showing an embodiment of a sensing circuit according to the present invention is shown. Figure 6B A control flow chart showing another embodiment of a sensing circuit according to the present invention is shown.

[0027] Figures 7 and 8 Control flow charts showing two embodiments of the sensing circuit according to the present invention.

[0028] Figures 9 and 10 Control flow charts showing two other embodiments of the sensing circuit according to the present invention.

[0029] Figure 11 A schematic diagram showing a specific embodiment of a sensing circuit according to the present invention is shown.

[0030] Figures 12A and 12B A control flow chart showing two specific embodiments of the sensing circuit according to the present invention is shown.

[0031] Figure 12C Display corresponds to Figures 12A and 12B Graph showing the characteristics of an embodiment of the present invention.

[0032] Figures 13A and 13B A control flow chart showing two specific embodiments of the sensing circuit according to the present invention is shown.

[0033] Figure 13C Display corresponds to Figures 13A and 13B Graph showing the characteristics of an embodiment of the present invention.

[0034] Figures 14A and 14B A control flow chart showing two specific embodiments of the sensing circuit according to the present invention is shown. DETAILED DESCRIPTION

[0035] The drawings in the present invention are schematic diagrams, mainly intended to illustrate the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn according to scale.

[0036] Figure 4A characteristic curve diagram of an embodiment of a sensing circuit according to the present invention is shown. As shown, the sensing circuit according to the present invention has multiple thresholds, thereby determining the level range corresponding to the input signal Vin. Furthermore, the sensing circuit according to the present invention also has corresponding multiple hysteresis. Specifically, each level range Int[k] has corresponding multiple limit thresholds and corresponding hysteresis. The limit thresholds include an upper limit threshold Vthuu[k], an upper limit threshold Vthul[k], a lower limit threshold Vthdu[k], and a lower limit threshold Vthdl[k]. k is a positive integer from 1 to N, where N is the total number of level ranges corresponding to the input signal Vin, and N is a positive integer greater than 1.

[0037] When the input signal Vin is rising, the upper threshold value Vthuu[k] is used to determine whether the level interval corresponding to the input signal Vin has transitioned from the level interval Int[k] to the adjacent higher level interval Int[k+1], while the upper threshold value Vthul[k] is used to determine whether the level interval corresponding to the input signal Vin has transitioned from the adjacent lower level interval Int[k-1] to the level interval Int[k]. In one embodiment, the upper threshold value Vthuu[k] of the level interval Int[k] is substantially equal to the upper threshold value Vthul[k+1] of the level interval Int[k+1], and the upper threshold value Vthul[k] of the level interval Int[k] is substantially equal to the upper threshold value Vthuu[k-1] of the level interval Int[k-1].

[0038] On the other hand, when the signal Vin is falling, the lower threshold Vthdl[k] is used to determine whether the level interval corresponding to the input signal Vin has transitioned from the level interval Int[k] to the adjacent lower level interval Int[k-1], while the upper threshold Vthdu[k] is used to determine whether the level interval corresponding to the input signal Vin has transitioned from the adjacent higher level interval Int[k+1] to the level interval Int[k]. In one embodiment, the lower threshold Vthdl[k] of the level interval Int[k] is substantially equal to the upper threshold Vthdu[k-1] of the level interval Int[k-1], and the upper threshold Vthdu[k] of the level interval Int[k] is substantially equal to the lower threshold Vthdl[k+1] of the level interval Int[k+1].

[0039] Specifically Figure 4For example, the level interval Int[3] corresponds to a limit threshold value including an upper limit threshold value Vthuu[3] = 2.2V, an upper limit threshold value Vthul[3] = 2.1V, a lower limit threshold value Vthdu[3] = 2.12V, and a lower limit threshold value Vthdl[3] = 2.02V. In this embodiment, the interval range Vstp of each level interval is 0.1V (excluding the highest and lowest level intervals), that is, the difference between the upper limit threshold value Vthuu[3] and the upper limit threshold value Vthul[3] (2.2-2.1=0.1), or the difference between the lower limit threshold value Vthdu[3] and the lower limit threshold value Vthdl[3] (2.12-2.02=0.1). It should be noted that, in one embodiment, the range of the highest and lowest level intervals may also be 0.1V. In other embodiments, the range of the highest and lowest level intervals may be other different values, which are related to the highest and lowest ranges of the input signal Vin.

[0040] On the other hand, the hysteresis Vhys is 80mV, which is the difference between the upper threshold Vthuu[3] and the lower threshold Vthdu[3] (2.2-2.12=0.08), or the difference between the upper threshold Vthul[3] and the lower threshold Vthdl[3] (2.1-2.02=0.08).

[0041] Figure 5 A characteristic curve diagram of another embodiment of the sensing circuit according to the present invention is shown. Figure 4 The embodiment is similar to the embodiment of Figure 5 In the embodiment, the hysteresis Vhys is equal to the range Vstp and is 0.1V. That is, the corresponding upper lower threshold Vthul[k] is equal to the lower upper threshold Vthdu[k]. Taking the level range Int[3] as an example, the upper lower threshold Vthul[3] and the lower upper threshold Vthdu[3] are both 2.1V. Therefore, the hysteresis Vhys in this embodiment is equal to the range Vstp, both 0.1V.

[0042] Generally speaking, to achieve effective hysteresis, the upper limit threshold Vthuu[k] is higher than the lower limit threshold Vthdu[k], and the upper limit threshold Vthul[k] is higher than the lower limit threshold Vthdl[k].

[0043] Figure 6AA control flow chart of an embodiment of a sensing circuit according to the present invention is shown. Within any designated level range, the sensing circuit of the present invention executes a corresponding range determination step S1000[k]. Based on a sampling frequency, the sensing circuit periodically determines and reassigns the corresponding level range according to the current level of the input signal Vin, and generates a corresponding range output signal Dout, which indicates the corresponding level range of the input signal, for example in digital format. The range determination step S1000[k] includes steps S100[k] and S200[k].

[0044] Please continue reading Figure 6A Step S100[k] includes: Step S110[k]: when the input signal Vin is higher than the corresponding upper limit threshold Vthuu[k] for m consecutive times within a first overdue period (i.e., before the first overdue period expires) (i.e., S111[k] is yes for m consecutive times, i.e., step S112[k] is yes), designate an adjacent higher level interval as the next level interval (corresponding to step S113[k]), and perform the interval determination step corresponding to the next level interval, i.e., relative to the current level interval Int[k], then perform the interval determination step S1000[k+1] corresponding to the level interval Int[k+1].

[0045] It should be noted that, for the sake of convenience, in this embodiment, the sequence number k of the level interval changes in the same direction as the corresponding input signal range. In other words, the larger the k value, the higher the level range of the corresponding input signal Vin.

[0046] It should also be noted that herein, in the comparison steps for determining whether the input signal Vin exceeds the current level interval Int[k], such as steps S111[k] and S121[k], when a "yes" determination is made m times consecutively (i.e., corresponding to a "yes" determination in step S112[k] or step S122[k]), this is indicated by a filtered positive signal mYes, the same below. In a preferred embodiment, m is a positive integer greater than 1. In one aspect, the filtered positive signal mYes indicates that the input signal Vin has continuously exceeded the current level interval Int[k] in the same direction.

[0047] Step S100[k] also includes: Step S120[k]: When the input signal Vin is lower than the corresponding downward lower limit threshold Vthdl[k] for m consecutive times within a second overdue period (i.e., before the second overdue period expires) (i.e., S121[k] is yes for m consecutive times, i.e., step S122[k] is yes), designate an adjacent lower level interval as the next level interval (corresponding to step S123[k]), and perform the interval judgment step S1000[k-1] corresponding to the next level interval Int[k-1].

[0048] In addition, when neither step S110[k] nor step S120[k] designates any adjacent level interval as the next level interval, the corresponding step S200[k] is performed. In other words, when the first overdue period has expired and the input signal Vin has not been higher than the corresponding upper limit threshold Vthuu[k] for m consecutive times (i.e., S115[k] is yes), and when the second overdue period has expired and the input signal Vin has not been lower than the corresponding lower limit threshold Vthdl[k] for m consecutive times (i.e., S125[k] is yes), the corresponding step S200[k] is performed.

[0049] Next, in step 200[k], an interval output signal Dout[k] corresponding to the level interval Int[k] is generated, and then the process proceeds to step S100[k] corresponding to the level interval Int[k].

[0050] In one embodiment, the sampling frequency can be used to determine the time point for comparing the input signal Vin with the limiting threshold in the aforementioned step.

[0051] Please also see Figure 5 Specifically, taking k as 2 and m as 3 as an example, step S110[2] corresponds to: when the input signal Vin is higher than the corresponding upper limit threshold Vthuu[2] (i.e., 2.1V) for three consecutive times within the first overdue period, the level interval Int[3] is designated as the next level interval, and the interval judgment step S1000[3] corresponding to the next level interval Int[3] is performed. Step S120[2] corresponds to: when the input signal Vin is lower than the corresponding lower limit threshold Vthdl[2] (i.e., 1.9V) for three consecutive times within a second overdue period, the level interval Int[1] is designated as the next level interval, and the interval judgment step S1000[1] corresponding to the next level interval Int[1] is performed.

[0052] In addition, when neither step S110[2] nor step S120[2] designates any adjacent level interval as the next level interval, the corresponding step S200[2] is performed. In other words, when the first overdue period has expired and the input signal Vin has not been higher than the corresponding upper limit threshold Vthuu[2] (i.e., 2.1V) for three consecutive times, and when the second overdue period has expired and the input signal Vin has not been lower than the corresponding lower limit threshold Vthdl[2] (i.e., 1.9V) for three consecutive times, the corresponding step S200[2] is performed.

[0053] Next, in step 200[2], an interval output signal Dout[2] corresponding to the level interval Int[2] is generated, and then the process proceeds to step S100[2] corresponding to the level interval Int[2]. In one embodiment, the interval output signal Dout[k] may be a digital signal of at least one bit. For example, Dout[2] may be represented by a binary code 0010, taking 4 bits as an example.

[0054] It should be noted that, in one embodiment, the number of consecutive times of step S111[k] and the number of consecutive times of step S121[k] may be equal, while in other embodiments, the two may not be equal. This embodiment is described by exemplifying that the two are equal (i.e., both are m times), and is not intended to limit the present invention. In addition, the number of times of the aforementioned comparison steps (e.g., S111[k] and S121[k]) is based on the aforementioned sampling frequency for comparison, judgment, and counting. In one embodiment, such as in steps S112[k] and S122[k], the count of the judgment results may be reset upon entering step S110[k] or step S120[k], respectively. In one embodiment, the first overdue period and the second overdue period may be equal, while in other embodiments, the two may not be equal. In one embodiment, the first overdue period and the second overdue period may be related to the aforementioned sampling frequency, that is, for example, they may be counted based on the period of the sampling frequency. In one embodiment, the first overdue period and the second overdue period may be reset when entering step S110[k] or step S120[k], respectively.

[0055] Furthermore, from the perspective of repeating the operation instruction, as shown in step S113[k] in the figure, when the condition of S112[k] is met, the adjacent higher level interval Int[k+1] is designated as the next level interval (i.e., k_nxt=k+1 in S113[k]), and the interval determination step S1000[k_nxt=k+1] corresponding to the next level interval (k_nxt=k+1) is continued. The same applies to k_nxt=k-1 in S123[k]. Here, k_nxt indicates the sequence number of the next level interval, and the same applies hereinafter.

[0056] Figure 6B A control flow chart showing another embodiment of the sensing circuit according to the present invention is shown. Figure 6A The embodiment is similar to the embodiment of Figure 6B Step S110[k] further includes: determining whether the input signal Vin is lower than the corresponding upper limit threshold Vthuu[k] for m consecutive times within the first overdue period (i.e., step S114[k]), and Figure 6B Step S120[k] also includes: determining whether the input signal Vin is higher than the corresponding downward lower limit threshold Vthdl[k] for m consecutive times within the second overdue period (i.e., step S124[k]), wherein when neither step S110[k] nor step S120[k] designates any adjacent level interval as the next level interval, and the first overdue period has expired (S115[k]) or the judgment result of step S114[k] is yes, and the second overdue period has expired (S125[k]) or the judgment result of step S124[k] is yes, the corresponding step S200[k] is performed. It should also be noted that herein, in the comparison steps for determining whether the input signal Vin exceeds the range of the current level interval Int[k], such as steps S111[k] and S121[k], when the "No" determination is made m times consecutively (i.e., corresponding to a "Yes" determination in step S114[k] or step S124[k]), the filtered negative signal mNo is used as an indicator, and the same applies hereinafter. In one aspect, the filtered negative signal mNo indicates that the input signal Vin has not exceeded the range of the current level interval Int[k] for m times consecutively before the corresponding expiration period has expired.

[0057] Specifically, Figure 6A and Figure 6B In this embodiment, multiple level ranges are determined by comparing the input signal Vin with an upper threshold value Vthuu[k] and a lower threshold value Vthdl[k], respectively, each with a corresponding hysteresis. Furthermore, by determining whether the input signal Vin exceeds or does not exceed the limit threshold value m times in a row, a filtering effect is applied to the comparison between the input signal Vin and the limit threshold value. Specifically, after filtering, the comparison between the input signal Vin and the limit threshold value is determined with certainty.

[0058] Furthermore, the first and second overdue periods also filter the comparison between the input signal Vin and the limit threshold. This means that even after filtering, the relationship between the input signal Vin and the limit threshold cannot be definitively determined. Therefore, this embodiment adopts a conservative approach, maintaining the level interval Int[k] unchanged. The filtering bandwidth is related to the aforementioned sampling frequency, the number of consecutive times m, and the first and second overdue periods.

[0059] Figures 7 and 8 Control flow charts showing two embodiments of the sensing circuit according to the present invention. Figure 7 corresponds to Figure 6A and 6B The simplified control flow diagram, Figure 7 In the embodiment, when a range change occurs in step S110[k] or step S120[k], when performing the next range determination step S1000[k_nxt], step S200[k_nxt] is first performed, where k_nxt indicates the order of the next level range, for example, k+1 or k-1, and the same applies hereinafter. Figure 6A and 6B Operational strategies and Figure 7 same.

[0060] Figure 8 Similar to Figure 7 The embodiment is different in that Figure 8 In the embodiment, when a section change occurs in step S110[k] or step S120[k], step S100[k_nxt] is first performed when performing the next section determination step S1000'[k_nxt].

[0061] Figures 9 and 10 Control flow charts showing two other embodiments of the sensing circuit according to the present invention. Figure 9 Similar to Figure 7 The embodiment is different in that Figure 9 In the embodiment of step S100'[k], step S120[k] is performed first, and then step S110[k] is performed. Figure 7 In step S100[k], step S110[k] is performed first, and then step S120[k] is performed. Figure 10 Similar to Figure 8 The embodiment is different in that Figure 10 In the embodiment of step S100'[k], step S120[k] is performed first, and then step S110[k] is performed. Figure 8In step S100[k], step S110[k] is performed first, and then step S120[k] is performed.

[0062] It is worth noting that, when the level range is not changed, the step S100[k] (or S100'[k]), S110[k] and S120[k], whichever is executed earlier, will be followed by the step S110[k] and S120[k], whichever is executed later.

[0063] Figure 11 A schematic diagram of a specific embodiment of the sensing circuit according to the present invention (sensing circuit 1011) is shown. In one embodiment, the multi-level interval sensing circuit 1011 with multiple hysteresis includes a comparison circuit 10 and a control circuit 20. The comparison circuit 10 is used to compare the input signal Vin with the corresponding limit threshold to generate a comparison result CPO. The control circuit 20 is used to periodically select the corresponding limit threshold and sample the comparison result CPO based on a sampling frequency, and execute the corresponding interval judgment step S1000[k] to generate an interval output signal Dout to indicate the level interval Int[k] corresponding to the input signal Vin, wherein the corresponding limit threshold is generated according to at least one limit threshold required in the interval judgment step S1000[k]. Specifically, for example, Figure 6B In step S110[k], the comparison circuit 10 is used to compare the input signal Vin with the corresponding upper limit threshold Vthuu[k] (i.e., S111[k]), and in step S120[k], the comparison circuit 10 is used to compare the input signal Vin with the corresponding lower limit threshold Vthdl[k] (i.e., S121[k]).

[0064] It should be noted that, in some embodiments, the comparison circuit 10 does not need to directly compare the input signal Vin with the corresponding limit threshold, but can obtain the corresponding comparison result CPO by comparing related signals. Detailed embodiments are described below.

[0065] Please continue reading Figure 11In one embodiment, the control circuit 20 includes a digital filter circuit 21 and an interval judgment circuit 22. The digital filter circuit 21 includes: m flip-flops (DF[1]-DF[3], taking m=3 as an example), which are connected in series in sequence and are used to sample and transfer the comparison results in a time sequence and periodically based on the sampling frequency, wherein the state output signals of the m flip-flops (i.e., the state output signals Q corresponding to the flip-flops DF[1]-DF[3]) correspond to the m consecutive sampling signals of the comparison results. In other words, the state output signals Q of the flip-flops DF[1]-DF[3] correspond to the comparison results of the latest sampling and the previous two samplings. In addition, in one embodiment, the digital filter circuit 21 also includes: an AND logic circuit 27 with m input terminals, which is used to receive the state output signals of the m flip-flops to determine whether they are all enabled (e.g., high level), and the enabled filtered affirmative signal mYes is used to indicate that the aforementioned step S111[k] or S121[k] is judged as "yes" for m consecutive times. In addition, the interval determination circuit 22 is further configured to determine the next level interval according to whether the m consecutive sampling signals are enabled and / or expired, and then execute the interval determination step S1000 [k_nxt] corresponding to the next level zone Int [k_nxt].

[0066] Specifically, in this embodiment, the interval judgment circuit 22 may correspond to Figure 6A , and the following operations are performed in steps S110[k] and S120[k]: Step S110[k] includes: when the filtered affirmative signal mYes is enabled within the first overdue period, indicating that the input signal Vin is higher than the corresponding upper limit threshold Vthuu[k] for m consecutive times, designating the adjacent higher level interval (i.e., Int[k+1]) as the next level interval. Step S120[k] includes: when the filtered affirmative signal mYes is enabled within the second overdue period, indicating that the input signal Vin is lower than the corresponding lower limit threshold Vthdl[k] for m consecutive times, designating the adjacent lower level interval (i.e., Int[k-1]) as the next level interval. If the corresponding filtered affirmative signal mYes in step S110[k] or step S120[k] is not enabled within the corresponding first overdue period or second overdue period, another step in S100[k] is performed, or the corresponding step S200[k] is performed. In one embodiment, when the corresponding filtered affirmative signal mYes in step S110[k] and step S120[k] is not enabled within the corresponding first overdue period or second overdue period, the corresponding step S200[k] is performed.

[0067] Please continue reading Figure 11In one embodiment, the digital filter circuit 21 further includes: an AND logic circuit 26 having m input terminals, for receiving the status output signals of m flip-flops to determine whether they are all at a low level, and outputting a filtered negation signal mNo to indicate that the aforementioned step S111[k] or S121[k] is judged as "No" for m consecutive times.

[0068] In this embodiment, the interval judgment circuit 22 also corresponds to Figure 6B , and the following operations are performed in step S114[k] and step S124[k]: Step S114[k] includes: judging whether the input signal Vin is lower than the corresponding upper limit threshold Vthuu[k] for m times in a row in the first overdue period according to whether the filtered negation signal mNO is enabled in the first overdue period. Step S124[k] includes: judging whether the input signal Vin is higher than the corresponding lower limit threshold Vthdl[k] for m times in a row in the second overdue period according to whether the filtered negation signal mNo is enabled in the second overdue period. When the corresponding negation signal mNo is not enabled in the corresponding first overdue period or the second overdue period, another step in S100[k] or the corresponding step S200[k] is performed. Specifically, the digital filter circuit 21 is used to perform the following operations: Figure 6B Steps S112[k], S114[k], S122[k] or S124[k] in the process.

[0069] Please continue reading Figure 11 In one embodiment, the comparison circuit 10 includes: a comparator 11, for comparing a reference signal Vref with an input-related signal Vinr related to the input signal Vin to generate a comparison result CPO; in this embodiment, the control circuit 10 further includes: an adjustment circuit 24, for generating a corresponding adjustment signal Adj according to a corresponding limit threshold (for example, corresponding to the upper limit threshold Vthuu[k] in step S111[k] or the lower limit threshold Vthdl[k] in S121[k]), for adjusting the input-related signal Vinr, so that the comparison between the reference signal Vref and the input-related signal Vinr corresponds to the comparison between the input signal Vin and the corresponding limit threshold.

[0070] Specifically, in this embodiment, the adjustment signal Adj is used to adjust the voltage division ratio of the voltage divider circuit 12 to achieve the aforementioned adjustment. In other embodiments, the reference signal can also be adjusted by the adjustment signal Adj to fix the input related signal Vinr. Figure 11 The adjustable voltage divider circuit 12 is re-configured on the path of the reference signal Vref.

[0071] In addition, if the comparison and determination directions in the determination steps S111[k] and S121[k] are different, in one embodiment, the comparison and determination directions may be different. Figure 11 As shown, a logic circuit (e.g., multiplexer 28) is configured after comparator 11 to change its logic level according to the requirements of the determination step. In one embodiment, the comparison results CPOB and CPO are inverted, and the comparison result CPOD is a signal whose logic level is adjusted by multiplexer 28. In other embodiments, this function can also be configured to switch between the non-inverting and inverting input terminals of comparator 11, or a corresponding logic circuit can be used to replace the aforementioned AND logic circuit 26.

[0072] In one embodiment, the interval determination circuit 22 is further configured to time the first overdue period and / or the second overdue period to determine whether timeout (i.e., TO) has occurred in the aforementioned step S110[k] or step S120[k]. In one embodiment, the control circuit 20 further includes an oscillator 23 for providing a clock signal Slow_clk. In this embodiment, the interval determination circuit 22 generates a sampling frequency VDET_CLK based on the clock signal Slow_clk to operate the flip-flops DF[1]-DF[3] to periodically sample the comparison result based on the aforementioned sampling frequency. In one embodiment, the digital filter circuit 21 further includes a flip-flop 25 coupled between the comparator 11 and the flip-flops DF[1]-DF[3] to pre-sample the comparison result CPO (or CPOD) based on a clock signal that is inversely phased with the flip-flops DF[1]-DF[3], thereby ensuring that the comparison result CPO sampled by the digital filter circuit 21 has reached stability.

[0073] Next, several more specific embodiments will be proposed based on the aforementioned sensing circuit 1011 and the aforementioned interval determination process.

[0074] Figures 12A and 12B A control flow chart showing two specific embodiments of the sensing circuit according to the present invention is shown. Figure 12C Display corresponds to Figures 12A and 12B In this embodiment, the sensing circuit has three level intervals (Int[1], Int[2], Int[3]), and the interval range Vstp and hysteresis are both 0.1V (in one embodiment, excluding the highest and lowest level intervals). Specifically, taking the level interval Int[2] as an example, Figure 12C As shown, the corresponding limiting thresholds include an upper limit threshold Vthuu[2]=2.1V, an upper limit threshold Vthul[2]=2.0V, a lower limit threshold Vthdu[2]=2.0V, and a lower limit threshold Vthdl[2]=1.9V.

[0075] It is worth noting that in this embodiment, the level interval Int[3] is the highest level interval, therefore, it only has an upper lower limit threshold Vthul[3]=2.1V and a lower lower limit threshold Vthdl[3]=2.0V, but no upper limit threshold. In addition, the level interval Int[1] is the lowest level interval, therefore, it only has an upper upper limit threshold Vthuu[1]=2.0V and a lower upper limit threshold Vthdu[1]=1.9V, but no lower limit threshold.

[0076] See also Figure 12A In one embodiment, the Figure 6B 、 Figure 7 and Figure 11 And get Figure 12A A specific interval judgment process is provided, so that the sensing circuit has Figure 12C The characteristic curve of the present invention is first reset in step S000. In the reset step S000, the interval output signal Dout is first reset, and the order of the level interval is reset at the same time. For example, in this embodiment, the initial level interval is designated as Int[3], and the corresponding interval judgment step S1000[3] is performed. Then, step S120[3] in step S100[3] is executed, that is, whether the input signal Vin is lower than the lower limit threshold value Vthdl[3] (2.0V) for more than m times in a row. When the filtered affirmative signal mYes turns to enable before the timeout, k=2 is designated, and the interval judgment step S1000[2] corresponding to the next level interval Int[2] is performed. In this embodiment, the initial level interval is designated as Int[3]. Figure 7 , when performing the interval judgment step S1000[2], first perform step S200[2].

[0077] If step S120[3] expires, or the filtered negation signal mNo is enabled before the timeout, the corresponding step S200[3] is performed, that is, the interval output signal Dout is updated to correspond to the level interval Int[3].

[0078] Please continue reading Figure 12A When k=2 is specified, the interval judgment step S1000[2] will be performed. This embodiment corresponds to Figure 7When performing the interval judgment step S1000[2], first perform step S200[2], that is, first update the interval output signal Dout to correspond to the level interval Int[2], then perform steps S110[2] and S120[2] in S100[2], and then decide to perform the adjacent interval judgment step S1000[1] or interval judgment step S1000[3] based on similar judgment results, or maintain the level interval Int[2] and perform the interval judgment step S1000[2] again. By repeating the cycle, the level interval corresponding to the input signal Vin can be judged, and the function of hysteresis and filtering can be achieved at the same time.

[0079] It should be noted that the reset step S000 can arbitrarily specify the initial value of the interval sequence k and enter the step S100[k] of the corresponding initial level interval Int[k]. After resetting the step S000, it can be connected to one of the steps S110[k] or S120[k].

[0080] also, Figure 12A The order of step S110[2] and step S120[2] in the interval judgment step S1000[2] can be as follows Figure 9 The modes shown are interchangeable with each other.

[0081] See also Figure 12B In one embodiment, Figure 12C The embodiment can be based on Figure 6B 、 Figure 8 and Figure 11 And get Figure 12B A specific interval judgment process, Figure 12B Examples and Figure 12A Similarly, the difference is that when the level interval changes and it is decided to perform the adjacent interval determination step S1000[k_nxt], step S100[k_nxt] is performed first. Specifically, in this embodiment, if step S110[k_nxt] is present, step S110[k_nxt] is performed first. As mentioned above, in other embodiments, step S120[k_nxt] may also be performed first.

[0082] In addition, it is worth noting that, in this embodiment, when determining to perform the adjacent interval determination step S1000 [k_nxt], step S100 [k_nxt] is performed first, rather than step S200 [k_nxt] (i.e., generating the interval output signal Dout indicating the corresponding level interval). Therefore, compared with the embodiment, Figure 12A For the embodiment, the input signal Vin has a higher filtering effect.

[0083] Figures 13A and 13BA control flow chart showing two specific embodiments of the sensing circuit according to the present invention is shown. Figure 13C Display corresponds to Figures 13A and 13B Graph showing the characteristics of an embodiment of the present invention. Figure 13C In the embodiment, there are only two level intervals Int[1] and Int[2], so the level intervals Int[1] and Int[2] correspond to the lowest and highest level intervals respectively. Figures 13A and 13B Respectively Figures 12A and 12B Similarly, it shows that the multi-level range sensing circuit with multiple hysteresis according to the present invention can also be used in applications with only a single threshold (upward or downward) for determining the level range and a single hysteresis voltage.

[0084] Figures 14A and 14B A control flow chart showing two specific embodiments of the sensing circuit according to the present invention is shown. Figures 14A and 14B corresponds to Figure 5 A specific embodiment of Figures 14A and 14B and respectively Figures 12A and 12B Similarly, it shows that the multi-level range sensing circuit with multiple hysteresis according to the present invention can be generalized and extended to applications with any number of level ranges and requiring hysteresis.

[0085] The aforementioned input signal Vin can correspond to a voltage form, a current form, a power form, or any other form that requires distinguishing a level range. By simply configuring a corresponding comparison circuit according to the signal form, all the aforementioned embodiments can be used to determine the level range of the input signal.

[0086] It is worth noting that a non-limiting example of the application of the present invention is for detecting the power supply voltage of a wireless mouse. The level range corresponding to the power supply voltage determined according to the present invention can have high precision and low noise, and can be used in a wireless mouse. For example, parameters such as positioning accuracy, speed, and light intensity can be adjusted accordingly to the power supply voltage, thereby optimizing battery life and mouse performance.

[0087] The present invention has been described above with respect to the preferred embodiments, but the above description is only for those skilled in the art to easily understand the content of the present invention and is not intended to limit the broadest scope of the present invention. The various embodiments described are not limited to individual applications, but can also be applied in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or calculating or generating an output result according to a certain signal", which is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or ratio conversion on the signal, and then processing or calculating the converted signal to generate an output result. It can be seen that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed here one by one. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A multi-level range sensing circuit with multiple hysteresis, configured to sense the level of an input signal and determine whether the input signal's level is within one of a plurality of level ranges with hysteresis, the plurality of level ranges being arranged in order according to the level of the input signal, wherein each level range has corresponding limit thresholds and a hysteresis, wherein the plurality of limit thresholds include a corresponding upper limit threshold and a lower limit threshold. The multi-level range sensing circuit with multiple hysteresis comprises: a comparison circuit for generating a comparison result based on a comparison between the input signal and the corresponding limit threshold; and a control circuit configured to periodically select the corresponding limit threshold based on a sampling frequency and sample the comparison result to perform a range determination step to generate a range output signal indicating the level range corresponding to the input signal, wherein the corresponding limit threshold is selected from at least one limit threshold corresponding to the range determination step, wherein the range determination step includes steps S100 and S200, wherein a current level range is determined based on the previous range determination step or a reset step; Step S100 includes: Step S110: When the input signal exceeds the upper limit threshold corresponding to the current level interval for a predetermined number of times consecutively within a first overdue period, designate an adjacent level interval among the multiple level intervals whose corresponding input signal level range is higher than the current level interval as a next level interval, and perform the interval determination step corresponding to the next level interval; as well as Step S120: When the input signal is lower than the lower limit threshold corresponding to the current level interval for a predetermined number of times consecutively within a second overdue period, designate an adjacent level interval among the multiple level intervals whose corresponding input signal level range is lower than the current level interval as a next level interval, and perform the interval determination step corresponding to the next level interval; When neither step S110 nor step S120 designates any adjacent level interval as the next level interval, the corresponding step S200 is performed; in Step S200 includes generating the interval output signal corresponding to the level interval, and then entering step S100 corresponding to the level interval.

2. The multi-level range sensing circuit with multiple hysteresis as claimed in claim 1, wherein: Step 110 further includes step S114: determining whether the input signal is lower than the corresponding upper limit threshold value for a corresponding predetermined number of times continuously within the first overdue period; Step S120 further includes step S124: determining whether the input signal is higher than the corresponding downward lower limit threshold for a corresponding predetermined number of times continuously within the second overdue period; When neither step S110 nor step S120 designates any adjacent level interval as the next level interval, and the following conditions are met, the corresponding step S200 is performed: The first overdue period has expired or the determination result of step S114 is yes, and the second overdue period has expired or the determination result of step S124 is yes.

3. The multi-level range sensing circuit with multiple hysteresis as claimed in claim 1, wherein: The following steps are followed to determine the interval corresponding to the level interval: Step S200, step S100; or Step S100, step S200.

4. The multi-level range sensing circuit with multiple hysteresis as claimed in claim 1, wherein: The hysteresis is equal to the interval range corresponding to the level interval.

5. The multi-level range sensing circuit with multiple hysteresis as claimed in claim 1, wherein: When the corresponding level interval is a highest level interval, the corresponding step S110 is skipped; When the corresponding level interval is a lowest level interval, the corresponding step S120 is skipped.

6. The multi-level range sensing circuit with multiple hysteresis as claimed in claim 1, wherein: The input signal corresponds to a voltage form.

7. The multi-level range sensing circuit with multiple hysteresis as claimed in claim 2, wherein: The control circuit includes a digital filter circuit and an interval judgment circuit, wherein The digital filter circuit includes: a corresponding predetermined plurality of flip-flops connected in series for sampling and transferring the comparison result in a time sequence according to the sampling frequency, wherein the state output signals of the corresponding predetermined plurality of flip-flops each correspond to a predetermined plurality of consecutive sub-sampling signals of the comparison result; The interval determination circuit is used to execute the interval determination step according to whether the corresponding predetermined plurality of consecutive sub-sampling signals are at the same level and / or are overdue.

8. The multi-level range sensing circuit with multiple hysteresis as claimed in claim 7, wherein: The digital filtering circuit also includes: A logic circuit having a corresponding plurality of predetermined input terminals, for receiving the status output signals of the corresponding plurality of predetermined flip-flops to determine whether they are all enabled, and enabling a filtered positive signal; The interval judgment circuit performs the following operations: Step S110 includes: when the filtered positive signal becomes enabled within the first overdue period, indicating that the input signal is higher than the corresponding upper limit threshold for a corresponding predetermined number of times, designating an adjacent level interval among the plurality of level intervals whose corresponding input signal level range is higher than the current level interval as a next level interval; Step S120 includes: when the filtered positive signal becomes enabled within the second overdue period, indicating that the input signal is lower than the corresponding lower threshold for a corresponding predetermined number of times, designating an adjacent level interval among the plurality of level intervals whose corresponding input signal level range is lower than the current level interval as a next level interval; and When the corresponding filtered affirmative signals in step S110 and step S120 are not turned to enabled within the corresponding first overdue period or the corresponding second overdue period, the corresponding step S200 is performed.

9. The multi-level range sensing circuit with multiple hysteresis as claimed in claim 8, wherein: The digital filtering circuit also includes: Another AND logic circuit having corresponding predetermined multiple input terminals, for receiving the status output signals of the corresponding predetermined multiple flip-flops to determine whether they are all prohibited and enable a filtered negation signal; The interval determination circuit further performs the following operations: Step S114 includes: determining whether the input signal is lower than the corresponding upper limit threshold for a corresponding predetermined number of times continuously within the first overdue period according to whether the filtered negative signal is enabled within the first overdue period; and Step S124 includes: determining whether the input signal is higher than the corresponding downlink lower threshold for a corresponding predetermined number of times in the second overdue period according to whether the filtered negative signal is enabled in the second overdue period.

10. The multi-level range sensing circuit with multiple hysteresis as claimed in claim 7, wherein: The comparison circuit includes: a comparator for comparing a reference signal with an input-related signal related to the input signal to generate the comparison result; The control circuit also includes: an adjustment circuit for generating a corresponding adjustment signal according to the corresponding limit threshold, for adjusting the input-related signal or the reference signal so that the comparison between the reference signal and the input-related signal corresponds to the comparison between the input signal and the corresponding limit threshold.

11. The multi-level range sensing circuit with multiple hysteresis as claimed in claim 7, wherein: The interval determination circuit is further configured to time the first overdue period and / or the second overdue period.

12. The multi-level range sensing circuit with multiple hysteresis as claimed in claim 1, wherein: The interval determination step further includes the resetting step, wherein the resetting step includes: Reset the output signal of this interval; designating an initial level range as the current level range; and Step S100 corresponding to the initial level interval is performed.

13. A method for sensing multiple level ranges with multiple hysteresis, the method comprising: sensing the level of an input signal to determine whether the input signal is within one of a plurality of level ranges with hysteresis; the plurality of level ranges being arranged in order of the input signal level; each level range having corresponding limit thresholds and a hysteresis; the plurality of limit thresholds including a corresponding upper limit threshold and a lower limit threshold; the method comprising: generating a comparison result according to the comparison between the input signal and the corresponding limit threshold; and Based on a sampling frequency, the corresponding limit threshold is periodically selected and the comparison result is sampled to perform a range determination step to generate a range output signal indicating the level range corresponding to the input signal, wherein the corresponding limit threshold is selected from at least one limit threshold corresponding to the range determination step. The range determination step includes steps S100 and S200, wherein a current level range is determined based on the previous range determination step or a reset step; Step S100 includes: Step S110: When the input signal exceeds the upper limit threshold corresponding to the current level interval for a predetermined number of times consecutively within a first overdue period, designate an adjacent level interval among the multiple level intervals whose corresponding input signal level range is higher than the current level interval as a next level interval, and perform the interval determination step corresponding to the next level interval; as well as Step S120: When the input signal is lower than the lower limit threshold corresponding to the current level interval for a predetermined number of times consecutively within a second overdue period, designate an adjacent level interval among the multiple level intervals whose corresponding input signal level range is lower than the current level interval as a next level interval, and perform the interval determination step corresponding to the next level interval; When neither step S110 nor step S120 designates any adjacent level interval as the next level interval, the corresponding step S200 is performed; in Step S200 includes generating the interval output signal corresponding to the level interval, and then entering step S100 corresponding to the level interval.

14. The method of claim 13 for sensing multiple level ranges with multiple hysteresis, wherein: Step 110 further includes step S114: determining whether the input signal is lower than the corresponding upper limit threshold value for a corresponding predetermined number of times continuously within the first overdue period; Step S120 further includes step S124: determining whether the input signal is higher than the corresponding downward lower limit threshold for a corresponding predetermined number of times continuously within the second overdue period; When neither step S110 nor step S120 designates any adjacent level interval as the next level interval, and the following conditions are met, the corresponding step S200 is performed: The first overdue period has expired or the determination result of step S114 is yes, and the second overdue period has expired or the determination result of step S124 is yes.

15. The method of claim 13 for sensing multiple level ranges with multiple hysteresis, wherein: The following steps are followed to determine the interval corresponding to the level interval: Step S200, step S100; or Step S100, step S200.

16. The method of claim 13 for sensing multiple level ranges with multiple hysteresis, wherein: The hysteresis is equal to the interval range corresponding to the level interval.

17. The method of claim 13 for sensing multiple level ranges with multiple hysteresis, wherein: When the corresponding level interval is a highest level interval, the corresponding step S110 is skipped; When the corresponding level interval is a lowest level interval, the corresponding step S120 is skipped.

18. The method of claim 13 for sensing multiple level ranges with multiple hysteresis, wherein: The input signal corresponds to a voltage form.

19. The method of claim 13 for sensing multiple level ranges with multiple hysteresis, wherein the range determination step further comprises the resetting step, wherein the resetting step comprises: Reset the output signal of this interval; designating an initial level range as the current level range; as well as Step S100 corresponding to the initial level interval is performed.

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