Silicon wafer processing method

Abstract

The application provides a silicon wafer processing method, comprising the following steps: establishing flatness models of the first to the nth single-step processes, and establishing a flatness model of a final product according to the flatness models; obtaining a target flatness of the mth single-step process according to the flatness model of the final product, and performing the mth single-step process on the silicon wafer combined with the flatness model of the mth single-step process, and obtaining an actual flatness of the mth single-step process; adjusting the target flatness of the m+1th single-step process by using the actual flatness of the mth single-step process, and performing the m+1th single-step process on the silicon wafer combined with the flatness model of the m+1th single-step process; wherein n is a positive integer greater than 1, and m=1, 2,..., n-1. The target flatness of the single-step process is set by using the above model, the process parameters and the equipment parameters of the corresponding single-step process are optimized, and the difference between the target flatness and the actual flatness of the previous single-step process is adjusted by using the next single-step process, thereby solving the problem of improving the flatness of the silicon wafer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit manufacturing, and particularly relates to a silicon wafer processing method. BACKGROUND

[0002] With the development of integrated circuit processing technology, especially the improvement of chip integration and working frequency, the requirement for the flatness of large-size silicon wafers is also higher and higher. The flatness of a silicon wafer generally includes ESFQR (Edge Site Frontsurface referenced least sQuares / Range), SFQR (Site Frontsurface referenced least sQuares / Range), GBIR (Global Backsurface-referenced Ideal plane / Range) and other flatness indexes.

[0003] Taking the processing of a 300mm-diameter silicon wafer for integrated circuits as an example, the process starts from a crystal bar and generally includes wire cutting, grinding, chemical etching, double-side polishing, final polishing, epitaxy and other processes. Each process has a specific and different impact on the flatness of the silicon wafer. Meanwhile, the impact is irreversible. Under the condition of a certain overall polishing thickness, the result of a previous process directly affects the process adjustment margin of a subsequent process, so that the silicon wafer cannot finally obtain the optimal flatness.

[0004] Therefore, there is an urgent need for a processing method for improving the flatness of a silicon wafer. SUMMARY

[0005] The present application aims to provide a silicon wafer processing method to solve the problem of improving the flatness of a silicon wafer.

[0006] To solve the above technical problems, the present application provides a silicon wafer processing method, comprising: establishing a flatness model of the first to the nth single-step process, and establishing a flatness model of a final product according to the flatness model of the first to the nth single-step process; obtaining a target flatness of the mth single-step process according to the flatness model of the final product, performing the mth single-step process on a product silicon wafer based on the flatness model of the mth single-step process and the target flatness of the mth single-step process, and obtaining actual flatness data of the mth single-step process; adjusting the flatness model of the final product according to the actual flatness data of the mth single-step process to obtain a target flatness of the m+1th single-step process, and performing the m+1th single-step process on the product silicon wafer based on the flatness model of the m+1th single-step process and the target flatness of the m+1th single-step process; wherein n is a positive integer greater than 1, and m = 1, 2,..., n-1.

[0007] Optionally, the first to the nth single-step process are in turn a double-sided polishing process, a final polishing process, and an epitaxial process.

[0008] Optionally, the planarization capability of the double-sided polishing process is greater than that of the final polishing process, and the planarization capability of the final polishing process is greater than that of the epitaxial process.

[0009] Optionally, the flatness model of the final product is Toutput = Tinput - Tdsp - Tfp + Tepi; wherein Tinput is a flatness model before the double-sided polishing process, Tdsp is a flatness model of the double-sided polishing process, Tfp is a flatness model of the final polishing process, and Tepi is a flatness model of the epitaxial process.

[0010] Optionally, the flatness model of the double-sided polishing process is related to pressure of the double-sided polishing process, time of the double-sided polishing process, Gap of the double-sided polishing process, equipment number of the double-sided polishing process, polishing pad of the double-sided polishing process, and number of input silicon wafers of the double-sided polishing process.

[0011] Optionally, the flatness model of the final polishing process is related to polishing partition pressure of the final polishing process, time of the final polishing process, equipment number of the final polishing process, polishing head number of the final polishing process, polishing pad of the final polishing process, and number of input silicon wafers of the final polishing process.

[0012] Optionally, the flatness model of the epitaxial process is related to gas flow of the epitaxial process, temperature of the epitaxial process, power distribution of the epitaxial process, epitaxial equipment number, and number of input silicon wafers of the epitaxial equipment.

[0013] Optionally, the flatness model of each single-step process is established by using machine learning method according to historical data of each single-step process.

[0014] Optionally, the historical data of each single-step process comprises process parameters, equipment parameters and actual flatness data of the corresponding single-step process.

[0015] Optionally, the actual flatness data of each single-step process is measured by using a flatness tester.

[0016] In summary, the silicon wafer processing method provided by the present application optimizes the target flatness of each single-step process and the process parameters and equipment parameters of the corresponding single-step process by using the established flatness model of the final product and the flatness model of each single-step process, and can also adjust the next single-step process based on the flatness model of the final product according to the difference between the target flatness and the actual flatness of the previous single-step process during the execution of the single-step process, so as to obtain a better final flatness and improve the silicon wafer flatness. BRIEF DESCRIPTION OF DRAWINGS

[0017] Those skilled in the art will understand that the provided drawings are for better understanding of the present application and do not constitute any limitation on the scope of the present application. Among them:

[0018] Figure 1 is a flowchart of the silicon wafer processing method provided by the present application for improving the silicon wafer flatness.

[0019] Figure 2 is a flowchart of the model established by using machine learning provided by the present application. DETAILED DESCRIPTION

[0020] In order to make the purpose, advantages and characteristics of the present application clearer, the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be noted that the drawings are very simplified and not drawn to scale, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. In addition, the structures shown in the drawings are often part of the actual structures. In particular, the emphasis shown in each drawing is different, and sometimes different scales are used.

[0021] As used in the present application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. The term "or" is generally employed in its sense including "and / or" unless the content clearly dictates otherwise. The term "at least two" is generally employed in its sense including "two or more" unless the content clearly dictates otherwise. In addition, the terms "first," "second," "third," etc. are used only to describe a particular object and do not imply or suggest relative importance or imply a specific number of the indicated technical features. Thus, features qualified with "first," "second," "third," etc. can expressly or implicitly include one or at least two of the features unless the context clearly dictates otherwise.

[0022] The present application provides a silicon wafer processing method, which establishes a flatness model of each single-step process and a flatness model of a final product, executes a corresponding single-step process by using the flatness model of the final product and the flatness model of the single-step process, obtains actual flatness data of the single-step process after each single-step process is executed, adjusts the flatness model of the final product according to the actual flatness data of the single-step process, optimizes a target flatness of each single-step process and execution conditions of the corresponding single-step process, and achieves an optimal process result of the flatness of the final product by a feedback type cyclic optimization mode.

[0023] Figure 1 FIG. 1 is a flowchart of a silicon wafer processing method provided by an embodiment of the present application.

[0024] As shown in FIG. 1, the silicon wafer processing method provided by the embodiment includes the following steps: Figure 1

[0025] S01: Establishing a flatness model of a first single-step process to an nth single-step process, and establishing a flatness model of a final product according to the flatness model of the first single-step process to the nth single-step process;

[0026] S02: Obtaining a target flatness of the mth single-step process according to the flatness model of the final product, executing the mth single-step process on a product wafer based on the flatness model of the mth single-step process and the target flatness of the mth single-step process, and obtaining actual flatness data of the mth single-step process;

[0027] S03: Adjusting the flatness model of the final product according to the actual flatness data of the mth single-step process to obtain a target flatness of the m+1th single-step process, and executing the m+1th single-step process on the product wafer based on the flatness model of the m+1th single-step process and the target flatness of the m+1th single-step process;

[0028] Wherein, n is a positive integer greater than 1, and m = 1, 2,..., n-1. ​

[0029] Specifically, the silicon wafer in the embodiments of the present application can be a silicon wafer after line cutting, grinding and chemical etching process, and the initial flatness thereof is the flatness after chemical etching, including three indexes of ESFQR (Edge Site Frontsurface referenced least sQuares / Range), SFQR (Site Frontsurface referenced least sQuares / Range) and GBIR (Global Backsurface-referenced Ideal plane / Range). It is not difficult to understand that the final target flatness of the silicon wafer is different due to the difference in use, and therefore, the number of single-step processes required by the silicon wafer is also different. For example, the silicon wafer is used to make discrete devices with low requirements, which only needs two single-step processes. In the embodiments of the present application, the flatness requirement of the silicon wafer is high, and three single-step processes are required, which are double-sided polishing process, final polishing process and epitaxial process in sequence.

[0030] In actual process, the effects of double-sided polishing process, final polishing process and epitaxial process on the flatness of the silicon wafer are different. In general, the planarization capability of the double-sided polishing process is greater than that of the final polishing process, and the planarization capability of the final polishing process is greater than that of the epitaxial process. If the target flatness of the previous single-step process is set unreasonably, under the condition that the total polishing thickness is constant, it will seriously affect the flatness of the subsequent single-step process, so that it is difficult to achieve a better final flatness. On the other hand, under different process conditions, the double-sided polishing process, the final polishing process and the epitaxial process can present completely different flatness, and they can be complementary to each other or not. For example, in some specific embodiments, the double-sided polishing process grinds the middle part of the silicon wafer more, resulting in a surface morphology of the silicon wafer with a concave middle part, the final polishing process grinds the edge part of the silicon wafer more to correct the surface morphology of the silicon wafer, and the epitaxial process presents other surface morphology according to the formation mode and type. Therefore, in order to improve the final flatness of the silicon wafer, the flatness of the silicon wafer can be managed as a whole, especially the setting of the target flatness of each single-step process is optimized. Of course, the more preferred scheme is to perform separate process optimization for each single-step process to further improve the flatness of the silicon wafer.

[0031] Figure 2 is a flowchart of establishing a model by machine learning provided by the embodiments of the present application.

[0032] As Figure 2As shown, in the embodiments of the present application, the establishment of the flatness model of the final product and the flatness model of the single-step process can both adopt the same steps, which are as follows:

[0033] S010: Obtain historical data, remove bad samples, pre-process the data, form a first correspondence table and a second correspondence table;

[0034] S011: Train a generation model according to the first correspondence table;

[0035] S012: Verify the model using the second correspondence table, judge whether the verification result is within a preset range, if not, return to modify the model.

[0036] Of course, the historical data obtained for the establishment of the flatness model of the final product and the flatness model of the single-step process are different. The historical data required for the establishment of the flatness model of the single-step process includes the process parameters, equipment parameters and actual flatness data corresponding to the single-step process. Each single-step process can establish a corresponding flatness model, wherein the actual flatness data of the single-step process can be used as the input of the first correspondence table and the second correspondence table, and the process parameters and equipment parameters corresponding thereto can be used as the output.

[0037] In the embodiments, the flatness model of the double-side polishing process is related to the pressure of the double-side polishing process, the time of the double-side polishing process, the Gap (the distance between the polishing pads of the two sides) of the double-side polishing process, the equipment number of the double-side polishing process, the polishing pad of the double-side polishing process, and the number of input silicon wafers of the double-side polishing process. The flatness model of the final polishing process is related to the polishing partition pressure of the final polishing process, the time of the final polishing process, the equipment number of the final polishing process, the polishing head number of the final polishing process, the polishing pad of the final polishing process, and the number of input silicon wafers of the final polishing process. The flatness model of the epitaxial process is related to the gas flow of the epitaxial process, the temperature of the epitaxial process, the power distribution of the epitaxial process, the epitaxial equipment number, and the number of input silicon wafers of the epitaxial equipment.

[0038] The historical data obtained by establishing the flatness model of the final product includes initial flatness and flatness of each single-step process (including n single-step processes, n is a positive integer greater than 1), wherein the initial flatness can be the flatness before processing of the silicon wafer (setting of the target flatness of the first single-step process), or can be the actual flatness of the previous single-step process (setting of the target flatness of the mth single-step process, 2≤m≤n-1), and the flatness of the final product is the actual flatness of the last single-step process (the nth single-step process). In practice, in order to improve the accuracy of the setting of the target flatness of the single-step process, the flatness model of the final product can also be further classified according to different types of silicon wafers (N-type or P-type) and the adopted epitaxial formation mode. The initial flatness and the actual flatness of the previous single-step process can be the input of the first corresponding table and the second corresponding table, and the target flatness of the next single-step process is the output. It should be noted that, unlike the flatness model of the single-step process, the flatness model of the final product can dynamically adjust the target flatness of the next single-step process according to the actual flatness of the previous single-step process, so as to improve the final flatness of the silicon wafer. The specific process is as follows: the actual flatness of the previous single-step process is substituted (input) into the flatness model of the final product, and the target flatness of the next single-step process is obtained (output).

[0039] In the embodiment, in combination with the previously established flatness models of the single-step processes, the flatness model Toutput of the final product can be represented as:

[0040] Toutput=Tinput-Tdsp-Tfp+Tepi;

[0041] Wherein, Tinput is the flatness model before the double-side polishing process, Tdsp is the flatness model of the double-side polishing process, Tfp is the flatness model of the final polishing process, and Tepi is the flatness model of the epitaxial process. In the processing of the silicon wafer, the double-side polishing process and the final polishing process are both grinding processes, which thin the overall thickness of the silicon wafer, while the epitaxial process is a growth process, which increases the overall thickness of the silicon wafer. The changes in the overall thickness of the silicon wafer can be used to represent the single-step processes and to schematically represent the changes in flatness.

[0042] It should be noted that the historical data obtained above can first remove bad data, i.e. data that is obviously not in the normal range or deviates from the normal range, before forming the first corresponding table and the second corresponding table, and then the data is preprocessed.

[0043] Specifically, the first correspondence table is used to generate a model by machine learning training, and the second correspondence table is used to verify the model. The data amount of the first correspondence table is larger, for example, accounting for 80%, and the data amount of the second correspondence table is relatively small, for example, accounting for 20%. There are various ways to generate a model by machine learning training. Since the input and output in the model are fixed, in the embodiment, a supervised learning algorithm which is relatively easy to implement can be used. If the verification result of the model by using the second correspondence table is not within the preset range, it indicates that the model is not accurate enough, and the parameters of the model can be returned to modify, re-output the model and verify until the verification is qualified.

[0044] After the model is established, steps S02 and S03 can be performed to apply the model to the processing of the silicon wafer to obtain a better flatness. In the embodiment, a flatness tester is used to measure the flatness of the silicon wafer. When the model is applied to the processing of the silicon wafer, it can be intervened from the first single-step process or from other single-step processes (for example, the second single-step process). To ensure the effect of improving the flatness of the silicon wafer processing, the silicon wafer processing process in the embodiment is intervened from the first single-step process.

[0045] The silicon wafer processed by chemical etching is used as the raw material to obtain the initial flatness Tinput. The Tinput is input into the flatness model of the final product Toutput=Tinput-Tdsp-Tfp+Tepi to obtain the target flatness of the double-side polishing process. The target flatness is input into the flatness model of the double-side polishing process Tdsp to obtain the process parameters and equipment parameters of the single-step process. The double-side polishing process is performed in this way, and the actual flatness Tdsp0 of the double-side polishing process is obtained. The actual flatness Tdsp0 is input and updated into the flatness model of the final product Toutput=Tinput-Tdsp0-Tfp+Tepi, and the target flatness of the final polishing process is obtained accordingly. The target flatness is used in combination with the flatness model of the final polishing process Tfp to obtain the process parameters and equipment parameters of the final polishing process. The final polishing process is performed in this way, and the actual flatness Tfp0 of the final polishing process is obtained. The flatness model of the final product is updated to Toutput=Tinput-Tdsp0-Tfp0+Tepi. The latest flatness model of the final product is used to obtain the target flatness of the epitaxial process, and the process parameters and equipment parameters of the epitaxial process are obtained in combination with the flatness model of the epitaxial process Tepi. The epitaxial process is performed accordingly to obtain the flatness of the final product.

[0046] In the above processing, the flatness model of the final product can be used to reasonably distribute the target flatness of each single-step process, especially the first single-step process (e.g. double-side polishing process) which has the strongest processing capability and the greatest influence on the flatness of the final product. Further, the flatness model of the single-step process can be used to improve the accuracy of the single-step process execution, so that the actual flatness is closer to the target flatness. Further, in the subsequent single-step process, the actual flatness of the previous single-step process can be used to update the flatness model of the final product, and then the target flatness of the single-step process can be dynamically adjusted and set according to the actual execution, so as to achieve better flatness of the final product.

[0047] To further improve the accuracy of the flatness model of the final product and reduce the difference between the target flatness and the actual flatness of the single-step process, historical data in the processing can be accumulated, and the above model can be continuously optimized and improved using the above historical data.

[0048] In summary, the silicon wafer processing method provided by the present application uses the established flatness model of the final product and the flatness model of the single-step process to optimize the setting of the target flatness of each single-step process and the corresponding process parameters and equipment parameters, and in the process of executing the single-step process, the difference between the target flatness and the actual flatness of the previous single-step process can be used to adjust the next single-step process based on the flatness model of the final product, so as to obtain better final flatness, thereby solving the problem of further improving the flatness of the silicon wafer.

[0049] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or change made by a person skilled in the art based on the above disclosure is within the protection scope of the claims.

Claims

1. A method for processing silicon wafers, characterized in that, Used to process the same silicon wafer; The silicon wafer processing method includes: Establish flatness models for the first to nth single-step processes, and establish a flatness model for the final product based on the flatness models for the first to nth single-step processes. The target flatness of the m-th single-step process is obtained based on the flatness model of the final product. The m-th single-step process is then performed on the product silicon wafer based on the flatness model of the m-th single-step process and the target flatness of the m-th single-step process, and the actual flatness data of the m-th single-step process is obtained. The flatness model of the final product is adjusted according to the actual flatness data of the m-th single-step process to obtain the target flatness of the (m+1)-th single-step process. The (m+1)-th single-step process is performed on the product silicon wafer based on the flatness model of the (m+1)-th single-step process and the target flatness of the (m+1)-th single-step process. Where n is a positive integer greater than 1, and m = 1, 2, ..., n-1; The first to nth single-step processes are, in sequence, double-sided polishing, final polishing, and epitaxial process.

2. The silicon wafer processing method as described in claim 1, characterized in that, The planarization capability of the double-sided polishing process is greater than that of the final polishing process, and the planarization capability of the final polishing process is greater than that of the epitaxial process.

3. The silicon wafer processing method as described in claim 2, characterized in that, The flatness model of the final product is as follows: Toutput=Tinput-Tdsp-Tfp+Tepi; Among them, Tinput is the flatness model before double-sided polishing, Tdsp is the flatness model of double-sided polishing, Tfp is the flatness model of the final polishing process, and Tepi is the flatness model of the epitaxial process.

4. The silicon wafer processing method as described in claim 3, characterized in that, The flatness model of the double-sided polishing process is related to the pressure, time, gap, equipment number, polishing pad, and number of silicon wafers used in the double-sided polishing process.

5. The silicon wafer processing method as described in claim 3, characterized in that, The flatness model of the final polishing process is related to the polishing zone pressure, the time of the final polishing process, the equipment number, the polishing head number, the polishing pad, and the number of silicon wafers used in the final polishing process.

6. The silicon wafer processing method as described in claim 3, characterized in that, The flatness model of the epitaxial process is related to the gas flow rate, temperature, power distribution, equipment number, and number of silicon wafers used in the epitaxial process.

7. The silicon wafer processing method as described in claim 1, characterized in that, Based on historical data of each individual process step, a flatness model for each individual process step is established using machine learning methods.

8. The silicon wafer processing method as described in claim 7, characterized in that, The historical data for each individual process step includes the corresponding process parameters, equipment parameters, and actual flatness data.

9. The silicon wafer processing method according to any one of claims 1 to 8, characterized in that, The actual flatness data of each individual process step were obtained by measuring with a flatness tester.

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