A planar gallium nitride device and its fabrication method
By segmenting the gate cells in gallium nitride devices, the problem of edge region breakdown effect is solved, improving device reliability and withstand voltage, while maintaining device performance while saving costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-22
- Publication Date
- 2026-03-10
AI Technical Summary
Existing gallium nitride devices are prone to breakdown in the edge region, causing the device to cease operation.
By setting a gate body and multiple gate units in the gate region, the gate units are arranged in parallel on the barrier layer and segmented so that each gate unit is located between the corresponding drain unit and source unit. Different gate structures are used in the edge region and the middle region to enhance the voltage withstand capability of the edge region.
This effectively reduces the breakdown effect in the edge region of gallium nitride devices, improves device reliability and withstand voltage, saves consumables, and maintains device performance and withstand voltage.
Smart Images
Figure CN115224125B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a planar gallium nitride device and a preparation method thereof. BACKGROUND
[0002] GaN (gallium nitride) is a third-generation semiconductor material, which has a very high critical breakdown field. In theory, a GaN-based device has a very high breakdown voltage. Gallium nitride semiconductors are widely used in the world as materials for light equipment represented by light emitting diodes (LEDs) and laser diodes (LDs). Further, in recent years, as electronic devices represented by transistors, gallium nitride semiconductors have attracted attention, and are particularly expected to be applied in high-voltage power devices and high-frequency power devices due to their very excellent material properties, such as wide band gap, high electron mobility, fast saturated electron speed, and high breakdown voltage.
[0003] However, the existing gallium nitride devices are prone to breakdown effect in the edge region, which further causes the device to stop working. SUMMARY
[0004] To solve the above technical problems, the present application provides a planar gallium nitride device and a preparation method thereof, which can solve the problem that the existing gallium nitride devices are prone to breakdown effect in the edge region, which further causes the device to stop working.
[0005] A first aspect of the present application provides a planar gallium nitride device, comprising: a source region, a drain region, a channel layer, a barrier layer, a passivation layer, and a gate region; wherein,
[0006] The source region comprises a source main body and a plurality of source units, and the plurality of source units are arranged in parallel and respectively contact the source main body.
[0007] The drain region comprises a drain main body and a plurality of drain units, and the plurality of drain units are arranged in parallel and respectively contact the drain main body.
[0008] The gate region comprises a gate main body and a plurality of gate units, and the gate region is arranged on the barrier layer, the plurality of gate units are arranged in parallel and respectively contact the gate main body.
[0009] Each of the gate units is arranged in segments, and each of the gate units is arranged between the corresponding plurality of drain units and the plurality of source units.
[0010] In one embodiment, the gate unit comprises: a first gate voltage-resisting element, a second gate voltage-resisting element, and a gate element.
[0011] Wherein, the first end of the first gate withstand voltage element is in contact with the gate body, and the second end of the first gate withstand voltage element is connected in series with the gate element and then in contact with the second gate withstand voltage element.
[0012] In one embodiment, the lengths of both the first gate withstand element and the second gate withstand element are less than the length of the gate element.
[0013] In one embodiment, the first gate withstand element and the second gate withstand element are "convex" shaped structures, and the top of the "convex" shaped structure is in contact with the barrier layer.
[0014] In one embodiment, the first gate withstand element and the second gate withstand element are trapezoidal structures, and the top of the trapezoidal structure is in contact with the barrier layer.
[0015] In one embodiment, the number of source cells is the same as the number of drain cells, the number of gate cells is greater than the number of source cells, and the number of gate cells is greater than the number of drain cells.
[0016] In one embodiment, the plurality of drain cells are respectively arranged in a cross configuration with the plurality of source cells.
[0017] In one embodiment, the widths of both the first gate withstand element and the second gate withstand element are greater than the width of the gate element.
[0018] In one embodiment, the thickness of both the first gate withstand element and the second gate withstand element is equal to the thickness of the gate element.
[0019] A second aspect of this application provides a method for fabricating a planar gallium nitride device, comprising:
[0020] Provide semiconductor substrates;
[0021] A source region and a drain region are sequentially formed on the semiconductor substrate; wherein, the source region includes a source body and a plurality of source units, the plurality of source units are arranged in parallel and respectively contact the source body; the drain region includes a drain body and a plurality of drain units, the plurality of drain units are arranged in parallel and respectively contact the drain body;
[0022] A channel layer is formed on the semiconductor substrate; wherein the channel layer includes a plurality of channel units, and the plurality of channel units are respectively disposed between adjacent source units and drain units;
[0023] A barrier layer is formed on the channel layer; wherein the barrier layer includes a plurality of barrier units, wherein each of the plurality of barrier units corresponds one-to-one with a plurality of channel units;
[0024] A gate region and a passivation layer are formed on the channel layer; wherein, the gate region includes a gate body and a plurality of gate cells, the gate region is disposed on the barrier layer, the plurality of gate cells are arranged in parallel and respectively contact the gate body; each gate cell is segmented, and each gate cell is disposed between the corresponding plurality of drain cells and the plurality of source cells; the passivation layer includes a plurality of passivation cells, the plurality of passivation cells are respectively disposed between adjacent gate cells and drain cells, and the plurality of passivation cells are also disposed between adjacent gate cells and source cells.
[0025] The beneficial effects of this application embodiment compared with the prior art are as follows: by setting the gate region including the gate body and multiple gate units, the gate region is disposed on the barrier layer, and the multiple gate units are arranged in parallel and respectively in contact with the gate body; wherein, each gate unit is segmented, and each gate unit is disposed between the corresponding multiple drain units and multiple source units, the gate units are segmented, and different gate structures are used in the edge region and the middle region of the device, which can solve the problem that existing gallium nitride devices are prone to breakdown effect in the edge region, causing the device to stop working. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the vertical cross-sectional structure of a planar gallium nitride device provided in one embodiment of this application;
[0027] Figure 2 This is a schematic diagram of the horizontal cross-sectional structure of a planar gallium nitride device provided in one embodiment of this application;
[0028] Figure 3 This is a schematic diagram of the horizontal cross-sectional structure of a planar gallium nitride device provided in another embodiment of this application;
[0029] Figure 4 This is a schematic diagram of the vertical cross-sectional structure of a planar gallium nitride device provided in another embodiment of this application;
[0030] Figure 5 This is a schematic flowchart of a planar gallium nitride device fabrication method according to an embodiment of this application;
[0031] Figure 6 This is a schematic diagram of the formation of the source and drain regions provided in one embodiment of this application;
[0032] Figure 7 This is a schematic diagram of the formation of a channel layer provided in one embodiment of this application;
[0033] Figure 8 This is a schematic diagram of the formation of a barrier region provided in one embodiment of this application;
[0034] Figure 9 This is a schematic diagram of the formation of the gate region and passivation layer provided in one embodiment of this application. Detailed Implementation
[0035] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0036] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0037] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0038] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.
[0039] Gallium nitride (GaN), as a third-generation semiconductor material, possesses a very high critical breakdown electric field, theoretically resulting in very high breakdown voltages for GaN-based devices. Gallium nitride semiconductors are widely used worldwide as materials in optical devices, such as light-emitting diodes (LEDs) and laser diodes (LDs). Furthermore, due to the excellent material properties of gallium nitride semiconductors, including wide bandgap, high electron mobility, high saturated electron velocity, and high breakdown voltage, they have attracted attention in recent years as electronic devices, particularly transistors, with applications in high-voltage and high-frequency power devices anticipated.
[0040] However, existing gallium nitride devices are prone to breakdown in the edge region, causing the device to cease operation.
[0041] To address the aforementioned technical problems, embodiments of this application provide a planar gallium nitride device, as shown in the reference. Figure 1 , Figure 2 As shown, the planar gallium nitride device includes: a source region 10, a drain region 20, a channel layer 40, a barrier layer 50, a passivation layer 60, and a gate region 30.
[0042] Specifically, the source region 10 includes a source body 12 and a plurality of source units 11, the plurality of source units 11 being arranged in parallel and respectively contacting the source body 12; the drain region 20 includes a drain body 22 and a plurality of drain units 21, the plurality of drain units 21 being arranged in parallel and respectively contacting the drain body 22; the gate region 30 includes a gate body 32 and a plurality of gate units 31, the gate region 30 being disposed on the barrier layer 50, the plurality of gate units 31 being arranged in parallel and respectively contacting the gate body 32; wherein, each gate unit 31 is segmented, and each gate unit 31 is disposed between the corresponding plurality of drain units 21 and the plurality of source units 11.
[0043] In this embodiment, the channel layer 40, the barrier layer 50, and the passivation layer 60 are stacked, and the channel layer 40, the barrier layer 50, and the passivation layer 60 are divided into multiple sub-units by multiple drain units 21, multiple gate units 31, and multiple source units 11.
[0044] In some embodiments, the channel layer 40 includes a plurality of channel units 41, wherein each channel unit 41 is disposed between adjacent source units 11 and drain units 21 and is in contact with the source units 11 and drain units 21.
[0045] Furthermore, the channel unit 41 is perpendicular to the corresponding source unit 11 and drain unit 21.
[0046] In this embodiment, the barrier layer 50 includes a plurality of barrier units 51, and the plurality of barrier units 51 are respectively in contact with a plurality of channel units 41.
[0047] Each barrier unit 51 is disposed between the corresponding source unit 11 and drain unit 21.
[0048] In this embodiment, the passivation layer 60 between adjacent drain unit 21 and source unit 11 is divided into two passivation units 61 by the gate unit 31. The two passivation units 61 are respectively disposed between the gate unit 31 and the drain unit 21, and between the gate unit 31 and the source unit 11.
[0049] Multiple passivation units 61 are respectively disposed on corresponding barrier units 51. It can be understood that each barrier unit 51 is disposed between the corresponding passivation unit 61 and the channel unit 41. Each gate unit 31 is disposed between the corresponding source unit 11 and the drain unit 21, and is in contact with the corresponding barrier unit 51.
[0050] In some embodiments, the source unit 11 and the drain unit 21 have the same thickness, the passivation unit 61 and the gate unit 31 have the same thickness, and the total thickness of the gate unit 31, the barrier unit 51 and the channel unit 41 is the same as the thickness of the drain unit 21 or the source unit 11.
[0051] In some embodiments, the region between adjacent source cells 11 and drain cells 21 is divided into three layers, wherein the first layer is a channel cell 41, the second layer is a barrier cell 51, and the third layer is a passivation cell 61 and a gate cell 31.
[0052] In this embodiment, reference Figure 1 , Figure 2 As shown, multiple gate units 31, multiple drain units 21, and multiple source units 11 are arranged in parallel, with each gate unit 31 disposed between the corresponding multiple drain units 21 and multiple source units 11. In this embodiment, each gate unit 31 is segmented, meaning each gate unit 31 is composed of different materials and structures, and is positioned in regions where gallium nitride devices are prone to breakdown (see reference). Figure 2 Strengthening the material and structure of the gate unit 31 in regions A and B can improve the reliability of gallium nitride devices and prevent breakdown effects in the edge regions.
[0053] In this embodiment, the number of source units 11 is the same as the number of drain units 21, and the number of gate units 31 is greater than the number of source units 11. Specifically, the source units 11 and drain units 21 are spaced apart. It can be understood that each drain unit 21 is disposed between adjacent source units 11, and multiple gate units 31 are disposed between adjacent source units 11 and drain units 21, that is, one drain unit 21 and two gate units 31 are disposed between adjacent source units 11.
[0054] In this embodiment, the planar gallium nitride device further includes a semiconductor substrate, which is disposed at the bottom of the channel layer 40, the source region 10 and the drain region 20, and is in contact with the bottom of the channel layer 40, the source region 10 and the drain region 20.
[0055] In one embodiment, reference Figure 3 As shown, the gate unit 31 includes: a first gate withstand voltage element 311, a second gate withstand voltage element 312, and a gate element 313.
[0056] Specifically, the first end of the first gate withstand voltage element 311 is in contact with the gate body 32, and the second end of the first gate withstand voltage element 311 is connected in series with the gate element 313 and then in contact with the second gate withstand voltage element 312.
[0057] In this embodiment, breakdown effects are prone to occur in the edge regions of gallium nitride devices, leading to decreased device reliability and ultimately causing the device to cease operation. This application addresses this problem by segmenting the gate unit 31: a first gate withstand voltage element 311 and a second gate withstand voltage element 312 are provided in the regions where reliability issues are more likely to occur, while a gate element 313 is provided in the middle region of the device, where reliability issues are less likely to occur. This resolves the problem of existing gallium nitride devices being prone to breakdown effects in the edge regions, thus preventing the device from continuing to operate.
[0058] In this embodiment, the structure of the first gate withstand voltage element 311 is the same as that of the second gate withstand voltage element 312, while the structure of the gate element 313 is different from that of the first gate withstand voltage element 311 and the second gate withstand voltage element 312. It is understood that the first gate withstand voltage element 311 uses a structure with large parasitic capacitance or high withstand voltage, while the gate element 313 uses a structure with less parasitic capacitance and low withstand voltage to save materials and reduce costs. In this embodiment, the first gate withstand voltage unit, the gate element 313, and the second gate withstand voltage unit are connected in series to form the gate unit 31. The first gate withstand voltage element 311 and the second gate withstand voltage element 312 are disposed in the regions at both ends of the gallium nitride device where breakdown effects are prone to occur (see reference). Figure 2 The middle region (A and B) greatly reduces the breakdown effect at the edge of the gallium nitride device, reduces the electric field and stress of the gallium nitride device, and since the first gate withstand voltage element 311 and the second gate withstand voltage element 312 are only disposed at both ends of the gate unit 31, the performance of the middle region of the gate unit 31 is retained at the same time, maximizing the performance of the gallium nitride device and improving the withstand voltage capability of the device.
[0059] In one embodiment, reference Figure 3 As shown, the length L1 of the first gate withstand voltage element 311 and the second gate withstand voltage element 312 is both less than the length L2 of the gate element 313.
[0060] In this embodiment, the first gate withstand voltage element 311 and the second gate withstand voltage element 312 are only disposed in the region at both ends of the gallium nitride device (approximately 10%-30%) where breakdown effects are likely to occur (see reference). Figure 2In the middle region (region A and region B), the middle region is the gate element 313. By doing so, the first gate withstand voltage element 311 and the second gate withstand voltage element 312 with reinforcement structure are not set in the region where the device is not prone to breakdown effect. By setting the length L1 of the first gate withstand voltage element 311 and the second gate withstand voltage element 312 to be smaller than the length L2 of the gate element 313, the problem of the breakdown effect in the edge region of gallium nitride device can be solved while saving materials.
[0061] In one embodiment, reference Figure 1 and Figure 3 As shown, the first gate withstand element 311 and the second gate withstand element 312 have a "convex" shaped structure, and the top of the "convex" shaped structure is in contact with the barrier layer 50.
[0062] In this embodiment, the width of the top of the "convex" shaped structure is smaller than the width of the bottom of the "convex" shaped structure. It can be understood that the width of the portion of the first gate withstand voltage element 311 and the second gate withstand voltage element 312 near the barrier layer 50 is smaller than the width away from the barrier layer 50. This is because gallium nitride devices are prone to breakdown at their edges and surfaces during operation, reducing device reliability. Therefore, the width of the portion of the first gate withstand voltage element 311 and the second gate withstand voltage element 312 near the barrier layer 50 is set smaller than the width away from the barrier layer 50 to solve this problem. However, if the width of the first gate withstand voltage element 311 is increased... If the width of element 311 and the second gate withstand element 312 is the same both away from and near the barrier layer 50, it will increase the on-resistance of the gallium nitride device during operation. Therefore, the width is set larger only in the region where the first gate withstand element 311 and the second gate withstand element 312 are prone to breakdown effects away from the barrier layer 50, and smaller at the ends of the first gate withstand element 311 and the second gate withstand element 312 near the barrier layer 50. This operation can reduce the on-resistance and solve the problem of breakdown effects easily occurring in the edge region of the gallium nitride device.
[0063] In one embodiment, reference Figure 4 As shown, the first gate withstand element 311 and the second gate withstand element 312 are trapezoidal structures, and the top of the trapezoidal structure is in contact with the barrier layer 50.
[0064] Specifically, the trapezoidal structure includes a first step, a second step, and a third step, wherein the width of the first step is less than the width of the second step, and the width of the third step is less than the width of the third step. That is, the first step is the top of the trapezoidal structure and contacts the barrier layer 50. The first gate withstand element 311 and the second gate withstand element 312 are set with a larger width in the edge region of the device and near the surface, and then their widths are gradually reduced. By setting the width of the first gate withstand element 311 and the second gate withstand element 312 near the barrier layer 50 to be smaller than their width away from the barrier layer 50, and by setting them in a trapezoidal distribution, the problem of easy breakdown in the edge region of gallium nitride devices can be solved, and the on-resistance of the gallium nitride device can be maintained without increasing it during operation, thus maximizing the performance of the gallium nitride device while improving its withstand voltage capability.
[0065] In one embodiment, the number of source cells 11 is the same as the number of drain cells 21, and the number of gate cells 31 is greater than the number of source cells 11 and the number of gate cells 31 is greater than the number of drain cells 21. Specifically, the source cells 11 and drain cells 21 are spaced apart. It can be understood that each drain cell 21 is located between adjacent source cells 11, and multiple gate cells 31 are respectively located between adjacent source cells 11 and drain cells 21. That is, one drain cell 21 and two gate cells 31 are located between adjacent source cells 11.
[0066] In one embodiment, multiple drain cells 21 are respectively arranged in a cross configuration with multiple source cells 11.
[0067] In this embodiment, the number of source units 11 is the same as the number of drain units 21, and the number of gate units 31 is greater than the number of source units 11. Specifically, the source units 11 and drain units 21 are spaced apart. It can be understood that each drain unit 21 is disposed between adjacent source units 11, and multiple gate units 31 are disposed between adjacent source units 11 and drain units 21, that is, one drain unit 21 and two gate units 31 are disposed between adjacent source units 11.
[0068] In one embodiment, reference Figure 3 As shown, the width W1 of the first gate withstand element 311 and the second gate withstand element 312 is greater than the width W2 of the gate element 313.
[0069] Specifically, the first gate withstand voltage element 311 and the second gate withstand voltage element 312 are disposed in the edge regions (approximately 10%-30% of the area) at both ends of the gallium nitride device where breakdown effects are prone to occur, and the gate element 313 is disposed in the middle region. Because the probability of breakdown effects occurring in the edge regions is much greater than that in the middle regions, the width W1 of the first gate withstand voltage element 311 and the second gate withstand voltage element 312 in the areas where breakdown effects are prone to occur is greater than the width W2 of the gate element 313. This can solve the problem that the edge regions of gallium nitride devices are prone to breakdown effects, causing the devices to cease operation.
[0070] In one embodiment, reference Figure 4 As shown, the thickness H of the first gate withstand voltage element 311 and the second gate withstand voltage element 312 is equal to the thickness of the gate element 313.
[0071] Specifically, the first gate withstand voltage element 311, the second gate withstand voltage element 312, and the gate element 313 constitute the gate unit 31. Since the thickness of the gate unit 31 is constant, the thickness H of the first gate withstand voltage element 311 and the second gate withstand voltage element 312 is set to be equal to the thickness of the gate element 313. This can ensure the stability of the power device performance and extend the service life of the power device.
[0072] In one embodiment, the channel layer 40 is GaN, the barrier layer 50 is AlGaN, and the passivation layer 60 is SiN.
[0073] This application also provides a method for fabricating a planar gallium nitride device, referring to... Figure 5 As shown, it includes steps S10-S50.
[0074] Step S10: Provide a semiconductor substrate 70.
[0075] Step S20: Reference Figure 6 As shown, a source region 10 and a drain region 20 are sequentially formed on a semiconductor substrate 70; wherein, the source region 10 includes a source body 12 and a plurality of source units 11, the plurality of source units 11 being arranged in parallel and respectively contacting the source body 12; the drain region 20 includes a drain body 22 and a plurality of drain units 21, the plurality of drain units 21 being arranged in parallel and respectively contacting the drain body 22.
[0076] Step S30: Reference Figure 7 As shown, a channel layer 40 is formed on a semiconductor substrate 70; wherein, the channel layer 40 includes a plurality of channel units 41, and the plurality of channel units 41 are respectively disposed between adjacent source units 11 and drain units 21.
[0077] Step S40: Reference Figure 8As shown, a barrier layer 50 is formed on the channel layer 40; wherein the barrier layer 50 includes a plurality of barrier units 51, wherein the plurality of barrier units 51 correspond one-to-one with the plurality of channel units 41.
[0078] Step S50: Reference Figure 9 As shown, a gate region 30 and a passivation layer 60 are formed on the channel layer 40. The gate region 30 includes a gate body 32 and a plurality of gate units 31. The gate region 30 is disposed on the barrier layer 50. The plurality of gate units 31 are arranged in parallel and are in contact with the gate body 32 respectively. Each gate unit 31 is segmented and each gate unit 31 is disposed between a plurality of drain units 21 and a plurality of source units 11. The passivation layer 60 includes a plurality of passivation units 61. The plurality of passivation units 61 are disposed between adjacent gate units 31 and drain units 21 respectively. The plurality of passivation units 61 are also disposed between adjacent gate units 31 and source units 11.
[0079] In this embodiment, in step S30, the channel layer 40 includes a plurality of channel units 41, wherein the plurality of channel units 41 are respectively disposed between adjacent source units 11 and drain units 21 and are in contact with source units 11 and drain units 21, and the plurality of channel units 41 are respectively perpendicular to source units 11 and drain units 21; and the plurality of channel units 41 are respectively located at the bottom ends of source units 11 and drain units 21.
[0080] In this embodiment, in step S40, the barrier layer 50 includes a plurality of barrier units 51, which are respectively in contact with a plurality of channel units 41, and are respectively in contact with the source unit 11 and the drain unit 21; wherein, the plurality of barrier units 51 are located at the top of the corresponding channel unit 41, away from the bottom of the source unit 11 and the drain unit 21.
[0081] In this embodiment, in step S50, the passivation layer 60 includes a plurality of passivation units 61. The plurality of passivation units 61 are respectively disposed between adjacent gate units 31 and drain units 21, and are also disposed between adjacent gate units 31 and source units 11. The plurality of passivation units 61 are respectively disposed on corresponding barrier units 51. It can be understood that the plurality of barrier units 51 are respectively disposed between corresponding passivation units 61 and channel units 41. The plurality of gate units 31 are respectively disposed between corresponding source units 11 and drain units 21, and are in contact with corresponding barrier units 51. It can be understood that the source units 11 and drain units 21 have the same thickness, the passivation units 61 and gate units 31 have the same thickness, and the total thickness of the gate units 31, barrier units 51, and channel units 41 is the same as the thickness of either the drain unit 21 or the source unit 11. It can also be understood that the region between adjacent source unit 11 and drain unit 21 is divided into three layers, wherein the first layer is channel unit 41, the second layer is barrier unit 51, and the third layer is passivation unit 61 and gate unit 31.
[0082] In this embodiment, in step S20, multiple gate units 31, multiple drain units 21, and multiple source units 11 are arranged in parallel, with each gate unit 31 disposed between the corresponding multiple drain units 21 and multiple source units 11. In this embodiment, each gate unit 31 is segmented, meaning each gate unit 31 is composed of different materials and structures. By reinforcing the material and structure of the gate unit 31 in regions where gallium nitride devices are prone to breakdown, the reliability of the gallium nitride device and its withstand voltage capability can be improved.
[0083] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0084] The units described as separate components may or may not be physically separate. The components that display data may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.
[0085] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A planar gallium nitride device, characterized by, The planar gallium nitride device comprises a source region, a drain region, a channel layer, a barrier layer, a passivation layer and a gate region; wherein, The source region comprises a source main body and a plurality of source units, and the plurality of source units are arranged in parallel and respectively contact the source main body; The drain region comprises a drain main body and a plurality of drain units, and the plurality of drain units are arranged in parallel and respectively contact the drain main body; The gate region comprises a gate main body and a plurality of gate units, and the gate region is arranged on the barrier layer, the plurality of gate units are arranged in parallel and respectively contact the gate main body; Each of the gate units is arranged in sections, and each of the gate units is arranged between a plurality of the drain units and a plurality of the source units; the gate unit comprises a first gate voltage-resistant element, a second gate voltage-resistant element and a gate element; The first end of the first gate voltage-resistant element contacts the gate main body, and the second end of the first gate voltage-resistant element contacts the second gate voltage-resistant element after being connected in series with the gate element.
2. The planar gallium nitride device of claim 1, wherein, The lengths of the first gate voltage-resistant element and the second gate voltage-resistant element are both less than the length of the gate element.
3. The planar gallium nitride device of claim 1, wherein, The first gate voltage-resistant element and the second gate voltage-resistant element are in a "convex" shape structure, and the top of the "convex" shape structure contacts the barrier layer.
4. The planar gallium nitride device of claim 1, wherein, The first gate voltage-resistant element and the second gate voltage-resistant element are in a trapezoidal structure, and the top of the trapezoidal structure contacts the barrier layer.
5. The planar gallium nitride device of claim 1, wherein, The number of the source units is the same as the number of the drain units, the number of the gate units is greater than the number of the source units, and the number of the gate units is greater than the number of the drain units.
6. The planar gallium nitride device of claim 1, wherein, The plurality of drain units are arranged in cross with the plurality of source units.
7. The planar gallium nitride device of claim 1, wherein, The widths of the first gate voltage-resistant element and the second gate voltage-resistant element are both greater than the width of the gate element.
8. The planar gallium nitride device of Claim 1, wherein, The thicknesses of the first gate voltage-resistant element and the second gate voltage-resistant element are both equal to the thickness of the gate element.
9. A method of fabricating a planar gallium nitride device, comprising: Comprising: A semiconductor substrate is provided; A source region and a drain region are sequentially formed on the semiconductor substrate; wherein the source region comprises a source main body and a plurality of source units, and the plurality of source units are arranged in parallel and respectively contact the source main body; the drain region comprises a drain main body and a plurality of drain units, and the plurality of drain units are arranged in parallel and respectively contact the drain main body; A channel layer is formed on the semiconductor substrate; wherein the channel layer comprises a plurality of channel units, and the plurality of channel units are respectively arranged between adjacent source units and drain units; A barrier layer is formed on the channel layer; wherein the barrier layer comprises a plurality of barrier units, and the plurality of barrier units respectively correspond to the plurality of channel units one by one; A passivation layer is formed on the barrier layer; wherein the passivation layer comprises a plurality of passivation units, and the plurality of passivation units respectively correspond to the plurality of barrier units one by one; Forming a gate region and a passivation layer on the channel layer; wherein the gate region comprises a gate main body and a plurality of gate units, the gate region is provided on the barrier layer, and the plurality of gate units are arranged in parallel and respectively contact the gate main body; each of the gate units is arranged in sections, and each of the gate units is arranged between a corresponding plurality of drain units and a plurality of source units; the passivation layer comprises a plurality of passivation units, the plurality of passivation units are respectively arranged between adjacent gate units and drain units, and the plurality of passivation units are also arranged between adjacent gate units and source units; the gate unit comprises a first gate voltage-resistant element, a second gate voltage-resistant element, and a gate element; wherein a first end of the first gate voltage-resistant element contacts the gate main body, and a second end of the first gate voltage-resistant element contacts the second gate voltage-resistant element after being connected in series with the gate element.
Citation Information
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