Analog-to-digital converter and method

Abstract

An analog-to-digital converter includes a capacitor module, a comparator, a control signal generating unit and a register. In a normal mode, the capacitor module is configured to receive a first input signal in a sampling phase, and generate a first sample signal and a second sample signal according to the first input signal in a conversion phase. The control signal generating unit is configured to adjust the first sample signal or the second sample signal in the conversion phase. The comparator is coupled to the capacitor module. In the normal mode, the comparator is configured to compare the first sample signal and the second sample signal in the conversion phase to generate n comparison signals. The register is configured to store a first comparison signal as a first digital output signal, and output the first digital output signal in the normal mode.

Description

TECHNICAL FIELD

[0001] The present invention relates to an analog-to-digital converter and method, and more particularly, to a successive approximation register (SAR) analog-to-digital converter and method. BACKGROUND

[0002] In a successive approximation register analog-to-digital conversion operation, a signal is processed through sampling, comparison and internal digital-to-analog conversion steps to generate a final output digital signal. However, in the above-mentioned process, the signal can be contaminated with different types of noise, such as quantization noise and thermal noise, due to imperfections of the device itself. These noises reduce the signal-to-noise and distortion ratio (SNDR) of the signal after digital-to-analog conversion, and thus reduce the quality of the final output digital signal. Therefore, how to reduce the noise of the signal has become one of the problems that the field desires to solve. SUMMARY

[0003] An analog-to-digital converter is disclosed for converting an input signal into an n-bit first digital output signal. The analog-to-digital converter includes a first capacitor module, a first comparator, a control signal generation unit and a first register. In a normal mode, the first capacitor module is configured to receive a first input signal in a sampling phase, and generate a first sampling signal and a second sampling signal based on the first input signal in a conversion phase. The control signal generation unit is configured to adjust the first sampling signal or the second sampling signal in the conversion phase. The first comparator is coupled to the first capacitor module, wherein in the normal mode, the first comparator is configured to compare the first sampling signal and the second sampling signal in the conversion phase to generate n first comparison signals. The first register is configured to store the first comparison signals as the first digital output signal, and output the first digital output signal in the normal mode.

[0004] An analog-to-digital conversion method is disclosed for converting an input signal into an n-bit first digital output signal, which includes the following steps: receiving a first input signal in a sampling phase in a normal mode; generating a first sampling signal and a second sampling signal based on the first input signal in a conversion phase in the normal mode; comparing the first sampling signal and the second sampling signal in the conversion phase in the normal mode to generate n first comparison signals; and storing the first comparison signals as the first digital output signal, and outputting the first digital output signal in the normal mode. The step of generating the first sampling signal and the second sampling signal based on the first input signal in the conversion phase in the normal mode includes adjusting the first sampling signal or the second sampling signal.

[0005] Compared with the prior art, the analog-to-digital converter and the method of the present application calculate the mean value of the signal to obtain the partial DC offset of the signal, and adjust the common-mode voltage of the input signal of the comparator according to the partial DC offset to change the residual value, thereby improving the signal-to-noise distortion ratio of the output signal. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various embodiments of the application can be best understood with reference to the following description and drawings. It should be noted that the various features of the drawings are not drawn to scale. In fact, the dimensions of some of the features can have been intentionally exaggerated or reduced for the sake of clarity.

[0007] Figure 1 For some embodiments of the present application, a schematic diagram of an analog-to-digital converter.

[0008] Figure 2 For some other embodiments of the present application, a schematic diagram of an analog-to-digital converter.

[0009] Figure 3 For some embodiments of the present application, a schematic diagram of an analog-to-digital converter.

[0010] Figure 4 For some embodiments of the present application, a flowchart of an analog-to-digital conversion method. DETAILED DESCRIPTION

[0011] Figure 1 For some embodiments according to the present application, a schematic diagram of an analog-to-digital converter (ADC) 10. The ADC 10 is used to sample an input signal SI to perform analog-to-digital conversion, and accordingly outputs an n-bit digital output signal SO1.

[0012] In Figure 1 In an embodiment, the ADC 10 is a successive-approximation register analog-to-digital converter (SAR ADC), which includes a sample-and-hold circuit SH, a capacitor module 100, a comparator COM1, a register RG1, and a control signal generation unit 200.

[0013] The operation of ADC 10 alternates between a sampling phase and a conversion phase. During the sampling phase, the sample-and-hold circuit SH samples the input signal SI to generate a sampled signal SS. The input signal SI is a differential signal, including a positive input signal SI1 and a negative input signal SI2 (hereinafter referred to as signals SI1 and SI2). Correspondingly, the sampled signal SS includes a positive sampled signal SS1 and a negative sampled signal SS2 (hereinafter referred to as signals SS1 and SS2). During the conversion phase, the sample-and-hold circuit SH stops sampling the input signal SI; the capacitor module 100 transmits signals SS1 and SS2 to comparator COM1 for n comparison operations to sequentially generate n comparison signals SD1 to SDn. Register RG1 stores the n comparison signals SD1 to SDn. During each comparison operation, the existing comparison signals SD1 to SDn are output as an n-bit digital output signal SO1, where the comparison signal SDx represents the value of the x-th bit of the n-bit digital output signal SO1. After the n comparison operations are completed, register RG1 is reset. In each comparison operation performed by comparator COM1, control signal generation unit 200 generates control signal SC1 based on the current digital output signal SO1 and transmits it to capacitor module 100. This allows capacitor module 100 to adjust the magnitudes of signal SS1 and / or signal SS2 based on control signal SC1 before each comparison operation, and then perform the next comparison operation.

[0014] like Figure 1 As shown, the control signal generation unit 200 includes a calculation circuit 210 and an adjustment circuit 220. In some embodiments, the calculation circuit 210 calculates the digital value represented by the nth bit in the digital output signal SO1 based on the nth comparison operation; the adjustment circuit 220 generates a control signal SC1 based on this digital value. For the capacitor module 100, one digital value corresponds to one configuration of the capacitor module 100. The adjustment circuit 220 generates the control signal SC1 based on the digital value represented by the nth bit in the digital output signal SO1, causing the capacitor module 100 to switch to that configuration according to the control signal SC1. When the capacitor module operates in different configurations, different adjustment effects can be provided for signals SS1 and SS2.

[0015] In analog-to-digital conversion, the output digital signal usually has quantization error compared to the input analog signal due to the limited resolution of the digitized signal. In addition, quantization noise is also introduced in the process of analog-to-digital conversion and presented in the output digital signal. Therefore, the difference between the actually obtained digital signal and the analog signal is called residual value, which includes quantization noise and quantization error and causes distortion of the digital signal, thereby reducing the signal-to-noise distortion ratio of the digital signal. In some embodiments, the quantization noise of the digital output signal SO1 includes the offset of the signals SS1 and SS2, the offset of the comparator COM1, and the noise caused by the charge injection effect of the capacitor module 100, etc. The offset of the signals SS1 and SS2 may

[0016] To reduce the distortion of the digital output signal SO, the present application proposes a scheme to generate a control signal SC1 to control the capacitor module 100, so that the residual value contributed by the above-mentioned offset to the digital output signal SO1 can be effectively reduced in real time when analog-to-digital conversion is performed. In other words, the present application can reduce the residual value contributed by the above-mentioned offset to the digital output signal SO1 before transmitting the residual value of the digital output signal SO1. In this way, the signal-to-noise distortion ratio of the ADC 10 and the operating range of the ADC 10 can be improved. In short, the operation of the ADC 10 has a correction mode and a normal mode. The operation of the normal mode can correspond to the operation of a general ADC to convert an input signal into a digital output signal. Before the normal mode, the ADC 10 first enters the correction mode to estimate the above-mentioned offset, and then reduces the estimated offset in real time in the normal mode. The details are as follows.

[0017] In the calibration mode, the sample-and-hold circuit SH samples the offset test signal ST in the sampling phase. The offset test signal ST is a differential signal pair including a positive offset test signal ST1 and a negative offset test signal ST2 (hereinafter referred to as signal ST1 and signal ST2). The signal ST1 and the signal ST2 are default values used to measure the DC offset of the signal SS1 and the signal SS2 and the DC offset of the comparator COM1. In this embodiment, the common mode voltage of the signal ST1 and the signal ST2 is 0. Specifically, the signal ST1 and the signal ST2 can be both set to 0 to simplify the operation. The signal ST1 and the signal ST2 are sampled as a positive offset test sample signal STS1 and a negative offset test sample signal STS2 (hereinafter referred to as signal STS1 and signal STS2). In the calibration mode, the comparator COM1 performs n comparison operations on the signal STS1 and the signal STS2 in the conversion phase to sequentially generate n offset comparison signals STD1-STDn. The register RG1 outputs the n offset comparison signals STD1-STDn as an n-bit digital output signal SO1. Because the signal ST1 and the signal STS2 are both set to 0, the digital value of the digital output signal SO1 is theoretically 0 at this time. However, in some embodiments, due to the DC offset caused by the capacitor module 100 and the comparator COM1, the digital output signal SO1 in the calibration mode is not equal to 0. Thus, the value of the digital output signal SO1 in the calibration mode includes at least the DC offset caused by the capacitor module 100 and the DC offset caused by the comparator COM1. For ease of description, the digital output signal SO1 generated by the signal ST1 and the signal ST2 with a common mode voltage of 0 in the calibration mode is referred to as an offset reference signal SR1.

[0018] After obtaining the offset reference signal SR1, the control signal generating unit 200 calculates the offset value of the offset reference signal SR1 and generates the control signals SC1 and SC2 according to the offset value and transmits the control signals SC1 and SC2 to the capacitor module 100. The calculation circuit 210 calculates the offset value of the offset reference signal SR1. For example, when the theoretical value of the offset reference signal SR1 (because the signal ST1 and the signal ST2 are both 0) should be 0, the value of the offset reference signal SR1 actually obtained is the offset value caused by other components (such as the capacitor module 100 and the comparator COM1) on the offset reference signal SR1. In some embodiments, the calculation circuit 210 is also used to store the offset value of the offset reference signal SR1 obtained in the correction mode. In the normal mode, at each comparison operation, the calculation circuit 210 adds the digital value calculated according to the digital output signal SO1 to the offset value, so that the adjustment circuit 220 can generate the control signals SC1 and SC2 according to the offset value and use the control signals SC1 and SC2 to adjust the signals SS1 and SS2 in the conversion stage. More specifically, in the normal mode, at the nth comparison operation, the calculation circuit 210 adds the digital value of the nth bit of the digital output signal SO1 to the offset value of the offset reference signal SR1 obtained in the correction mode; the adjustment circuit 220 generates the control signals SC1 and SC2 according to the added result; and the capacitor module 100 adjusts the sizes of the signals SS1 and SS2 according to the control signals SC1 and SC2 to perform the comparison of the next bit. Because the control signals SC1 and SC2 at this time correspond to the configuration of the capacitor module 100 including the digital value of the nth bit of the digital output signal SO1 and the offset value of the offset reference signal SR1 obtained in the correction mode, the capacitor module 100 can not only adjust the signals SS1 and SS2 to perform the general SAR ADC operation, but also can reduce the absolute value of the common-mode voltage between the signals SS1 and SS2 before the signals SS1 and SS2 are transmitted to the comparator COM1. In this way, the comparator COM1 can perform the comparison operation according to the signals SS1 and SS2 with less DC offset.

[0019] The capacitor module 100 includes a positive-end capacitor array 110, a negative-end capacitor array 115, a switch device 120, and a switch device 125. The positive-end capacitor array 110 and the switch device 120 are used to process the signals STS1 and SS1, and the negative-end capacitor array 115 and the switch device 125 are used to process the signals STS2 and SS2. Because the signals are differential signal pairs, the following description only describes the positive-end operation in detail, and part of the negative-end operation is omitted.

[0020] The positive end capacitor array 110 includes a plurality of capacitors in parallel, and the capacitance values of the capacitors can be designed in a manner similar to that of a general SAR ADC. For example, the capacitance values of the capacitors can increase in a fixed ratio, such as the capacitance value of a subsequent capacitor being twice that of a previous capacitor. Thus, when different capacitors are switched from the reference voltage VREF1 to the reference voltage VREF2, the amount of change in the signal SS1 is also different. The capacitors each include a first end (also referred to as an upper plate) and a second end (also referred to as a lower plate). The first ends of the capacitors are coupled to the sample-and-hold circuit SH and the comparator COM1, and the second ends of the capacitors are each selectively electrically connected to the reference voltage VREF1 or the reference voltage VREF2 by the switching device 120, where the reference voltage VREF1 is greater than the reference voltage VREF2. In some embodiments, the reference voltage VREF2 is equal to the system ground. The switching device 120 switches the second ends of the positive end capacitor array 110 to the reference voltage VREF1 or the reference voltage VREF2 according to the control signal SC1 to adjust the size of the signal SS1.

[0021] In the normal mode, the control signal generation unit 200 generates the control signal SC1 according to the offset value of the offset reference signal SR1 obtained in the calibration mode in addition to generating the control signal SC1 according to the digital output signal SO1 in the conversion phase. The switching device 120 receives the control signal SC1 and adjusts the size of the signal SS1 and reduces the absolute value of the common-mode voltage between the signal SS1 and the signal SS2 according to the control signal SC1 before each comparison by the comparator COM1. When the absolute value of the common-mode voltage between the signal SS1 and the signal SS2 is reduced, i.e., the noise of the signal SS1 and the signal SS2 is reduced, the signal-to-noise distortion ratio of the signal SS1 and the signal SS2 is improved, thereby improving the signal-to-noise distortion ratio of the digital output signal SO1. In some embodiments, when the capacitor module 100 reduces the absolute value of the common-mode voltage between the signal SS1 and the signal SS2, only one of the signal SS1 and the signal SS2 is adjusted to substantially achieve the effect of adjusting the common-mode voltage. In some embodiments, the capacitor module 100 only reduces part of the absolute value of the common-mode voltage between the signal SS1 and the signal SS2, such as reducing the absolute value of the common-mode voltage between the signal SS1 and the signal SS2 to only half of the original, to effectively improve the signal-to-noise distortion ratio of the signal SS1 and the signal SS2. In other embodiments, the capacitor module 100 eliminates the common-mode voltage between the signal SS1 and the signal SS2 according to the control signal SC1.

[0022] Similarly, the negative capacitor array 115 includes a first end and a second end. The first end is coupled to the sample-and-hold circuit SH and the comparator COM1, and the second end is selectively electrically connected to the reference voltage VREF3 or the reference voltage VREF2 through the switch device 125, where the reference voltage VREF2 is greater than the reference voltage VREF3. In some embodiments, the reference voltage VREF2 is equal to the common-mode voltage of the reference voltage VREF1 and the reference voltage VREF3. The switch device 125 switches the second end of the negative capacitor array 115 to the reference voltage VREF3 or the reference voltage VREF2 according to the control signal SC2 to adjust the size of the signal SS2. The negative capacitor array 115 is symmetrically arranged with the positive capacitor array 110, which will not be described here.

[0023] In Figure 1 some embodiments, the control signal SC1 is used to adjust the size of the signal SS1 to reduce the absolute value of the common-mode voltage between the signal SS1 and the signal SS2. However, the present application is not limited thereto. In other embodiments, the ADC 10 can generate a control signal SC3 (shown in Figure 2 ) different from the control signal SC1. The control signal SC1 is used to reduce the absolute value of the common-mode voltage between the signal SS1 and the signal SS2, and the control signal SC3 is used to adjust the size of the signal SS1, and a control signal SC4 (shown in Figure 2 ) different from the control signal SC2 is generated. The control signal SC2 is used to reduce the absolute value of the common-mode voltage between the signal SS1 and the signal SS2, and the control signal SC4 is used to adjust the size of the signal SS2. Please refer to Figure 2 . Figure 2 For other embodiments according to the present application, a schematic diagram of the ADC 10 is shown. Compared with Figure 1 , the capacitor module 100 further includes a DC offset adjustment circuit 130 and a DC offset adjustment circuit 135, and the control signal generation unit 200 further generates a control signal SC3 and a control signal SC4.

[0024] In Figure 2 some embodiments, the control signal generation unit 200 generates the control signal SC1 and the control signal SC2 according to the offset reference signal SR1 obtained in the calibration mode, and generates the control signal SC3 and the control signal SC4 according to the digital output signal SO1 obtained in the normal mode. The control signal SC1 and the control signal SC2 are used to adjust the common-mode voltage between the signal SS1 and the signal SS2. The control signal SC3 and the control signal SC4 are respectively used to adjust the signal SS1 and the signal SS2 before each comparison operation of the comparator COM1.

[0025] In the normal mode, the control signal generating unit 200 transmits the control signal SC1 to the DC offset adjustment circuit 130 in the conversion phase. In some embodiments, the control signal SC1 does not change after being generated, i.e. the control signal SC1 is constant throughout the normal mode. In other words, the common mode voltage between the signal SS1 and the signal SS2 is adjusted to the same value throughout the normal mode. In addition, the control signal generating unit 200 transmits the control signal SC3 to the switching module 120, so that the switching module 120 adjusts the size of the signal SS1 before each comparison operation according to the control signal SC3.

[0026] The DC offset adjustment circuit 130 includes a plurality of capacitors and a plurality of inverters, but is not limited thereto. The first end of each capacitor is coupled to the first end of the positive capacitor array 110, and the second end of each capacitor is coupled to the control signal SC1 through an inverter, respectively. In other words, the control signal SC1 is used to control the bias voltage of the capacitors of the DC offset adjustment circuit 130 to adjust the signal SS1. The DC offset adjustment circuit 135 is symmetrically arranged with the DC offset adjustment circuit 130, which will not be described here.

[0027] Reference Figure 3 . Figure 3 For some embodiments of the present application, a schematic diagram of an ADC 30. The ADC 30 is a time-interleaved (TI) SAR ADC. The ADC 30 includes the ADC 10 and an ADC 11, wherein the ADC 10 and the ADC 11 have the same structure and operation.

[0028] The ADC 10 and the ADC 11 share the sample-and-hold circuit SH, and the ADC 11 further includes a capacitor module 101, a comparator COM2, a register RG2, and a control signal generating circuit 201.

[0029] In the calibration mode, the ADC 10 and the ADC 11 first sample the offset test signal ST, and obtain the offset reference signal SR1 corresponding to the ADC 10 and the offset reference signal SR2 corresponding to the ADC 11 (i.e. the digital output signal SO2 obtained in the calibration mode). Then, the control signals SC1, SC2 and the control signals SC5, SC6 are generated according to the offset reference signal SR1 and the offset reference signal SR2, respectively.

[0030] In the normal mode, the ADC 10 and the ADC 11 alternately sample the input signal SI to generate the signal SS1, SS2 and the signal SS3, SS4, respectively. Then, the ADC 10 and the ADC 11 alternately generate the digital output signal SO1 and the digital output signal SO2.

[0031] In some embodiments, ADC 30 may include ADC 10 as... Figure 1 The architecture of ADC 10 or Figure 2 The architecture of ADC10 in ADC30 is similar to that of ADC11. Figure 1 The architecture of the ADC10 in the text is similar to... Figure 2 The architecture of ADC 10 in the text.

[0032] refer to Figure 4 . Figure 4 This is a flowchart of an analog-to-digital conversion method 40 in some embodiments of the present invention. In some embodiments, it may be provided by... Figure 1 or Figure 2 The ADC 10 uses analog-to-digital conversion method 40 to generate a digital output signal SO1. More specifically, the ADC 10 uses analog-to-digital conversion method 40 to adjust signals SS1 and SS2 to reduce the DC offset of the ADC 10, thereby improving the signal-to-noise distortion ratio of the digital output signal SO1. Analog-to-digital conversion method 40 includes steps S41, S42, S43, S44, S45, S46, S47, S48, and S49. For ease of understanding, analog-to-digital conversion method 40 follows... Figure 1 The reference symbols in the text are used for illustration. Furthermore, the analog-to-digital conversion method 40 is not limited to steps S41-S49. In a further embodiment, the analog-to-digital conversion method 40 also includes... Figures 1 to 3 The steps described above for operating ADC10 and ADC30.

[0033] In step S41, in the calibration mode, the offset test signal ST is received in the sampling stage. In step S42, in the calibration mode, the signals STS1 and STS2 are generated in the conversion stage in accordance with the offset test signal ST. In step S43, in the calibration mode, the n offset comparison signals STD1-SDTn are generated by comparing the signals STS1 and STS2 in the conversion stage. In step S44, the offset comparison signals STD1-SDTn are stored as the offset reference signal SR1. In step S45, the DC offset is calculated in accordance with the offset reference signal SR1, and the control signals SC1 and SC2 are generated in accordance with the DC offset. In some embodiments, the DC offset is the offset value of the offset reference signal SR1. In step S46, in the normal mode, the input signal SI is received in the sampling stage. In step S47, in the normal mode, the signals SS1 and SS2 are generated in the conversion stage in accordance with the input signal SI. In some embodiments, step S47 further comprises adjusting the common-mode voltage of the signals SS1 and SS2 in accordance with the control signals SC1 and SC2. In step S48, in the normal mode, the n comparison signals SD1-SDn are generated by comparing the signals SS1 and SS2 in the conversion stage. In step S49, the comparison signals SD1-SDn are stored as the digital output signal SO1, and the digital output signal SO1 is output in the normal mode.

[0034] The analog-digital conversion method 40 reduces the absolute value of the common-mode voltage between the signals SS1 and SS2 after the DC offset is obtained. Therefore, when the DC offset of the common-mode voltage between the signals SS1 and SS2 is reduced, the signal noise distortion ratio of the digital output signal SO1 is improved.

[0035] The above description merely illustrates some embodiments of the present application and is not intended to limit the scope of the present application. The skilled in the art can easily utilize the contents of the present application as a basis to design or modify other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. The skilled in the art should understand that these equivalent embodiments still belong to the spirit and scope of the present application, and can be variously changed, replaced and modified without departing from the spirit and scope of the present application.

[0036] Legend of reference numerals:

[0037] 10: analog-digital converter

[0038] 100: capacitor module

[0039] 110: positive terminal capacitor array

[0040] 115: negative terminal capacitor array

[0041] 120: switching device

[0042] 125: switching device

[0043] 200: control signal generation unit

[0044] 210: calculation circuit

[0045] 220: adjustment circuit

[0046] SH: sample-and-hold circuit

[0047] COM1: comparator

[0048] RG1: register

[0049] VREF1: reference voltage

[0050] VREF2: reference voltage

[0051] VREF3: reference voltage

[0052] CLK: frequency

[0053] ST: offset test signal

[0054] ST1: offset test signal

[0055] ST2: offset test signal

[0056] SI: input signal

[0057] SI1: input signal

[0058] SI2: input signal

[0059] STS: offset test sample signal

[0060] STS1: offset test sample signal

[0061] STS2: offset test sample signal

[0062] SS: sample signal

[0063] SS1: sample signal

[0064] SS2: sample signal

[0065] STD1: offset comparison signal

[0066] STDn: offset comparison signal

[0067] SD1: comparison signal

[0068] SDn: comparison signal

[0069] SO1: digital output signal

[0070] SR1: offset reference signal

[0071] SC1: control signal

[0072] SC2: control signal

[0073] 130: DC offset control circuit

[0074] 135: DC offset control circuit

[0075] SC3: control signal

[0076] SC4: control signal

[0077] 30: analog-digital converter

[0078] 11: analog-digital converter

[0079] 101: capacitor module

[0080] 201: control signal generation unit

[0081] COM2: comparator

[0082] RG2: register

[0083] SC5: control signal

[0084] SC6: control signal

[0085] SO2: digital output signal

[0086] SR2: offset reference signal

[0087] 40: analog-digital conversion method

[0088] S41: step

[0089] S42: step

[0090] S43: step

[0091] S44: step

[0092] S45: step

[0093] S46: step

[0094] S47: step

[0095] S48: step

[0096] S49: step

Claims

1. An analog-to-digital converter for converting an input signal into a first digital output signal of n bits, comprising: a first capacitor module for receiving a first input signal in a sampling phase and generating a first sampling signal and a second sampling signal according to the first input signal in a conversion phase in a normal mode; a first control signal generating unit for adjusting the first sampling signal or the second sampling signal in the conversion phase; a first comparator coupled to the first capacitor module, wherein the first comparator is configured to compare the first sampling signal and the second sampling signal in the conversion phase to generate n first comparison signals in the normal mode, wherein n is a positive integer; and a first register for storing the n first comparison signals as the first digital output signal and outputting the first digital output signal in the normal mode; wherein in a calibration mode, the first capacitor module is configured to receive a first offset test signal in the sampling phase and generate a first offset test sampling signal and a second offset test sampling signal according to the first offset test signal in the conversion phase; the first comparator is configured to compare the first offset test sampling signal and the second offset test sampling signal in the conversion phase to generate n first offset comparison signals; and the first register is configured to store the n first offset comparison signals as the first digital output signal, and wherein the first control signal generating unit is configured to calculate a first DC offset of the analog-to-digital converter according to the first digital output signal in the calibration mode, generate a first control signal according to the first DC offset, and the first DC offset comprises a common-mode voltage of the first offset test sampling signal and the second offset test sampling signal.

2. The analog-to-digital converter of claim 1, wherein the first capacitor module comprises: a positive terminal capacitor array having a first terminal and a second terminal, wherein in the normal mode, the positive terminal capacitor array is configured to receive a first positive input signal of the first input signal at the first terminal of the positive terminal capacitor array in the sampling phase and generate the first sampling signal to a positive input terminal of the first comparator at the first terminal of the positive terminal capacitor array in the conversion phase; and a negative terminal capacitor array having a first terminal and a second terminal, wherein in the normal mode, the negative terminal capacitor array is configured to receive a first negative input signal of the first input signal at the first terminal of the negative terminal capacitor array in the sampling phase and generate the second sampling signal to a negative input terminal of the first comparator at the first terminal of the negative terminal capacitor array in the conversion phase.

3. The analog-to-digital converter of claim 2, wherein the first capacitor module further comprises: a first switch device coupled to the second terminal of the positive terminal capacitor array for selectively electrically connecting each capacitor in the positive terminal capacitor array to a first reference voltage or a second reference voltage; and a second switch device coupled to the second terminal of the negative terminal capacitor array for selectively electrically connecting each capacitor in the negative terminal capacitor array to a third reference voltage or the second reference voltage. ​ ​ wherein in the conversion phase of the normal mode, the first switch device is configured to selectively electrically connect each capacitor in the positive-end capacitor array to the first reference voltage or the second reference voltage according to the first control signal to adjust the common-mode voltage of the first sampling signal and the second sampling signal.

4. The analog-to-digital converter of claim 3, wherein in the conversion phase of the normal mode, the first control signal generating unit is further configured to generate the first control signal according to the first digital output signal, and when the first comparator generates each of the n first comparison signals, the first switch device is further configured to electrically connect each capacitor in the positive-end capacitor array to the first reference voltage or the second reference voltage according to the first control signal, and the second switch device is further configured to electrically connect each capacitor in the negative-end capacitor array to the third reference voltage or the second reference voltage according to the first control signal.

5. The analog-to-digital converter of claim 4, wherein the first control signal generating unit is further configured to generate a second control signal according to the first digital output signal, and when the first comparator generates each of the n first comparison signals, the first switch device is further configured to electrically connect each capacitor in the positive-end capacitor array to the first reference voltage or the second reference voltage according to the second control signal, and the first capacitor module further comprises: a direct current offset adjusting circuit coupled to the first comparator and configured to adjust the common-mode voltage of the first sampling signal and the second sampling signal according to the first control signal.

6. The analog-to-digital converter of claim 1, further configured to convert the input signal into a second digital output signal of n bits, and the analog-to-digital converter further comprises: a second capacitor module configured to receive a second input signal in the sampling phase and generate a third sampling signal and a fourth sampling signal according to the second input signal in the conversion phase in the normal mode; a second control signal generating unit configured to adjust the third sampling signal or the fourth sampling signal in the conversion phase; a second comparator coupled to the second capacitor module, wherein in the normal mode, the second comparator is configured to compare the third sampling signal and the fourth sampling signal to generate n second comparison signals in the conversion phase; and a second register configured to store the n second comparison signals as a second digital output signal and output the second digital output signal in the normal mode.

7. The analog-to-digital converter of claim 6, wherein in the calibration mode, the second capacitor module is configured to receive a second offset test signal in the sampling phase and generate a third offset test sampling signal and a fourth offset test sampling signal according to the second offset test signal in the conversion phase, the second comparator is configured to compare the third offset test sampling signal and the fourth offset test sampling signal to generate n second offset comparison signals in the conversion phase, the second register is configured to store the n second offset comparison signals as the second digital output signal, and the second register is configured to store the n second offset comparison signals as the second digital output signal, and wherein the second control signal generating unit is configured to calculate a second DC offset of the analog-to-digital converter according to the second digital output signal in the calibration mode, and to generate a third control signal according to the second DC offset.

8. An analog-to-digital conversion method for converting an input signal into an n-bit first digital output signal, comprising: in a normal mode, receiving a first input signal in a sampling phase; in the normal mode, generating a first sampling signal and a second sampling signal according to the first input signal in a conversion phase; in the normal mode, comparing the first sampling signal and the second sampling signal to generate n first comparison signals in the conversion phase; and storing the n first comparison signals as the first digital output signal, and outputting the first digital output signal in the normal mode; wherein the step of generating the first sampling signal and the second sampling signal according to the first input signal in the conversion phase in the normal mode comprises: adjusting the first sampling signal or the second sampling signal; and wherein in a calibration mode, a first offset test signal is received in the sampling phase; in the calibration mode, a first offset test sampling signal and a second offset test sampling signal are generated according to the first offset test signal in the conversion phase; in the calibration mode, the first offset test sampling signal and the second offset test sampling signal are compared to generate n first offset comparison signals in the conversion phase; the n first offset comparison signals are stored as the first digital output signal; and a first DC offset is calculated according to the first digital output signal in the calibration mode, and a first control signal is generated according to the first DC offset, wherein the first DC offset comprises a common-mode voltage of the first offset test sampling signal and the second offset test sampling signal. ​

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