Waveform generation circuit

Abstract

A waveform generating circuit includes a core circuit, an acquisition calculation circuit, a latch circuit and a digital-to-analog conversion circuit. The core circuit establishes a plurality of digital data. The acquisition calculation circuit generates a first data string and a second data string according to the digital data. The latch circuit receives and latches the first and second data strings, and uses the first and second data strings as a first input data and a second input data, respectively. The digital-to-analog conversion circuit receives and converts the first and second input data to generate a first output waveform and a second output waveform. After the core circuit establishes the digital data, the acquisition calculation circuit, the latch circuit and the digital-to-analog conversion circuit operate independently of the core circuit. The operation of the acquisition calculation circuit, the latch circuit and the digital-to-analog conversion circuit does not require the intervention of the core circuit, which can reduce the power consumption of the core circuit. When the core circuit is idle, the acquisition calculation circuit, the latch circuit and the digital-to-analog conversion circuit continue to operate.

Description

Technical Field

[0001] The invention relates to an electronic circuit, and in particular to a waveform generating circuit. Background Art

[0002] With the advancement of technology, the types and functions of electronic products are increasing. There are many electronic components inside electronic products. These multiple components often require a variety of waveforms, such as sine waves, square waves, sawtooth waves, and triangle waves. Known waveform generating circuits generate a variety of waveforms by using the duty cycle of pulse width modulation (PWM) signals in combination with external resistors and capacitors. However, the characteristics of external components are easily affected by the ambient temperature, which in turn affects the waveform generated by the waveform generating circuit. Summary of the invention

[0003] One embodiment of the present invention provides a waveform generating circuit, comprising a core circuit, an acquisition calculation circuit, a latch circuit, and a digital-to-analog conversion circuit. The core circuit establishes a plurality of digital data. The acquisition calculation circuit generates a first data string and a second data string according to the digital data. The latch circuit receives and latches the first and second data strings, and uses the first and second data strings as a first input data and a second input data, respectively. The digital-to-analog conversion circuit receives and converts the first and second input data to generate a first output waveform and a second output waveform. After the core circuit establishes the digital data, the acquisition calculation circuit, the latch circuit, and the digital-to-analog conversion circuit operate independently of the core circuit.

[0004] Since the operation of the acquisition calculation circuit, latch circuit and digital analog conversion circuit does not require the intervention of the core circuit, the power consumption of the core circuit can be reduced. In addition, when the core circuit is idle, the acquisition calculation circuit, latch circuit and digital analog conversion circuit continue to operate. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 4 is a schematic diagram of a waveform generating circuit of the present invention.

[0006] Figure 2 The relationship between the digital data and the data string of the data table of the present invention.

[0007] Figure 3 FIG. 4 is another schematic diagram of the waveform generating circuit of the present invention.

[0008] Figure 4 It is a schematic diagram of the relationship between the data table and the data string of the present invention.

[0009] Figure 5 Schematic diagram of the output waveform of the present invention.

[0010] Figure 6 It is an application schematic diagram of the waveform generating circuit of the present invention.

[0011] Reference Numbers

[0012] 100, 300: Waveform generation circuit

[0013] 110, 310, 610: core circuit

[0014] 120, 320, 620: Memory

[0015] 121, 321, 621: Data table

[0016] 130, 330, 630: Get calculation circuit

[0017] 140, 340, 640: Latch circuit

[0018] 141, 142, 341-343: Latch

[0019] 150, 350, 650: Digital to analog conversion circuit

[0020] 151, 152, 351~353: Digital-to-analog converter DS1~DS3: Data string

[0021] P1~P3: Pins

[0022] CLK1, CLK2: clock signal

[0023] DIN_DAC0~DIN_DAC2: input data

[0024] DAC0_OUT~DAC2_OUT: Output waveform

[0025] D0~D11: digital data

[0026] 360: Trigger Circuit

[0027] 370, 380: Switching circuit

[0028] 371, 372, 381-383: switch

[0029] S1~S18: Sampling time points

[0030] 600: Operating system

[0031] 660: Application Circuit

[0032] 670: Sensing Circuit

[0033] SFB: Feedback signal

[0034] GRPEN, SC1~SC3: switching signal

[0035] AVDD, DVDD, AGND, DGND, VREFP, VREFM: Voltage

[0036] PON: Power-on control signal

[0037] pd: power-off signal DETAILED DESCRIPTION

[0038] In order to make the purpose, features and advantages of the present invention more clearly understood, the following embodiments are specifically cited and described in detail with reference to the accompanying drawings. The present invention specification provides different embodiments to illustrate the technical features of different implementations of the present invention. Among them, the configuration of each element in the embodiment is for illustrative purposes and is not intended to limit the present invention. In addition, some repetitions of the figure numbers in the embodiments are for the purpose of simplifying the description and do not mean the relevance between different embodiments.

[0039] Figure 1 Schematic diagram of the waveform generating circuit of the present invention. As shown in the figure, the waveform generating circuit 100 includes a core circuit 110, an acquisition calculation circuit 130, a latch circuit 140 and a digital analog conversion circuit 150. In this embodiment, the acquisition calculation circuit 130, the latch circuit 140 and the digital analog conversion circuit 150 operate independently of the core circuit 110. Since the operation of the acquisition calculation circuit 130, the latch circuit 140 and the digital analog conversion circuit 150 does not require the intervention of the core circuit 110, the power consumption of the core circuit 110 can be reduced. In addition, when the core circuit 110 is idle, the acquisition calculation circuit 130, the latch circuit 140 and the digital analog conversion circuit 150 continue to operate.

[0040] The core circuit 110 establishes digital data. In one possible embodiment, the core circuit 110 may establish a data table 121, and the data table 121 stores a plurality of digital data. The core circuit 110 stores the data table 121 in a memory 120. The present invention does not limit the architecture of the core circuit 110. In one possible embodiment, the core circuit 110 is a microcontroller (MCU). In another possible embodiment, the core circuit 110 is a part of the circuit inside the microcontroller. In this example, the acquisition calculation circuit 130, the latch circuit 140 and the digital-to-analog conversion circuit 150 are another part of the circuit inside the microcontroller.

[0041] The acquisition calculation circuit 130 generates data strings DS1 and DS2 according to the digital data of the data table 121. In this embodiment, the acquisition calculation circuit 130 has pins P1 and P2. Pin P1 repeatedly outputs the data string DS1. Pin P2 repeatedly outputs the data string DS2. Both the data strings DS1 and DS2 include the digital data of the data table 121. In a possible embodiment, the acquisition calculation circuit 130 acquires the digital data of the data table 121 in a first preset order to generate the data string DS1, and acquires the digital data of the data table 121 in a second preset order to generate the data string DS2. The first preset order is different from the second preset order.

[0042] Figure 2 1 is the relationship between the digital data of the data table 121 and the data strings DS1 and DS2. In the present embodiment, the data table 121 includes digital data D0-D11 and is stored in the memory 120. In one possible embodiment, the memory 120 has a plurality of memory cells, and different memory cells correspond to different addresses. In this example, the digital data D0-D1 are respectively stored in the memory cells corresponding to the addresses 00-0B. In other embodiments, the digital data D0-D11 are stored in different registers. The present invention does not limit the number of digital data in the data table 121. In other embodiments, the data table 121 may have more or less digital data.

[0043] The acquisition calculation circuit 130 arranges the digital data D0-D11 according to a preset algorithm to generate data strings DS1 and DS2. For example, the acquisition calculation circuit 130 may select one from addresses 00-0B as a first starting address and another from addresses 00-0B as a second starting address according to the preset algorithm. In this example, the acquisition calculation circuit 130 may use address 02 as the first starting address. The acquisition calculation circuit 130 reads the digital data in sequence starting from address 02 to generate the data string DS1. After reading the digital data D11 at address 0B, the acquisition calculation circuit 130 starts reading the digital data from address 00. Therefore, the data sequence of the data string DS1 is D2-D11, D0, D1. In addition, the acquisition calculation circuit 130 may use address 06 as the second starting address. The acquisition calculation circuit 130 reads the digital data in sequence starting from address 06 to generate the data string DS2. After reading the digital data D11 at address 0B, the acquisition calculation circuit 130 starts reading digital data from address 00. Therefore, the data sequence of the data string DS2 is D6-D11, D0-D5.

[0044] In addition, the acquisition calculation circuit 130 may determine a scanning time interval according to a preset algorithm, and output the data of the data strings DS1 and DS2 according to the scanning time interval. In a possible embodiment, the acquisition calculation circuit 130 may adjust the scanning time interval according to a feedback signal, and output the data of the data strings DS1 and DS2 according to the adjusted scanning time interval.

[0045] Please go back Figure 1 , the latch circuit 140 receives and latches the data strings DS1 and DS2. In the present embodiment, the latch circuit 140 is coupled to the pin P1 to receive the data string DS1. The latch circuit 140 latches the data string DS1 and outputs the latched data (or input data) DIN_DAC0 according to a clock signal CLK1. In this example, the latch circuit 140 is further coupled to the pin P2 to receive the data string DS2. The latch circuit 140 latches the data string DS2 and outputs the latched data (or input data) DIN_DAC1 according to the clock signal CLK1. In the present embodiment, the latch circuit 140 synchronously provides the input data DIN_DAC1 and DIN_DAC0.

[0046] The present invention does not limit the architecture of the latch circuit 140. Any circuit with a latch function can be used as the latch circuit 140. In the present embodiment, the latch circuit 140 includes latches 141 and 142. The latch 141 is coupled to the pin P1 to receive and latch the data string DS1. The latch 141 uses the latched data string DS1 as the input data DIN_DAC0 according to a clock signal CLK1. The latch 142 is coupled to the pin P2 to receive and latch the data string DS2, and uses the latched data string DS2 as the input data DIN_DAC1 according to the clock signal CLK1. In a possible embodiment, the latches 141 and 142 synchronously output the input data DIN_DAC0 and DIN_DAC1.

[0047] The present invention does not limit the types of latches 141 and 142. In one possible embodiment, latches 141 and 142 are SR triggers. In this example, the input terminal S of latch 141 is coupled to pin P1 to receive data string DS1. The clock terminal of latch 141 receives clock signal CLK1. The output terminal Q of latch 141 is used to provide input data DIN_DAC0. In addition, the input terminal S of latch 142 is coupled to pin P2 to receive data string DS2. The clock terminal of latch 142 receives clock signal CLK1. The output terminal Q of the latch is used to provide input data DIN_DAC1.

[0048] The digital-to-analog conversion circuit 150 receives and converts the input data DIN_DAC0 and DIN_DAC1 to generate the output waveforms DAC0_OUT and DAC1_OUT. In one possible embodiment, the digital-to-analog conversion circuit 150 further receives a clock signal CLK2. In this example, the digital-to-analog conversion circuit 150 synchronously converts the input data DIN_DAC0 and DIN_DAC1 according to the clock signal CLK2 to synchronously generate the output waveforms DAC0_OUT and DAC1_OUT. In some embodiments, the phase difference between the output waveforms DAC0_OUT and DAC1_OUT is fixed.

[0049] The present invention does not limit the structure of the digital-to-analog conversion circuit 150. In this embodiment, the digital-to-analog conversion circuit 150 includes digital-to-analog converters 151 and 152. The digital-to-analog converter 151 converts the input data DIN_DAC0 according to the clock signal CLK2 to generate the output waveform DAC0_OUT. The digital-to-analog converter 152 converts the input data DIN_DAC1 according to the clock signal CLK2 to generate the output waveform DAC1_OUT. The present invention does not limit the types of the digital-to-analog converters 151 and 152. In one possible embodiment, the digital-to-analog converters 151 and 152 are resistive digital-to-analog converters (RDAC).

[0050] Since the digital data provided by the acquisition calculation circuit 130 can be used by multiple digital-to-analog converters, circuit area can be saved and power consumption can be reduced. In addition, the acquisition calculation circuit 130 provides different digital data to the digital-to-analog conversion circuit 150 at the same time. Therefore, the digital-to-analog conversion circuit 150 can provide multiple output waveforms.

[0051] In some embodiments, after the core circuit 110 creates the digital data D0-D11, it does not need to participate in the operation of the acquisition calculation circuit 130. At this time, the core circuit 110 may enter an idle mode, thereby reducing the power consumption of the core circuit 110. Furthermore, since the memory 120 only needs to store a single data table 121, the available space of the memory 120 can be increased. In other embodiments, the core circuit 110 may perform other operations (different from the operation of the acquisition calculation circuit 130), thereby increasing the utilization rate of the core circuit 110.

[0052] Figure 3 FIG. 3 is another schematic diagram of a waveform generating circuit of the present invention. The waveform generating circuit 300 includes a core circuit 310, an acquisition calculation circuit 330, a latch circuit 340 and a digital-to-analog conversion circuit 350. Since the characteristics of the core circuit 310 are similar to Figure 1The core circuit 110 of the embodiment is not described in detail. In addition, in the present embodiment, the acquisition calculation circuit 330 further provides a data string DS3. In this example, the acquisition calculation circuit 330 has a pin P3 for outputting the data string DS3. Since the acquisition calculation circuit 330 generates the data string DS3 in the same manner as the data string DS1, it is not described in detail.

[0053] Figure 4 Schematic diagram of the relationship between the data table 321 and the data strings DS1-DS3 of the present invention. The acquisition calculation circuit 330 may use addresses 02, 06 and 0A as the first to third starting addresses respectively. In this example, the acquisition calculation circuit 330 starts reading digital data from addresses 02, 06 and 0A respectively to generate data strings DS1-DS3. In this embodiment, the data sequence of the data string DS1 is D2-D11, D0, D1, the data sequence of the data string DS2 is D6-D11, D0-D5, and the data sequence of the data string DS3 is D10, D11, D0-D9.

[0054] In some embodiments, when the acquisition calculation circuit 330 selects different starting addresses, the corresponding output waveforms have different phase differences. For example, assume that the acquisition calculation circuit 330 starts reading digital data from address 02 and uses the read result as data string DS1, and starts reading digital data from address 06 and uses the read result as data string DS2. In this example, there is a first phase difference between the output waveform DAC0_OUT and the output waveform DAC1_OUT. However, when the acquisition calculation circuit 330 starts reading digital data from address 05 and uses the read result as data string DS2, there is a second phase difference between the output waveform DAC0_OUT and the output waveform DAC1_OUT. In this example, the second phase difference may be smaller than the first phase difference. In some embodiments, when the acquisition calculation circuit 330 starts reading digital data from address 07 and uses the read result as data string DS2, there is a third phase difference between the output waveform DAC0_OUT and the output waveform DAC1_OUT. In this example, the third phase difference may be greater than the first phase difference.

[0055] Please go back Figure 3 , the latch circuit 340 receives and latches the data strings DS1-DS3, and uses the latched data strings DS1-DS3 as input data DIN_DAC0-DIN_DAC2 respectively according to the clock signal CLK1. In this embodiment, the latch circuit 340 includes latches 341-343. Since the characteristics of the latches 341-343 are similar to Figure 1 The latch 141 is not described in detail.

[0056] The digital-to-analog conversion circuit 350 receives and converts input data DIN_DAC0 to DIN_DAC2 to generate output waveforms DAC0_OUT to DAC2_OUT. In one possible embodiment, the digital-to-analog conversion circuit 350 includes digital-to-analog converters 351 to 353. The digital-to-analog converter 351 converts the input data DIN_DAC0 according to the clock signal CLK2 to generate the output waveform DAC0_OUT. The digital-to-analog converter 352 converts the input data DIN_DAC1 according to the clock signal CLK2 to generate the output waveform DAC1_OUT. The digital-to-analog converter 353 converts the input data DIN_DAC2 according to the clock signal CLK2 to generate the output waveform DAC2_OUT. Since the characteristics of the digital-to-analog converters 351 to 353 are similar to Figure 1 The digital-to-analog converter 151 is not described in detail.

[0057] In a possible embodiment, the waveform generating circuit 300 further includes a trigger circuit 360. The trigger circuit 360 generates a clock signal CLK2 to trigger the digital-to-analog converters 351-353. Take the digital-to-analog converter 351 as an example. When the digital-to-analog converter 351 receives the clock signal CLK2, the digital-to-analog converter 351 starts to convert the input data DIN_DAC0.

[0058] In this embodiment, the waveform generating circuit 300 further includes a switch circuit 370. The switch circuit 370 is coupled between the trigger circuit 360 and the digital-to-analog converters 352 and 353. When a trigger event occurs, the switch circuit 370 transmits the clock signal CLK2 to the digital-to-analog converters 352 and 353. Therefore, the digital-to-analog converters 352 and 353 operate simultaneously. However, when the trigger event does not occur, the switch circuit 370 does not transmit the clock signal CLK2 to the digital-to-analog converters 352 and 353. Therefore, only the digital-to-analog converter 351 operates, while the digital-to-analog converters 352 and 353 stop operating.

[0059] The present invention does not limit the architecture of the switch circuit 370. In one possible embodiment, the switch circuit 370 includes switches 371 and 372. The switch 371 is coupled between the trigger circuit 360 and the digital-to-analog converter 353, and receives the switching signal GRPEN. The switch 372 is coupled between the trigger circuit 360 and the digital-to-analog converter 352, and receives the switching signal GRPEN. When a trigger event occurs, the switching signal GRPEN is enabled. Therefore, the switches 371 and 372 are turned on. When the trigger event does not occur, the switching signal GRPEN is not enabled. Therefore, the switches 371 and 372 are not turned on.

[0060] In other embodiments, switches 371 and 372 receive different switching signals. In this example, when different trigger events occur, the corresponding switching signals are enabled to turn on the corresponding switches. For example, when the first trigger event occurs, switch 371 is turned on. When the first trigger event does not occur, switch 371 is not turned on. In this example, when the second trigger event occurs, switch 372 is turned on. When the second trigger event does not occur, switch 372 is not turned on.

[0061] In this embodiment, the digital-to-analog converters 351-353 further receive operating voltages AVDD, DVDD, AGND, and DGND. The operating voltages AVDD and AGND are used for analog components inside the digital-to-analog converter, wherein the operating voltage AVDD is higher than the operating voltage AGND. The operating voltages DVDD and DGND are used for digital components inside the digital-to-analog converter, wherein the operating voltage DVDD is higher than the operating voltage DGND.

[0062] In some embodiments, the digital-to-analog converters 351-353 further receive a power-on control signal PON. When the operating voltages AVDD, DVDD, AGND, and DGND are not yet stable, the power-on control signal PON is disabled. Therefore, the digital-to-analog converters 351-353 are temporarily inactive. When the operating voltages AVDD, DVDD, AGND, and DGND are stable, the power-on control signal PON is enabled. Therefore, the digital-to-analog converters 351-353 start to operate.

[0063] In other embodiments, the digital-to-analog converters 351-353 further receive reference voltages VREFP and VREFM. Taking the digital-to-analog converter 351 as an example, the digital-to-analog converter 351 may have a resistor string. The resistor string receives the reference voltages VREFP and VREFM, and performs a voltage division operation on the reference voltage VREFP to generate a plurality of divided voltages. In one possible embodiment, the digital-to-analog converter 351 selects and outputs a corresponding divided voltage according to the value of the input data DIN_DAC2.

[0064] In another embodiment, the digital-to-analog converters 351-353 further receive a power down signal (power down) pd. In this example, when the power down signal pd is enabled, the digital-to-analog converters 351-353 enter a power saving mode. In the power saving mode, the digital-to-analog converters 351-353 suspend their operations.

[0065] In other embodiments, the waveform generating circuit 300 further includes a switching circuit 380. The switching circuit 380 includes switches 381-383. The switch 381 is coupled to the digital-to-analog converter 351. The switch 382 is coupled to the digital-to-analog converter 352. The switch 383 is coupled to the digital-to-analog converter 353. In this example, the switches 381-383 are respectively controlled by the switching signals SC1-SC3. When the switching signals are enabled, the corresponding switches output the corresponding output waveforms. Taking the switch 383 as an example, when the switching signal SC3 is enabled, the switch 383 outputs the output waveform DAC2_OUT. When the switching signal SC3 is not enabled, the switch 383 stops outputting the output waveform DAC2_OUT.

[0066] Figure 5 Schematic diagram of output waveforms DAC0_OUT~DAC2_OUT. At sampling time points S1~S12, the acquisition calculation circuit 330 sequentially outputs digital data D2~D11, D0, and D1 through pin P1. In this example, the digital data D2~D11, D0, and D1 constitute a data string DS1. The latch 341 latches the digital data D2~D11, D0, and D1, and sequentially outputs the digital data D2~D11, D0, and D1 of the data string DS1 according to the clock signal CLK1. The digital-to-analog converter 351 converts the digital data D2~D11, D0, and D1 into an analog signal. In this embodiment, the output waveform DAC0_OUT generated by the digital-to-analog converter 351 is a sine wave, but it is not intended to limit the present invention. In other embodiments, the amplitude and shape of the output waveform DAC0_OUT can be adjusted by adjusting the values ​​of the digital data D2~D11, D0, and D1. In some embodiments, by adjusting the time interval between the sampling time points S1-S12, the frequency of the output waveform DAC0_OUT can be adjusted. When the amount of data in the data string DS1 is larger, the output waveform DAC0_OUT is smoother.

[0067] In this embodiment, at sampling time points S1-S12, the acquisition calculation circuit 330 sequentially outputs digital data D10, D11, D0-D9 through the pin P2. In this example, the digital data D10, D11, D0-D9 constitute a data string DS2. The latch 342 latches the digital data D10, D11, D0-D9, and sequentially outputs the digital data D10, D11, D0-D9 to the digital-to-analog converter 352 according to the clock signal CLK1. The digital-to-analog converter 352 converts the digital data D10, D11, D0-D9 into analog signals. In this embodiment, the output waveform DAC1_OUT generated by the digital-to-analog converter 352 is also a sine wave.

[0068] At sampling time points S1-S12, the acquisition calculation circuit 330 sequentially outputs digital data D6-D11, D0-D5 through the pin P3. In this example, the digital data D6-D11, D0-D5 constitute the data string DS3. The latch 343 latches the digital data D6-D11, D0-D5, and sequentially outputs the digital data D6-D11, D0-D5 of the data string DS3 to the digital-to-analog converter 353 according to the clock signal CLK1. The digital-to-analog converter 353 converts the digital data D6-D11, D0-D5 into analog signals. The output waveform DAC2_OUT generated by the digital-to-analog converter 353 is also a sine wave.

[0069] In this embodiment, the phase difference between the output waveforms DAC0_OUT to DAC2_OUT remains unchanged. For example, the output waveforms DAC0_OUT and DAC1_OUT have a phase difference of 120 degrees, and the output waveforms DAC1_OUT and DAC2_OUT have a phase difference of 120 degrees. In other embodiments, after the sampling time point S12, the acquisition calculation circuit 330 continues to repeatedly output the data strings DS1 to DS3 through the pins P1 to P3. Therefore, the digital-to-analog converters 351 to 353 each generate a continuous sine wave.

[0070] Figure 6 Schematic diagram of the application of the waveform generating circuit of the present invention. As shown in the figure, the operating system 600 includes a core circuit 610, an acquisition calculation circuit 630, a latch circuit 640, a digital-to-analog conversion circuit 650, an application circuit 660 and a sensor circuit 670. The core circuit 610 establishes a plurality of digital data. In one possible embodiment, the data table 621 records the digital data established by the core circuit 610. In another possible embodiment, the operating system 600 further includes a memory 620 for storing the data table 621. Since the characteristics of the core circuit 610 and the data table 621 are the same as Figure 1 The core circuit 110 and the data table 121 are not described in detail.

[0071] The acquisition calculation circuit 630 generates data strings DS1-DS3 according to the digital data of the data table 121, and outputs the data strings DS1-DS3 according to a sampling time interval. Each of the data strings DS1-DS3 includes the digital data of the data table 121. Since the acquisition calculation circuit 630 generates the data strings DS1-DS3 in the same manner as Figure 1 The manner in which the acquisition calculation circuit 130 generates the data strings DS1-DS3 is not described in detail. In other embodiments, the acquisition calculation circuit 630 may generate more or fewer data strings.

[0072] In this embodiment, the acquisition calculation circuit 630 adjusts the sampling time interval according to a feedback signal SFB to generate an updated sampling time interval. In this example, the acquisition calculation circuit 630 outputs the data strings DS1-DS3 according to the updated sampling time interval. In a possible embodiment, the acquisition calculation circuit 630 adjusts the sampling time interval according to the feedback signal SFB to generate an updated sampling time interval. Figure 5 Taking the scanning time points S1 and S2 as an example, the acquisition calculation circuit 630 may reduce or increase the scanning time interval between the scanning time points S1 and S2. In this example, when the sampling time interval of the scanning time points S1 to S12 changes, the frequency of the output waveforms DAC0_OUT to DAC2_OUT also changes accordingly.

[0073] The latch circuit 640 receives and latches the data strings DS1-DS3, and uses the data strings DS1-DS3 as input data DIN_DAC0-DIN_DAC2, respectively. Figure 1 The characteristics of the latch circuit 140 are similar, so they are not described again. In this embodiment, the latch circuit 640 outputs the input data DIN_DAC0 to DIN_DAC2 simultaneously.

[0074] The digital-to-analog conversion circuit 650 receives the input data DIN_DAC0-DIN_DAC2 and converts the input data DIN_DAC0-DIN_DAC2 from digital format to analog format. In this example, the digital-to-analog conversion circuit 650 outputs the converted analog signals as the output waveforms DAC0_OUT-DAC2_OUT. Figure 1 The characteristics of the digital-to-analog conversion circuit 150 are similar, so they are not described in detail. In this embodiment, the digital-to-analog conversion circuit 650 provides output waveforms DAC0_OUT to DAC2_OUT at the same time.

[0075] The application circuit 660 operates according to the output waveforms DAC0_OUT to DAC2_OUT. The present invention does not limit the type of the application circuit 660. In one possible embodiment, the application circuit 660 includes a motor. In this case, the application circuit 660 may further include an amplifier circuit (not shown). The amplifier circuit processes the output waveforms DAC0_OUT to DAC2_OUT to generate a signal sufficient to drive the motor. Therefore, the motor operates according to the output waveforms DAC0_OUT to DAC2_OUT. In other embodiments, the application circuit 660 may include a speaker or a light-emitting device. In this case, the application circuit 660 emits a sound or emits light according to the output waveforms DAC0_OUT to DAC2_OUT.

[0076] The sensing circuit 670 detects the operating state of the application circuit 660 to generate a feedback signal SFB. In one embodiment, the sensing circuit 670 includes at least one Hall sensor. The Hall sensor generates a feedback signal SFB according to the motor speed. In this example, the acquisition calculation circuit 630 adjusts the feedback signal SFB according to the feedback signal SFB. Figure 5 The sampling time interval of the scanning time point.

[0077] For example, during an initial period, the acquisition calculation circuit 630 first sets the time interval of the sampling time points (eg Figure 5 The sampling time interval is set to the interval between two adjacent sampling time points, and then the data string DS1~DS3 is output. At this time, the frequency of the output waveform DAC0_OUT~DAC2_OUT may be equal to a first frequency (or preset frequency). When the acquisition calculation circuit 630 learns that the motor speed has changed (such as faster or slower) according to the feedback signal SFB, the acquisition calculation circuit 630 adjusts the time interval of the sampling time points to generate an updated sampling time interval. The acquisition calculation circuit 630 outputs the data string DS1~DS3 according to the updated sampling time interval to adjust the frequency of the output waveform DAC0_OUT~DAC2_OUT. At this time, the frequency of the output waveform DAC0_OUT~DAC2_OUT may be equal to a second frequency. In this example, the second frequency is different from the first frequency. In other embodiments, the sensor circuit 670 includes an audio sensor or a photo sensor.

[0078] In some embodiments, the phase difference between the output waveforms DAC0_OUT and DAC1_OUT is 120 degrees, and the phase difference between the output waveforms DAC1_OUT and DAC2_OUT is 120 degrees. In other embodiments, after the core circuit 610 establishes the digital data, the acquisition calculation circuit 630, the latch circuit 640, and the digital-to-analog conversion circuit 650 can operate independently of the core circuit 610. In this example, once the core circuit 610 establishes the digital data, the acquisition calculation circuit 630, the latch circuit 640, and the digital-to-analog conversion circuit 650 operate independently according to the digital data established by the core circuit 610. The core circuit 610 does not need to intervene in the operation of the calculation circuit 630, the latch circuit 640, and the digital-to-analog conversion circuit 650.

[0079] In this embodiment, even when the core circuit 610 is idle, the acquisition calculation circuit 630, the latch circuit 640 and the digital-to-analog conversion circuit 650 continue to operate. In addition, the application circuit 660 and the sensor circuit 670 also continue to operate. In this example, since the acquisition calculation circuit 630 adjusts the sampling time interval according to the feedback signal SFB, the core circuit 610 can perform other operations.

[0080] In other embodiments, when the acquisition calculation circuit 630 adjusts the sampling time interval, the acquisition calculation circuit 630 may maintain outputting three specific data, so that the digital-to-analog conversion circuit 650 maintains outputting three DC values ​​of different levels. For example, the acquisition calculation circuit 630 may use a first specific data, a second specific data, and a third specific data as data strings DS1-DS3, respectively. Therefore, the output waveforms DAC0_OUT-DAC2_OUT are maintained at a first specific level, a second specific level, and a third specific level, respectively. In a possible embodiment, the first to third specific levels are different.

[0081] In some embodiments, the acquisition calculation circuit 630 stops updating the data string DS1-DS3 according to the feedback signal SFB. In this example, when the magnetic flux or voltage received by the sensor circuit 670 reaches a preset value, the acquisition calculation circuit 630 starts to adjust the sampling time interval. Since the operation of adjusting the sampling time interval does not require the intervention of the core circuit 610, the power consumption of the core circuit 610 can be saved. In other embodiments, when the output waveform generated by the digital-to-analog conversion circuit 650 does not have a complete cycle, the digital-to-analog conversion circuit 650 continues to output the corresponding output waveform until the corresponding waveform has a complete cycle, and the digital-to-analog conversion circuit 650 will act according to the adjusted input data.

[0082] Unless otherwise defined, all terms (including technical and scientific terms) herein are generally understood by those skilled in the art. In addition, unless expressly stated, the definitions of terms in general dictionaries should be interpreted as consistent with the meanings in articles in the relevant technical field, and should not be interpreted as ideal or overly formal. Although the terms "first", "second", etc. may be used to describe various components, data, and levels, these components, data, and levels should not be limited by these terms. These terms are only used to distinguish one component, data, and level from another component, data, and level.

[0083] Although the present invention has been described above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the definition of the above claims.

Claims

1. A waveform generating circuit, characterized in that: include: One core circuit, builds multiple digital data; an acquisition calculation circuit, generating a first data string and a second data string according to the plurality of digital data, and outputting the first data string through a first pin, and outputting the second data string through a second pin; a latch circuit, receiving and latching the first data string and the second data string, and using the first data string and the second data string as a first input data and a second input data respectively; and a digital-to-analog conversion circuit, receiving and converting the first input data and the second input data to generate a first output waveform and a second output waveform; After the core circuit establishes the plurality of digital data, the acquisition calculation circuit, the latch circuit and the digital-to-analog conversion circuit operate independently of the core circuit.

2. The waveform generating circuit according to claim 1, wherein: When the core circuit is idle, the acquisition calculation circuit, the latch circuit and the digital-to-analog conversion circuit operate.

3. The waveform generating circuit according to claim 1, wherein: The latch circuit includes: a first latch, coupled to the first pin, for receiving the first data string and using the first data string as the first input data according to a first clock signal; and A second latch is coupled to the second pin and is used for receiving the second data string and using the second data string as the second input data according to the first clock signal.

4. The waveform generating circuit according to claim 3, characterized in that: The digital-to-analog conversion circuit comprises: a first digital-to-analog converter, converting the first input data according to a second clock signal to generate the first output waveform; and A second digital-to-analog converter converts the second input data according to the second clock signal to generate the second output waveform.

5. The waveform generating circuit according to claim 4, characterized in that: Also includes: a third latch receiving a third data string and using the third data string as a third input data according to the first clock signal; and a third digital-to-analog converter, converting the third input data according to the second clock signal to generate a third output waveform; The acquisition calculation circuit generates the third data string according to the plurality of digital data, and outputs the third data string through a third pin, and the third latch is coupled to the third pin.

6. The waveform generating circuit according to claim 1, wherein: The acquisition calculation circuit acquires the multiple digital data in a first preset order to generate the first data string, and acquires the multiple digital data in a second preset order to generate the second data string. The first preset order is different from the second preset order.

7. The waveform generating circuit according to claim 1, wherein: When a trigger event occurs, the digital-to-analog conversion circuit starts converting the first input data and the second input data.

8. The waveform generating circuit according to claim 1, wherein: The first data string and the second data string include the plurality of digital data.

9. The waveform generating circuit according to claim 1, wherein: At a first sampling time point, the acquisition calculation circuit outputs a first data in the first data string through the first pin, and outputs a second data in the second data string through the second pin; At a second sampling time point, the acquisition calculation circuit outputs a third data in the first data string through the first pin, and outputs a fourth data in the second data string through the second pin, and the third data is equal to the second data or the fourth data.

10. The waveform generating circuit according to claim 1, wherein: The phase difference between the first output waveform and the second output waveform is fixed.

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