A fast Fourier transform digital signal noise processing method based on FPGA

Abstract

The present invention discloses a fast Fourier transform digital noise processing method based on FPGA. The flexible digital circuit processing technology is combined with the FFT algorithm, and the floating point number calculation function of the DSP in the FPGA chip is utilized. By appropriately expanding the digital effective word length and retaining the high and low bits of the output data maximum effective bit truncation principle, the digital truncation noise of the FFT algorithm based on the FPGA chip is reduced to the maximum extent without significantly increasing the FPGA resource occupation, the FFT analysis sensitivity based on the FPGA chip is improved, and the analysis dynamic range of the FFT is expanded. Compared with the traditional FFT algorithm based on the FPGA chip, the present invention has less resource occupation, and at the same time, the effective bits of the data are retained to the maximum extent, and the truncation noise of the digital signal is reduced.

Description

[0001] Technology Neighborhood

[0002] The invention belongs to the field of electronic information technology, and more specifically, relates to a fast Fourier transform digital signal noise processing method based on FPGA. Background Art

[0003] With the rapid development of modern new materials and MEMS technology, the integration of chips is getting higher and higher, and the working speed is getting faster and faster. Digital signal processing core devices such as ADC, DAC, DSP and FPGA are also developing rapidly. The working frequency band has expanded from hundreds of megahertz to tens of gigahertz, breaking through many functional limits of analog circuits, allowing a large number of signal processing functions to be transferred from analog circuits to digital circuits, achieving a significant improvement in the level of signal processing in fields from detection, navigation to communication.

[0004] Chip resources, operating speed, and effective processing bit number in digital circuits have always been three important performances that restrict each other and represent the level of signal processing. Faced with signals in the frequency bands of tens or even hundreds of gigahertz and complex computing functions such as FFT and DSP, the signal processing of digital chips often sacrifices the number of effective processing bits to meet related needs. For example, the conversion bit number of ADCs of tens of gigahertz generally does not exceed 16 bits, and most are 8 or 12 bits. The corresponding word lengths of FFT and DSP algorithms are also based on this standard, which limits the dynamic range and sensitivity of signal processing. In particular, the ability to identify weak spectral lines of signals based on FFT is greatly limited. The dynamic range, an important indicator of spectrum analysis, is completely subject to the limited working word length of digital circuit modules.

[0005] The finite word length of a digital signal processing system represents the difference between the maximum and minimum values ​​of the processed signal. The truncation error caused by the finite word length in the process of digital signal processing will be superimposed on the noise of the digital circuit input signal in the form of digital noise, thereby deteriorating the sensitivity index of the system and limiting the detection and analysis of weak signals (such as atmospheric radiation, cosmic radio, etc.).

[0006] In digital signal analysis and processing, the finite word length effect can cause three types of errors: analog-to-digital converter (ADC) quantization error, binary finite word length coefficient quantization error, and truncation error during the operation process. Among the three errors, the quantization error caused by the ADC depends on the number of conversion bits of the analog-to-digital converter and is determined by the performance of the device itself; the coefficient quantization error and truncation error are determined by the digital signal processing model. In floating-point signal processing, that is, general-purpose computer operations, due to the large number of operation bits, the finite word length effect is not obvious, the resulting error is small, and the impact on the signal-to-noise ratio is not significant. However, in fixed-point operations, such as digital signal processing based on FPGA, due to the constraints of limited resources, the increase in the number of operation bits will greatly consume chip resources. This problem is generally solved by setting a finite word length, but this will lead to a significant increase in digital noise. Studying the finite word length effect in the fixed-point operation process and reducing the impact of truncation noise are important studies to improve the signal processing capabilities of digital chips.

[0007] For N-point discrete Fourier transform:

[0008]

[0009] The Fast Fourier Transform (FFT) established by butterfly operation can simplify the operation, greatly reduce the amount of calculation and improve the calculation speed. The calculation process of the FFT core based on FPGA involves complex multiplication and addition. The primary problem of fixed-point number operation with effective word length is to prevent overflow. Since the maximum output signal word length of each level of butterfly operation in FFT is twice its input signal. For the FFT of L data, there are n=log2L levels of bow ties, so the maximum value of the final output signal length of FFT is 2n=L times the input signal. Therefore, the following two methods are generally used to solve the overflow. The first is to change the effective word length of the input signal to 1 / L of the original, and the second is to distribute the reduction factor of 1 / L to each level of operation, that is, to truncate the effective word length of the output of each level and change its word length to 1 / 2 of the original.

[0010] Although the above method can prevent overflow, the reduction of the effective word length is essentially digital truncation, which will introduce greater digital noise, deteriorate the signal-to-noise ratio of the processed signal, and reduce the sensitivity of system analysis. Especially in FFT operations on FPGA chips with high development freedom, how to reduce the digital noise caused by digital signal processing, maximize the signal-to-noise ratio, and improve the sensitivity of system analysis and dynamic range is a new challenge in the field of digital signal processing. Summary of the invention

[0011] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a fast Fourier transform digital noise processing method based on FPGA to solve the problem that the FFT algorithm based on large-scale integrated circuits is limited by chip resources, resulting in increased digital noise and decreased analysis sensitivity during the analysis and calculation process.

[0012] To achieve the above-mentioned object of the invention, the fast Fourier transform digital noise processing method based on FPGA of the present invention is characterized by comprising the following steps:

[0013] (1) According to the analog-to-digital conversion (ADC) output data word length M, set the basic effective word length of FPGA processing to M;

[0014] (2) Decompose the FFT processing flow according to the FFT butterfly algorithm, L = 2 n The FFT butterfly operation of time domain data is decomposed into n-level calculations;

[0015] (3) The first level of the FFT butterfly algorithm is an addition and subtraction operation. The maximum word length is increased by one overflow bit, that is, the word length of the real and imaginary parts of the output result is increased by one bit. When the ADC output data word length is M, the word length of each output data processed in the first level is set to 2(M+1), and the total output word length is 2 n+1 (M+1);

[0016] (4) The second-level processing of the FFT butterfly algorithm is also an addition and subtraction operation. The maximum word length is increased by one bit to overflow, that is, the word length of the real and imaginary parts of the output result is increased by one bit each; the word length of each output data of the second-level processing is set to 2(M+2) bits, and the total output word length is 2 n+1 (M+2);

[0017] (5) The third level of the FFT butterfly algorithm involves complex multiplication of the input data and the rotation factor. Let the rotation factor have the same word length as the input data of this level: the real part and the imaginary part are M+2 bits each, that is, there are 2(M+2) bits. The floating point number of the DSP core is used for calculation. The DSP core calculation output is truncated in high and low bits according to the principle of retaining the maximum number of significant bits of the output data. The word length of each output data changes from 4(M+2)+2 to 2(M+3), and the total output word length is 2 n+1 (M+3), the truncation flag is set at the same time, and the subsequent calculation bits are aligned according to the truncation flag;

[0018] The principle of retaining the maximum number of effective bits of the output data is as follows: high-bit truncation is to truncate all high bits before the first non-zero bit of the output data to ensure that the highest bit of the output data is non-zero; low-bit truncation is to ensure that the word length of the output data is the same as the word length of the input data; the truncation flag is the number of bits of high-bit truncation, and the data is padded with zeros and aligned according to the truncation flag in subsequent calculations;

[0019] (6) The 4th to nth level processing of the FFT butterfly algorithm also involves complex multiplication of the input data and the rotation factor. For the i-th level processing, i = 4, 5, ..., n, let the rotation factor have the same word length as the input data, with the real part and the imaginary part each having M + i-1 bits, that is, 2 (M + i-1) bits. The floating point number of the DSP core is used for calculation. The high and low bits of the DSP core calculation output are truncated according to the principle of retaining the maximum number of significant bits of the output data. The word length of each output data changes from 4 (M + i-1) to 2 (M + i), and the total output word length is 2 n+1 (M+i), and set the truncation flag at the same time. The subsequent calculation bits are aligned according to the truncation flag. The word length of each output data of the FFT butterfly algorithm is 2(M+n), and the total data output word length is 2 n+1 (M+n).

[0020] The object of the invention of the present invention is achieved in this way:

[0021] The invention relates to a fast Fourier transform digital noise processing method based on FPGA, which combines a flexible digital circuit processing word length setting technology with an FFT algorithm, fully utilizes the floating point number calculation function of a DSP in an FPGA chip, appropriately expands the effective word length in the calculation process, and performs high and low bit truncation respectively according to the principle of retaining the maximum effective bit number of output data during truncation. This method reduces the digital truncation noise of the FFT algorithm based on the FPGA digital chip to the maximum extent without significantly increasing the FPGA resource occupation, improves the FFT analysis sensitivity based on the FPGA chip, and expands the analysis dynamic range of the FFT.

[0022] Compared with the traditional FFT algorithm based on FPGA chip, the present invention increases the resource occupation by n*2n+1, but retains the data valid bits to the greatest extent and reduces the digital signal truncation noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a flowchart of a specific implementation of the fast Fourier transform digital noise processing method based on FPGA of the present invention;

[0024] Figure 2 It is a 5-level FFT butterfly operation signal flow graph;

[0025] Figure 3 It is the signal flow graph of the first level processing of the FFT butterfly algorithm;

[0026] Figure 4 It is the signal flow graph of the second level processing of the FFT butterfly algorithm;

[0027] Figure 5 It is the signal flow graph of the third level processing of the FFT butterfly algorithm;

[0028] Figure 6 Two specific examples of the method of retaining the maximum number of significant digits of the output data truncation, where (a) is the case where the input data is slightly larger, and (b) is the case where the input data is smaller;

[0029] Figure 7 Comparison chart of the experimental results of the traditional FFT algorithm and the present invention. DETAILED DESCRIPTION

[0030] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0031] Figure 1 It is a flowchart of a specific implementation of the fast Fourier transform digital noise processing method based on FPGA of the present invention.

[0032] In this embodiment, if Figure 1 As shown, the fast Fourier transform digital noise processing method based on FPGA of the present invention comprises the following steps:

[0033] Step S1: Set the effective word length M

[0034] According to the analog-to-digital conversion (ADC) output data word length M, set the basic effective word length of FPGA processing to M.

[0035] Step S2: Decompose the FFT process into n levels

[0036] Decompose the FFT processing flow according to the FFT butterfly algorithm, L = 2 n The FFT butterfly operation of time domain data is decomposed into n-level calculations.

[0037] Step S3: FFT butterfly algorithm first level processing, each output data word length increases by one bit

[0038] The first level of the FFT butterfly algorithm is an addition and subtraction operation, and the maximum word length is increased by one overflow bit. Since the processed data is a complex number, the real and imaginary word lengths of the output result (i.e., output data) are increased by one bit each. In this way, when the ADC output data word length is M, the word length of each output data processed by the first level FFT is set to 2(M+1), and the total output word length is 2 n+1 (M+1). This ensures that no digital noise is generated in the first stage of the FFT butterfly algorithm processing.

[0039] Step S4: FFT butterfly algorithm second level processing, each output data word length increases by one bit

[0040] The second level of processing of the FFT butterfly algorithm is also an addition and subtraction operation. The maximum word length is increased by one bit to overflow, and the real and imaginary word lengths of the output results are increased by one bit each. Each output data of the second level processing is 2(M+2) bits, and the total output word length is 2 n +1 (M+2), similarly, it can be ensured that no digital noise is generated in the first stage processing of the FFT butterfly algorithm.

[0041] Step S5: FFT butterfly algorithm third level processing and maximum effective bit number truncation

[0042] The third level of the FFT butterfly algorithm involves complex multiplication of the input data and the rotation factor. Let the rotation factor have the same word length as the input data of this level: M+2 bits for the real part and M+2 bits for the imaginary part, that is, 2(M+2) bits. The floating point number of the DSP core is used for calculation, where the word length of each output data after multiplication is 4(M+2), and after addition and subtraction operations, the word length becomes 4(M+2)+2, and the total output word length is 2 n+2 (M+2)+2 n+1 Bit.

[0043] With the addition of complex multiplication, the output data occupies a geometric increase in FPGA chip resources. In order to minimize the truncation noise and not increase the resource usage, the DSP core calculation output is truncated in high and low bits according to the principle of retaining the maximum number of significant bits of the output data. The word length of each output data is changed from 4(M+2)+2 to 2(M+3), and the total output word length is 2 n+1 (M+3), and set the truncation flag at the same time. The subsequent calculation bits are aligned according to the truncation flag.

[0044] The principle of truncation for retaining the maximum number of valid bits of the output data is as follows: high-bit truncation is to truncate all high bits before the first non-zero bit of the output data to ensure that the highest bit of the output data is non-zero; low-bit truncation is to ensure that the word length of the output data is the same as the word length of the input data; the truncation flag is the number of high-bit truncation bits, and in subsequent calculations, data is padded with zeros for alignment based on the truncation flag.

[0045] Step S5: FFT butterfly algorithm stage 4 to stage n processing, and maximum significant digit truncation

[0046] The 4th to nth level processing of the FFT butterfly algorithm also involves complex multiplication of the input data and the rotation factor. For the i-th level, i=4,5,…,n, let the rotation factor be the same as the word length of the input data, with the real and imaginary parts each having M+i-1 bits, that is, 2(M+i-1) bits. The floating-point numbers of the DSP core are used for calculations, and the DSP core calculation output is truncated at the high and low bits respectively according to the principle of retaining the maximum number of significant bits of the output data. At the same time, the overflow phenomenon of addition and subtraction operations is considered, and the word length of each output data is changed from 4(M+i-1) to 2(M+i), and the total output word length is 2 n+1 (M+i), and set the truncation flag at the same time, and the subsequent calculation bits are aligned according to the truncation flag.

[0047] Compared with the traditional FFT algorithm based on FPGA chip, the present invention increases the resource occupation by n*2 n+1 , but retains the valid data bits to the greatest extent and reduces the digital signal truncation noise.

[0048] Examples

[0049] Figure 2 The present invention is 32=2 5 A signal flow diagram showing a 5-stage FFT butterfly operation on time domain data output by (i.e., n=5) analog-to-digital converters (ADCs).

[0050] In this embodiment, if Figure 2 As shown, 32 analog-to-digital conversion (ADC) output time domain data, represented as: {x(0), x(1), ..., x(30), x(31)}, are reordered to form a new sequence {x(0), x(16), ..., x(15), x(31)} in reverse binary order, and then five-level processing is performed.

[0051] For level 1 treatment, follow Figure 3 The signal stream performs FFT butterfly operation on the 32 sorted data at the first level of addition and subtraction.

[0052] The first-level butterfly operation only involves the addition and subtraction of complex numbers. When operating in FPGA, considering that the result may have a one-bit overflow, the word length of the real and imaginary parts of the operation result is increased by one bit to ensure that no error is introduced during the calculation process. The word length of each data of the first-level input Reverse_order_first_stage[0] and [1] is 2M, and the total word length is 64M. According to the above principle, the word length of each data of the output Output_first_stage[0] and [1] is 2(M+1), and the total word length is 64(M+1).

[0053] For Level 2 treatment, follow Figure 4 The signal flow performs the second-level addition and subtraction calculations on the first-level output data of the butterfly operation.

[0054] The input of the second stage is the 32 complex data output by the first stage, each data word length is 2(M+1), and the total word length is 64(M+1). Figure 4 As shown, there are 8 groups of butterfly operations performed on the second-level input, such as Figure 2 As shown. For each group, the first and third only involve addition and subtraction operations, and the second and fourth involve multiplication by -i. For the complex number a+bi, multiplication by -i equals b-ai. Therefore, the real and imaginary parts of the second-level butterfly operation output data are enlarged by 1 bit to ensure that the result does not introduce noise. That is, each output data word length is 2 (M+2), and the total word length is 64 (M+2).

[0055] according to Figure 5 The signal flow performs the third-level calculation on the output data of the second-level butterfly operation. The input of the third level is the 32 complex data output by the second level, each data word length is 2 (M + 2), and the total word length is 64 (M + 2). However, unlike the first two levels which only involve addition and subtraction operations, the third level involves complex multiplication of input data and rotation factors, and needs to consider the quantization of the rotation factors and the truncation of the output results.

[0056] Let the rotation factor be the same as the word length of the input data, that is, 2(M+2) bits. The word length of the result obtained after complex multiplication of the input data and the rotation factor is 4(M+2). The calculation process is as follows Figure 5 shown. Figure 5 Input_third_stage[5] and Input_third_stage[7] in the output are multiplied by the rotation factor, and the resulting word length is 4(M+2). Since the word length of the other 6 data is still 2(M+2), they are expanded to a word length of 4(M+2) before addition and subtraction operations are performed.

[0057] In the process of floating-point calculation for multiplication and addition and subtraction using DSP, no truncation is performed. The output data is truncated at the high and low bits respectively according to the principle of retaining the maximum number of effective digits. At the same time, the truncation flag is set, and the data is aligned according to the flag in subsequent calculations. Figure 5 Input data Re(d i ) is 2, and the rotation factor Re(W 32 4) The result after multiplication is Figure 6 (a) is shown. According to the traditional method (such as Figure 6 (a) virtual box), the output data has an effective number of 1; according to the present invention, the truncation (such as Figure 6 (a) solid box), the output data effective number of bits is 8, the same as the input data word length, that is, without increasing the chip resource usage, the output data effective number of bits is greatly improved. If the input data is smaller, such as Figure 6 (b) shows that Re(di) is 1, then after multiplication with the rotation factor and truncation in the traditional way, the output data is zero; after truncation according to the present invention, the output data is non-zero, and its effective number of bits is the same as the input data word length. The principle of retaining the maximum effective number of bits of the output data can realize FFT analysis of weak input signals, reduce digital truncation noise, and improve FFT analysis sensitivity.

[0058] Figure 6 In (a), if the high-order digit is truncated to 7, the truncated flag data is 7. In subsequent addition and subtraction operations, all data are padded with zeros according to the flag information and aligned.

[0059] According to the output word length setting rules of the 1st and 2nd levels, the real and imaginary parts of the addition and subtraction operations are expanded by 1 bit, and the final output data word length is 2(M+3), and the total word length is 64(M+3).

[0060] Perform the fourth and fifth level calculations on the third level output data of the butterfly operation. Figure 2 As shown, the fourth and fifth level calculations divide the 32 previous level output data into four groups and two groups for butterfly operations respectively. Similar to the third level, there are complex multiplications with rotation factors in the fourth and fifth level calculations. The floating point calculation function and output truncation method of the DSP in the third level are also used. The input data word length of the fourth level is 2 (M + 4), and the total word length is 64 (M + 4). The input data word length of the fifth level is 2 (M + 5), and the total word length is 64 (M + 5).

[0061] Compared with the FFT input data word length, the word length of each complex output data increases by 10 bits, but the truncation noise is greatly reduced. At the same time, the "principle of retaining the maximum number of effective bits of output data" fully utilizes the FPGA resources to maximize the effective word length of the calculation process and output data.

[0062] Compared with the traditional FFT algorithm, the digital noise of the present invention is greatly reduced. Figure 7 The horizontal axis number in the figure represents the number of butterfly operations, and the vertical axis represents the noise of the output signal. After five-level FFT operations, the FFT algorithm of the present invention reduces the output signal noise by more than 7dB compared with the traditional FFT algorithm.

[0063] In all digital signal analyses, fixed-point operations involve truncation processing. In addition to the above-mentioned FFT signal analysis processing, the present invention can also be used for truncation processing of other digital signal analysis fixed-point operations, if the method of the present invention is used, which also falls within the scope of the present invention, that is, the present invention is not limited to FFT signal analysis, and also includes other digital signal fixed-point operation models. In addition, the truncated word length is not limited to the output data increasing by 1 bit compared to the input data, and any truncated word length designed according to the sensitivity requirements of the signal analysis falls within the scope of the present invention.

[0064] Although the above describes an illustrative specific embodiment of the present invention to facilitate the understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiment. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

Claims

1. A fast Fourier transform digital signal noise processing method based on FPGA, characterized in that: The following steps are involved: (1) According to the analog-to-digital conversion output data word length M, set the FPGA processing effective word length to M; (2) Decompose the FFT processing flow according to the FFT butterfly algorithm, L = 2 n The FFT butterfly operation of time domain data is decomposed into n-level calculations; (3) The first level of the FFT butterfly algorithm is an addition and subtraction operation. The maximum word length is increased by one overflow bit, that is, the word length of the real and imaginary parts of the output result is increased by one bit. When the ADC output data word length is M, the word length of each output data processed in the first level is set to 2(M+1), and the total output word length is 2 n+1 (M+1); (4) The second-level processing of the FFT butterfly algorithm is also an addition and subtraction operation. The maximum word length is increased by one bit to overflow, that is, the word length of the real and imaginary parts of the output result is increased by one bit each, and the word length of each output data of the second-level processing is set to 2(M+2) bits. The total output word length is 2 n+1 (M+2); (5) The third level of FFT butterfly algorithm processing involves complex multiplication of input data and rotation factors. The rotation factors are set to have the same word length as the input data of this level, with M+2 bits for the real part and M+2 bits for the imaginary part, that is, 2(M+2) bits. The floating point numbers of the DSP core are used for calculation. The output of the DSP core calculation is truncated at the high and low bits respectively according to the principle of retaining the maximum number of significant bits of the output data. The word length of each output data changes from 4(M+2)+2 to 2(M+3), and the total output word length is 2 n+1 (M+3), the truncation flag is set at the same time, and the subsequent calculation bits are aligned according to the truncation flag; The principle of retaining the maximum number of effective bits of the output data is as follows: high-bit truncation is to truncate all high bits before the first non-zero bit of the output data to ensure that the highest bit of the output data is non-zero; low-bit truncation is to ensure that the word length of the output data is the same as the word length of the input data; the truncation flag is the number of bits of high-bit truncation, and the data is padded with zeros and aligned according to the truncation flag in subsequent calculations; (6) The 4th to nth level processing of the FFT butterfly algorithm also involves complex multiplication of the input data and the rotation factor. For the i-th level processing, i = 4, 5, ..., n, the rotation factor is set to have the same word length as the input data, with the real part and the imaginary part each having M + i-1 bits, that is, 2 (M + i-1) bits. The floating point number of the DSP core is used for calculation. The DSP core calculation output is truncated at the high and low bits respectively according to the principle of retaining the maximum number of significant bits of the output data. The word length of each output data changes from 4 (M + i-1) to 2 (M + i), and the total output word length is 2 n+1 (M+i), and set the truncation flag at the same time. The subsequent calculation bits are aligned according to the truncation flag. The word length of each output data of the FFT butterfly algorithm is 2(M+n), and the total data output word length is 2 n+1 (M+n).

2. The FPGA-based fast Fourier transform digital signal noise processing method according to claim 1, characterized in that: According to the principle of retaining the maximum number of valid digits of the output data, the high and low bits are truncated respectively: During the FFT processing, the output data of all processing nodes involved in multiplication calculations are truncated in high and low bits respectively according to the principle of retaining the maximum number of significant digits of the output data, and the truncation flag is set at the same time, and the flag is aligned in subsequent calculations.

3. The FPGA-based fast Fourier transform digital signal noise processing method according to claim 1, characterized in that: The output data word length of the processing nodes involved in addition and subtraction calculations increases by 2 bits: In order to prevent the overflow of 1 bit in the addition and subtraction calculation steps, the word length of the real and imaginary parts of the complex output data is increased by 1 bit respectively relative to the input data, and the word length of each output data is increased by 2 bits in total.

4. The FPGA-based fast Fourier transform digital signal noise processing method according to claim 1, characterized in that: Using the built-in DSP floating-point arithmetic function of FPGA to perform calculations without truncation: In the processing nodes involving multiplication calculation, the DSP floating-point operation function is used to set the word length of the rotation factor to be the same as the word length of the node input data. No truncation is performed in the multiplication, addition, and subtraction processes, and only the node output data is truncated.

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