FPGA (Field Programmable Gate Array) comprehensive tool carry chain optimization method and device oriented to continuous addition of same numbers

Abstract

The invention provides an FPGA (Field Programmable Gate Array) comprehensive tool carry chain optimization method and device oriented to continuous addition of the same number. The method comprises the following steps: acquiring the same signal and continuous addition times n in a first addition unit; acquiring a binary array b [0-log2n] of continuous addition times; if b [i] = 1, generating a left shift operation unit, mapping the left shift operation unit into a trigger unit chain table, and storing an output signal of the trigger unit chain table into an array N1; generating log2n second addition units according to the array N1, and storing output signals of the second addition units to an array C to obtain sets N2 and N3; acquiring a mapping set from the first-stage output signal which does not need to be processed to a second addition unit, and updating sets N2 and N3; and traversing each signal sig in the sets N2 and N3, and mapping a second addition unit corresponding to the signal sig into a carry chain unit chain table. The resource allocation of the carry chain can be optimized, and the number of logic resources after synthesis is reduced.

Description

Technical Field

[0001] This application belongs to the technical field of FPGA software design, and particularly relates to an optimization method and device for carry chains of an FPGA synthesis tool for consecutive addition of the same numbers. Background Art

[0002] Logic synthesis is an important step in the software design process of FPGA (Field Programmable Gate Array) EDA (Electronic Design Automation). It converts the Verilog / VHDL circuit file at the behavioral level or register-transfer level (RTL) input by the user into a netlist file composed of basic FPGA logic units such as look-up tables (Luts) and flip-flops (FFs). FPGA logic synthesis includes two stages: synthesis and mapping. Synthesis converts the circuit file at the behavioral level or RTL into a logic netlist composed of gate circuits; mapping maps the logic netlist composed of gate circuits into a netlist file composed of basic FPGA logic units.

[0003] Area, that is, the number of resources, is an important indicator of FPGA logic synthesis tools. Reducing the number of resources after FPGA logic synthesis plays a very important role in improving the routing rate and timing performance of FPGA software. The carry chain unit is the basic logic unit for the FPGA synthesis tool to implement addition and subtraction operations. The addition of multiple identical numbers is called consecutive addition of the same numbers, which is a common design in application circuits. Traditional FPGA synthesis tools still adopt the processing method of ordinary carry chains when facing consecutive addition of the same numbers, without considering the special rules during consecutive addition of the same numbers, resulting in excessive occupation of logic units.

[0004] Therefore, it is crucial to provide a solution to the problem that ordinary carry chains in FPGA synthesis do not consider the special rules during consecutive addition of the same numbers, resulting in excessive occupation of logic units. Summary of the Invention

[0005] This application discloses an optimization method and device for carry chains of an FPGA synthesis tool for consecutive addition of the same numbers, which can optimize the resource allocation of carry chains, reduce the number of logic resources after synthesis, and optimize the FPGA synthesis area.

[0006] Other objectives and advantages of this application can be further understood from the technical features disclosed in this application.

[0007] For achieving one or some or all of the above purposes or other purposes, in a first aspect, the present application provides an FPGA synthesis tool carry chain optimization method for same-number consecutive addition, and the method includes: Obtain each addition unit with same-number consecutive addition in a circuit netlist as a first addition unit, and count the same signal sig and the consecutive addition times n in the first addition unit; Obtain a binary representation array b[0 - log2n] of the consecutive addition times of each first addition unit; For each bit i in the array b[0 - log2n], if b[i] = 1, generate a left shift operation unit; Map each generated left shift operation unit into a trigger unit linked list, and store the output signal of the trigger unit linked list into a signal array N1; Generate log2n addition units according to the signal array N1 as second addition units, store the output signal of the second addition units into an array C, and use the output signal C[log2n] of the last second addition unit as the output signal of the first addition unit to obtain a set N2 and a set N3, where the set N2 and the set N3 do not intersect with each other; Obtain a mapping set of output signals that do not need to be processed at the first level to the second addition units through iterative analysis, and update the set N2 and the set N3; Traverse each signal sig in the updated set N2 and set N3, and starting from the first bit, map the second addition unit corresponding to the signal sig into a carry chain unit linked list.

[0008] In an implementation manner, the input A - end signal of the left shift operation unit is equal to the signal sig, and the input B - end signal of the left shift operation unit is equal to log2n - i + 1, indicating the number of bits that the left shift operation unit needs to shift left.

[0009] In an implementation manner, the step of mapping each generated left shift operation unit into a trigger unit linked list and storing the output signal of the trigger unit linked list into a signal array N1 includes: Obtain the input A - end signal sig_a, the input B - end signal sig_b, and the output Y - end signal sig_y of the left shift operation unit, where the bit width of the signal sig_a is w; Convert the signal sig_b into an integer variable m; Loop through the variable i from 0 to m - 1, and set the signal sig_y[i] equal to 0; Loop through the variable i from m to m + w - 1, and generate a trigger unit, where the input D - end signal of the trigger unit is equal to the signal sig_a[i - m], and the output Q - end signal is equal to the signal sig_y[i].

[0010] In one embodiment, log2n addition units are generated according to the signal array N1 as the second addition units, and the output signals of the second addition units are stored in the array C. The output signal C[log2n] of the last second addition unit is used as the output signal of the first addition unit to obtain sets N2 and N3, including: Create a new signal array C, set C[0]=N1[0], traverse each bit i in the array N1, where i ranges from 0 to log2n - 1, and map the addition operation C[i]+N1[i + 1] to a second addition unit with the output signal C[i + 1]; If log2n is greater than 2, set the 0th bit of each signal between C[1] and C[log2n - 1] to 0, and insert the mapping of each signal to its corresponding second addition unit into set N2; when b[log2n]=0, set the 0th bit of C[log2n] to 0, and insert the mapping of C[log2n] to its corresponding second addition unit into set N2; otherwise, set the 0th bit of C[log2n] equal to the 0th bit of C[log2n - 1], and insert the mapping of C[log2n] to its corresponding second addition unit into set N3.

[0011] In one embodiment, the method of obtaining the mapping set of the output signals that do not need to be processed at the first level to the second addition units through iterative analysis and updating sets N2 and N3 includes: Traverse the second addition units in the circuit netlist. If the input A - end signal and the input B - end signal of the second addition unit can both be found in set N2, then insert the mapping relationship of the output signal of the second addition unit to the second addition unit into set N2; otherwise, if the input A - end signal and the input B - end signal of the second addition unit can both be found in set N3, then insert the mapping relationship of the output signal of the second addition unit to the second addition unit into set N3; if set N2 has changed, enter the next iteration.

[0012] In one embodiment, the method of mapping the second addition unit into a carry - chain unit linked list includes: Obtain the input A - end signal sig_a, the input B - end signal sig_b, and the output Y - end signal sig_y of the second addition unit, and obtain the minimum bit - width w1 of the signal sig_a; Traverse the variable i from 0 to w1 - 1; Create a first logic unit c1 of the combinational logic type. The input - port signals of the first logic unit c1 are assigned as sig_a[i] and sig_b[i], the output - port signal of the first logic unit c1 is assigned as sig_y[i], and a carry - output signal is generated; If i = 0, set the lookup table mask equal to the first mask value; otherwise, generate a carry input signal for the first logic unit c1 and assign it to the carry output signal of the previous-level unit, and set the lookup table mask equal to the second mask value. In one implementation, the method of mapping the second adder unit into a carry chain unit linked list further includes: Obtain the maximum bit width w2 of the signal sig_b, and traverse i from w1 to w2 - 1; Create a second logic unit c2 of combinational logic type. The input signal of the second logic unit c2 is assigned to the i-th bit of the signal with the larger bit width of sig_a and sig_b, the output port signal is assigned to sig_y[i], generate a carry output signal, generate a carry input signal and assign it to the carry output signal of the previous-level unit, and set the lookup table mask equal to the third mask value; Create a third logic unit c3 of combinational logic type. The output port signal of the third logic unit c3 is assigned to sig_y[w2], generate a carry input signal and assign it to the carry output signal of the previous-level unit, and set the lookup table mask equal to the fourth mask value.

[0013] In a second aspect, the present application provides an FPGA synthesis tool carry chain optimization device for consecutive addition of the same number, and the device is used to implement the FPGA synthesis tool carry chain optimization method for consecutive addition of the same number in any item of the first aspect. The device includes: An adder unit acquisition and analysis module, configured to acquire each adder unit for consecutive addition of the same number in the circuit netlist as the first adder unit, count the same signal sig and the consecutive addition times n in the first adder unit; obtain the binary representation array b[0 - log2n] of the consecutive addition times of each first adder unit; A flip-flop unit linked list generation module, configured to, for each bit i in the array b[0 - log2n], if b[i] = 1, generate a left shift operation unit; map each generated left shift operation unit into a flip-flop unit linked list, and store the output signal of the flip-flop unit linked list into the signal array N1; A signal processing and generation module, generate log2n adder units as the second adder units according to the signal array N1, store the output signals of the second adder units into the array C, use the output signal C[log2n] of the last second adder unit as the output signal of the first adder unit to obtain the set N2 and the set N3, where the set N2 and the set N3 do not intersect; obtain the mapping set of the output signals that do not need to be processed at the first level to the second adder units through iterative analysis, and update the set N2 and the set N3; The carry chain unit linked list generation module is used to traverse each signal sig in the updated set N2 and set N3, and map the second adder unit corresponding to the signal sig into a carry chain unit linked list starting from the first bit.

[0014] In a third aspect, the present application provides a computer-readable storage medium, in which program code is stored, and the program code is called by a processor to execute the carry chain optimization method of the FPGA synthesis tool for consecutive addition of the same number according to any one of the first aspects.

[0015] In a fourth aspect, the present application provides an electronic device, including one or more processors; a memory; one or more application programs, wherein one or more application programs are stored in the memory and configured to be executed by one or more processors, and one or more application programs are configured to execute the carry chain optimization method of the FPGA synthesis tool for consecutive addition of the same number according to any one of the first aspects.

[0016] The above carry chain optimization method and device of the FPGA synthesis tool for consecutive addition of the same number generate corresponding left shift operation units and adder units through the binary representation of the consecutive addition times, making the resource allocation more accurate, avoiding the generation of unnecessary adders, reducing the occupation of adder resources in the FPGA, reducing the resource consumption, and adopting the structures of the trigger unit linked list and the carry chain unit linked list, making the signal transmission more orderly and efficient, and improving the resource utilization efficiency.

[0017] To make the above and other purposes, features and advantages of the present application more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes the following detailed description. Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a flowchart of a carry chain optimization method of an FPGA synthesis tool for consecutive addition of the same number according to the present application.

[0020] Figure 2 It is a flowchart of mapping a left shift operation unit into a trigger unit linked list according to the present application.

[0021] Figure 3 It is a flowchart of generating an adder unit from a signal array according to the present application.

[0022] Figure 4A flowchart for obtaining a set of carry chain signals at the first level that do not need to be processed in this application.

[0023] Figure 5 A flowchart for mapping an adder unit into a linked list of carry chain units in this application.

[0024] Figure 6 A block diagram of a carry chain optimization device for an FPGA synthesis tool for consecutive addition of the same number in this application. Detailed implementation

[0025] Regarding the foregoing and other technical contents, features and effects of this application, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. Terms such as "first" and "second" in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of this application.

[0026] Reference Figure 1 , the embodiments of this application provide a carry chain optimization method for an FPGA synthesis tool for consecutive addition of the same number, including the following steps: Step 1: Traverse each logic unit of the add type in the circuit netlist, analyze the first adder unit for each consecutive addition of the same number, and count the same signal sig and the consecutive addition times n in the first adder unit; execute Steps 2-5.

[0027] Step 2: For each first adder unit for consecutive addition of the same number, obtain an array b[0-log2n] of the binary representation of the consecutive addition times n of the first adder unit.

[0028] Step 3: For each bit i in the array b[0-log2n], where i ranges from 0 to log2n, if b[i]=1, generate a left shift operation (shl) unit s. The input A terminal signal of the left shift operation unit s is equal to the signal sig, and the input B terminal signal of the left shift operation unit s is equal to log2n-i+1, indicating the number of bits that the left shift operation unit s needs to shift left.

[0029] Step 4: Map each left shift operation unit s generated in Step 3 into a linked list d of several levels of flip-flop (DFF) units, and store the output signal of the linked list d of flip-flop units in the signal array N1.

[0030] Step 5: Generate log2n adder units according to the signal array N1 as the second adder unit a2. The output signals of the second adder unit a2 are stored in the array C, and the output signal C[log2n] of the last second adder unit a2 is used as the output signal of the first adder unit a1 to obtain set N2 and set N3, where set N2 and set N3 are non - overlapping.

[0031] Create a new signal array C and set C[0]=N1[0]; traverse each bit i in the signal array N1, where i ranges from 0 to log2n - 1, and map the addition operation C[i]+N1[i + 1] to an adder unit with the output signal C[i + 1]; use C[log2n] as the output signal of the first adder unit; If log2n>2, assign the 0th bit of each signal from C[1] to C[log2n - 1] to 0, and insert the mapping of each signal to its adder unit into set N2; If b[log2n]=0, assign the 0th bit of C[log2n] to 0, and insert the mapping of C[log2n] to its adder unit into set N2; Otherwise, assign the 0th bit of C[log2n] to the 0th bit of C[log2n - 1], and insert the mapping of C[log2n] to its adder unit into set N3.

[0032] Step 6: Obtain the mapping set of the output signals that do not need to be processed to the adder units at the first level through iterative analysis, and update set N2 and set N3.

[0033] Iteratively traverse each second adder unit a2 in the circuit netlist to obtain the input A - end signal sig1 and the input B - end signal sig2 of the second adder unit a2. If both sig1 and sig2 can be found in set N2, then insert the mapping relationship of the output signal of the second adder unit a2 to the second adder unit a2 into set N2; otherwise, if either sig1 or sig2 can be found in set N2, then insert the mapping relationship of the output signal of the second adder unit a2 to the second adder unit a2 into set N3; if there is a change in set N2, enter the next iteration; otherwise, exit this step.

[0034] Step 7: Traverse each signal sig in set N2 and set N3, starting from the 1st bit, and map the adder unit corresponding to the signal sig into a carry - chain unit linked list.

[0035] In this embodiment, the corresponding left shift operation unit and adder unit are generated through the binary representation of the number of consecutive addition operations, making the resource allocation more accurate, avoiding the generation of unnecessary adders, reducing the occupation of adder resources in the FPGA, and mapping the left shift operation unit into a linked list of flip-flop units, which can utilize flip-flop resources more efficiently, reduce the redundant use of flip-flops, so as to reduce the number of logic resources after FPGA synthesis and reduce the area of FPGA synthesis.

[0036] Meanwhile, adopting the structure of the linked list of flip-flop units and the linked list of carry chain units makes the signal transmission more orderly and efficient, improving the utilization efficiency of resources. Through the hierarchical construction and mapping of the carry chain, a carry management with clear structure, high resource efficiency and strong flexibility is realized, reducing the delay nodes in the carry chain, shortening the signal propagation path, enabling the carry signal to be generated and transmitted faster, and thus accelerating the execution of the consecutive addition operation of the same number.

[0037] In an optional implementation manner, in step 4, each generated left shift operation unit s is mapped into a linked list d of several levels of flip-flop units, and the output signal of the linked list d of flip-flop units is stored in the signal array N1, refer to Figure 2 , and the specific steps are as follows: Step 41: Obtain the input A-end signal sig_a, the input B-end signal sig_b of the left shift operation unit s, and the output Y-end signal is sig_y, where the bit width of the signal sig_a is w.

[0038] Step 42: Convert the signal sig_b into an integer variable m.

[0039] Step 43: Loop through the variable i = 0 to m - 1, and set the signal sig_y[i] = 0.

[0040] Step 44: Loop through the variable i = m to m + w - 1, and execute step 45.

[0041] Step 45: Generate a flip-flop unit, where the input D-end signal of the flip-flop unit is equal to the signal sig_a[i - m], and the output Q-end signal is equal to the signal sig_y[i].

[0042] In this embodiment, by obtaining the input and output signals of the left shift operation unit, then determining the left shift number through the conversion signal, and then performing the padding operation on the low bits, and further using the flip-flop unit to store and transmit the left-shifted signal, the left shift operation of the input signal is realized while keeping the signal bit width unchanged, thus mapping the left shift operation unit into a linked list of flip-flop units, which can utilize flip-flop resources more efficiently, reduce the redundant use of flip-flops, and reduce the resource consumption of the FPGA.

[0043] In an alternative embodiment, the specific method of generating log2n adder units according to the signal array N1 in step 5 as the second adder units and using the output signal of the last second adder unit a2 as the output signal of the first adder unit a1 refers to Figure 3 , and the detailed steps are as follows: Step 51: Create a new signal array C and set C[0]=N1[0].

[0044] Step 52: Traverse each bit i in the array N1, where i ranges from 0 to log2n - 1, and execute steps 53 - 54.

[0045] Step 53: Map the addition operation C[i]+N1[i + 1] to an adder unit with the output signal being C[i + 1] as the second adder unit a2.

[0046] Step 54: If i>0, set the 0th bit of C[i]=0 (i.e., if log2n>2, set the 0th bit of each signal from C[1] to C[log2n - 1]=0), and insert the mapping from C[i] to its second adder unit a2 into the set N2.

[0047] Step 55: Use C[log2n] as the output signal of the first adder unit a1.

[0048] Step 56: If b[log2n]=0, execute step 57; otherwise execute step 58.

[0049] Step 57: Set the 0th bit of C[log2n]=0, and insert the mapping from C[log2n] to its second adder unit a2 into the set N2.

[0050] Step 58: Set the 0th bit of C[log2n]=the 0th bit of C[log2n - 1], and insert the mapping from C[log2n] to its second adder unit a2 into the set N3.

[0051] In this embodiment, adder units and signal bits are dynamically generated according to the value of log2n, enabling the method to adapt to different scales of consecutive addition operations of the same number, having good scalability, and avoiding the generation of unnecessary adder units, thus saving adder resources in the FPGA.

[0052] In an alternative embodiment, referring to Figure 4 , the specific method of obtaining the sets N2 and N3 that do not need to be processed at the first level through iterative analysis in step 6 includes the following steps: Step 61: Traverse each second adder unit a2 in the circuit netlist and execute steps 62 - 64.

[0053] Step 62: Obtain the input A - end signal sig1 and the input B - end signal sig2 of the second adder unit a2.

[0054] Step 63: If both the signal sig1 and the signal sig2 can be found in the set N2, then insert the mapping relationship from the output signal of the second adder unit a2 to the second adder unit a2 into the set N2, and execute Step 65; otherwise, execute Step 64.

[0055] Step 64: If either the signal sig1 or the signal sig2 can be found in the set N2, then insert the mapping relationship from the output signal of the second adder unit a2 to the second adder unit a2 into the set N3; otherwise, exit the processing of adder a and enter the processing of the next adder unit.

[0056] Step 65: If there is a change in the carry - chain signal set N2, then transfer to Step 1 and enter the next iteration; otherwise, exit this process.

[0057] In this embodiment, by iteratively analyzing to obtain the sets N2 and N3 that do not need to be processed at the first level, the carry - chain structure can be streamlined, removing those parts that do not need to be processed. This optimization reduces the redundant nodes in the carry - chain, making the carry - chain more efficient. By checking and classifying the input signals, unnecessary adder units are avoided from being generated, and the mapping relationship between the signals and the adder units is inserted into the set N2 or N3, making the management of signals more efficient and avoiding waste of resources.

[0058] In an alternative embodiment, as Figure 5 shown, in Step 7, traverse each signal sig in the sets N2 and N3, and map the add unit corresponding to sig into a carry - chain unit linked list starting from the first bit. The method of mapping a second adder unit a2 into a carry - chain unit linked list specifically includes the following steps: Step 71: Obtain the input A - end signal sig_a, the input B - end signal sig_b, and the output Y - end signal sig_y of the second adder unit a2, and obtain the minimum bit - width w1 of the signal sig_a and the maximum bit - width w2 of the signal sig_b.

[0059] Step 72: Traverse the variable i from 0 to w1 - 1, and execute Steps 73 - 74.

[0060] Step 73: Create a first logic unit c1 of the combinational logic (LCELL_COMB) type. The input - port signals of the first logic unit c1 are assigned as sig_a[i] and sig_b[i], the output - port signal is assigned as sig_y[i], and a carry - output (COUT) signal is generated.

[0061] Step 74: If i = 0, the lookup table mask lut_mask = 6688; otherwise, generate a carry input (CIN) signal for the first logic unit c1 = the COUT signal of the previous-level unit, and set the lookup table mask lut_mask = 96E8.

[0062] Step 75: Traverse i from w1 to w2 - 1, and execute Step 76.

[0063] Step 76: Create a second logic unit c2 of type LCELL_COMB. Assign the input signal of the second logic unit c2 to the i-th bit of the signal with the larger bit width between sig_a and sig_b, assign the output port signal to sig_y[i], generate a COUT carry output signal and a CIN carry input signal = the COUT signal of the previous-level unit, and set the lookup table mask lut_mask = 5AA0.

[0064] Step 77: Create a third logic unit c3 of type LCELL_COMB. Assign the output port signal of the third logic unit c3 to sig_y[w2], generate a CIN input port signal = the COUT signal of the previous-level unit, and set the lookup table mask lut_mask = F0F0.

[0065] In this embodiment, independent combinational logic units are created for each bit according to the bit width of the input signal, and different lookup table mask values are set to distinguish different functions, which speeds up the execution speed of the addition operation, reduces unnecessary circuit parts, and improves the utilization efficiency of resources; and by generating a carry output signal for each bit, the carry signal can be quickly generated and transmitted, reducing the delay caused by carry bit by bit.

[0066] It should be understood that at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0067] Based on the same inventive concept, the embodiment of the present application also provides an FPGA synthesis tool carry chain optimization device for adding the same numbers continuously. The implementation solution for solving the problem of this device is similar to the implementation solution described in the above method. Therefore, the specific limitations can be referred to the limitations on the FPGA synthesis tool carry chain optimization method for adding the same numbers continuously in the above text, and will not be repeated here.

[0068] Reference Figure 6, a carry chain optimization device for an FPGA synthesis tool for same-number consecutive addition provided by an embodiment of the present application, the device includes: An adder unit acquisition and analysis module, configured to acquire each adder unit of same-number consecutive addition in a circuit netlist as a first adder unit, count the same signal sig and the consecutive addition times n in the first adder unit; acquire a binary representation array b[0-log2n] of the consecutive addition times of each first adder unit; A flip-flop unit linked list generation module, configured to, for each bit i in the array b[0-log2n], if b[i]=1, generate a left shift operation unit; map each generated left shift operation unit into a flip-flop unit linked list, and store the output signal of the flip-flop unit linked list into a signal array N1; A signal processing and generation module, generate log2n adder units as second adder units according to the signal array N1, store the output signals of the second adder units into an array C, use the output signal C[log2n] of the last second adder unit as the output signal of the first adder unit, to obtain a set N2 and a set N3, where the set N2 and the set N3 do not intersect; obtain a mapping set of output signals that do not need to be processed at the second level to the second adder units through iterative analysis, and update the set N2 and the set N3; A carry chain unit linked list generation module, configured to traverse each signal sig in the updated set N2 and set N3, and map the second adder unit corresponding to the signal sig into a carry chain unit linked list starting from the first bit.

[0069] In one embodiment, the present application further provides a computer-readable storage medium, in which program code is stored, and the program code is called by a processor to execute a method for optimizing a carry chain of an FPGA synthesis tool for same-number consecutive addition as described in any one of the above.

[0070] In one embodiment, the present application further provides an electronic device, the electronic device includes one or more processors; a memory; one or more application programs, where one or more application programs are stored in the memory and configured to be executed by one or more processors, and one or more application programs are configured to execute a method for optimizing a carry chain of an FPGA synthesis tool for same-number consecutive addition as described in any one of the above.

[0071] It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of separate embodiments for clarity can also be provided in a single embodiment by combination. Conversely, the various features of the present disclosure described in the context of a single embodiment for clarity can also be provided separately or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. An optimization method for the carry chain of an FPGA synthesis tool for consecutive addition of the same number, characterized in that The method includes: Obtain each adder unit with the same number of consecutive additions in the circuit netlist as the first adder unit, and count the same signal sig and the number of consecutive additions n in the first adder unit; Obtain the binary representation array b[0-log2n] of the number of consecutive additions of each first adder unit; For each bit i in the array b[0-log2n], if b[i]=1, generate a left shift operation unit; Map each generated left shift operation unit into a linked list of flip-flop units, and store the output signal of the linked list of flip-flop units into the signal array N1; Generate log2n adder units according to the signal array N1 as the second adder units, store the output signals of the second adder units into the array C, and use the output signal C[log2n] of the last second adder unit as the output signal of the first adder unit to obtain the sets N2 and N3, where the set N2 and the set N3 are non-overlapping; Obtain the mapping set of the output signals that do not need to be processed at the first level to the second adder units through iterative analysis, and update the sets N2 and N3; Traverse each signal sig in the updated sets N2 and N3, and starting from the first bit, map the second adder unit corresponding to the signal sig into a carry chain unit linked list.

2. The carry chain optimization method for an FPGA synthesis tool for consecutive addition of the same number according to claim 1, wherein The input A terminal signal of the left shift operation unit is equal to the signal sig, and the input B terminal signal of the left shift operation unit is equal to log2n-i+1, indicating the number of bits that the left shift operation unit needs to shift left.

3. A carry chain optimization method for an FPGA synthesis tool for consecutive addition of the same number according to claim 2, characterized in that, The step of mapping each generated left shift operation unit into a linked list of flip-flop units and storing the output signal of the linked list of flip-flop units into the signal array N1 includes: Obtain the input A terminal signal sig_a, the input B terminal signal sig_b, and the output Y terminal signal sig_y of the left shift operation unit, where the signal sig_a has a bit width of w; Convert the signal sig_b into an integer variable m; Loop through the variable i from 0 to m-1 and set the signal sig_y[i] equal to 0; Loop through the variable i from m to m+w-1 and generate a flip-flop unit, where the input D terminal signal of the flip-flop unit is equal to the signal sig_a[i-m], and the output Q terminal signal is equal to the signal sig_y[i].

4. A carry chain optimization method for an FPGA synthesis tool for consecutive addition of the same number according to claim 1, characterized in that The step of generating log2n adder units according to the signal array N1 as the second adder units, storing the output signals of the second adder units into the array C, and using the output signal C[log2n] of the last second adder unit as the output signal of the first adder unit to obtain the sets N2 and N3 includes: Create a new signal array C, set C[0]=N1[0], traverse each bit i in the array N1, i from 0 to log2n-1, and map the addition operation C[i]+N1[i+1] into a second adder unit with the output signal C[i+1]; If log2n is greater than 2, set the 0th bit of each signal between C[1] and C[log2n - 1] to 0, and insert the mapping of each signal to its corresponding second adder unit into set N2; when b[log2n] = 0, set the 0th bit of C[log2n] to 0, and insert the mapping of C[log2n] to its corresponding second adder unit into set N2; otherwise, set the 0th bit of C[log2n] equal to the 0th bit of C[log2n - 1], and insert the mapping of C[log2n] to its corresponding second adder unit into set N3.

5. A carry chain optimization method for an FPGA synthesis tool for consecutive addition of the same number according to claim 1, characterized in that The method of obtaining the mapping set of the output signals that do not need to be processed at the first level to the second adder unit through iterative analysis and updating set N2 and set N3 includes: Traverse the second adder units in the circuit netlist. If the input A - end signal and the input B - end signal of the second adder unit can both be found in set N2, then insert the mapping relationship between the output signal of this second adder unit and this second adder unit into set N2; otherwise, if the input A - end signal and the input B - end signal of the second adder unit can both be found in set N3, then insert the mapping relationship between the output signal of this second adder unit and this second adder unit into set N3; if set N2 has changed, enter the next iteration.

6. The carry chain optimization method for an FPGA synthesis tool for consecutive addition of the same number according to claim 1, wherein The method of mapping the second adder unit into a carry - chain unit linked list includes: Obtain the input A - end signal sig_a, the input B - end signal sig_b, and the output Y - end signal sig_y of the second adder unit, and obtain the minimum bit - width w1 of the signal sig_a. Traverse the variable i from 0 to w1 - 1. Create a first logic unit c1 of combinational logic type. Assign the input port signals of the first logic unit c1 to sig_a[i] and sig_b[i], assign the output port signal of the first logic unit c1 to sig_y[i], and generate a carry - out signal. If i = 0, set the lookup - table mask equal to the first mask value; otherwise, generate a carry - in signal for the first logic unit c1 and assign it to the carry - out signal of the previous - level unit, and set the lookup - table mask equal to the second mask value.

7. A carry chain optimization method for an FPGA synthesis tool for same-number consecutive addition according to claim 6, characterized in that The method of mapping the second adder unit into a carry - chain unit linked list further includes: Obtain the maximum bit - width w2 of the signal sig_b, and traverse i from w1 to w2 - 1. Create a second logic unit c2 of combinational logic type. Assign the input signal of the second logic unit c2 to the i - th bit of the signal with the larger bit - width between sig_a and sig_b, assign the output port signal to sig_y[i], generate a carry - out signal, generate a carry - in signal and assign it to the carry - out signal of the previous - level unit, and set the lookup - table mask equal to the third mask value. Create a third logic unit c3 of combinational logic type. Assign the output port signal of the third logic unit c3 to sig_y[w2], generate a carry - in signal and assign it to the carry - out signal of the previous - level unit, and set the lookup - table mask equal to the fourth mask value.

8. An FPGA synthesis tool carry chain optimization device for consecutive addition of the same number, characterized in that The device is used to implement an optimization method for carry chains of an FPGA synthesis tool for consecutive addition of the same number as described in any one of claims 1-7. The device includes: An addition unit acquisition and analysis module, configured to acquire each addition unit for consecutive addition of the same number in the circuit netlist as the first addition unit, count the same signal sig and the number of consecutive additions n in the first addition unit; acquire the binary representation array b[0-log2n] of the number of consecutive additions of each first addition unit; A flip-flop unit linked list generation module, configured to, for each bit i in the array b[0-log2n], if b[i]=1, generate a left shift operation unit; map each generated left shift operation unit into a flip-flop unit linked list, and store the output signal of the flip-flop unit linked list into the signal array N1; A signal processing and generation module, generates log2n addition units as the second addition units according to the signal array N1, stores the output signals of the second addition units into the array C, and uses the output signal C[log2n] of the last second addition unit as the output signal of the first addition unit to obtain sets N2 and N3, where the set N2 and the set N3 do not intersect; obtain the mapping set of the output signals that do not need to be processed at the first level to the second addition units through iterative analysis, and update the sets N2 and N3; A carry chain unit linked list generation module, configured to traverse each signal sig in the updated sets N2 and N3, and map the second addition unit corresponding to the signal sig into a carry chain unit linked list starting from the first bit.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores program codes, and the program codes are called by a processor to execute an optimization method for carry chains of an FPGA synthesis tool for consecutive addition of the same number as described in any one of claims 1-7.

10. An electronic device, characterized in that, Comprising one or more processors; A memory; One or more application programs, wherein the one or more application programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more application programs are configured to execute an optimization method for carry chains of an FPGA synthesis tool for consecutive addition of the same number as described in any one of claims 1-7.

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