A content-related and address-related compatible memory and working method

Abstract

The present invention discloses a content-dependent and address-dependent compatible memory and operating method, which saves storage resources, improves data storage and recognition efficiency, and is highly efficient and practical. The memory comprises an address decoder, a write trigger, a match trigger, a comparison circuit, an address-dependent output data selector, and a content-dependent output address recognition encoder. The output of the address decoder is connected to the input of the write trigger and the input of the match trigger, respectively. The outputs of the write trigger and the match trigger are both connected to the comparison circuit for comparing the output results of the write trigger and the match trigger. The output of the comparison circuit is connected to the output data selector and the output address recognizer, respectively.

Description

Technical Field

[0001] The present invention relates to the technical field of memory circuits, and in particular to a content-related and address-related compatible memory and a working method. Background Art

[0002] A content-addressable memory (CAM) device is a memory device designed to accelerate any application that requires fast database searches. CAM devices compare input search data with a table of stored data and report the addresses where the data matches. In other words, in a CAM device, access to stored data in a CAM array does not begin with an address. Instead, the input search data (e.g., a search keyword) is first provided to the CAM array. A comparison operation is then performed to identify one or more row locations (i.e., entry addresses) in the CAM array that contain data that "matches" the input search data. In this manner, stored data is accessed based on its content rather than its address. Therefore, CAM devices, due to their fast search capabilities, are widely used in devices requiring fast content searches.

[0003] However, in certain situations, some storage devices require both content-related access and address-related access for specific data. Therefore, it is necessary to design content-related memory and address-related memory separately. The existing memory cannot meet the access search requirements of both requirements at the same time. However, setting up two memories wastes storage resources. At the same time, transmitting data between the two memories will cause transmission delays, resulting in problems such as untimely data feedback and inefficient data recognition. Summary of the Invention

[0004] In order to solve the problems existing in the prior art, the present invention provides a content-related and address-related compatible memory and working method, which saves storage resources, improves data storage and recognition efficiency, and is highly efficient and practical.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A content-dependent and address-dependent compatible memory includes an address decoder, a write trigger, a match trigger, a comparison circuit, an address-dependent output data selector, and a content-dependent output address recognition encoder;

[0007] Among them, the output end of the address decoder is respectively connected to the input end of the write trigger and the input end of the match trigger, the output ends of the write trigger and the match trigger are both connected to the comparison circuit for comparing the output results of the write trigger and the match trigger, and the output end of the comparison circuit is respectively connected to the output data selector and the output address identifier.

[0008] The address decoder includes a page decoder and a body decoder.

[0009] Furthermore, a write storage body is provided at the output end of the write trigger, and the write storage body is used to store data written according to the address.

[0010] Preferably, the write memory bank is an 18-bit address-related write memory bank.

[0011] Furthermore, an address-related read / write logic module is provided at the input end of the write trigger.

[0012] Furthermore, a matching storage body is provided at the output end of the matching trigger, and the matching storage body is used to store content-based query data.

[0013] Preferably, the matching memory bank is an 18-bit content-dependent matching memory bank.

[0014] Furthermore, a content-dependent read enable module is provided at the input end of the matching trigger.

[0015] A method for operating a memory compatible with content-related and address-related memory, based on the memory of the present invention, includes the steps of querying a memory address based on content-related information, specifically as follows:

[0016] Input data passes through the address decoder to select the number of pages in the memory and the individual selection of the memory bank;

[0017] According to the read / write command, based on the processing result of the address decoder and the input signal, the write trigger of 18 bits of write data in a certain bank is enabled, and at the rising edge of the clk clock, the write data is stored to the output end of the write trigger according to the address correlation;

[0018] According to the processing result of the address decoder and the content-related read signal, the match trigger of the 18-bit content-related query input data in a certain bank is enabled, and the content-related query data is stored at the output end of the match trigger at the rising edge of the clk clock;

[0019] Compare the corresponding data bits of the output results of the write trigger and the match trigger. When the output results are equal, the data match is successful.

[0020] The comparison result is input into the output address identifier to realize the address output according to the content-related query.

[0021] Furthermore, the method further includes the step of reading the storage content according to the address, which is specifically as follows:

[0022] According to the processing result of the address decoder and the read signal related to the address, the output signal of the write trigger and the match trigger is output to the output end of the output data selector to complete the output of the content of a certain unit of the memory;

[0023] The output signal of one of the above individuals is read and output as a selection signal of a page of the output data selector, thereby realizing output of content related to address query.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] This invention, targeting content-dependent memory circuits, designs a high-efficiency memory circuit capable of both content-dependency and address-dependency. By deeply understanding the inherent connection and integrated design of content-dependent and address-dependent memories, two characteristic evaluation metrics are proposed: resource utilization and read access time. By using triggers and comparison circuits to construct an evaluation model for a high-efficiency memory that combines both content-dependency and address-dependency, the circuit can simultaneously implement both content-dependent and address-dependent access to specific data in specific situations using the same memory. This eliminates the need for separate design of content-dependent and address-dependent memories, avoiding the exponential increase in resource utilization associated with using separate content-dependent and address-dependent memories, as well as the transmission delays associated with transferring data between the two memories, thereby improving data storage and recognition efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a block diagram of the composition of the content-related and address-related compatible memory of the present invention;

[0027] Figure 2 The present invention provides a circuit diagram of a content-related and address-related compatible memory. DETAILED DESCRIPTION

[0028] The principles and features of the present invention are further described in detail below with reference to the accompanying drawings. The examples provided are intended only to illustrate the present invention and are not intended to limit the scope of the present invention. It should be noted that the drawings are all simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0029] It should be noted that when a component is referred to as being "fixed to" another component, it may be directly on the other component or there may be a central component. When a component is referred to as being "connected to" another component, it may be directly connected to the other component or there may be a central component. When a component is referred to as being "disposed on" another component, it may be directly disposed on the other component or there may be a central component.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0031] The present invention provides a content-related and address-related compatible memory, such as Figure 1 As shown, it includes an address decoder, a write trigger, a match trigger, a comparison circuit, an address-related output data selector, and a content-related output address recognition encoder;

[0032] Among them, the output end of the address decoder is respectively connected to the input end of the write trigger and the input end of the match trigger, the output ends of the write trigger and the match trigger are both connected to the comparison circuit for comparing the output results of the write trigger and the match trigger, and the output end of the comparison circuit is respectively connected to the output data selector and the output address identifier.

[0033] The present invention designs a high-efficiency memory circuit that is both content-related and address-related, focusing on content-related memory circuits. The invention further explores the inherent connection and integrated design of content-related memory and address-related memory, and proposes two characteristic evaluation indicators: resource occupancy and read access time. By using triggers and comparison circuits to construct a high-efficiency memory that is both content-related and address-related as an evaluation model, the same memory can be used to access specific data in specific situations both according to content-related access and address-related access. There is no need to design content-related memory and address-related memory separately, thus avoiding the exponential increase in resource occupancy caused by using independent content-related memory and independent address-related memory, and also avoiding the transmission delay caused by transmitting data between the two memories, thereby improving the efficiency of data storage and recognition. The memory described in the present invention verifies the feasibility and effectiveness of the evaluation model through examples.

[0034] The address decoder can be divided into a page decoder and a body decoder. The page decoder is used to select a certain page in the memory pages, and the body decoder is used to select a certain unit in the units in a certain page of the memory.

[0035] Furthermore, a write storage body is provided at the output end of the write trigger, and the write storage body is used to store data written according to the address.

[0036] In this embodiment, the write memory bank is an 18-bit address-related write memory bank.

[0037] Furthermore, an address-related read / write logic module is provided at the input end of the write trigger, for performing a logic "AND" or "OR" operation on the address decoder result and the read / write signal.

[0038] Furthermore, a matching storage body is provided at the output end of the matching trigger, and the matching storage body is used to store content-based query data.

[0039] In this embodiment, the matching memory bank is an 18-bit content-related matching memory bank.

[0040] Furthermore, a content-dependent read enable module is provided at the input end of the matching trigger.

[0041] The present invention also provides a method for operating a memory compatible with content correlation and address correlation, including the steps of querying a memory address according to content correlation, specifically as follows:

[0042] Input data passes through the address decoder to select the number of pages in the memory and the individual selection of the memory bank;

[0043] According to the read / write command, based on the processing result of the address decoder and the input signal, the write trigger of 18 bits of write data in a certain bank is enabled, and at the rising edge of the clk clock, the write data is stored to the output end of the write trigger according to the address correlation;

[0044] According to the processing result of the address decoder and the content-related read signal, the match trigger of the 18-bit content-related query input data in a certain bank is enabled, and the content-related query data is stored at the output end of the match trigger at the rising edge of the clk clock;

[0045] Compare the corresponding data bits of the output results of the write trigger and the match trigger. When the output results are equal, the data match is successful.

[0046] The comparison result is input into the output address identifier to realize the address output according to the content-related query.

[0047] The present invention also provides a method for operating a memory compatible with content-related and address-related memory, including the steps of reading the memory content according to address-related memory, specifically as follows:

[0048] According to the processing result of the address decoder and the read signal related to the address, the output signal of the write trigger and the match trigger is output to the output end of the output data selector to complete the output of the content of a certain unit of the memory;

[0049] The output signal of one of the above individuals is read and output as a selection signal of a page of the output data selector, thereby realizing output of content related to address query.

[0050] Example

[0051] This embodiment provides a high-efficiency memory that is both content-related and address-related, such as Figure 1 The following figure shows a block diagram of the memory structure, including an input address decoder, a read enable for content-dependent operations, 32 memory pages, a matching memory bank for 18-bit content-dependent read operations, an address-dependent output multiplexer, content-dependent output address recognition logic, and an encoder. Each memory page contains 32 memory banks, each of which contains an 18-bit address-dependent write memory bank, read / write control logic, and output result comparison circuitry.

[0052] The input and output signals of the memory in this embodiment are as follows Figure 2 As shown in , the details are as follows:

[0053] (1) Input signal

[0054] clk: memory working clock;

[0055] addr[9:0]: The address input when the memory reads / writes data according to address-related operations;

[0056] data[17:0]: data input when the memory is written according to the address;

[0057] wr: The write signal input when the memory is written according to the address;

[0058] datatag[17:0]: data content entered when the memory queries the address based on content;

[0059] match: The query (read) signal input when the memory queries the address based on content correlation;

[0060] rd: The read signal input when the memory reads data according to address-related operations.

[0061] (2) Output signal:

[0062] addro[9:0]: The output address when performing content-related read address operation;

[0063] datao[17:0]: data output when performing address-related read data operations.

[0064] The circuit diagram of the memory in this embodiment is as follows Figure 2 As shown, its working principle is as follows:

[0065] First, this embodiment has two address decoders: bank decoder Y1 and page decoder Y2. Data passes through the address decoders, with the upper five bits of the address passing through page decoder Y2 to select one of the 32 pages; the lower five bits of the address passing through bank decoder Y1 to select one of the 32 banks within a page.

[0066] Then, different processing is performed according to different read / write commands, including the following processing procedures:

[0067] (1) The process of writing input data into memory according to address.

[0068] Perform a logical AND operation on the address decoder result and the write signal to enable the trigger of the 18-bit write data in a bank, and implement the function of writing data according to the address on the rising edge of the clk clock.

[0069] like Figure 2 As shown, the output terminal Q of the write trigger such as trigger D1 and D3 in the figure always latches the written data for subsequent address-related read operations and content-related write operations until the next write operation on this individual.

[0070] (2) The process of querying (reading) the memory address based on content relevance.

[0071] 2.1 The address decoder result and the content-dependent query (read) signal are logically ANDed. This enables the match triggers for the 18-bit content-dependent query input data tag within a bank. On the rising edge of the clk clock, the content-dependent query input data tag is latched. The Q outputs of the match triggers, such as flip-flops D2 and D4, latch the data tag until the next match operation.

[0072] 2.2 Trigger result comparison

[0073] The output results of write triggers D1, D3, etc. are compared with the output results of match triggers D2, D4, etc. The comparison circuit is composed of Figure 2This is achieved by G3-G9 in the example. When both the write trigger and the match trigger for a particular bit output "1," G3 or G6 outputs a high level. When both the write trigger and the match trigger for a particular bit output "0," G4 or G7 outputs a high level. Therefore, when the outputs of the write trigger and the match trigger for a particular bit are equal (both "1" or "0"), G5 or G8 outputs a high level, indicating that the data bit has successfully matched.

[0074] When the outputs of the 18-bit data write trigger and the match trigger in a body are equal, that is, when all the inputs of G9 are "1", G9 outputs a high level, indicating that a data match is successful.

[0075] 2.3 Query address identification

[0076] Using the comparison results of each individual in the previous step, identification is performed as follows:

[0077] The results of each individual in the same page are "ORed" together as the corresponding page input of the page encoder B2;

[0078] The results of the banks with the same serial number in each page are ORed together and input as the corresponding bank to bank encoder B1.

[0079] The output of the body encoder B1 is used as the output low address addro[4:0]; the output of the page encoder B2 is used as the output high address addro[9:5].

[0080] addro[9:0] is the address output for content-dependent query memory.

[0081] (3) The process of reading the memory contents (data) according to the address

[0082] 3.1 Output data from a page

[0083] The address decoder result and the read signal (rd) are logically ANDed together. The output is used as the selection signal for a certain path (bank) of the 32-way selector M1, and the data of this memory bank (the output Q signal of flip-flops D1, D3, etc.) is output to the output of M1.

[0084] 3.2 Final output of data

[0085] In the previous step, the 32 selection signals in the same page are logically "ORed" (through G10, etc.) to serve as the selection signal of a certain channel (page) of the 32-channel selector M33. The input data of this selector is the output signal of M1, etc. in the previous step.

[0086] The output of M33 is the final data of the address-related readout.

[0087] As can be seen from the above embodiments, the content-dependent and address-dependent compatible memory of the present invention can search for addresses based on content, as well as content based on addresses. This combines the characteristics of both CAM (content-dependent memory) and RAM, and is widely applicable to tasks requiring both content-dependent and address-dependent memory, such as hardware implementation of the LZW compression algorithm. The combined design of the two memories enables resource sharing and savings, while also eliminating data transmission delays between the two memories.

[0088] Therefore, the present invention provides a highly efficient memory circuit that combines both content-related and address-related functions. This circuit addresses the drawbacks of existing content-related and address-related memories, which require separate designs and occupy two resources. By integrating the content-related and address-related memories and adopting efficient memory design measures, the memory can be accessed both by content and by address, thus meeting practical applications requiring both content-related and address-related access to specific data in specific situations. A single circuit achieves the functions of both memories while eliminating the time overhead of data transmission.

[0089] The content-dependent and address-dependent compatible memory described in this invention has been successfully applied to a certain telemetry system. The memory circuit described in this invention enables both reading memory data by address and querying the memory address of the data based on the data. This achieves a memory circuit with both address-dependent and data-dependent functions, saving resources and reducing the time required for data transfer.

[0090] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any ordinary technician in this industry can smoothly implement the present invention as shown in the drawings and described above. However, any equivalent changes, modifications and evolutions made by technicians familiar with this profession without departing from the scope of the technical solution of the present invention using the technical content disclosed above are all equivalent embodiments of the present invention. At the same time, any equivalent changes, modifications and evolutions made to the above embodiments based on the essential technology of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. A method for operating a content-dependent and address-dependent compatible memory, characterized in that: The steps of querying the storage address according to content are as follows: The input data passes through the address decoder to select the page number of the memory page and the individual memory bank; According to the read / write command, based on the processing result of the address decoder and the input signal, the write trigger of 18 bits of write data in a certain bank is enabled, and at the rising edge of the clk clock, the write data is stored to the output end of the write trigger according to the address correlation; According to the processing result of the address decoder and the content-related read signal, the match trigger of the 18-bit content-related query input data in a certain bank is enabled, and the content-related query data is stored at the output end of the match trigger at the rising edge of the clk clock; Compare the corresponding data bits of the output results of the write trigger and the match trigger. When the output results are equal, the data match is successful. The comparison result is input into the output address identifier to realize the address output according to the content-related query; The step of reading the memory content according to the address is also included, as follows: According to the processing result of the address decoder and the read signal related to the address, the output signal of the write trigger and the match trigger is output to the output end of the output data selector to complete the output of the content of a certain unit of the memory; The output signal of one of the above individuals is read and output as a selection signal of a page of the output data selector, thereby realizing the output of the content queried according to the address.

2. A content-related and address-related compatible memory, characterized in that: The operating method of the content-dependent and address-dependent compatible memory according to claim 1 comprises an address decoder, a write trigger, a match trigger, a comparison circuit, an address-dependent output data selector, and a content-dependent output address identification encoder; Among them, the output end of the address decoder is respectively connected to the input end of the write trigger and the input end of the match trigger, the output ends of the write trigger and the match trigger are both connected to the comparison circuit for comparing the output results of the write trigger and the match trigger, and the output end of the comparison circuit is respectively connected to the output data selector and the output address identifier.

3. The content-related and address-related compatible memory according to claim 2, characterized in that: The address decoder includes a page decoder and a bank decoder.

4. The content-dependent and address-dependent compatible memory according to claim 2, characterized in that: The output end of the write trigger is provided with a write storage body, and the write storage body is used to store data written according to the address.

5. The content-dependent and address-dependent compatible memory according to claim 4, characterized in that: The write memory bank is an 18-bit address-related write memory bank.

6. The content-dependent and address-dependent compatible memory according to claim 2, characterized in that: The input end of the write trigger is provided with an address-related read-write logic module.

7. The content-dependent and address-dependent compatible memory according to claim 2, characterized in that: The output end of the matching trigger is provided with a matching storage body, and the matching storage body is used to store content-based query data.

8. The content-dependent and address-dependent compatible memory according to claim 7, characterized in that: The matching memory bank is an 18-bit content-related matching memory bank.

9. The content-dependent and address-dependent compatible memory according to claim 2, characterized in that: The input end of the matching trigger is provided with a content-dependent read enable module.

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