Apparatus, method, and electronic device for analyzing in-chip flash signals

Abstract

The embodiment of the present disclosure discloses a device, method and electronic equipment for analyzing chip-in flash memory signals, wherein the device comprises: a signal acquisition module, configured to acquire flash memory signals of a flash memory medium port in a chip; and a signal analysis module, configured to perform protocol analysis on the flash memory signals to obtain corresponding analysis results. Through the signal acquisition module and the signal analysis module in the chip, the embodiment of the present disclosure realizes real-time protocol analysis of the flash memory signals in the chip, avoids frequent output of the flash memory signals by the chip to external devices, thus greatly reduces the transmission time, effectively improves the flash memory signal analysis efficiency and real-time performance, and effectively reduces the flash memory medium debugging cost.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a flash memory signal analysis technology, in particular to an apparatus, a method and an electronic device for analyzing a chip-in flash memory signal. BACKGROUND

[0002] As a kind of non-volatile memory, flash memory medium is widely used in various data storage scenarios, but due to the problems of board-level signal integrity, internal protocol program processing error, flash memory particle compatibility, etc., it is easy to cause the abnormal work of flash memory medium, therefore, it is necessary to debug and probe the working state of flash memory particle. In the related art, a special flash memory medium signal protocol analyzer is usually purchased, and the analyzer is used to debug and probe the working state of the flash memory particle by capturing the real-time signal of the input / output (IO) port of the flash memory medium. However, the existing method has poor real-time performance. SUMMARY

[0003] In order to solve the above technical problems of high cost of flash memory medium debugging, the present disclosure is proposed. Embodiments of the present disclosure provide an apparatus, a method and an electronic device for analyzing a chip-in flash memory signal.

[0004] According to one aspect of an embodiment of the present disclosure, an apparatus for analyzing a chip-in flash memory signal is provided, comprising: a signal acquisition module, configured to acquire a flash memory signal of a flash memory medium port in the chip; and a signal analysis module, configured to perform protocol analysis on the flash memory signal to obtain a corresponding analysis result.

[0005] According to another aspect of an embodiment of the present disclosure, a method for analyzing a chip-in flash memory signal is provided, comprising: acquiring a flash memory signal of a flash memory medium port in the chip; and performing protocol analysis on the flash memory signal to obtain a corresponding analysis result.

[0006] According to still another aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, which stores a computer program for executing the method for analyzing a chip-in flash memory signal according to any one of the above embodiments of the present disclosure; or the storage medium is used to store the data required to be stored by the apparatus for analyzing a chip-in flash memory signal according to any one of the above embodiments, so that the apparatus can realize the corresponding functions when working.

[0007] According to a further aspect of the embodiments of the present disclosure, an electronic device is provided, which comprises: a processor; a memory for storing executable instructions of the processor; the processor is configured to read the executable instructions from the memory and execute the instructions to implement the method for analyzing the in-chip flash memory signal according to any of the above embodiments of the present disclosure; or the electronic device comprises the device for analyzing the in-chip flash memory signal according to any of the above embodiments.

[0008] Based on the device, method, electronic device and storage medium for analyzing the in-chip flash memory signal provided by the above embodiments of the present disclosure, the signal acquisition module and the signal analysis module are arranged in the chip, the in-chip protocol analysis of the flash memory signal is realized, and thus the protocol analysis of the flash memory signal can be realized in a low-cost manner, which can avoid using an expensive external flash medium signal protocol analyzer and effectively reduce the debugging cost of the flash medium.

[0009] The technical solutions of the present disclosure will be described in further detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. The drawings provided in the present disclosure serve to provide a further understanding that assists in elucidating the present disclosure, and form a part of the specification. The drawings provided in the present disclosure together with the present disclosure serve to explain the present disclosure, and do not constitute a limitation of the present disclosure. In the drawings, the same reference numerals generally indicate the same components or steps.

[0011] Figure 1 is an exemplary application scenario of the device for analyzing the in-chip flash memory signal provided by the present disclosure;

[0012] Figure 2 is a structural schematic diagram of the device for analyzing the in-chip flash memory signal provided by an exemplary embodiment of the present disclosure;

[0013] Figure 3 is a structural schematic diagram of the device for analyzing the in-chip flash memory signal provided by another exemplary embodiment of the present disclosure;

[0014] Figure 4 is a structural schematic diagram of the device for analyzing the in-chip flash memory signal provided by another exemplary embodiment of the present disclosure;

[0015] Figure 5 is an exemplary schematic diagram of the first preset data structure provided by an exemplary embodiment of the present disclosure;

[0016] Figure 6 is a structural schematic diagram of the device for analyzing the in-chip flash memory signal provided by another exemplary embodiment of the present disclosure;

[0017] Figure 7 is a structural schematic diagram of the signal acquisition module 21 provided by another example embodiment of the present disclosure;

[0018] Figure 8 is an example schematic diagram of the second preset data structure provided by an example embodiment of the present disclosure;

[0019] Figure 9 is a structural schematic diagram of the device for analyzing the in-chip flash memory signal provided by yet another example embodiment of the present disclosure;

[0020] Figure 10 is a data structure arrangement schematic diagram of the first cache module 23 provided by an example embodiment of the present disclosure;

[0021] Figure 11 is a structural schematic diagram of the device for analyzing the in-chip flash memory signal provided by yet another example embodiment of the present disclosure;

[0022] Figure 12 is a structural schematic diagram of the signal analysis module 22 provided by another example embodiment of the present disclosure;

[0023] Figure 13 is a readout process schematic diagram of the analysis result provided by an example embodiment of the present disclosure;

[0024] Figure 14 is a structural schematic diagram of the device for analyzing the in-chip flash memory signal provided by yet another example embodiment of the present disclosure;

[0025] Figure 15 is a flowchart of the method for analyzing the in-chip flash memory signal provided by an example embodiment of the present disclosure;

[0026] Figure 16 is a flowchart of the method for analyzing the in-chip flash memory signal provided by another example embodiment of the present disclosure;

[0027] Figure 17 is a flowchart of the method for analyzing the in-chip flash memory signal provided by yet another example embodiment of the present disclosure;

[0028] Figure 18 is a flowchart of the method for analyzing the in-chip flash memory signal provided by yet another example embodiment of the present disclosure;

[0029] Figure 19 is a structural schematic diagram of an application embodiment of the electronic device of the present disclosure. DETAILED DESCRIPTION

[0030] Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of embodiments of the present disclosure, and the present disclosure should not be limited to the described embodiments.

[0031] It should be noted that the relative arrangement, numerical expressions, and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0032] Those skilled in the art can understand that the terms "first", "second", and the like in the embodiments of the present disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they represent a logical order between them.

[0033] It should also be understood that in the embodiments of the present disclosure, "multiple" can mean two or more, and "at least one" can mean one, two, or more.

[0034] It should also be understood that for any component, data, or structure mentioned in the embodiments of the present disclosure, it can be understood as one or more in general, without explicit limitation or in the context of the preceding and following text giving the opposite indication.

[0035] In addition, the term "and / or" in the present disclosure is only a description of the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in the present disclosure generally represents an "or" relationship between the front and rear associated objects.

[0036] It should also be understood that the description of various embodiments of the present disclosure emphasizes the differences between various embodiments, and the same or similar parts can be referred to each other, and for the sake of brevity, will not be repeated.

[0037] At the same time, it should be understood that, for the convenience of description, the size of each part shown in the drawings is not drawn in accordance with the actual proportional relationship.

[0038] The following description of at least one example embodiment is merely illustrative in nature and is in no way limiting to the disclosure and its application or uses.

[0039] Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail, but should be considered part of the specification where appropriate.

[0040] It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0041] Embodiments of the present disclosure can be applied to terminal devices, computer systems, servers, and the like electronic devices, which can operate with many other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with terminal devices, computer systems, servers, and the like electronic devices include, but are not limited to, personal computers, server computers, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, minicomputers, mainframe computers, and distributed cloud computing technology environments including any of the above systems, and the like.

[0042] Terminal devices, computer systems, servers, and the like electronic devices can be described in the general context of computer system-executable instructions, such as program modules, being executed by the computer system. Generally, program modules can include routines, programs, objects, components, logic, data structures, and the like, which perform particular tasks or implement particular abstract data types. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules can be located in local or remote computer system storage media including storage devices.

[0043] Summary of the Disclosure

[0044] In the process of implementing the present disclosure, the inventors found that when flash media is applied to various data storage scenarios, due to problems such as board-level signal integrity, internal protocol program processing errors, flash grain compatibility, and the like, the flash media is prone to work abnormally, and therefore, the working state of the flash grain needs to be debugged and probed. In the related art, a special flash media signal protocol analyzer is usually purchased, and the analyzer is used to debug and probe the working state of the flash grain by capturing the real-time signals of the IO (input / output) port of the flash media. However, the existing method has poor real-time performance.

[0045] Example Overview

[0046] Figure 1is an exemplary application scenario of the device for analyzing in-chip flash memory signals provided by the present disclosure. The flash memory controller is a controller for receiving flash memory read-write commands from an upstream (such as a processor) and converting them into flash memory particle control signals that meet preset protocol standards to control flash memory particles of a flash memory medium to complete desired read-write behaviors. The device for analyzing in-chip flash memory signals (referred to as the device) of the present disclosure is arranged in a chip to collect flash memory signals of a flash memory medium port in the chip, perform protocol analysis on the flash memory signals, obtain analysis results, and can transmit the analysis results to an external terminal for user viewing. Since the protocol analysis is performed in real time in the chip, the chip avoids frequently outputting flash memory signals to external devices, thereby greatly reducing transmission time, effectively improving flash memory signal analysis efficiency and real-time performance, and effectively reducing flash memory medium debugging costs, solving the problem of high flash memory medium debugging costs in the prior art.

[0047] Example Device

[0048] Figure 2 is a structural schematic diagram of the device for analyzing in-chip flash memory signals provided by an exemplary embodiment of the present disclosure. The present embodiment can be applied on a chip. As shown in Figure 2 , the device comprises a signal collection module 21 and a signal analysis module 22.

[0049] The signal collection module 21 is configured to collect flash memory signals of a flash memory medium port in the chip. The signal analysis module 22 is configured to perform protocol analysis on the flash memory signals collected by the signal collection module 21 to obtain corresponding analysis results.

[0050] The flash media port refers to an IO port for accessing the flash media for reading and writing, and the flash signal refers to a signal obtained by sampling an IO communication signal for communication with the flash media, such as sampling an IO communication signal between the flash controller and the flash media to obtain a flash signal. For example, the IO communication signal between the flash controller and the flash media includes flash control signals and data signals corresponding to signal line pairs defined by the flash protocol, such as ALE (address latch enable), CLE (command latch enable), WE (write enable), CE (chip select enable), DQ (data), and DQS (data strobe). The effective physical signal behavior on these signal lines is sampled to obtain the flash signal. The specific content of the IO communication signal of the flash media is not described here. The signal collection can set a sampling rule, such as signal bit width, duty cycle, sampling delay, sampling record trigger condition, etc., which can be set according to actual needs. The sampling rule can be set through the configuration register of the signal collection module, and the user can set the timing combination condition of the trigger signal sampling when the flash communication is in synchronous or asynchronous timing mode through the configuration register. The timing combination condition of the trigger signal sampling refers to the condition that the timing of the signals on the above-mentioned signal lines meets, and the signal sampling is triggered when the timing combination meets the timing combination condition. The signal obtained by sampling is the effective physical signal. For example, when the control of the flash needs to be analyzed, only the control signal can be sampled during sampling. The control signal can include the command signal and the address signal. The effective physical signal of the command signal can be determined by the CLE high level, WE pulse, and DQ (data). The effective physical signal of the address signal can be determined by the ALE high level, WE pulse, and DQ. In addition, the communication between the flash controller and the flash media also includes data signals, which can be realized by CLE and ALE low level, DQ, and WE pulse. For example, when the ALE signal or the CLE signal is high, it indicates that the flash media is controlled, and the control signal can be collected. The effective physical signal behavior can include the read control behavior and the write control behavior of the flash controller to the flash media. The detection rule of different timing signals from flash particles produced by different manufacturers can also be set by configuring the sampling trigger condition register. The timing of the IO communication signal of the flash media IO interface is not described here. The signal collection module of the present disclosure can record the signal timing phase relationship and effective time period between each signal line according to the detection rule. The specific content of the flash signal can be set according to actual needs, such as the flash signal, which can include synchronous / asynchronous identification, channel index, event type (address, command), event sampling value, data length, etc., without limitation. Protocol analysis refers to converting the flash signal into a flash protocol operation event according to a preset protocol conversion rule, and then determining an analysis result based on the flash protocol operation event.The flash protocol operation event refers to a protocol-level flash operation event, and is information of a flash protocol operation behavior that can be implemented by a flash signal. For example, it is determined through analysis of a certain group of flash signals that a write operation is performed on a flash medium, and complete operation information of the write operation (such as a flash grain channel identifier of the write operation, an operation type (write operation), an operation address (address for writing), operation content (content for writing), a relationship with other events, and the like) is recorded as a complete operation event at the protocol level of the flash, that is, a flash protocol operation event. The analysis result can include an index number, a predecessor pointer of an event, a synchronous / asynchronous identifier, a channel index, an operation type, an operation address, operation content (value), a data address pointer, a data length, a time marker, a successor pointer of an event, and the like, without limitation.

[0051] Optionally, the flash signals collected and the analysis result obtained can be stored in the chip. When needed by a user, the flash signals and / or the analysis result can be obtained from the chip for viewing. The collected flash signals and / or the analysis result can also be output to an external terminal in real time or at a fixed time for viewing by a user. The actual demand can be set.

[0052] The device for analyzing flash signals in a chip provided in the embodiment can realize real-time protocol analysis of the flash signals in the chip through the signal collection module and the signal analysis module in the chip, avoid frequent output of the flash signals from the chip to an external device, greatly reduce transmission time, effectively improve flash signal analysis efficiency and real-time performance, and effectively reduce the cost of flash medium debugging, thereby solving the problem of high cost of flash medium debugging in the prior art.

[0053] Figure 3 FIG. 6 is a structural schematic diagram of the device for analyzing flash signals in a chip provided in another example embodiment of the disclosure.

[0054] In an optional example, the device of the disclosure can further include a first cache module 23 for storing the flash signals and the analysis result. The first cache module 23 can be any memory or a preset area in the memory on the chip. For example, the first cache module is a cache area in DDR (double data rate synchronous dynamic random access memory) memory, which can be set according to actual demand.

[0055] In actual application, different cache areas can be divided for the flash signals and the analysis result, which can be set according to actual demand.

[0056] Figure 4 FIG. 7 is a structural schematic diagram of the device for analyzing flash signals in a chip provided in another example embodiment of the disclosure.

[0057] In an optional example, the signal analysis module 22 comprises:

[0058] The protocol analysis unit 221 is configured to convert the flash signal into a flash protocol operation event according to a protocol conversion rule corresponding to the flash signal, and determine an analysis result based on the flash protocol operation event.

[0059] The protocol conversion rule can be set according to actual needs. The user can set a corresponding protocol conversion rule for different flash signals according to actual needs to adapt to the analysis of various types of flash signals. Specifically, the analysis module of the present disclosure can be implemented by a certain processor, such as a RISC-V processor. The processor executes a protocol analysis program to convert the flash signal into a flash protocol operation event according to the corresponding protocol conversion rule. The protocol analysis program can be configured by the user through the main processor of the chip to the protocol analysis processor. The user can set a corresponding protocol analysis program for different flash signals according to actual needs to implement different protocol conversion rules. For example, the signal behavior of the flash medium is affected by the transmission protocol specification followed by the manufacturer and the model, resulting in differences in physical signals in actual operation. By setting different protocol conversion rules for different signals and then sampling different flash medium behaviors according to different protocol conversion rules, the device of the present disclosure can be applied to signal collection and analysis of various types of flash media, improving the versatility of the device of the present disclosure. The flash protocol operation event refers to the flash protocol operation behavior information corresponding to the flash signal. The analysis result determined based on the flash protocol operation event can include at least one flash protocol operation event, which can be set according to actual needs, such as for the collected flash signal, a plurality of flash protocol operation events are obtained through analysis, and the plurality of flash protocol operation events are taken as the analysis result, which is not limited in detail.

[0060] In an optional example, the signal analysis module 22 further comprises a configuration register unit 222.

[0061] The configuration register unit 222 is configured to store the protocol analysis program. The signal analysis module 22 is further configured to read and execute the protocol analysis program from the configuration register unit, perform protocol analysis on the flash signal to obtain a corresponding analysis result, and store the analysis result in the first preset cache area in the first cache module according to the first preset data structure.

[0062] The configuration register unit 222 can be any in-chip memory or preset storage area in the memory, and can be set according to actual needs, for example, can be a cache space on an in-chip SRAM (Static Random-Access Memory). The protocol analysis program is an application program used to be executed to analyze the flash signal and obtain an analysis result. The first preset data structure can be set according to actual needs, and is not limited specifically. The configuration register unit 222 is connected with the protocol analysis unit 221, and the specific connection mode is not limited. The first preset cache area is a cache area set for storing the analysis result.

[0063] Exemplarily, Figure 5 is an exemplary schematic diagram of the first preset data structure provided by an exemplary embodiment of the present disclosure. In this example, the flash protocol operation event is written into the first preset cache area in the form of a linked list data structure, wherein the index number represents the index of the current event (flash protocol operation event) in the linked list, that is, the position of the event in the linked list; the event predecessor pointer is a pointer pointing to the previous event of the current event; the synchronous / asynchronous identifier indicates whether the signal transmission type corresponding to the current event is asynchronous or synchronous; the Channel index is the flash particle channel identifier operated by the current event, and each flash particle in the flash medium corresponds to a connection channel; the CE index is the chip select enable index corresponding to the current event; the operation type is the operation type corresponding to the current event, and the operation type includes three basic types of reading, writing and erasing. For each basic type, more granular types can be further divided according to the operation on the flash medium, such as read block, read page, etc. The operation address is the address operated by the current event; the operation content (value) is the specific operation content of the current event, which can be set according to actual needs; the data address pointer is a pointer pointing to the storage address of the data content involved in the current event. For the data content carried in the flash signal, the flash signal is split into control signal content and data content for storage. After the data content is stored in a certain area, the first address pointer in the control signal content points to the first address of the storage space corresponding to the data content. After the flash signal is analyzed according to the protocol, the flash protocol operation event involving the data content also points to the first address of the storage space of the data content through the second address pointer, so as to avoid data copying in the analysis process; the data length is the length of the data content; the time mark is the time point at which the current event is completed; the description terminator is the end identifier of the first preset data structure of the current event; and the event successor pointer is a pointer pointing to the next event of the current event in the linked list.

[0064] In practical application, the first preset data structure is not limited to the link list structure and content in the above figure, and the specific structure and content can be set according to actual requirements, as long as the flash protocol operation event sequence of analysis can be clearly indicated.

[0065] In an optional example, the configuration register unit 222 includes a first storage subunit 2221 and a second storage subunit 2222.

[0066] The first storage subunit 2221 is configured to store a protocol analysis program, and the second storage subunit 2222 is configured to store a first read pointer and a first write pointer corresponding to the first preset cache area. The first read pointer and the first write pointer are used to identify a first storage state of the first preset cache area in which a newly generated analysis result is stored.

[0067] The first storage subunit 2221 can be an instruction tightly coupled memory (ITCM). The second storage subunit can be a configuration register space. The first storage subunit 2221 and the second storage subunit 2222 are respectively connected with the protocol analysis unit 221, and the specific connection manner is not limited, for example, the protocol analysis unit 221 is connected with the first storage subunit 2221 through an instruction bus unit (IBU) interface, and accesses the second storage subunit 2222 through an additional configuration bus unit (CBU) interface. The first read pointer and the first write pointer are respectively used to control the read and write operations on the first preset cache area, so that the first storage state of the first preset cache area in which the newly generated analysis result is stored can be determined through the addresses respectively pointed to by the first read pointer and the first write pointer. The first storage state can include two states of a new analysis result storage state and a new analysis result non-storage state. For example, when the first read pointer and the first write pointer are equal, it indicates that there is no new analysis result, and when there is a difference between the first write pointer and the first read pointer, that is, a new analysis result write operation is generated, but no new read operation is generated, it indicates that the new analysis result is stored, and the specific principle is not described again. Correspondingly, each time the analysis result write operation is performed, the first write pointer needs to be updated, and each time the analysis result read operation is performed, the first read pointer needs to be updated, so as to maintain the first read pointer and the first write pointer in real time, so that the first read pointer and the first write pointer can accurately identify the first storage state of the first preset cache area in which the newly generated analysis result is stored, and the chip processor or the external terminal can know whether there is a newly generated analysis result in real time. The external terminal is, for example, a debugging host, and after the debugging tool program on the debugging host detects that a new analysis result has been generated through detecting the difference between the first read pointer and the first write pointer, the new analysis result is read through a connection channel (such as a peripheral component interconnect express (PCIe) channel) of the first preset cache area, and the first read pointer is updated after the reading is completed. That is, the first read pointer is maintained by the party (such as the debugging host) that reads the analysis result, and the first write pointer is maintained by the party (such as the protocol analysis unit) that writes the analysis result.

[0068] The present disclosure is used to identify the first storage state of the first preset cache area in which the newly generated analysis result is stored by maintaining the first read pointer and the first write pointer, so that the host that needs to read the analysis result can detect whether there is a newly generated analysis result in real time, and view in time, thereby improving the real-time output of the analysis result.

[0069] In an optional example, the configuration register unit 222 further comprises: a third storage subunit 2223, configured to store a second read pointer and a second write pointer corresponding to a second preset cache area in the first cache module; the second read pointer and the second write pointer are used to identify a second storage state of the second preset cache area in which the unanalyzed flash signals are stored.

[0070] The second preset cache area is a preset cache area in the first cache module 23 for storing the collected flash signals. The second read pointer and the second write pointer are used to maintain the read-write operation of the flash signals. The second write pointer is updated every time a flash signal write operation is performed, and the second read pointer is updated every time a flash signal read operation is performed, so that the second read pointer and the second write pointer point to the current read position and the current write position respectively, thereby determining whether there is a newly written flash signal in the second preset cache area that has not been analyzed based on the second read pointer and the second write pointer. The second storage state includes two states: storing the unanalyzed flash signals and not storing the unanalyzed flash signals. The specific principle of the second read pointer and the second write pointer identifying the second storage state of the second preset cache area in which the unanalyzed flash signals are stored is similar to that of the first read pointer and the first write pointer, and will not be repeated here. The second read pointer is maintained by the party that reads the flash signals (such as the protocol analysis unit 221), that is, the protocol analysis unit 221 reads the flash signals once, and after the read operation is completed, the second read pointer is updated. The second write pointer register is maintained by the party that writes the flash signals (such as the signal collection module 21), that is, the signal collection module 21 writes the flash signals once, and after the write operation is completed, the second write pointer is updated.

[0071] The present disclosure identifies the second storage state of the second preset cache area in which the unanalyzed flash signals are stored through the second read pointer and the second write pointer, so that the signal analysis module 22 or the protocol analysis unit 221 can detect the unanalyzed flash signals in real time or at a fixed time, and analyze them in time to obtain the analysis result.

[0072] In an optional example, the second storage subunit 2222 comprises: a first read pointer register 22221 and a first write pointer register 22222. The first read pointer register 22221 is configured to store the first read pointer; and the first write pointer register 22222 is configured to store the first write pointer.

[0073] In an optional example, the third storage subunit 2223 comprises: a second read pointer register 22231 and a second write pointer register 22232. The second read pointer register 22231 is configured to store the second read pointer; and the second write pointer register 22232 is configured to store the second write pointer.

[0074] Figure 6is a structural schematic diagram of an apparatus for analyzing in-chip flash memory signals provided by another exemplary embodiment of the present disclosure.

[0075] In an optional example, the apparatus of the present disclosure further comprises a first updating module 24 and a second updating module 25.

[0076] The first updating module 24 is configured to update the second write pointer after the flash memory signals are written in the second preset cache area; and the second updating module 25 is configured to update the second read pointer after the flash memory signals in the second preset cache area are read.

[0077] Specifically, the second read pointer can also be updated and maintained by the second updating module 25, and the second write pointer can also be updated and maintained by the first updating module 24. For example, after the signal collection module 21 writes the flash memory signals into the second preset cache area, the signal collection module 21 sends a second write pointer update command to the first updating module 24, and the first updating module 24 updates the second write pointer. For another example, after the signal analysis module 22 reads the flash memory signals for analysis, the signal analysis module 22 sends a second read pointer update command to the second updating module 25 to control the second updating module 25 to update the second read pointer. The specific command mode can be set according to actual needs, and the present disclosure does not make any limitation.

[0078] In an optional example, the second read pointer and the second write pointer can be directly maintained by the reading side and the writing side without the need of the first updating module and the second updating module. The specific mode can be set according to actual needs.

[0079] In an optional example, the apparatus of the present disclosure further comprises a third updating module 26 and a fourth updating module 27. The third updating module 26 is configured to update the first write pointer after the analysis results are written in the first preset cache area; and the fourth updating module 27 is configured to update the first read pointer in response to an update command after the analysis results are read.

[0080] Specifically, similar to the second read pointer and the second write pointer, the first read pointer can be updated and maintained by the fourth updating module 27, and the first write pointer can be updated and maintained by the third updating module 26. For example, after the terminal detects newly generated analysis results, the terminal reads the newly generated analysis results. After the reading operation is completed, the terminal sends a first read pointer update command to the fourth updating module 27, and the fourth updating module 27 updates the first read pointer in the first read pointer register in response to the update command of the terminal. The specific principle will not be described again. The terminal can be a host device where the apparatus of the present disclosure is located. The update command of the terminal can be transmitted by a main processor of a system on chip (SoC), or can be transmitted by other possible ways. The specific communication principle between the terminal and the SoC will not be described again.

[0081] In an optional example, the signal acquisition module 21 comprises a signal probe unit 211 and a signal recording unit 212.

[0082] The signal probe unit 211 is used to be mounted on the port of the flash medium to acquire the flash signal of the port, and the signal recording unit 212 is used to store the acquired flash signal according to a second preset data structure.

[0083] The signal probe unit 211 can adopt any implementable probe structure, and the specific implementation is not limited. The second preset data structure can be set according to actual needs, and the present disclosure is not limited. The signal recording unit 212 stores the flash signal into a second preset cache area of the first cache module 23.

[0084] An exemplary structure of the signal acquisition module 21 is shown in FIG. 2B. Figure 7 An exemplary structure of the signal acquisition module 21 is shown in FIG. 2B.

[0085] An exemplary structure of the signal acquisition module 21 is shown in FIG. 2B. Figure 8 An exemplary structure of the signal acquisition module 21 is shown in FIG. 2B.

[0086] In practical applications, the second preset data structure is not limited to the above-mentioned linked list structure, and the specific structure and content can be set according to actual needs, as long as the collected flash signal content can be clearly described.

[0087] Figure 9 is a structural schematic diagram of an apparatus for analyzing a flash signal in a chip provided by another exemplary embodiment of the present disclosure.

[0088] In an optional example, the first cache module 23 includes a first preset cache area 231 and a second preset cache area 232. The first preset cache area 231 is configured to store analysis results, and the second preset cache area 232 is configured to store flash signals.

[0089] The second preset cache area 232 includes a control signal content area 2321 configured to store control signal content in the flash signal and a data content area 2322 configured to store data content in the flash signal. The control signal content is pointed to a first address of a corresponding data content space segment by a first address pointer. A flash protocol operation event in the analysis results is pointed to a first address of a corresponding data content space segment by a second address pointer.

[0090] Specifically, since the sampled flash signal contains a large amount of data, in order to facilitate the management of the cache space, the second preset cache area 232 is divided into the control signal content area 2321 and the data content area 2322. The control signal content is pointed to a first address of a corresponding data content space segment by a first address pointer. After the signal analysis module 22 reads the unanalyzed flash signal in the second preset cache area, the generated analysis results are recorded in the first preset cache area after analysis and processing. The flash protocol operation event in the analysis results involves the data content in the flash signal, and is pointed to a first address of a corresponding data content space segment by a second address pointer. Therefore, the large amount of memory data copying in the analysis process can be avoided, and the management efficiency of the cache space is effectively improved.

[0091] Exemplarily, Figure 10 is a data structure arrangement schematic diagram of the first cache module 23 provided by an exemplary embodiment of the present disclosure. In the data structure arrangement schematic diagram, data ptr in the control signal content of the flash signal represents a first address pointer, and data ptr in the flash protocol operation event represents a second address pointer.

[0092] Figure 11 is a structural schematic diagram of an apparatus for analyzing a flash signal in a chip provided by another exemplary embodiment of the present disclosure.

[0093] In an optional example, the device of the present disclosure further comprises a second cache module 28 configured to store an unfinished protocol analysis task in the case of interleaving of multiple flash memory operations.

[0094] Specifically, the analysis result generated by the protocol analysis may need to be obtained based on multiple flash memory signal analyses, and the read order of the flash memory signal is read according to the order of the pointer, and there is a yield scheduling in the task scheduling in the flash memory controller, and there is time-sharing multiplexing of the IO interface for the execution of different commands to ensure the effective use of the channel bandwidth by each flash memory operation task as much as possible, which causes the relative existence of signal execution of each operation task to be interleaved, so that there may be a flash memory signal of another analysis task generated while an analysis task is not completed. In order to solve this problem, the device of the present disclosure is provided with a second cache module 28 configured to temporarily store an unfinished protocol analysis task in the case of interleaving of multiple flash memory operations, so that the flash memory signal required by the unfinished protocol analysis task can be obtained subsequently, and the protocol analysis can be continued to obtain the analysis result, and then stored in the first cache module, thereby ensuring that the device of the present disclosure can cope with the interleaving case and complete the protocol analysis of all flash memory signals in the case of interleaving of multiple flash memory task IO signal phase sequences at the IO port of the flash memory medium.

[0095] In an optional example, in order to simplify the device of the present disclosure and at the same time ensure that the signal analysis is completed as soon as possible, the first read pointer, the first write pointer, the second read pointer and the second write pointer in the present disclosure are all one-way moving pointers, and the pointer backtracking operation is prohibited.

[0096] Figure 12 FIG. 2 is a structural schematic diagram of the signal analysis module 22 provided by another exemplary embodiment of the present disclosure.

[0097] In an optional example, the signal analysis module 22 further comprises an output unit 223 configured to output the analysis result to a terminal.

[0098] The terminal can be a host provided with the device of the present disclosure, or can be an external terminal, and the specific terminal is not limited. The output unit 223 can be connected to the terminal through a preset connection mode, and the preset connection mode can be set according to actual needs, and the present disclosure is not limited. For example, for the host where the device of the present disclosure is located, the analysis result can be output to the host through a PCIe interface, or the host can read the analysis result through a PCIe interface. For the terminal of an external device, the analysis result can be output to the terminal through a UART (Universal Asynchronous Receiver / Transmitter) interface, so that the analysis result can be output to the terminal through the UART interface. The specific output object can be set according to actual needs.

[0099] In an optional example, the signal analysis module 22 further comprises a first configuration unit 224 and / or a second configuration unit 225.

[0100] The first configuration unit 224 is configured to write the protocol analysis program into the configuration register unit in response to a protocol analysis program write command; and the second configuration unit 225 is configured to write corresponding configuration information into the configuration register unit in response to a configuration command.

[0101] The protocol analysis program write command can be triggered by a user through a host connected to the device of the present disclosure to write the protocol analysis program into the configuration register unit, so that the device of the present disclosure can read the protocol analysis program from the configuration register unit to perform the protocol analysis task when starting to work. Similarly, the configuration command can be triggered by the user, and the configuration information can include the sampling rule of the signal acquisition module, the detection rule of different time sequence signals, other related information required for executing the protocol analysis program to complete the analysis task, etc., which can be set according to actual needs. Correspondingly, the configuration register unit can include a storage subunit or a register for storing various configuration information, which can be set according to actual needs, and the present disclosure is not limited. The configuration register unit can be set as an SRAM with multiple access interfaces, which is connected to the SoC system bus. The main processor (CPU) in the SoC can also configure or input the protocol analysis program of the device of the present disclosure through the bus interface.

[0102] The present disclosure provides configuration function for users, so that users can configure according to actual needs to adapt to the protocol analysis of flash memory signals of various flash media, further improving the versatility of the device of the present disclosure. Specifically, the signal behavior of the flash memory particles of the flash media is affected by the manufacturer, the transmission protocol specification and the model, and the physical signals in actual operation exist differences. The user can configure the corresponding sampling rule and protocol analysis program according to the different flash particle behaviors, so as to realize the customization of protocol analysis rule for the signal behavior of different types of flash particles, and can be repeatedly configured, has high programmability, can be flexibly adapted to different manufacturers and models of flash particles to complete the protocol analysis of specified flash signal behavior, effectively improves the user experience on the basis of reducing the cost of flash signal protocol analysis.

[0103] In practical applications, when the device of the present disclosure has no protocol analysis task (i.e. the second read pointer is in a read empty state, i.e. the second read pointer is equal to the second write pointer), it can be determined to be in a standby state, the device of the present disclosure suspends the protocol analysis program, and can detect the difference between the second read pointer and the second write pointer in a polling manner to determine whether there is an unprocessed flash signal. When an unprocessed flash signal is detected, it enters a working state, reads the unprocessed flash signal from the second preset cache area for protocol analysis, and increments the second read pointer register according to the number of read flash signals until it is equal to the second write pointer register. The flash protocol operation events obtained by the protocol analysis are written into the first preset cache area through the data bus channel. The working state of the device of the present disclosure can be divided into two modes: a high-speed mode (PCIe mode) and a low-speed mode (UART mode). The high-speed mode is suitable for scenarios with high flash working bandwidth, and the low-speed mode is suitable for scenarios with low transmission bandwidth in simple cases. The working mode can be determined according to actual needs. For example, when working in a high-speed mode, the device of the present disclosure can update the valid content write pointer register of the first preset cache area on the BAR space register of the PCIe interface (PCIe Endpoint, which is the bus protocol interface between the debug host and the device of the present disclosure) of the debug host. The valid content write pointer register is exposed to the user space of the debug host through memory mapping. The debug tool program running on the debug host can determine that new analysis results have been generated through the valid content write pointer register, and then read the newly generated analysis results through the PCIe channel. After completing the PCIe read transmission, the first read pointer register is updated, and an interrupt is triggered, so that the debug host reads the analysis results to the user space of the debug host through the interrupt service program of the PCIe driver layer for relevant personnel to view or analyze. The communication principle between the debug host and the system on chip is not described again. When working in a low-speed mode, the device of the present disclosure transmits the analysis results of the analysis to the RX (receive) end of the UART of the external device through the TX (transport) channel of the UART interface for the external device to obtain or analyze relevant content. When the second write pointer is in a write full state, the device of the present disclosure can select record overwrite or stop record operation according to the relevant configuration. In this example, the first write pointer of the first preset cache area storing the analysis results is maintained by the signal analysis module of the device of the present disclosure, and the first read pointer is maintained by the DMA (Direct Memory Access) control logic of the PCIe interface.

[0104] For example,Figure 13 is a schematic diagram of an analysis result reading process provided by an example embodiment of the present disclosure. In the diagram, Protocol Buffer represents a first preset cache area, Buffer Ptr Reg represents a pointer register identifying the state of the first preset cache area, which can include a first read pointer register and a first write pointer register, or the pointer register is a pointer register representing the difference between the first write pointer register and the first read pointer register, which can be set according to actual requirements. PCIe BAR Space represents a PCIe BAR space, PCIe DMA represents the DMA control logic of a PCIe interface, and Buffer Ptr Reg is mapped to the PCIe BAR space. In process (1), the host polling obtains the pointer register of the BAR space, and when it is detected that the first preset cache area stores content with a length greater than or equal to 4 KB, the reading process is performed. In the reading operation of (2), the host initiates a PCIe operation to the SoC, which is sent to the NVMe (Non-Volatile Memory Host Controller Interface Specification) module (NVMe Engine) through the PCIe EndPoint, and PCIe Lane represents a PCIe channel. In process (3), the read task operation information processed by the NVMe module is sent to the PCIe DMA, and the host memory physical page destination address to which the read information is sent is obtained. In process (4), the PCIe DMA starts to transmit the analysis result content pointed to by the current pointer to the target memory address required by the host in units of 4K, and Read Buffer represents the memory of the host.

[0105] When the bandwidth of the flash memory is high, the present disclosure uses a high-speed mode transmission protocol based on PCIe transmission to transmit the analysis result, so as to avoid the overflow of the first preset cache area storing the analysis result due to insufficient analysis result export rate, thereby ensuring the accuracy and reliability of the analysis result.

[0106] In actual applications, the device of the present disclosure can also be divided into modules in other ways, and the specific division is not limited to the above-mentioned way.

[0107] In an optional example, Figure 14is a structural schematic diagram of an apparatus for analyzing in-chip flash memory signals provided by another exemplary embodiment of the present disclosure. In this example, the apparatus of the present disclosure includes a processor, a signal acquisition module, a configuration register, a first cache module, and a peripheral interface UART. The configuration register is a cache space on an on-chip SRAM, including an ITCM for storing a protocol analysis program, a first read pointer register for storing a first read pointer, a first write pointer register for storing a first write pointer, a second read pointer register for storing a second read pointer, and a second write pointer register for storing a second write pointer. The ITCM is an instruction tightly coupled memory of the processor. The structure and function of the signal acquisition module are consistent with the foregoing. The processor is configured to read and execute the protocol analysis program from the ITCM, implement protocol analysis of the flash memory signals in the second preset cache area, and write the analysis results to the first preset cache area. The processor can also output the flash memory signals and / or the analysis results to an external terminal through the peripheral interface UART. The processor can be connected to other parts through corresponding interfaces, such as the IBU (Instruction Bus Unit, instruction bus unit) interface, the CBU (Configuration Bus Unit, configuration bus unit) interface, the PBU (Peripheral Bus Unit, peripheral bus unit) interface, the DBU (Data Bus Unit, data bus unit) interface, the AXI (Advanced eXtensible Interface, advanced extensible interface), etc. The specific connection mode is not limited to these interfaces in the figure, and can be set according to actual needs. The specific implementation function of the apparatus in this example is consistent with the foregoing embodiments or optional examples, and will not be described here. Optionally, the processor can be any processor suitable for a system on a chip (SoC), such as a processor based on the RISC-V instruction set architecture, without limitation.

[0108] Example Method

[0109] Figure 15 is a flowchart of a method for analyzing in-chip flash memory signals provided by an exemplary embodiment of the present disclosure. The method of this embodiment can be implemented by the corresponding apparatus embodiment of the present disclosure, as shown in Figure 15 The method includes the following steps:

[0110] Step 301, acquiring flash memory signals of a flash memory medium port in a chip.

[0111] Step 302, performing protocol analysis on the flash memory signals to obtain corresponding analysis results.

[0112] For specific operations of each step in this embodiment, refer to the foregoing apparatus embodiment, which will not be described here.

[0113] Figure 16 is a flowchart of a method for analyzing in-chip flash memory signals provided by another example embodiment of the present disclosure.

[0114] In an optional example, the method of the present disclosure further comprises:

[0115] Step 303, storing the flash memory signals.

[0116] Step 304, storing the analysis results.

[0117] In an optional example, the protocol analysis of the flash memory signals in step 302 to obtain corresponding analysis results comprises:

[0118] Step 3021, converting the flash memory signals into flash memory protocol operation events according to the protocol conversion rules corresponding to the flash memory signals, and determining the analysis results based on the flash memory protocol operation events.

[0119] In an optional example, the protocol analysis program is stored in the configuration register unit, and step 302 specifically comprises: reading and executing the protocol analysis program from the configuration register unit, performing protocol analysis on the flash memory signals to obtain corresponding analysis results, and storing the analysis results in the first preset cache area in the first cache module according to the first preset data structure.

[0120] Figure 17 is a flowchart of a method for analyzing in-chip flash memory signals provided by another example embodiment of the present disclosure.

[0121] In an optional example, the storing of the flash memory signals in step 303 comprises:

[0122] Step 3031, storing the flash memory signals in the second preset cache area.

[0123] The second read pointer and the second write pointer corresponding to the second preset cache area are stored in the configuration register unit, and the second read pointer and the second write pointer are used to identify the second storage state of the unanalyzed flash memory signals stored in the second preset cache area.

[0124] In an optional example, the storing of the analysis results in step 304 comprises:

[0125] Step 3041, storing the analysis results in the first preset cache area.

[0126] The first read pointer and the first write pointer corresponding to the first preset cache area are stored in the configuration register unit, and the first read pointer and the first write pointer are used to identify the first storage state of the newly generated analysis results stored in the first preset cache area.

[0127] In an optional example, the method of the present disclosure further comprises:

[0128] Step 305, updating the second write pointer after the flash signal is written in the second preset cache area.

[0129] Step 306, updating the second read pointer after the flash signal in the second preset cache area is read.

[0130] In an optional example, the method of the present disclosure further comprises:

[0131] Step 307, updating the first write pointer after the analysis result is written in the first preset cache area.

[0132] Step 308, updating the first read pointer after the analysis result is read in response to the update command of the terminal.

[0133] In an optional example, the flash signal of the flash media port in the collection chip in step 301 comprises:

[0134] Step 3011, collecting the flash signal of the port by the signal probe unit mounted on the port of the flash media.

[0135] Step 3031 specifically comprises: storing the collected flash signal according to the second preset data structure to the second preset cache area.

[0136] In an optional example, the second preset cache area comprises: a control signal content area and a data content area. Correspondingly, step 3031 specifically comprises: storing the control signal content in the flash signal to the control signal content area, and storing the data content in the flash signal to the data content area; wherein the control signal content is pointed to the first address of the corresponding data content space segment by the first address pointer; the flash operation event in the analysis result is pointed to the first address of the corresponding data content space segment by the second address pointer.

[0137] In an optional example, the method of the present disclosure further comprises: storing the unfinished protocol analysis task in the case of multiple flash operations.

[0138] In an optional example, the method of the present disclosure further comprises: step 402, outputting the analysis result to the terminal.

[0139] Figure 18 is a flowchart of the method for analyzing the flash signal in the chip provided by another exemplary embodiment of the present disclosure.

[0140] In an optional example, the method of the present disclosure further comprises:

[0141] Step 403, in response to the protocol analyzer write command, write the protocol analyzer to the configuration register unit.

[0142] Corresponding step 302 specifically includes:

[0143] Step 3021a, read and execute the protocol analyzer from the configuration register unit, and perform protocol analysis on the flash signal to obtain the corresponding analysis result, and store the analysis result in the first preset cache area in the first cache module according to the first preset data structure.

[0144] In an optional example, the method of the present disclosure further includes:

[0145] Step 404, in response to the configuration command, write the corresponding configuration information to the configuration register unit.

[0146] The specific operations of each step in the method embodiments of the present disclosure and each optional example are described above in the corresponding device embodiments, and will not be repeated here.

[0147] Any one of the methods for analyzing the flash signal in the chip provided by the embodiments of the present disclosure can be executed by any appropriate device with data processing capability, including but not limited to: terminal devices and servers, etc. Alternatively, any one of the methods for analyzing the flash signal in the chip provided by the embodiments of the present disclosure can be executed by a processor, such as a processor executing any one of the methods for analyzing the flash signal in the chip mentioned by the embodiments of the present disclosure by calling the corresponding instructions stored in the memory. The following will not be repeated.

[0148] Example Electronic Device

[0149] The embodiments of the present disclosure also provide an electronic device, including: a memory, configured to store a computer program; and a processor, configured to execute the computer program stored in the memory, and when the computer program is executed, implement the method for analyzing the flash signal in the chip according to any one of the embodiments of the present disclosure.

[0150] Figure 19 FIG. 1 is a structural schematic diagram of an application embodiment of the electronic device of the present disclosure. In this embodiment, the electronic device 10 includes one or more processors 11 and a memory 12.

[0151] The processor 11 can be a central processing unit (CPU) or other forms of processing units with data processing capability and / or instruction execution capability, and can control other components in the electronic device 10 to perform desired functions.

[0152] The memory 12 can include one or more computer program products that can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory, for example, can include random access memory (RAM), cache memory, and / or the like. The non-volatile memory, for example, can include read only memory (ROM), hard disk drives, flash memory, and / or the like. The computer-readable storage media can store one or more computer program instructions implementing the methods of the various embodiments of the present disclosure described above and / or other desired function. Various contents such as input signals, signal components, noise components, and the like can also be stored in the computer-readable storage media.

[0153] In one example, the electronic device 10 can further include an input device 13 and an output device 14, which are interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0154] For example, the input device 13 can be the microphone or the microphone array described above, which is used to capture the input signal of the sound source.

[0155] In addition, the input device 13 can further include, for example, a keyboard, a mouse, and the like.

[0156] The output device 14 can output various information including the determined distance information, direction information, and the like to the outside. The output device 14 can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0157] Of course, in order to simplify, Figure 19 Only some of the components of the electronic device 10 related to the present disclosure are shown in FIG. 1, and components such as buses, input / output interfaces, and the like are omitted. In addition, the electronic device 10 can further include any other appropriate components according to the specific application.

[0158] Example Computer Program Product and Computer-Readable Storage Medium

[0159] In addition to the above-described methods and devices, embodiments of the present disclosure can also be a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods according to various embodiments of the present disclosure described in the above "Exemplary Methods" section of the specification.

[0160] The computer program product can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device or entirely on the remote computing device or server.

[0161] Furthermore, embodiments of the present disclosure can also be a computer readable storage medium, having stored thereon computer program instructions which, when executed by a processor, cause the processor to perform steps of the methods described in the above “Exemplary Methods” section according to various embodiments of the present disclosure.

[0162] The computer readable storage medium can be any combination of one or more computer readable media. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0163] The above describes the basic principles of the present disclosure in combination with specific embodiments, but it should be noted that the advantages, benefits, effects and the like mentioned in the present disclosure are only examples and are not limiting, and these advantages, benefits, effects and the like cannot be considered as the must-haves of each embodiment of the present disclosure. In addition, the above specific details are only for the purpose of example and understanding, and the above details do not limit the present disclosure to the must-haves of the above specific details.

[0164] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between each embodiment can be referred to each other. For system embodiments, since they are basically corresponding to method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0165] The block diagrams of devices, apparatuses, equipment, systems referred to in this disclosure are merely illustrative examples and are not intended to require or imply that the connection, arrangement, configuration must be as shown in the block diagrams. These devices, apparatuses, equipment, systems can be connected, arranged, configured in any manner as will be appreciated by those skilled in the art. Words such as "include," "contain," "have," and the like are open-ended words that are to be interpreted to mean "including but not limited to," and are not to be interpreted as limiting the described embodiment to features, elements, and / or steps disclosed herein. The words "or" and "and" as used herein are to be interpreted as the word "and / or," and are not to be interpreted as requiring both features, elements, and / or steps disclosed herein. The word "such as" as used herein is to be interpreted as the phrase "such as but not limited to," and is not to be interpreted as limiting the described embodiment to features, elements, and / or steps disclosed herein.

[0166] The methods and apparatuses of this disclosure can be implemented in a number of ways. For example, the methods and apparatuses of this disclosure can be implemented using software, hardware, firmware, or any combination of these. The above described order of steps for the methods is merely illustrative, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, the disclosure can also be implemented as a program recorded in a recording medium, which includes machine readable instructions for implementing the methods according to the disclosure. Thus, the disclosure also covers a recording medium storing a program for executing the methods according to the disclosure.

[0167] It is also important to note that the devices, equipment, and methods of this disclosure can be embodied in a variety of ways. These variations are contemplated as being within the scope of the present disclosure.

[0168] The above description of the disclosed aspects is given for illustrative purposes and is not intended to limit the scope of the disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0169] The above description has been given for illustrative and descriptive purposes. In addition, this description is not intended to limit embodiments of the disclosure to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain modifications, permutations, additions, and sub-combinations thereof.

Claims

1. An apparatus for analyzing flash signals in a chip, comprising: a signal acquisition module configured to acquire flash signals of a flash media port in the chip; a signal analysis module configured to perform protocol analysis on the flash signals and obtain corresponding analysis results; wherein the signal acquisition module comprises: a signal probe unit configured to be mounted on the flash media port and acquire flash signals of the port; a signal recording unit configured to store the acquired flash signals according to a second preset data structure.

2. The apparatus of claim 1, further comprising: a first cache module configured to store the flash signals and the analysis results.

3. The apparatus of claim 2, wherein, The first cache module comprises: a first preset cache area configured to store the analysis results; a second preset cache area configured to store the flash signals; wherein the second preset cache area comprises: a control signal content area configured to store control signal content in the flash signals; a data content area configured to store data content in the flash signals; wherein the control signal content is pointed to a first address of a corresponding data content space segment by a first address pointer; a flash protocol operation event in the analysis results is pointed to a first address of a corresponding data content space segment by a second address pointer.

4. The apparatus of claim 1, wherein, The signal analysis module comprises: a protocol analysis unit configured to convert the flash signals into flash protocol operation events according to corresponding protocol conversion rules of the flash signals, and determine analysis results based on the flash protocol operation events.

5. The apparatus of claim 1, wherein, The signal analysis module further comprises: a configuration register unit configured to store a protocol analysis program; The signal analysis module is further configured to read and execute the protocol analysis program from the configuration register unit, perform protocol analysis on the flash signals to obtain corresponding analysis results, and store the analysis results in the first preset cache area of the first cache module according to a first preset data structure.

6. The apparatus of claim 5, wherein, The configuration register unit comprises: a first storage subunit configured to store the protocol analysis program; a second storage subunit configured to store a first read pointer and a first write pointer corresponding to the first preset cache area; the first read pointer and the first write pointer are used to identify a first storage state of the first preset cache area in which newly generated analysis results are stored.

7. The apparatus of claim 5, wherein, The configuration register unit further comprises: a third storage subunit configured to store a second read pointer and a second write pointer corresponding to a second preset cache area in the first cache module; the second read pointer and the second write pointer are used to identify a second storage state of the second preset cache area in which unanalyzed flash signals are stored.

8. The apparatus of claim 1, further comprising: a second cache module configured to store unfinished protocol analysis tasks in a plurality of flash operation insertion cases.

9. A method for analyzing flash signals in a chip, comprising: acquiring flash signals of a flash media port in the chip; performing protocol analysis on the flash signals and obtaining corresponding analysis results; wherein the acquiring flash signals of the flash media port in the chip comprises: acquiring the flash signal of the port through a signal probe unit mounted on the port of the flash medium; the method further comprises: storing the acquired flash signal according to a second preset data structure. 10.A computer readable storage medium, the storage medium storing a computer program, the computer program being used to execute the method for analyzing the in-chip flash signal according to claim 9; or, the storage medium being used to store the data required to be stored by the device for analyzing the in-chip flash signal according to any one of claims 1-8, so that the device can realize the corresponding function when working. 11.An electronic device, the electronic device comprising: a processor; a memory for storing executable instructions of the processor; the processor, for reading the executable instructions from the memory and executing the instructions to realize the method for analyzing the in-chip flash signal according to claim 9; or, the electronic device comprising: the device for analyzing the in-chip flash signal according to any one of claims 1-8.

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