Method for manufacturing silicon carbide device with terminal protection structure

Abstract

The present disclosure relates to a method for manufacturing a silicon carbide device with a terminal protection structure. The method includes: generating a first dielectric layer on a substrate, the material of the substrate including silicon carbide; forming a target area of ​​the silicon carbide device in the substrate, and removing the first dielectric layer, the target area including the JFET area, the body area, the N-type source doping area and the P-type doping area; generating a gate area above the target area, etching the substrate to form an isolation trench; forming a continuous second dielectric layer above a preset covering object, the preset covering object being at least the isolation trench; wherein the terminal protection structure of the silicon carbide device includes the isolation trench and the second dielectric layer, and the position of the isolation trench is different from that of the JFET area, the N-type source doping area and the P-type doping area. The terminal protection structure in the manufactured silicon carbide device has a short characteristic length, a small device area, good performance, and a simple process, which can reduce the device size and reduce costs.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor device manufacturing, and in particular to a method for manufacturing a silicon carbide device with a terminal protection structure. Background Art

[0002] High-voltage power semiconductor devices are typically equipped with terminal protection structures. These specialized protection structures are designed to reduce local electric fields, improve surface breakdown voltage and reliability, and bring the device's actual breakdown voltage closer to the ideal value of a parallel-plane junction. In related art, these terminal protection structures suffer from long lengths, large chip area occupation, complex manufacturing processes, and high costs. For example, for devices with a breakdown voltage of around 1200V, the junction terminal protection structure is approximately 100μm or even longer. Summary of the Invention

[0003] In view of this, the present disclosure proposes a method for manufacturing a silicon carbide device with a terminal protection structure to solve the above technical problems.

[0004] According to one aspect of the present disclosure, a method for manufacturing a silicon carbide device having a terminal protection structure is provided, comprising:

[0005] Generating a first dielectric layer on a substrate, wherein the material of the substrate includes silicon carbide;

[0006] forming a target region of the silicon carbide device in the substrate and removing the first dielectric layer, the target region including a JFET region, a body region, an N-type source doped region, and a P-type doped region;

[0007] Generating a gate region above the target region, and etching the substrate to form an isolation trench;

[0008] forming a continuous second dielectric layer above a predetermined covering object to complete the manufacture of the silicon carbide device, wherein the predetermined covering object includes at least the isolation trench;

[0009] The terminal protection structure of the silicon carbide device includes the isolation trench and the second dielectric layer, and the position of the isolation trench is different from that of the JFET region, the N-type source doping region, and the P-type doping region.

[0010] In a possible implementation, the substrate includes a silicon carbide layer and an epitaxial layer, and a depth of the isolation trench is greater than or equal to 0.5 times the thickness of the epitaxial layer.

[0011] In a possible implementation, generating a gate region above the target region and etching the substrate to form an isolation trench include:

[0012] sequentially forming a gate dielectric layer and a polysilicon layer above the substrate;

[0013] Etching the polysilicon layer to generate a gate region above the target region;

[0014] etching the substrate and the gate dielectric layer to form an isolation trench;

[0015] Wherein, the preset covering object further includes: the exposed gate dielectric layer and the remaining polysilicon layer.

[0016] In a possible implementation, generating a gate region above the target region and etching the substrate to form an isolation trench include:

[0017] etching the substrate to form an isolation trench;

[0018] sequentially forming a gate dielectric layer and a polysilicon layer above the substrate;

[0019] Etching the polysilicon layer to generate a gate region above the target region;

[0020] Wherein, the preset covering object further includes: the exposed gate dielectric layer and the remaining polysilicon layer.

[0021] In a possible implementation, generating a gate region above the target region and etching the substrate to form an isolation trench include:

[0022] forming an intermediate dielectric layer above the substrate;

[0023] Based on the shape and size of the gate dielectric layer to be covered on the substrate, etching the intermediate dielectric layer to obtain an etched intermediate dielectric layer;

[0024] Generating a gate dielectric layer above the exposed substrate, and forming a polysilicon layer above the gate dielectric layer and the etched intermediate dielectric layer;

[0025] Etching the polysilicon layer to generate a gate region above the target region;

[0026] Sequentially etching the etched intermediate dielectric layer and the substrate to form isolation trenches;

[0027] If the etched intermediate dielectric layer remains above the substrate, the preset covering object further includes: the exposed gate dielectric layer, the remaining polysilicon layer, and the remaining etched intermediate dielectric layer.

[0028] In a possible implementation, the thickness of the first dielectric layer is and / or

[0029] The thickness of the gate dielectric layer is and / or

[0030] The thickness of the polysilicon layer is 0.2 μm-1 μm.

[0031] In a possible implementation, the thickness of the second dielectric layer is 0.5 μm-2.5 μm.

[0032] In a possible implementation, the thickness of the intermediate dielectric layer is 0.2 μm-1 μm.

[0033] In a possible implementation, the characteristic length of the terminal protection structure is 15 μm-50 μm.

[0034] The presently disclosed embodiment provides a method for manufacturing a silicon carbide device with a terminal protection structure. The manufactured silicon carbide device has a terminal protection structure that can reduce the local electric field, improve the surface breakdown voltage and reliability, and make the actual breakdown voltage of the device closer to the ideal value of a parallel plane junction. The terminal protection structure has a short characteristic length, occupies a small device area, has good performance, and is simple to manufacture. This can reduce the area size of the silicon carbide device and reduce the cost of the silicon carbide device.

[0035] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0037] Figure 1 A flow chart of a method for manufacturing a silicon carbide device with a terminal protection structure according to an embodiment of the present disclosure is shown.

[0038] Figure 2 A schematic flow chart of steps S301 and S302 in a method for manufacturing a silicon carbide device with a terminal protection structure according to an embodiment of the present disclosure is shown.

[0039] Figure 3-Figure 5 A flow chart of steps S303 and S304 in a method for manufacturing a silicon carbide device with a terminal protection structure according to an embodiment of the present disclosure is shown.

[0040] Figure 6 A schematic structural diagram showing a partial structure of a silicon carbide device with a terminal protection structure according to an embodiment of the present disclosure.

[0041] Figure 7 、 Figure 8 The figures respectively show a potential distribution diagram and a breakdown voltage curve diagram corresponding to a silicon carbide device with a terminal protection structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0043] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0044] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0045] The presently disclosed embodiment provides a method for manufacturing a silicon carbide device with a terminal protection structure. The manufactured silicon carbide device has a terminal protection structure that can reduce the local electric field, improve the surface breakdown voltage and reliability, and make the actual breakdown voltage of the device closer to the ideal value of a parallel plane junction. The terminal protection structure has a short characteristic length, occupies a small device area, has good performance, and is simple to manufacture. This can reduce the area size of the silicon carbide device and reduce the cost of the silicon carbide device.

[0046] Figure 1 FIG. 1 is a flow chart showing a method for manufacturing a silicon carbide device having a terminal protection structure according to an embodiment of the present disclosure. Figure 1 As shown, the method includes: steps S301 to S304. Figure 2 A schematic flow chart of steps S301 and S302 in a method for manufacturing a silicon carbide device with a terminal protection structure according to an embodiment of the present disclosure is shown. Figure 3-Figure 5 A schematic flow chart illustrating steps S303 and S304 of a method for manufacturing a silicon carbide device with a terminal protection structure according to an embodiment of the present disclosure is shown. The method provided by the present disclosure is described below in conjunction with the aforementioned figures. The silicon carbide device involved in the present disclosure can be a high-voltage power semiconductor device, such as a MOSFET, or other device requiring a terminal protection structure, but the present disclosure does not limit this.

[0047] In step S301, Figure 2 As shown, a first dielectric layer 11 is generated on a substrate 10 , wherein the material of the substrate 10 includes silicon carbide.

[0048] In this embodiment, the material of the first dielectric layer can be silicon dioxide, silicon nitride, etc., and the thickness of the first dielectric layer is The first dielectric layer is used to protect the substrate 10 to prevent damage to the substrate 10 caused by the process used in step S302 to prepare the target area. Therefore, the thickness and material of the first dielectric layer can be set according to the parameters of the process used in step S302, and this disclosure does not limit this.

[0049] In step S302, Figure 2 As shown, a target region of the silicon carbide device is formed in the substrate 10 and the first dielectric layer 11 is removed. The target region includes a JFET region 12, a body region 13, an N-type source doped region 14 and a P-type doped region 15.

[0050] In step S302, each region in the target region may be formed in sequence. Figure 2 As shown, a JFET region 12 , a body region 13 , an N-type source doping region 14 and a P-type doping region 15 are sequentially formed in the substrate 10 .

[0051] In this embodiment, the depths and other dimensions of the JFET region 12 , the body region 13 , the N-type source doping region 14 , and the P-type doping region 15 may be set as needed, and this disclosure does not impose any limitation thereto.

[0052] In this embodiment, after the target region is formed, high-temperature annealing may be performed to repair damage to the substrate 10 caused during the process of forming the target region.

[0053] In step S303, a gate region is generated above the target region, and the substrate is etched to form an isolation trench. The position of the isolation trench 18 is different from the positions of the JFET region 12, the N-type source doped region 14, and the P-type doped region 15. The isolation trench 18 can be located outside the entire silicon carbide device functional region (i.e., the region corresponding to the target region) so that the formed terminal protection structure is located outside the silicon carbide device functional region to protect the silicon carbide device.

[0054] In this embodiment, the gate region may include a gate dielectric layer and a polysilicon layer. The thickness of the gate dielectric layer may be The thickness of the polysilicon layer can be 0.2 μm-1 μm. For example, the thickness of the gate dielectric layer can be The thickness of the polysilicon layer may be 0.6 μm. Those skilled in the art may set the thickness of the gate dielectric layer and the polysilicon layer according to actual needs, and the present disclosure does not limit this.

[0055] In step S304, Figure 3-Figure 5 As shown, a continuous second dielectric layer 19 is formed on the predetermined covering object to complete the manufacturing of the silicon carbide device. The terminal protection structure of the silicon carbide device includes an isolation trench 18 and the second dielectric layer 19. The predetermined covering object includes at least the isolation trench 18.

[0056] In this embodiment, based on the order of preparing the gate region and the isolation trench, the implementation of step S303 may include the following implementations 1, 2, and 3. Figure 3-Figure 5 Implementation methods one, two, and three are explained.

[0057] Implementation method 1:

[0058] like Figure 3 As shown, after step S302, step S303 is performed: a gate dielectric layer 16 and a polysilicon layer 17 can be sequentially formed above the substrate 10. The polysilicon layer 17 is then etched according to a predetermined gate region shape to form a gate region 17'. Next, the gate dielectric layer 16 is etched according to predetermined trench positions and dimensions to obtain a remaining gate dielectric layer 16', thereby exposing the trench region of the substrate 10. Finally, the trench region of the substrate 10 is etched to form an isolation trench 18.

[0059] In this embodiment, the surface of the substrate 10 can be treated by a method such as high temperature thermal oxidation, so that the surface layer of the substrate 10 is oxidized to form a Figure 3 The gate dielectric layer 16 is made of silicon dioxide. A polysilicon layer 17 is then formed on the gate dielectric layer 16.

[0060] In this embodiment, the polysilicon layer 17, the substrate 10, and the gate dielectric layer 16 can be etched by photolithography and etching processes. For example, a photoresist can be first coated on the polysilicon layer 17, and then the photoresist is exposed and developed according to the shape and size of the preset gate region and the shape and size of the preset trench region. Thereafter, the polysilicon layer 17 is first etched by a corresponding etching process to form the gate region 17', and then the gate dielectric layer 16 and the substrate 10 are sequentially etched by a corresponding etching process to form the isolation trench 18. It is understood that those skilled in the art can set the implementation method of etching the polysilicon layer 17, the substrate 10, and the gate dielectric layer 16 according to actual needs, and the present disclosure does not limit this.

[0061] like Figure 3As shown, after step S303, step S304 is performed: forming a continuous second dielectric layer 19 above the preset covering object to complete the manufacturing of the silicon carbide device. Figure 3 As shown, the predetermined covering objects include: the isolation trench 18, the exposed gate dielectric layer 16', and the remaining polysilicon layer 17'. That is, the second dielectric layer 19 covers the surface of the isolation trench 18, the exposed gate dielectric layer 16', and the remaining polysilicon layer 17'. The thickness of the second dielectric layer 19 can be 0.5μm-2.5μm. The second dielectric layer 19 can be made of a material such as silicon dioxide and can be formed by deposition, thermal oxidation, or other methods, which are not limited in this disclosure. Figure 3 The terminal protection structure of the silicon carbide device shown includes an isolation trench 18 and the second dielectric layer 19 .

[0062] Implementation method 2:

[0063] like Figure 4 As shown, after step S302, step S303 is performed: first, the substrate 10 is etched to form an isolation trench 18 according to the preset trench position and size. Then, a gate dielectric layer 16 and a polysilicon layer 17 are sequentially formed above the substrate 10 and on the surface of the isolation trench 18. Then, the polysilicon layer 17 is etched according to the preset gate region shape to form a gate region 17'.

[0064] In this embodiment, the surface of the substrate 10 and the surface of the isolation trench 18 can be treated by high temperature thermal oxidation or the like, so that the surface of the substrate 10 and the isolation trench 18 are oxidized to form the following Figure 4 The gate dielectric layer 16 is made of silicon dioxide. A polysilicon layer 17 is then formed on the gate dielectric layer 16.

[0065] Among them, the polysilicon layer 17 and the substrate 10 can also be etched by photolithography and etching processes. For example, a photoresist can be first coated on the substrate 10, and then the photoresist is exposed and developed according to the shape and size of the preset groove area. The substrate 10 is then etched by a corresponding etching process to form the isolation groove 18. After the gate dielectric layer 16 and the polysilicon layer 17 are prepared, a photoresist is coated on the polysilicon layer 17, and then the photoresist is exposed and developed according to the shape and size of the preset gate area. Thereafter, the polysilicon layer 17 is etched by a corresponding etching process to form a gate area 17' above the target area. It is understandable that those skilled in the art can set the implementation method of etching the polysilicon layer 17 and the substrate 10 according to actual needs, and the present disclosure does not limit this.

[0066] like Figure 4As shown, after step S303, step S304 is performed: forming a continuous second dielectric layer 19 above the preset covering object to complete the manufacturing of the silicon carbide device. Figure 4 As shown, the predetermined covering objects include: the isolation trench 18, the exposed gate dielectric layer 16, and the remaining polysilicon layer 17'. That is, the second dielectric layer 19 covers the exposed gate dielectric layer 16 and the remaining polysilicon layer 17'. The thickness of the second dielectric layer 19 can be 0.5 μm to 2.5 μm. The second dielectric layer 19 can be made of a material such as silicon dioxide and can be formed by deposition, thermal oxidation, or other methods, which are not limited in this disclosure. Figure 4 The terminal protection structure of the silicon carbide device shown includes an isolation trench 18 , the second dielectric layer 19 and a gate dielectric layer 16 .

[0067] Implementation method three:

[0068] like Figure 5 As shown, after step S302, step S303 is performed: first, an intermediate dielectric layer 30 is formed on the substrate 10. Then, based on the shape and size of the gate dielectric layer to be covered on the substrate 10, the intermediate dielectric layer 30 is etched to obtain an etched intermediate dielectric layer 31. After that, the surface of the substrate 10 can be treated by a method such as high-temperature thermal oxidation, so that the surface layer of the substrate 10 is oxidized to form a Figure 6 The gate dielectric layer 16 is made of silicon dioxide. Figure 5 The oxide layer 311 is shown. A polysilicon layer 17 is then formed above the gate dielectric layer 16 and the etched intermediate dielectric layer 31. The polysilicon layer 17 is then etched according to a predetermined gate region shape to form a gate region 17' above the target region. Then, isolation trenches 18 are formed by etching the etched intermediate dielectric layer 31 and the substrate 10 according to predetermined trench positions and dimensions, leaving a portion of the etched intermediate dielectric layer 31 above the substrate 10.

[0069] The thickness of the intermediate dielectric layer 30 is greater than that of the gate dielectric layer 16 and may be 0.2 μm to 2 μm. For example, the thickness of the intermediate dielectric layer 30 may be 0.4 μm.

[0070] The polysilicon layer 17, substrate 10, and intermediate dielectric layer 30 can also be etched using photolithography and etching processes. For example, after forming the intermediate dielectric layer 30, photoresist can be applied to the intermediate dielectric layer 30. The photoresist is then exposed and developed based on the shape and size of the gate dielectric layer to be covered above the substrate 10. The intermediate dielectric layer 30 is then etched using a corresponding etching process to obtain an etched intermediate dielectric layer 31. After the gate dielectric layer 16 and polysilicon layer 17 are formed, photoresist is applied to the polysilicon layer 17. The photoresist is then exposed and developed based on the shape and size of the predetermined gate region. The polysilicon layer 17 is then etched using a corresponding etching process to form the gate region 17'. Subsequently, photoresist can be applied to the etched intermediate dielectric layer 31, the exposed gate dielectric layer 15, and the gate region 17'. The photoresist is then exposed and developed based on the shape and size of the predetermined trench region. Afterwards, the etched intermediate dielectric layer 31 and the substrate 10 are etched through a corresponding etching process to form isolation trenches 18, and finally the photoresist is removed. It is understood that those skilled in the art can set the implementation method of etching the polysilicon layer 17, the substrate 10, and the intermediate dielectric layer 30 according to actual needs, and this disclosure does not limit this.

[0071] like Figure 5 As shown, after step S303, step S304 is performed: a continuous second dielectric layer 19 is formed above the predetermined covering object, completing the fabrication of the silicon carbide device. The thickness of the second dielectric layer 19 can range from 0.5 μm to 2.5 μm. The second dielectric layer 19 can be made of a material such as silicon dioxide and can be formed by deposition, thermal oxidation, or other methods, which are not limited in this disclosure.

[0072] like Figure 5 As shown, since there is still a remaining post-etching intermediate dielectric layer 31 above the substrate 10, the predetermined covering objects include: the isolation trench 18, the exposed gate dielectric layer 16, the remaining polysilicon layer 17', and the remaining post-etching intermediate dielectric layer 31. That is, the second dielectric layer 19 covers the exposed gate dielectric layer 16, the remaining polysilicon layer 17', the remaining post-etching intermediate dielectric layer 31, and the surface of the isolation trench 18. The terminal protection structure of the silicon carbide device then includes the isolation trench 18, the second dielectric layer 19, and the remaining post-etching intermediate dielectric layer 31.

[0073] Figure 6 A schematic diagram of a partial structure of a silicon carbide device with a terminal protection structure according to an embodiment of the present disclosure is shown. In a possible implementation, as Figure 6As shown, the substrate 10 may include a silicon carbide layer 101 and an epitaxial layer 102. The depth h1 of the isolation trench 18 is greater than or equal to 0.5 times the thickness H1 of the epitaxial layer 102. For example, if the epitaxial layer thickness of a 1200V SiC MOS is 11 μm, the depth of the isolation trench may be greater than or equal to 5.5 μm. In some embodiments, the depth h1 of the isolation trench 18 may be close to the thickness H1 of the epitaxial layer 102.

[0074] In this embodiment, the isolation trench 18 may be formed by etching a region of the substrate 10 where the target region does not exist and a partial region where the body region 13 exists. Figure 6 As shown, a portion 131 of the body region 13 is etched away to form the isolation trench 18. In some embodiments, the isolation trench 18 may be formed by etching a region of the substrate 10 where no target region exists, which is not limited in the present disclosure.

[0075] In one possible implementation, Figure 3-Figure 5 As shown in FIG, the characteristic length L of the terminal protection structure provided by the present disclosure can be 15 μm-50 μm, which is significantly reduced compared to the terminal protection structure in the related art. For example, if the silicon carbide device is a 1200V silicon carbide device, the characteristic length of the terminal protection structure in the related art is about 100 microns, while the characteristic length L of the terminal protection structure provided by the present disclosure can be 15 μm-50 μm. Figure 3-Figure 5 The characteristic length L of the terminal protection structure shown can be 20 microns, which reduces the characteristic length of the terminal protection structure by several times.

[0076] Figure 7 、 Figure 8 The potential distribution diagram and breakdown voltage curve diagram of a silicon carbide device with a terminal protection structure according to an embodiment of the present disclosure are respectively shown. Since the isolation trench 18 is etched in this embodiment and then filled with the second dielectric layer (or the second dielectric layer and the third dielectric layer), the isolation trench 18 is located at the edge of the PN junction to be protected, so that the PN junction is close to an ideal parallel plane junction, thereby effectively improving the breakdown voltage of the PN junction (refer to Figure 7 、 Figure 8 The silicon carbide device with the terminal protection structure can effectively reduce the length of the terminal protection structure, thereby reducing the area of ​​the entire chip and reducing the chip cost.

[0077] It should be noted that although the above embodiment is used as an example to introduce the method for manufacturing a silicon carbide device with a terminal protection structure, those skilled in the art will understand that the present disclosure should not be limited to this embodiment. In fact, users can flexibly set the various parts of the terminal protection structure according to their personal preferences and / or actual application scenarios, as long as they comply with the technical solutions of the present disclosure.

[0078] While various embodiments of the present disclosure have been described above, the foregoing description is intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for manufacturing a silicon carbide device with a terminal protection structure, characterized in that: include: Generating a first dielectric layer on a substrate, wherein the material of the substrate includes silicon carbide; forming a target region of the silicon carbide device in the substrate and removing the first dielectric layer, the target region including a JFET region, a body region, an N-type source doped region, and a P-type doped region; Generating a gate region above the target region, and etching the substrate to form an isolation trench, wherein the substrate comprises a silicon carbide layer and an epitaxial layer, and the depth of the isolation trench is less than 0.5 times the thickness of the epitaxial layer; forming a continuous second dielectric layer on a predetermined covering object to complete the manufacture of the silicon carbide device, wherein the predetermined covering object at least includes the isolation trench, and the thickness of the second dielectric layer is 0.5 μm-2.5 μm; The terminal protection structure of the silicon carbide device includes the isolation trench and the second dielectric layer. The characteristic length of the terminal protection structure is 15 μm-20 μm. The position of the isolation trench is different from that of the JFET region, the N-type source doped region, and the P-type doped region, and is located outside the target region. The step of generating a gate region above the target region and etching the substrate to form an isolation trench comprises: forming an intermediate dielectric layer above the substrate; Based on the shape and size of the gate dielectric layer to be covered on the substrate, etching the intermediate dielectric layer to obtain an etched intermediate dielectric layer; Thermally oxidizing the surfaces of the substrate and the etched intermediate dielectric layer, so that the surface of the substrate is oxidized to form a gate dielectric layer, the surface of the etched intermediate dielectric layer is oxidized to form an oxide layer, and a polysilicon layer is formed above the gate dielectric layer and the etched intermediate dielectric layer; Etching the polysilicon layer to generate a gate region above the target region; Sequentially etching the etched intermediate dielectric layer and the substrate to form isolation trenches; If the etched intermediate dielectric layer remains above the substrate, the preset covering object further includes: the exposed gate dielectric layer, the remaining polysilicon layer, and the remaining etched intermediate dielectric layer.

2. The method according to claim 1, characterized in that The thickness of the first dielectric layer is and / or The thickness of the gate dielectric layer is and / or The thickness of the polysilicon layer is 0.2 μm-1 μm.

3. The method according to claim 1, characterized in that The thickness of the intermediate dielectric layer is 0.2 μm-1 μm.

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