Array substrate, manufacturing method thereof and display panel

Abstract

The application discloses an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a first active layer, a first source-drain layer and a first blocking member. The first active layer comprises a photosensitive part and a first active part connected with each other. The first active part is located on at least one side of the photosensitive part. One end of the first blocking member extends to the first source-drain layer. The opposite end of the first blocking member extends to at least the first active part. The photosensitive part is arranged in the area surrounded by the first blocking member. The non-target light, such as the reflected light or the side incident light, is blocked from entering the photosensitive part, the influence of the non-target light on the photosensitive part is reduced, and the measurement accuracy of the photosensitive diode to the target light is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a manufacturing method and a display panel. BACKGROUND

[0002] With the development of display panels, in-panel integration technology has become one of the important development directions of display panels. For example, in-panel ambient light technology, optical fingerprint technology, temperature sensor, etc. convert light, heat and other signals into electrical signals that can be read to obtain corresponding light signals or heat signals.

[0003] In the existing display panel integrating light control sensors, the light control sensors not only receive target light, but also receive non-target light reflected in the plane or incident from the side, which affects the measurement accuracy of the light control sensors. SUMMARY

[0004] The present application provides an array substrate, a manufacturing method and a display panel to solve the technical problem of low measurement accuracy of the existing light control sensors.

[0005] To solve the above-mentioned solutions, the technical solutions provided by the present application are as follows:

[0006] The present application provides an array substrate, which comprises:

[0007] A first active layer comprising a light sensing part and a first active part located on at least one side of the light sensing part, the light sensing part being connected to the first active part;

[0008] A first source-drain layer disposed on the first active layer; and

[0009] A first blocking member, one end of the first blocking member extending to the first source-drain layer, and the opposite end of the first blocking member extending to at least the first active part;

[0010] In the top view direction of the array substrate, the light sensing part is located within the area surrounded by the first blocking member.

[0011] In the array substrate of the present application, the array substrate further comprises:

[0012] A plurality of insulating layers disposed between the first active part and the first source-drain layer;

[0013] The light sensing part is disposed on the first active part, and the light sensing part is embedded in the plurality of insulating layers.

[0014] In the array substrate of the present application, in the plan view direction of the array substrate, the orthographic projection of the photosensitive portion on the first active portion is located within the first active portion, and the distance between any boundary of the orthographic projection of the photosensitive portion on the first active portion and the adjacent boundary in the first active portion is greater than 0.

[0015] In the array substrate of the present application, the first blocking member further comprises an overlapping segment, which is arranged in overlap with the first active portion in the plan view direction of the array substrate.

[0016] The first source-drain layer further comprises a first electrode, which is electrically connected with the first active portion through the overlapping segment.

[0017] In the array substrate of the present application, in the plan view direction of the array substrate, the first active portion and the photosensitive portion are located within the region enclosed by the first blocking member.

[0018] In the array substrate of the present application, the array substrate further comprises:

[0019] a first common electrode layer arranged on the first source-drain layer, the first common electrode layer comprising a plurality of first common electrodes, the first common electrodes being electrically connected with the first electrodes in the first source-drain layer;

[0020] a second common electrode layer arranged on the first common electrode layer, the second common electrode layer comprising a plurality of second common electrodes, the second common electrodes being electrically connected with the photosensitive portion;

[0021] In the plan view direction of the array substrate, the first common electrodes and the second common electrodes have an overlapping portion.

[0022] In the array substrate of the present application, the first active layer comprises the photosensitive portion, the first active portion and a second active portion arranged in the same layer, the first active portion and the second active portion being located on two sides of the photosensitive portion,

[0023] The material of the first active portion comprises an N-type semiconductor, and the material of the second active portion comprises a P-type semiconductor.

[0024] In the array substrate of the present application, the first source-drain layer comprises a first electrode and a second electrode arranged separately, the first electrode being electrically connected with the first active portion, and the second electrode being electrically connected with the second active portion.

[0025] The array substrate further comprises:

[0026] A first common electrode layer is disposed on the first source-drain electrode layer, and includes a plurality of first common electrodes, which are electrically connected with the first electrodes;

[0027] A second common electrode layer is disposed on the first common electrode layer, and includes a plurality of second common electrodes, which are electrically connected with the second electrodes.

[0028] The application further provides a manufacturing method of the array substrate, which comprises the following steps:

[0029] A substrate is provided;

[0030] A light-shielding layer and a buffer layer are sequentially formed on the substrate;

[0031] A first active layer is formed on the buffer layer, and includes a photosensitive part and a first active part located at least one side of the photosensitive part, and the photosensitive part is connected with the first active part;

[0032] A first blocking member and a first source-drain electrode layer are formed on the first active part, the first blocking member extends from the first source-drain electrode layer to the first active part in the first active layer, and in the top view direction of the array substrate, the photosensitive part is located in the area surrounded by the first blocking member.

[0033] The application further provides a display panel, which comprises the array substrate and a color resistance layer disposed on the array substrate, and the color resistance layer includes a plurality of second blocking members composed of black light-shielding materials, and one second blocking member corresponds to one first blocking member.

[0034] In the top view direction of the display panel, the second blocking member is located in the area surrounded by the first blocking member.

[0035] Beneficial effects: The application discloses an array substrate and a manufacturing method thereof, and a display panel. The array substrate comprises a first active layer, a first source-drain electrode layer and a first blocking member. The first active layer comprises a photosensitive part and a first active part connected with each other, and the first active part is located at least one side of the photosensitive part. One end of the first blocking member extends to the first source-drain electrode layer, and the opposite end of the first blocking member extends to at least the first active part. According to the application, the photosensitive part is arranged in the area surrounded by the first blocking member, so that the non-target light rays, such as reflected light rays or side incident light rays, are blocked from entering the photosensitive part, the influence of the non-target light rays on the photosensitive part is reduced, and the measurement accuracy of the photosensitive diode to the target light rays is improved. BRIEF DESCRIPTION OF DRAWINGS

[0036] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0037] Figure 1 This is a first cross-sectional view of the array substrate of this application;

[0038] Figure 2 This is a second cross-sectional view of the array substrate of this application;

[0039] Figure 3 This is a third cross-sectional view of the array substrate of this application;

[0040] Figure 4 for Figure 2 A first top view of the film layer of the middle array substrate;

[0041] Figure 5 for Figure 2 A second top view of the film layer in the middle array substrate;

[0042] Figure 6 This is the fourth cross-sectional view of the array substrate of this application;

[0043] Figure 7 for Figure 6 Top view of a portion of the film layer on the central array substrate;

[0044] Figure 8 This is a step diagram illustrating the fabrication process of the array substrate in this application;

[0045] Figures 9A-9J This is a process diagram illustrating the fabrication method of the array substrate in this application;

[0046] Figure 10 This is a cross-sectional view of the display panel of this application. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0048] Please see Figures 1-8 This application provides an array substrate 100, which may include a first active layer 401, a first source-drain layer 501 and a first blocking member 300, wherein the first source-drain layer 501 is disposed on the first active layer 401.

[0049] In the embodiment, the first active layer 401 comprises a light sensing part 180 and a first active part 411 located at least one side of the light sensing part 180, and the light sensing part 180 is connected with the first active part 411.

[0050] In the embodiment, one end of the first blocking member 300 extends to the first source-drain layer 501, and the other end of the first blocking member 300 extends to at least the first active part 411.

[0051] In the embodiment, in the plan view direction of the array substrate 100, the light sensing part 180 is located in the area surrounded by the first blocking member 300.

[0052] The application sets the light sensing part 180 in the area surrounded by the first blocking member 300, blocks the non-target light such as reflected in-plane or side incident light from entering the light sensing part 180, reduces the influence of the non-target light on the light sensing part 180, and improves the measurement accuracy of the light sensing diode T1 on the target light.

[0053] It should be noted that the array substrate 100 can comprise a light sensing diode T1 and a switching transistor T2 connected with the light sensing diode T1, and the light sensing diode T1 and the switching transistor T2 are both arranged in the thin film transistor layer of the array substrate 100, and the first active part 411 and the light sensing part 180 are part of the structure of the light sensing diode T1.

[0054] The technical solutions of the application will be described in combination with specific embodiments.

[0055] Please refer to Figures 1-3 , which is a cross-sectional view of the array substrate 100 of the application. The array substrate 100 can comprise a substrate 110 and a thin film transistor layer located on the substrate 110.

[0056] In the embodiment, the material of the substrate 110 can be glass, quartz or polyimide, etc. The thin film transistor layer can comprise a plurality of thin film transistors.

[0057] In the embodiment, the thin film transistor can be of etching blocking type, back channel etching type, etc., and is not specifically limited.

[0058] In the array substrate 100 of the application, please refer to Figure 2 , the thin film transistor layer can comprise:

[0059] A light shielding layer 120 is disposed on the substrate 110, and is configured to shield external light from entering the thin film transistor from the bottom. The light shielding layer 120 can be made of a black light shielding material, such as a black light shielding metal or a black organic material.

[0060] A buffer layer 130 is disposed on the light shielding layer 120, and is configured to isolate the light shielding layer 120 and an upper metal material. The buffer layer 130 can be made of a compound containing nitrogen, silicon and oxygen, such as a single-layer silicon oxide film or a silicon oxide-silicon nitride stacked structure.

[0061] An active pattern layer 140 is disposed on the buffer layer 130. The active material layer can be made of IGZO (indium gallium zinc oxide), a-Si (amorphous silicon) or LTPS (low temperature polysilicon). In this embodiment, the active material layer is made of a-Si.

[0062] In this embodiment, the active pattern layer 140 includes a first active layer 401 configured as the photodiode T1 and a second active layer 402 configured as the switching transistor T2. The first active layer 401 includes a first active portion 411, the second active layer 402 includes a first active portion 411 and a third active portion 413, and a channel portion 414 between the first active portion 411 and the third active portion 413. The photodiode T1 and the switching transistor T2 share the first active portion 411. The first active portion 411 and the third active portion 413 can be N-type semiconductors doped with phosphorus ions.

[0063] A gate insulating layer 150 is disposed on the active pattern layer 140. The gate insulating layer 150 covers the active pattern layer 140. The gate insulating layer 150 is uniformly laid to separate the active pattern layer 140 and a conductive layer on the gate insulating layer 150. The gate insulating layer 150 can be made of silicon oxide.

[0064] A first metal layer 160 is disposed on the gate insulating layer 150. The first metal layer 160 can include a plurality of gate lines and a gate electrode 161 configured as the switching transistor T2. The first metal layer 160 can be made of copper, molybdenum or molybdenum-titanium alloy.

[0065] A first interlayer insulating layer 170 is disposed on the first metal layer 160, and is formed as a whole layer. The first interlayer insulating layer 170 includes a first via hole 171 that penetrates the first interlayer insulating layer 170 and the gate insulating layer 150, and partially exposes the first active part 411. The first interlayer insulating layer 170 can be made of inorganic material containing silicon, oxygen and nitrogen, or organic material with flatness.

[0066] A light-sensing part 180 is disposed on the first interlayer insulating layer 170, and fills the first via hole 171. The light-sensing part 180 is connected to the first active part 411. The light-sensing part 180 can be made of the same material as the channel part 414.

[0067] A second interlayer insulating layer 190 is disposed on the light-sensing part 180, and is formed as a whole layer. The second interlayer insulating layer 190 can be made of the same material as the first interlayer insulating layer 170.

[0068] A second metal layer 200 is disposed on the second interlayer insulating layer. The second metal layer 200 can include a plurality of data lines, a first source-drain layer 501 constituting the light-sensing diode T1, and a second source-drain layer 502 constituting the switching transistor T2.

[0069] In this embodiment, the first source-drain layer 501 includes a first electrode 511, and the second source-drain layer 502 includes a first electrode 511 and a third electrode 513 disposed separately. The light-sensing diode T1 and the switching transistor T2 share the first electrode 511. The first electrode 511 and the third electrode 513 extend from the second metal layer 200 to the active pattern layer 140, i.e., the first electrode 511 and the third electrode 513 are connected to the second active layer 402 through a corresponding second via hole 172 that penetrates the second interlayer insulating layer, the first interlayer insulating layer 170 and the gate insulating layer 150. The first electrode 511 is connected to the first active part 411, and the third electrode 513 is connected to the third active part 413.

[0070] In this embodiment, the second metal layer 200 can be made of copper or molybdenum-titanium alloy, or copper or titanium.

[0071] A flat layer 210 is disposed on the second metal layer 200, the flat layer 210 is entirely laid, the flat layer 210 includes a plurality of third vias 173, the third vias 173 expose part of the first active part 411; the material of the flat layer 210 can be inorganic matter combined with nitrogen and oxygen and silicon or organic material with flatness.

[0072] A first common electrode layer 220 is disposed on the flat layer 210, the first common electrode layer 220 includes a plurality of first common electrodes 221, the first common electrodes 221 fill the third vias 173, and the first common electrodes 221 are electrically connected with the first active part 411 through the third vias 173; the material of the first common electrode layer 220 can be transparent conductive material such as indium tin oxide.

[0073] A passivation layer 230 is disposed on the first common electrode layer 220, the passivation layer 230 is entirely laid, the material of the passivation layer 230 can be inorganic matter combined with nitrogen and oxygen and silicon or organic material with flatness.

[0074] A second common electrode layer 240 is disposed on the passivation layer 230, the second common electrode layer 240 includes a plurality of second common electrodes 241, the second common electrodes 241 are connected through fourth vias 174 and the light sensing part 180, the fourth vias 174 pass through the passivation layer 230, the flat layer 210 and the second interlayer insulating layer; the material of the second common electrode layer 240 can be transparent conductive material such as indium tin oxide.

[0075] In the embodiment, in the plan view direction of the array substrate 100, the first common electrodes 221 and the second common electrodes 241 have overlapping parts, and the first common electrodes 221 and the second common electrodes 241 form the storage capacitor of the light sensing diode T1.

[0076] In the structure of Figure 1 In the structure of

[0077] In the embodiment, the light sensing part 180 can be disposed on the first active part 411, and the light sensing part 180 is embedded in the multi-layer insulating layer; for example In the structure of Figure 1 In the structure of Figure 2In the structure, the photosensitive part 180 is embedded in the gate insulating layer 150 and the first interlayer insulating layer 170; for example Figure 3 In the structure, the photosensitive part 180 is embedded in the gate insulating layer 150, the first interlayer insulating layer 170, and a portion of the second interlayer insulating layer.

[0078] exist Figures 1-3 In the structure, the thickness of the photosensitive part 180 gradually increases in the direction from the substrate 110 to the active pattern layer 140. Since the material of the photosensitive part 180 is amorphous silicon, the greater the thickness of the photosensitive part 180 when absorbing incident light, the higher the upper limit of the total amount of light that the photosensitive part 180 can absorb. Therefore, when the size allows, the thickness of the photosensitive part 180 is increased as much as possible to avoid errors in the measurement results of the photodiode T1 due to the incident light reaching the absorption limit of the photosensitive part 180.

[0079] by Figure 2 For example, please refer to the structure. Figure 4 and Figure 5 , Figure 4 for Figure 2 The first top view of a portion of the film layer on the central array substrate 100. Figure 5 for Figure 2 A second top view of the film layer of the middle array substrate 100.

[0080] exist Figure 4 In the structure, in the top view direction of the array substrate 100, the orthographic projection of the photosensitive part 180 on the first active part 411 is located within the first active part 411, and the distance between any boundary of the orthographic projection of the photosensitive part 180 on the first active part 411 and the adjacent boundary in the first active part 411 is greater than 0.

[0081] exist Figure 5 In the structure, in the top view direction of the array substrate 100, the photosensitive portion 180 overlaps with the first active portion 411, and the photosensitive portion 180 extends beyond the boundary of the first active portion 411. Although the top view of the photosensitive portion 180 extends beyond the boundary of the first active portion 411, since the photosensitive portion 180 and the first active portion 411 are connected through the first via 171, the contact surface between the photosensitive portion 180 and the first active portion 411 is the area of ​​the first via 171, that is, the first active portion 411 is essentially suspended above the first active portion 411.

[0082] and Figure 4 Compared to the structure, Figure 5 The photosensitive part 180 has a larger area, and the total amount of light received by the photosensitive part 180 per unit time is larger, resulting in better photosensitivity of the photodiode T1 than...Figure 4 The photodiode T1 is shown.

[0083] Referring to Figure 2 and Figure 4 The first electrode 511 can be connected with the first blocking member 300, and the first electrode 511 and the first blocking member 300 constitute a closed-loop blocking member.

[0084] In the embodiment, the first blocking member 300 further comprises an overlapping section 310, which is arranged to overlap the first active section 411 in the plan view direction of the array substrate 100, and the first electrode 511 is electrically connected with the first active section 411 through the overlapping section 310.

[0085] In the embodiment, the first blocking member 300 is only used for light blocking, and since the first blocking member 300 is made of a metal material, connecting the first blocking member 300 with the first electrode 511 can form a closed-loop blocking member to block non-target light rays, such as reflected or side incident light rays, from entering the light sensing section 180 in the photodiode T1, thereby improving the measurement accuracy of the photodiode T1 on the target light rays, and also avoiding the risk of short circuit of the first electrode 511 as a conductive metal; secondly, the first electrode 511 is the boundary of the closed-loop blocking member, thereby reducing the area occupied by the closed-loop blocking member.

[0086] In the structure shown in Figure 2 , the first electrode 511 extends from the first source-drain layer 501 to the first active section 411 and is connected with the first active section 411, and the first blocking member 300 can extend from the first source-drain layer 501 to the first active layer 401 and penetrate the gate insulating layer 150, i.e., the first blocking member 300 is in contact with the buffer layer 130.

[0087] Referring to Figure 5 , the first blocking member 300 and the photodiode T1 do not overlap, i.e., the first blocking member 300 and the first electrode 511 are arranged separately, and the photodiode T1 is located inside the first blocking member 300.

[0088] In the embodiment, the first active section 411 and the light sensing section 180 can be located in the area enclosed by the first blocking member 300 in the plan view direction of the array substrate 100.

[0089] In the structure shown in Figure 5On the basis of the structure shown, the first blocking member 300 can also extend to the buffer layer 130 and be connected with the light shielding layer 120, i.e. the first blocking member 300 and the light shielding layer 120 form a groove with an opening, which faces the first common electrode layer 220 and the second common electrode layer 240.

[0090] The present application uses the material constituting the source-drain layer to form the first blocking member 300 in the periphery of the photodiode T1, encloses the light sensing part 180 in the photodiode T1 inside the first blocking member 300, blocks the non-target light rays, such as the in-plane reflected light or the side incident light, from entering the light sensing part 180 in the photodiode T1, and improves the measurement accuracy of the photodiode T1 to the target light rays.

[0091] Please refer to Figure 6 and Figure 7 , Figure 6 is a fourth cross-sectional view of the array substrate 100 of the present application, Figure 7 is Figure 6 a top view of the partial film layers of the array substrate 100.

[0092] Compared with Figures 1-3 , Figure 6 the difference lies in:

[0093] In the array substrate 100 of the present application, the first active layer 401 of the photodiode T1 can include the light sensing part 180 and the first active part 411 and the second active part 412 located on both sides of the light sensing part 180, the first active part 411 and the second active part 412 are located on both sides of the light sensing part 180, the first active part 411 is arranged close to the switching transistor T2, and the second active part 412 is arranged away from the switching transistor T2.

[0094] In the present embodiment, the material of the first active part 411 includes an N-type semiconductor, and the material of the second active part 412 includes a P-type semiconductor. That is Figure 6The light-sensing part 180 in the array substrate 100 can be a channel of the light-sensing part 180. Incident light is irradiated on the light-sensing part 180 and is converted into a photoelectric current. The first common electrode 221 and the second common electrode 241 are charged, and the generated electrical signal is stored in a storage capacitor. After the light irradiation ends, the switch transistor T2 is opened, the storage capacitor is discharged, and the electrical signal stored in the storage capacitor is transmitted to the reading module through the switch transistor T2 to read the corresponding electrical signal. Alternatively, the incident light is irradiated on the light-sensing part 180 and is converted into a photoelectric current directly entering the reading module through the switch transistor T2. At the same time, the first common electrode 221 and the second common electrode 241 continue to be charged. After the reading module reads the photoelectric current of the light-sensing diode T1, the storage capacitor is discharged to continue reading by the reading module, thereby improving the accuracy of reading by the reading module.

[0095] In the array substrate 100 of the present application, referring to Figure 6 , the first source-drain layer 501 can include a first electrode 511 and a second electrode 512. The first electrode 511 and the second electrode 512 are separately arranged. The first electrode 511 is electrically connected to the first active part 411, and the second electrode 512 is electrically connected to the second active part 412.

[0096] Referring to Figure 6 , the second common electrode layer 240 includes a plurality of second common electrodes 241. The second common electrodes 241 are electrically connected to the second electrode 512 through fifth vias 175. The fifth vias 175 penetrate the passivation layer 230 and the planarization layer 210.

[0097] Referring to Figure 7 , the first blocking member 300 and the light-sensing diode T1 are not overlapped, that is, the first blocking member 300 and the first electrode 511 are separately arranged. The light-sensing diode T1 is located inside the first blocking member 300.

[0098] Referring to Figure 8 , the present application further provides a manufacturing method of an array substrate 100. The array substrate 100 includes a light-sensing diode T1 and a switch transistor T2 connected to each other. The manufacturing method of the array substrate 100 includes the following steps.

[0099] S10, providing a substrate 110;

[0100] Referring to Figure 9A , the material of the substrate 110 can be glass, quartz, or polyimide.

[0101] S20, sequentially forming a light-blocking layer 120 and a buffer layer 130 on the substrate 110;

[0102] Referring to Figure 9AThe light shielding layer 120 is arranged on the substrate 110, and is used to shield external light from entering the thin film transistor from the bottom. The material of the light shielding layer 120 can be black light shielding material, such as black light shielding metal or black organic material, etc.

[0103] Referring to Figure 9A The buffer layer 130 is arranged on the light shielding layer 120, and is used to isolate the light shielding layer 120 and the upper metal material. The material of the buffer layer 130 can include a compound composed of nitrogen element, silicon element and oxygen element, such as a single-layer silicon oxide film layer or a silicon oxide-silicon nitride stacked structure.

[0104] S30, forming a first active layer 401 including a first active part 411 on the buffer layer 130. The first active layer 401 includes a light sensing part 180 and the first active part 411 located at least one side of the light sensing part 180, and the light sensing part 180 is connected with the first active part 411.

[0105] In this embodiment, referring to Figure 9B The step S30 can include:

[0106] forming an amorphous silicon layer on the buffer layer 130;

[0107] forming the first active part 411 constituting the first active layer 401, the first active part 411 and the third active part 413 constituting the second active layer 402, and the channel part 414 located between the first active part 411 and the third active part 413 through a patterning process. The light sensing diode T1 and the switching transistor T2 share the first active part 411.

[0108] forming a gate insulating layer 150 on the first active layer 401;

[0109] Referring to Figure 9C The gate insulating layer 150 covers the first active layer 401 and the second active layer 402. The gate insulating layer 150 is laid in an integral layer, so that the conductive layers on the first active layer 401, the second active layer 402 and the gate insulating layer 150 are arranged separately. The material of the gate insulating layer 150 can be silicon oxide, etc.

[0110] forming a first metal layer 160 on the gate insulating layer 150;

[0111] Referring to Figure 9C The first metal layer 160 can include a plurality of gate lines and a gate constituting the switching transistor T2. The material of the first metal layer 160 can be copper, molybdenum or molybdenum-titanium alloy, etc.

[0112] Forming a first interlayer insulating layer 170 on the first metal layer 160;

[0113] Referring to Figure 9C , the first interlayer insulating layer 170 is laid in a whole layer, and the first interlayer insulating layer 170 includes a first via hole 171 which penetrates the first interlayer insulating layer 170 and the gate insulating layer 150 and partially exposes the first active part 411; the material of the first interlayer insulating layer 170 can be inorganic material combined with silicon and oxygen or organic material with flatness;

[0114] Forming a photosensitive part 180 on the first interlayer insulating layer 170;

[0115] Referring to Figure 9D , the photosensitive part 180 fills the first via hole 171, and the photosensitive part 180 is connected with the first active part 411; the material of the photosensitive part 180 can be the same as that of the channel part 414.

[0116] Forming a second interlayer insulating layer 190 on the photosensitive part 180;

[0117] Referring to Figure 9D , the second interlayer insulating layer 190 is laid in a whole layer, and the material of the second interlayer insulating layer 190 can be the same as that of the first interlayer insulating layer 170.

[0118] S40, forming a first blocking member 300 and a first source-drain layer 501 on the first active part 411, the first blocking member 300 extends from the first source-drain layer 501 to the first active part 411 in the first active layer 401, and in the top view direction of the array substrate 100, the photosensitive part 180 is located in the area surrounded by the first blocking member 300;

[0119] Referring to Figure 9E , step S40 can include:

[0120] Forming a second metal layer 200 on the second interlayer insulating layer 190, and forming the first blocking member 300, a plurality of data lines, the first source-drain layer 501 constituting the photosensitive diode T1 and the second source-drain layer 502 constituting the switching transistor T2 through a patterning process;

[0121] In the embodiment, the first source-drain layer 501 includes a first electrode 511, the second source-drain layer 502 includes the first electrode 511 and a third electrode 513, the first electrode 511 is shared by the photodiode T1 and the switching transistor T2, and the first electrode 511 and the third electrode 513 extend from the second metal layer 200 to the active pattern layer 140, i.e., the first electrode 511 and the third electrode 513 are connected with the second active layer 402 through the corresponding second via hole 172, the second via hole 172 penetrates through the second interlayer insulating layer, the first interlayer insulating layer 170 and the gate insulating layer 150, the first electrode 511 is connected with the first active part 411, and the third electrode 513 is connected with the third active part 413.

[0122] In the embodiment, the material of the second metal layer 200 can be copper or molybdenum-titanium alloy, copper or titanium, etc.

[0123] S50, forming a planar layer 210 on the second metal layer 200;

[0124] Please refer to Figure 9F , the planar layer 210 is arranged on the second metal layer 200, the planar layer 210 is laid in a whole layer, the planar layer 210 includes a plurality of third via holes 173, and the third via holes 173 expose part of the first active part 411; the material of the planar layer 210 can be inorganic matter combined with silicon, oxygen and nitrogen or organic material with flatness.

[0125] S60, forming a first common electrode layer 220 on the planar layer 210;

[0126] Please refer to Figure 9G , the first common electrode layer 220 is arranged on the planar layer 210, the first common electrode layer 220 includes a plurality of first common electrodes 221, the first common electrodes 221 fill the third via holes 173, and the first common electrodes 221 are electrically connected with the first active part 411 through the third via holes 173; the material of the first common electrode layer 220 can be transparent conductive material such as indium tin oxide.

[0127] S70, forming a passivation layer 230 on the first common electrode layer 220;

[0128] Please refer to Figure 9H , the passivation layer 230 is laid in a whole layer, and the material of the passivation layer 230 can be inorganic matter combined with silicon, oxygen and nitrogen or organic material with flatness.

[0129] S80, forming a second common electrode layer 240 on the passivation layer 230;

[0130] Please refer toFigure 9I The second common electrode layer 240 includes a plurality of second common electrodes 241 connected by fourth vias 174 and the photosensitive portion 180, the fourth vias 174 penetrating the passivation layer 230, the planarization layer 210, and the second insulating layer; the material of the second common electrode layer 240 can be transparent conductive material such as indium tin oxide.

[0131] In the embodiment, referring to Figure 9J The step S30 can further include:

[0132] forming an amorphous silicon layer on the buffer layer 130;

[0133] forming the first active portion 411, the second active portion 412, and the photosensitive portion 180 between the first active portion 411 and the second active portion 412 constituting the first active layer 401, and the first active portion 411 and the third active portion 413, and the channel portion 414 between the first active portion 411 and the third active portion 413 constituting the second active layer 402 by the patterning process, the first active portion 411 being shared by the photosensitive diode T1 and the switching transistor T2.

[0134] In the embodiment, the first active portion 411 and the second active portion 412 are separately arranged, and the material of the first active portion 411 includes N-type semiconductor, and the material of the second active portion 412 includes P-type semiconductor. Figure 9J In the embodiment, referring to

[0135] , Figure 10 , Figure 10 is a cross-sectional view of the display panel; the application further provides a display panel 400, which includes an array substrate 100 and a color resistance layer 50 arranged on the array substrate 100, the color resistance layer 50 includes a plurality of second blocking members 600 composed of black light shielding material, and one second blocking member 600 corresponds to one first blocking member 300.

[0136] In the embodiment, in the plan view direction of the display panel 400, the second blocking member 600 is located in the area surrounded by the first blocking member 300.

[0137] In the embodiment, referring to Figure 10 For a liquid crystal display panel, the second blocking member 600 corresponding to the first blocking member 300 is arranged on the color resistance layer 50 on the side of the color filter substrate 500; and for an OLED display panel, the color resistance layer 50 can be arranged on the light-emitting functional layer, and the second blocking member 600 can be integrated on the color resistance layer 50.

[0138] The application further provides a mobile terminal comprising the terminal body and the display panel, and the terminal body and the display panel are combined into one body. The terminal body can be a circuit board or other device bound to the display panel. The mobile terminal can be a mobile phone, a television, a notebook computer or other electronic device.

[0139] The application discloses an array substrate, a manufacturing method and a display panel. The array substrate comprises a first active layer, a first source-drain layer and a first blocking member. The first active layer comprises a photosensitive part and a first active part connected to each other. The first active part is located on at least one side of the photosensitive part. One end of the first blocking member extends to the first source-drain layer. The opposite end of the first blocking member extends to at least the first active part. In the application, the photosensitive part is arranged in the area surrounded by the first blocking member. The non-target light, such as reflected light or side incident light, is blocked from entering the photosensitive part, the influence of the non-target light on the photosensitive part is reduced, and the measurement accuracy of the photosensitive diode to the target light is improved.

[0140] In the above embodiments, the description of each embodiment has its own focus. The parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0141] The array substrate, the manufacturing method and the display panel provided by the embodiments of the application are described in detail above. The principles and implementation manners of the application are described by using specific examples in this paper. The above description of the embodiments is only used to help understand the technical solutions and the core ideas of the application. Those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced equivalently. The modification or replacement does not change the essence of the corresponding technical solutions out of the scope of the technical solutions of the embodiments of the application.

Claims

1. An array substrate, characterized by, The array substrate comprises: a first active layer comprising a photosensitive portion and a first active portion located at least one side of the photosensitive portion, the photosensitive portion being connected with the first active portion; a first source-drain layer disposed on the first active layer; and a first blocking member, one end of the first blocking member extending to the first source-drain layer, and the opposite end of the first blocking member extending to at least the first active portion; wherein, in the plan view direction of the array substrate, the photosensitive portion is located in the area surrounded by the first blocking member; the first source-drain layer further comprises a first electrode, the first electrode being electrically connected with the first active portion; the array substrate further comprises: a first common electrode layer disposed on the first source-drain layer, the first common electrode layer comprising a plurality of first common electrodes, the first common electrodes being electrically connected with the first electrode in the first source-drain layer; a second common electrode layer disposed on the first common electrode layer, the second common electrode layer comprising a plurality of second common electrodes, the second common electrodes being electrically connected with the photosensitive portion; the first common electrodes and the second common electrodes form a storage capacitor. The array substrate further comprises:

2. The array substrate of claim 1, wherein, a multilayer insulating layer disposed between the first active portion and the first source-drain layer; wherein, the photosensitive portion is disposed on the first active portion, and the photosensitive portion is embedded in the multilayer insulating layer. In the plan view direction of the array substrate, the orthographic projection of the photosensitive portion on the first active portion is located in the first active portion, and the distance between any boundary of the orthographic projection of the photosensitive portion on the first active portion and the adjacent boundary in the first active portion is greater than 0.

3. The array substrate of claim 2, wherein, The first blocking member further comprises an overlapping segment, in the plan view direction of the array substrate, the overlapping segment and the first active portion are arranged in an overlapping manner; the first electrode is electrically connected with the first active portion through the overlapping segment.

4. The array substrate of claim 2, wherein, In the plan view direction of the array substrate, the first active portion and the photosensitive portion are located in the area surrounded by the first blocking member.

5. The array substrate of claim 2, wherein, The array substrate further comprises: in the plan view direction of the array substrate, the first common electrodes and the second common electrodes have an overlapping portion.

6. The array substrate according to claim 4 or 5, wherein, The first active layer comprises the photosensitive portion, the first active portion and a second active portion arranged in the same layer, the first active portion and the second active portion being located at two sides of the photosensitive portion, wherein the material of the first active portion comprises an N-type semiconductor, and the material of the second active portion comprises a P-type semiconductor.

7. The array substrate of claim 1, wherein, The first source-drain layer comprises a first electrode and a second electrode arranged separately, the first electrode being electrically connected with the first active portion, and the second electrode being electrically connected with the second active portion; 8. The array substrate of claim 7, wherein, The second common electrode layer comprises a second common electrode, the second common electrode being electrically connected with the second electrode. The method comprises:

9. A manufacturing method of an array substrate, characterized by, providing a substrate; forming a light-shielding layer and a buffer layer on the substrate in sequence; forming a first active layer on the buffer layer, the first active layer comprising a photosensitive portion and a first active portion located at least one side of the photosensitive portion, the photosensitive portion being connected with the first active portion; ​ A first blocking member and a first source-drain layer are formed on the first active part, the first blocking member extending from the first source-drain layer to the first active part in the first active layer, and the photosensitive part is located in an area surrounded by the first blocking member in the plan view direction of the array substrate; The first source-drain layer further comprises a first electrode, and the first electrode is electrically connected with the first active part; The array substrate further comprises: A first common electrode layer is disposed on the first source-drain layer, and the first common electrode layer comprises a plurality of first common electrodes, and the first common electrodes are electrically connected with the first electrodes in the first source-drain layer; A second common electrode layer is disposed on the first common electrode layer, and the second common electrode layer comprises a plurality of second common electrodes, and the second common electrodes are electrically connected with the photosensitive part; The first common electrodes and the second common electrodes form a storage capacitor. The display panel comprises the array substrate according to any one of claims 1 to 8 and a color resistance layer disposed on the array substrate, the color resistance layer comprises a plurality of second blocking members composed of black light-shielding material, and one second blocking member corresponds to one first blocking member; 10. A display panel, characterized by, In the plan view direction of the display panel, the second blocking member is located in the area surrounded by the first blocking member. ​

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