Control device, system and method for a phase-locked loop

Abstract

The application discloses a control device, system and method of a phase-locked loop, and belongs to the technical field of communication. The control device of the phase-locked loop comprises a collector, a memory and a controller connected in sequence. The collector is configured to collect characteristic data at a working frequency locked by the phase-locked loop before the working of the phase-locked loop is interrupted. The memory is configured to store the characteristic data at the working frequency. The controller is configured to read the characteristic data at the working frequency stored in the memory if the phase-locked loop needs to be re-locked at the working frequency after the working of the phase-locked loop is interrupted, and control the phase-locked loop to be re-locked at the working frequency based on the characteristic data at the working frequency. The application collects and stores the characteristic data at the working frequency locked by the phase-locked loop, so that the phase-locked loop can be quickly re-locked at the working frequency based on the characteristic data, thereby realizing fast re-locking of the phase-locked loop.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a control device, system and method for a phase-locked loop. Background Technology

[0002] In the field of communication technology, electronic devices typically use PLLs (Phase Locked Loops) to lock the frequency and phase of clock signals to provide an accurate and stable clock source. In some applications, such as DDR (Double Data Rate) DDR, the PLL is interrupted when a clock source is not needed. It resumes operation only when a clock source is required again, thus saving power.

[0003] Since PLLs need to relock frequency and phase when resuming operation, and the process of PLL frequency locking is time-consuming, it can negatively impact the communication performance of electronic devices. Therefore, it is necessary to provide a control method for the phase-locked loop (PLL) to enable rapid relocking. Summary of the Invention

[0004] This application provides a control device, system, and method for a phase-locked loop (PLL) to enable rapid relocking of the PLL. The technical solution is as follows.

[0005] On the one hand, a phase-locked loop (PLL) control device is provided. The control device includes a data acquisition unit, a memory, and a controller. The input terminal of the data acquisition unit is connected to the PLL, the output terminal of the data acquisition unit is connected to the input terminal of the memory, the output terminal of the memory is connected to the input terminal of the controller, and the output terminal of the controller is connected to the PLL.

[0006] The data acquisition unit is configured to collect characteristic data of the operating frequency locked by the phase-locked loop during the current operation before the phase-locked loop is interrupted.

[0007] The memory is configured to store characteristic data at this operating frequency;

[0008] The controller is configured to, after a phase-locked loop (PLL) operation is interrupted, if the PLL needs to relock to the operating frequency, read the characteristic data at that operating frequency stored in the memory, and control the PLL to relock to the operating frequency based on the characteristic data at that operating frequency.

[0009] In one possible implementation, the controller includes an AD (Analogue Digital) / DA (Digital Analogue) converter and a comparator; the output of the data acquisition unit is connected to the analog input of the AD / DA converter; the digital output of the AD / DA converter is connected to the first input of the comparator, and the output of the memory is connected to the second input of the comparator; the output of the comparator is connected to the digital input of the AD / DA converter; and the analog output of the AD / DA converter is connected to a phase-locked loop (PLL).

[0010] In one possible implementation, the digital output of the AD / DA converter is connected to the input of the memory.

[0011] In one possible implementation, the comparator is integrated into the AD / DA converter; or, the AD / DA converter is integrated into the memory.

[0012] On the other hand, a control system for a phase-locked loop is provided, the control system including a control device for any of the aforementioned phase-locked loops and a phase-locked loop connected to the control device.

[0013] On the other hand, a control method for a phase-locked loop is provided, the method comprising:

[0014] Before the phase-locked loop (PLL) is interrupted, characteristic data of the operating frequency locked by the PLL during this operation is collected and stored.

[0015] After a phase-locked loop (PLL) operation is interrupted, if the PLL needs to relock to the operating frequency, it reads the stored characteristic data for that operating frequency and controls the PLL to relock to the operating frequency based on the characteristic data for that operating frequency.

[0016] In one possible implementation, controlling the phase-locked loop to relock to the operating frequency based on characteristic data at the operating frequency includes: charging the loop filter of the phase-locked loop based on the characteristic data at the operating frequency, so that the phase-locked loop relocks to the operating frequency.

[0017] In one possible implementation, the method further includes: during the charging process of the loop filter of the phase-locked loop based on the characteristic data at the operating frequency, collecting the characteristic data of the phase-locked loop, and stopping the charging of the loop filter when the difference between the collected characteristic data and the characteristic data at the operating frequency is less than a threshold.

[0018] In one possible implementation, the characteristic data at the operating frequency is the tuning voltage value of the phase-locked loop at that operating frequency; charging the loop filter of the phase-locked loop based on the characteristic data at the operating frequency includes: generating an analog current signal based on the tuning voltage value, and charging the loop filter of the phase-locked loop based on the analog current signal.

[0019] In one possible implementation, storing the feature data at the operating frequency includes: storing the feature data at the operating frequency in correspondence with the operating frequency; reading the stored feature data at the operating frequency includes: querying the stored operating frequency, determining the stored feature data at the operating frequency based on the operating frequency, and reading the feature data at the operating frequency.

[0020] In one possible implementation, after acquiring the characteristic data of the operating frequency locked by the phase-locked loop in this operation, the method further includes: converting the characteristic data of the operating frequency into a digital signal form suitable for storage; and controlling the phase-locked loop to relock the operating frequency based on the characteristic data of the operating frequency, including: controlling the phase-locked loop to relock the operating frequency based on the characteristic data of the operating frequency converted from digital signal form to analog signal form.

[0021] In one possible implementation, the characteristic data of the operating frequency locked by the phase-locked loop in this operation is collected, including: if the operating frequency locked by the phase-locked loop in this operation is different from the operating frequency locked in the previous operation, the characteristic data of the operating frequency locked by the phase-locked loop in this operation is collected.

[0022] The beneficial effects of the technical solutions provided in this application include at least the following:

[0023] This application collects and stores characteristic data of the operating frequency locked by the phase-locked loop during the current operation. Therefore, the phase-locked loop can be controlled to quickly relock to the operating frequency based on the characteristic data of the operating frequency, thereby realizing the rapid relocking of the phase-locked loop. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a phase-locked loop provided in an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of another phase-locked loop structure provided in an embodiment of this application;

[0027] Figure 3 This is a schematic diagram of the structure of a phase-locked loop control device provided in an embodiment of this application;

[0028] Figure 4 This is a schematic diagram of the structure of another phase-locked loop control device provided in the embodiments of this application;

[0029] Figure 5 This is a schematic diagram of the structure of another phase-locked loop control device provided in the embodiments of this application;

[0030] Figure 6 This is a schematic diagram of the structure of another phase-locked loop control device provided in the embodiments of this application;

[0031] Figure 7 This is a schematic diagram of the structure of a phase-locked loop control system provided in an embodiment of this application;

[0032] Figure 8 This is a flowchart of a phase-locked loop control method provided in an embodiment of this application;

[0033] Figure 9 This is a flowchart of another phase-locked loop control method provided in the embodiments of this application. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0035] In electronic devices, clock signals are used to synchronize the time between different components, ensuring normal communication. Clock signals are generated by clock generators; however, clock signals generated by clock generators often exhibit jitter, meaning their frequency and phase are not accurate or stable enough to be directly used for time synchronization between components. Therefore, phase-locked loops (PLLs) are needed to lock the frequency and phase of the clock signal, providing an accurate and stable clock source.

[0036] In some applications, the phase-locked loop (PLL) is interrupted when a clock source is not needed. The PLL is then resumed when the clock source is required again to achieve relocking and save power. These applications include, but are not limited to, storage applications, such as DDR memory with low-power modes. When DDR is in low-power mode, the clock source is frequently paused and resumed, which means the PLL needs to be repeatedly interrupted and resumed to achieve relocking.

[0037] In a phase-locked loop (PLL) circuit, the frequency is initially tuned to near the desired frequency through a frequency-locking process. During this process, the output frequency undergoes significant fluctuations until it stabilizes at the desired frequency. Next, the phase is fine-tuned through a phase-locking process, resulting in a smaller fluctuation in the output frequency. Since the frequency-locking and phase-locking processes are quite similar, the following explanation will use the frequency-locking process as an example.

[0038] See Figure 1 , Figure 1 An exemplary phase-locked loop (PLL) is shown. This PLL includes a ring-connected PFD (Phase Frequency Detector), CP (Charge Pump), LF (Loop Filter), VCO (Voltage Controlled Oscillator), and Fdiv (Feedback Divider). Figure 1 The phase-locked loop shown is a CPCPLL architecture.

[0039] During frequency locking, the PFD (Programmable Detector) identifies the phase difference between the reference clock signal (ref_clk) and the feedback clock signal (fb_clk). The PFD converts this phase difference between the frequencies of fb_clk and ref_clk into an error voltage control signal and sends it to the CP (Concurrent Processor). The CP converts this error voltage control signal into an error current, integrates it in the LF (Functional Current Processor), filters out high-frequency noise, and thus adjusts the VCO's control voltage. The VCO generates a clock signal with a specific frequency difference from the frequency to be locked. The Fdiv (Programmable Detector) divides the VCO's output clock signal and sends this feedback clock signal fb_clk to the PFD. The PFD then continues to compare the phase difference between the frequency of fb_clk and the input frequency of ref_clk to send a new error voltage control signal to the CP. This ref_clk frequency is the frequency to be locked. When the frequency of fb_clk lags behind the frequency of ref_clk that needs to be locked, the error voltage control signal is an up signal; when the frequency of the feedback clock signal leads the frequency that needs to be locked, the error voltage control signal is a down signal.

[0040] The above process will be repeated multiple times, that is, the output frequency of the VCO will be updated multiple times, constantly moving closer to the frequency that needs to be locked, until the frequency difference between the frequency of the clock signal generated by the VCO and the frequency that needs to be locked is less than the threshold, thereby completing the frequency locking and obtaining an accurate and stable clock signal.

[0041] For example, such as Figure 2 As shown, Figure 2 Another exemplary phase-locked loop is shown, which includes a ring-connected PD (Phase Detector), LF, VCO, and Fdiv. Compared to Figure 1 The PFD shown Figure 2 The PD shown no longer sends an error voltage control signal to the CP, but instead sends the error voltage control signal directly to the LF. Furthermore, Figure 2 The roles of LF, VCO, and Fdiv in the frequency locking process can be found in [reference needed]. Figure 1 The corresponding explanations will not be repeated here.

[0042] The above explains the process of frequency locking by a phase-locked loop (PLL), which is essentially a tracking process for the frequency to be locked. Afterward, the PLL can also perform a phase locking process, thereby obtaining a clock signal with accurate and stable frequency and phase.

[0043] In applications like DDR, the phase-locked loop (PLL) is interrupted when a clock source is not needed, and then resumed when a clock source is required again to achieve relocking. In these technologies, the PLL needs to relock both frequency and phase each time it resumes operation. As explained above, the frequency changes more significantly during frequency locking compared to phase locking. Therefore, the PLL relocking speed is slow. To address this, it is necessary to control the PLL to achieve rapid relocking, that is, to enable the PLL to quickly relock after an interruption.

[0044] This application provides a control device for a phase-locked loop (PLL). This control device is used to control the PLL so that after an interruption of operation, the PLL can quickly re-lock the required frequency. Next, in conjunction with... Figures 3-7 The structure of the control device is described in detail, and the functions of each component are briefly explained. Further detailed explanations of these functions can be found later in the text. Figure 8 Corresponding method implementation examples.

[0045] See Figure 3The control device 10 for the phase-locked loop includes a data acquisition unit 11, a memory 12, and a controller 13. The input terminal of the data acquisition unit 11 is connected to the phase-locked loop 20, the output terminal of the data acquisition unit 11 is connected to the input terminal of the memory 12, the output terminal of the memory 12 is connected to the input terminal of the controller 13, and the output terminal of the controller 13 is connected to the phase-locked loop 20.

[0046] The data acquisition unit 11 is configured to acquire characteristic data of the operating frequency locked by the phase-locked loop 20 during its current operation before the operation of the phase-locked loop 20 is interrupted. The memory 12 is configured to store the characteristic data at that operating frequency. The controller 13 is configured to, after the operation of the phase-locked loop 20 is interrupted, if the phase-locked loop 20 needs to relock to the operating frequency, read the characteristic data stored in the memory 12 at that operating frequency, and control the phase-locked loop 20 to relock to the operating frequency based on the characteristic data at that operating frequency.

[0047] For example, the characteristic data at the operating frequency is data generated by the phase-locked loop 20 when locking the operating frequency, or the characteristic data at the operating frequency is data generated based on the data generated by the phase-locked loop 20 when locking the operating frequency. This application embodiment does not limit the type of characteristic data at the operating frequency; any data capable of characterizing the operating frequency locked by the phase-locked loop 20 is acceptable, including but not limited to voltage or current data when the phase-locked loop 20 locks the operating frequency. Since the memory 12 stores the characteristic data of the phase-locked loop 20 at the locked operating frequency, when it is necessary to relock the operating frequency, the phase-locked loop 20 can be controlled to quickly relock the operating frequency based on the characteristic data at the operating frequency, shortening the time required to lock the operating frequency. Therefore, the phase-locked loop can achieve rapid relocking of the operating frequency after an interruption of operation.

[0048] In an exemplary embodiment, see Figure 4 The controller 13 includes an AD / DA converter 14 and a comparator 15. The output of the data acquisition unit 11 is connected to the analog input of the AD / DA converter 14. The digital output of the AD / DA converter 14 is connected to the first input of the comparator 15, and the output of the memory 12 is connected to the second input of the comparator 15. The output of the comparator 15 is connected to the digital input of the AD / DA converter 14, and the analog output of the AD / DA converter 14 is connected to the phase-locked loop 20.

[0049] In some implementations, see Figure 4The digital output of the AD / DA converter 14 is connected to the input of the memory 12. After the acquisition unit 11 acquires the characteristic data at the operating frequency in analog signal form, the AD / DA converter 14 can convert the characteristic data at the operating frequency in analog signal form into characteristic data at the operating frequency in digital signal form suitable for storage in the memory 12. Then, the AD / DA converter 14 can send the characteristic data at the operating frequency in digital signal form to the memory 12, and the memory 12 stores the characteristic data at the operating frequency in digital signal form. The characteristic data at the operating frequency in digital signal form is discrete in time and amplitude, and relatively concise, thus occupying less storage space and being suitable for storage. Accordingly, when the memory 12 needs to send the stored characteristic data at the operating frequency later, the memory 12 sends the characteristic data at the operating frequency in digital signal form.

[0050] During the process of controlling the phase-locked loop 20 to relock the operating frequency based on the characteristic data at that operating frequency, the data acquisition unit 11 continues to acquire the characteristic data of the phase-locked loop 20 and sends the acquired characteristic data to the AD / DA converter 14. The acquired characteristic data is in analog signal form. After the AD / DA converter 14 converts the acquired characteristic data in analog signal form into acquired characteristic data in digital signal form, it sends the acquired characteristic data in digital signal form to the comparator 15. In addition, the memory 12 sends the stored characteristic data at the operating frequency in digital signal form to the comparator 15.

[0051] Next, comparator 15 compares the feature data at the operating frequency with the acquired feature data, and generates and sends a control signal in digital form to AD / DA converter 14 based on the comparison result. For example, if the comparison result shows that the difference between the acquired feature data and the feature data at the operating frequency is not less than a threshold, it indicates that there is a large difference between the current frequency and the operating frequency to be locked, and it is necessary to continue to move closer to the operating frequency. In this case, the control signal is used to control phase-locked loop 20 to relock the operating frequency. Alternatively, if the comparison result shows that the difference between the acquired feature data and the feature data at the operating frequency is less than a threshold, it indicates that the current frequency and the operating frequency to be locked are close enough, and it is not necessary to continue to move closer to the operating frequency. Therefore, the control signal is used to stop controlling phase-locked loop 20.

[0052] In some implementations, see Figure 5 Comparator 15 is integrated into AD / DA converter 14. For example, in Figure 5In the process, the data acquisition unit 11 acquires feature data in analog signal form and sends the acquired feature data to the AD / DA converter 14. The AD / DA converter 14 converts the acquired feature data in analog signal form into acquired feature data in digital signal form, obtaining the acquired feature data in digital signal form. Furthermore, the memory 12 sends the stored feature data at the operating frequency to the AD / DA converter 14. Next, the AD / DA converter 14 compares the feature data at the operating frequency with the acquired feature data, generates a control signal in digital signal form based on the comparison result, and after converting this control signal into analog signal form, controls the phase-locked loop 20.

[0053] In some implementations, the AD / DA converter 14 is integrated into the memory 12, meaning that the memory 12 implements the function of the AD / DA converter 14. For example, after the acquisition unit 11 acquires the characteristic data of the phase-locked loop 20 in analog signal form at the operating frequency of the current operation, it transmits the characteristic data of the operating frequency in analog signal form to the memory 12, and the memory 12 converts the characteristic data of the operating frequency in analog signal form into characteristic data of the operating frequency in digital signal form suitable for storage in the memory 12.

[0054] In some implementations, see Figure 6 Both comparator 15 and AD / DA converter 14 are integrated into memory 12, meaning that memory 12 implements the functions of comparator 15 and AD / DA converter 14. For example, memory 12 receives characteristic data at the operating frequency in analog signal form sent by acquisition unit 11, converts this characteristic data at the operating frequency in analog signal form into characteristic data at the operating frequency in digital signal form, and stores it. Furthermore, during the process of controlling phase-locked loop 20 to relock the operating frequency, memory 12 also receives the acquired characteristic data sent by acquisition unit, converts the acquired characteristic data from analog signal form into digital signal form, compares the acquired characteristic data with the stored characteristic data at the operating frequency (both in digital signal form), and obtains a comparison result. Based on the comparison result, a control signal in digital signal form is generated, and after converting this control signal into analog signal form, the phase-locked loop 20 is controlled.

[0055] In other embodiments, the AD / DA converter 14 is integrated into the acquisition unit 11. For example, after the acquisition unit 11 acquires the characteristic data in analog signal form at the operating frequency locked by the phase-locked loop 20, it converts the characteristic data in analog signal form at the operating frequency into the characteristic data in digital signal form suitable for storage in the memory 12, and then transmits it to the memory 12 for storage.

[0056] For example, the controller 13 may be independent of the collector 11 and the memory 12, or it may be integrated into at least one of the collector 11 and the memory 12, that is, the function of the controller 13 may be implemented by at least one of the collector 11 and the memory 12.

[0057] It should be noted that the integration of different components in this application embodiment can reduce the number of components in the control device 10, thereby reducing the size of the control device 10 and enhancing its applicability. Furthermore, when integrating different components, it is necessary to ensure that the functions of each component can be implemented normally to avoid affecting the process of the control device 10 controlling the phase-locked loop 20. Normal function implementation includes, but is not limited to, implementing the function without affecting efficiency to avoid functional degradation caused by integration. For example, when integrating the comparator 15 and the AD / DA converter 14 into the memory 12, it is necessary not only to ensure that the memory 12 can perform its storage function normally, but also to ensure that the memory 12 can perform its analog-to-digital / digital-to-analog conversion function and its comparison function normally.

[0058] In an exemplary embodiment, the data acquisition unit 11 is also connected to the controller 13. For example, in the case where the data acquisition unit 11 acquires feature data of the phase-locked loop 20 (including but not limited to feature data at the operating frequency and the acquired feature data) as described above, the controller 13 can control the data acquisition unit 11 so that the data acquisition unit 11 acquires the feature data according to the control. Of course, if the data acquisition unit 11 is not connected to the controller 13, the data acquisition unit 11 can also acquire feature data through software configuration. This application embodiment does not limit the way the data acquisition unit 11 acquires feature data.

[0059] The structure of the phase-locked loop control device 10 has been described in detail above. Exemplarily, the components included in the control device 10, namely the data acquisition unit 11, the memory 12, the controller 13, the AD / DA converter 14, and the comparator 15, can all be independent hardware. Alternatively, the functions configured for each component of the control device 10 can be implemented by software. Exemplarily, the software includes program code, which can be stored in a computer-readable storage medium. This application embodiment does not limit the type of computer-readable storage medium.

[0060] Those skilled in the art should understand that the control devices described above are merely examples. Other existing or future components that are applicable to the control devices provided in the embodiments of this application should also be included within the scope of protection of the embodiments of this application, and are hereby incorporated by reference.

[0061] This application also provides a control system for a phase-locked loop. For example... Figures 3-7As shown, the control system includes a phase-locked loop control device 10 and a phase-locked loop 20 connected to the control device 10.

[0062] For example, see Figure 7 For the data acquisition unit 11 included in the control device 10, the input terminal of the data acquisition unit 11 is connected to the phase-locked loop 20 between the LF and the VCO. The AD / DA converter 14 is connected to the phase-locked loop 20 between the PFD and the LF. In some embodiments, see still Figure 7 When the phase-locked loop 20 includes a CP, the AD / DA converter 14 is connected to the phase-locked loop 20 between the CP and the LF.

[0063] It should be noted that, Figure 7 The LF shown is only one type of LF, and the LF included in the phase-locked loop 20 controlled by the control device 10 in this embodiment is not limited to this type of LF. In addition, the memory 12 mentioned above in this embodiment includes, but is not limited to, REG (Register), the collector 11 includes, but is not limited to, SH (Sample Hold) circuit, and the controller 13 includes, but is not limited to, processor, etc.

[0064] This application also provides a control method for a phase-locked loop, the steps of which can be performed by hardware (e.g., ...). Figures 3-7 (any of the control devices shown) and software (e.g., for implementing) Figures 3-7 Each of the control devices shown includes components configured to perform at least one of the functions. Figure 8 As shown, the method includes the following steps 801 and 802.

[0065] Step 801: Before the phase-locked loop (PLL) is interrupted, collect the characteristic data of the operating frequency locked by the PLL during this operation and store the characteristic data of the operating frequency.

[0066] During the operation of the phase-locked loop (PLL), the operation may be interrupted as needed. For example, upon receiving an interrupt signal, the operation may be terminated accordingly. Alternatively, the operation may be terminated according to a pre-configured interruption time.

[0067] Before interrupting operation, it is necessary to collect characteristic data of the operating frequency locked by the phase-locked loop during this operation. For example, this can be achieved by... Figures 3-7The acquisition unit 11 in any of the control devices 10 collects characteristic data at the operating frequency locked by the phase-locked loop (PLL) during this operation. For example, this characteristic data at the operating frequency is data generated by the PLL when locking to that operating frequency, or it is data generated based on the data generated by the PLL when locking to that operating frequency. This characteristic data at the operating frequency is equivalent to quantifying the state of the PLL locked to that operating frequency, and is therefore suitable for the PLL to relock to that operating frequency.

[0068] This application does not limit the characteristic data at the operating frequency. In some embodiments, the characteristic data at the operating frequency is the voltage tuning value (vtune) of the phase-locked loop when locked at that operating frequency. For example, the characteristic data at the operating frequency is the tuning voltage value between the LF and VCO of the phase-locked loop when locked at that operating frequency.

[0069] In an exemplary embodiment, characteristic data of the phase-locked loop at the operating frequency locked during this operation are collected, including the following two collection methods.

[0070] Data Acquisition Method 1: If the operating frequency locked by the phase-locked loop in this operation is different from the operating frequency locked in the previous operation, collect the characteristic data of the operating frequency locked by the phase-locked loop in this operation.

[0071] In acquisition method one, before interrupting the current operation of the phase-locked loop (PLL), the operating frequency locked in the previous operation is first acquired. Then, the operating frequency locked in the current operation is compared with the operating frequency locked in the previous operation to obtain the comparison result. This comparison process can be performed after the current operation begins, or it can be performed when it is confirmed that the current operation needs to be interrupted, such as after receiving an interrupt signal.

[0072] If the comparison result shows that the operating frequency locked in this operation is different from the operating frequency locked in the previous operation, then it is necessary to collect the characteristic data of the phase-locked loop at the locked operating frequency. For example, the characteristic data at this operating frequency can be collected when it is confirmed that the current operation needs to be interrupted. Alternatively, if the comparison result shows that the operating frequency locked in this operation is the same as the operating frequency locked in the previous operation, then it is not necessary to collect the characteristic data of the phase-locked loop at the locked operating frequency. For example, the current operation can be directly interrupted when it is confirmed that the current operation needs to be interrupted. For example, the number of operating frequencies locked in the previous operation is at least one. "The operating frequency locked in this operation is different from the operating frequency locked in the previous operation" includes: the operating frequency locked in this operation is different from each of at least one previously locked operating frequency. "The operating frequency locked in this operation is the same as the operating frequency locked in the previous operation" includes: the operating frequency locked in this operation is the same as any one of at least one previously locked operating frequency.

[0073] For example, the working frequency locked before this work includes, but is not limited to, the following four cases.

[0074] Scenario 1: This is the first operation of the phase-locked loop (PLL), and the locking frequency before this operation was zero. Since this is the first operation of the PLL, the PLL has not performed any operations before this operation, which is equivalent to the PLL locking frequency being zero before this operation.

[0075] Scenario 2: This operation is not the first operation of the phase-locked loop (PLL). The operating frequencies locked before this operation include the frequencies locked in each of the previous operations of the PLL. For example, if this is the 10th operation of the PLL, then the operating frequencies locked before this operation can be any frequencies locked in the previous 9 operations.

[0076] Scenario 3: This operation is not the first operation of the phase-locked loop (PLL). The operating frequency locked before this operation is any frequency locked in a reference number of previous operations of the PLL. The reference number is a positive integer, and this application does not limit the value of the reference number. For example, if this operation is the 10th operation of the PLL and the reference number is 5, then the operating frequencies locked before this operation include any frequency locked in the previous 5 operations, that is, any frequency locked in operations 5-9 of the PLL. In some embodiments, the reference number is 1, then the operating frequency locked before this operation is the frequency locked in the previous operation of the PLL.

[0077] Scenario 4: This operation is not the first operation of the phase-locked loop (PLL). The operating frequencies locked before this operation include any frequency locked by the PLL in each operation within the reference time period prior to this operation. The duration of the reference time period can be set empirically, and this application embodiment does not limit the duration of the reference time period. In some embodiments, the reference time period is adjacent to the time period in which the current operation occurs. For example, if this operation is the 10th operation of the PLL, and the operations within the reference time period are the 7th to 9th operations of the PLL, then the operating frequencies locked before this operation include any frequency locked by the PLL in the 7th to 9th operations. In other embodiments, the reference time period is not adjacent to the time period in which the current operation occurs. For example, if this operation is the 10th operation of the PLL, and the operations within the reference time period are the 2nd to 4th operations of the PLL, then the operating frequencies locked before this operation include any frequency locked by the PLL in the 2nd to 4th operations.

[0078] Data acquisition method two: Regardless of whether the operating frequency locked by the phase-locked loop in this operation is the same as the operating frequency locked in the previous operation, the characteristic data of the operating frequency locked by the phase-locked loop in this operation are collected.

[0079] In acquisition method two, before interrupting the current operation of the phase-locked loop, it is not necessary to obtain the operating frequency locked before the current operation as in acquisition method one, nor is it necessary to compare the operating frequency locked in the current operation with the operating frequency locked before the current operation. Instead, the characteristic data under the operating frequency locked in the current operation of the phase-locked loop can be directly acquired.

[0080] The above-described acquisition methods one and two are merely examples and are not intended to limit the method of acquiring feature data at the operating frequency of the current phase-locked loop in this embodiment. In an exemplary embodiment, after acquiring the feature data at the operating frequency of the current phase-locked loop, the method provided in this embodiment further includes: converting the feature data at the operating frequency into a digital signal form suitable for storage. For example, it can be obtained by... Figure 4 , Figure 5 and Figure 7 The AD / DA converter 14 in any of the control devices 10 converts the characteristic data at the operating frequency into a digital signal form suitable for storage.

[0081] The characteristic data at this operating frequency is in analog signal form. Analog signal form and digital signal form are two different representations of the characteristic data at this operating frequency. Compared to analog signal form, digital signal form is more suitable for storage. Therefore, the characteristic data at this operating frequency in analog signal form is converted into digital signal form to facilitate storage of the characteristic data at this operating frequency in digital signal form.

[0082] In some implementations, if other signal formats suitable for storage exist besides digital signals, the feature data at the operating frequency can be converted into other signal formats. In other implementations, if it is possible to store the feature data at the operating frequency in analog signal format, then the feature data at the operating frequency in analog signal format can be stored directly without conversion.

[0083] In summary, as long as the signal format of the feature data at the operating frequency is suitable for storage, the embodiments of this application can store the feature data at the operating frequency in a signal format suitable for storage. In the exemplary embodiments, the storage of the feature data at the operating frequency includes, but is not limited to, the following two storage methods.

[0084] Storage method one: Store the feature data at the operating frequency in the corresponding manner.

[0085] In some implementations, storage method one is suitable for storing both feature data at the current operating frequency and other feature data to avoid confusion between the feature data at the current operating frequency and other feature data. The other feature data refers to feature data locked at other frequencies by the phase-locked loop (PLL). These other frequencies include, but are not limited to, at least one of the operating frequencies locked before this operation and the operating frequencies that the PLL will lock after this operation. For example, other feature data is also stored corresponding to other frequencies.

[0086] In other words, having already stored the feature data for the working frequencies locked before this work session, we can continue to store the feature data for the working frequencies locked in this work session as well. Subsequently, we can also continue to store the feature data for the working frequencies locked after this work session.

[0087] In other implementations, storage method one is also applicable to situations where only the feature data of the current working frequency is stored, and no other feature data is stored.

[0088] Storage method two: Store the feature data at the working frequency locked in this operation, but do not store the working frequency itself.

[0089] Since storage method two does not store the feature data at the operating frequency in relation to that operating frequency, storing other feature data could lead to confusion between the feature data at that operating frequency and other feature data. Therefore, by way of example, storage method two is suitable for storing only the feature data at that operating frequency and not storing other feature data.

[0090] In some implementations, if feature data locked at a frequency previously locked for the current task has already been stored before storing the feature data locked at the current task's frequency, then the feature data locked at the current task's frequency needs to be deleted before storing the feature data locked at the current task's frequency. Similarly, before storing feature data locked at a frequency subsequently locked for the current task, the feature data locked at the current task's frequency also needs to be deleted.

[0091] This application embodiment does not limit the method of storing feature data at the operating frequency locked in the current operation. After storing the feature data at this operating frequency, the current operation of the phase-locked loop can be interrupted. For example, the process of collecting and storing feature data at the currently locked operating frequency is called calibration. Therefore, in this application embodiment, the current operation of the phase-locked loop is interrupted after calibration is completed. Furthermore, it should be noted that the frequency that the phase-locked loop needs to lock at is determined based on the application scenario of the phase-locked loop. Since the application scenario of the phase-locked loop does not change frequently, there is no need to frequently adjust the frequency that the phase-locked loop needs to lock at. Therefore, the probability that the operating frequency locked in the current operation is different from the operating frequency locked in the previous operation is small. Thus, this application embodiment does not need to frequently execute step 801 to complete the calibration, saving power consumption.

[0092] Step 802: After the phase-locked loop (PLL) operation is interrupted, if the PLL needs to relock the operating frequency, read the stored characteristic data at that operating frequency, and control the PLL to relock the operating frequency based on the characteristic data at that operating frequency.

[0093] After the phase-locked loop (PLL) interrupts its current operation, it may resume operation as needed. For example, upon receiving a recovery signal carrying the operating frequency, it is determined that the operating frequency needs to be relocked. Alternatively, it is determined that the operating frequency needs to be relocked after the configured recovery time has elapsed.

[0094] As explained in step 801, the characteristic data at the currently locked operating frequency is a quantization of the phase-locked loop's (PLL) state at that frequency. Therefore, this characteristic data is suitable for the PLL to relock to that frequency. Thus, when the PLL needs to relock to that frequency, the stored characteristic data at that frequency can be read, and the PLL can be controlled to relock to that frequency based on this data. Therefore, the VCO included in the PLL does not need to be like... Figure 1 , Figure 2 The corresponding description also mentions that the frequency is updated multiple times, which makes the time required for the phase-locked loop to relock to the operating frequency shorter, allowing the phase-locked loop to achieve rapid relocking after an interruption.

[0095] For example, it can be derived from Figure 3The controller 13 in the control device 10 shown reads the stored characteristic data at the operating frequency and controls the phase-locked loop to relock the operating frequency based on the characteristic data at the operating frequency. Optionally, it can be... Figure 4 , Figure 5 and Figure 7 The AD / DA converter 14 and comparator 15 in the control device 10 shown read the stored feature data at the operating frequency and control the phase-locked loop to relock the operating frequency based on the feature data at the operating frequency. During the relocking process, it is first necessary to read the stored feature data at the operating frequency. The method of reading the feature data at the operating frequency depends on the storage method used in step 801. In the exemplary embodiment, the method of reading the feature data at the operating frequency includes, but is not limited to, the following two.

[0096] Reading method one corresponds to storage method one in step 801. Since storage method one stores the characteristic data of the current working frequency locked by the phase-locked loop and the corresponding working frequency, reading method one first queries the stored working frequency, then determines the stored characteristic data of the current working frequency based on the current working frequency, and then reads the characteristic data of the current working frequency.

[0097] For example, if other frequencies and other characteristic data are stored, and the operating frequency locked by the phase-locked loop in this operation and the characteristic data at that operating frequency are also stored, the stored operating frequency is first retrieved from the stored operating frequency and other frequencies. Since the operating frequency and the characteristic data at that operating frequency are stored correspondingly, the characteristic data at that operating frequency stored corresponding to that operating frequency can be obtained, thereby realizing the reading of the characteristic data at that operating frequency.

[0098] Reading method two corresponds to storage method two in step 802. Since storage method two stores the feature data at the operating frequency, reading method two simply reads the feature data at that operating frequency.

[0099] It should be noted that the signal form of the feature data read at the operating frequency is unrelated to the reading method used, but is related to the signal form in which the feature data at that operating frequency is stored in step 801. For example, if the feature data at that operating frequency is stored in digital signal form in step 801, then the feature data read at that operating frequency will be in digital signal form. Therefore, controlling the phase-locked loop to relock the operating frequency based on the feature data at that operating frequency includes: controlling the phase-locked loop to relock the operating frequency based on the feature data at that operating frequency converted from digital signal form to analog signal form. In other words, after reading the feature data at that operating frequency in digital signal form, the feature data at that operating frequency is first converted from digital signal form to analog signal form, and then the phase-locked loop is controlled to relock the operating frequency based on the feature data at that operating frequency in analog signal form.

[0100] In some implementations, if the feature data read at the operating frequency is in a signal format other than digital, the feature data in that other format at the operating frequency can be converted into analog signal format. In other implementations, if it is possible to store the feature data at the operating frequency in analog signal format, then the feature data read at that operating frequency is already the feature data at that operating frequency in analog signal format, and therefore no further conversion is needed; the phase-locked loop can be controlled to relock the operating frequency based on the feature data at that operating frequency in analog signal format.

[0101] In summary, after reading the characteristic data at the operating frequency, it is necessary to control the phase-locked loop (PLL) to relock the operating frequency based on the characteristic data at that operating frequency. In an exemplary embodiment, controlling the PLL to relock the operating frequency based on the characteristic data at the operating frequency includes: charging the loop filter of the PLL based on the characteristic data at the operating frequency, thereby causing the PLL to relock the operating frequency.

[0102] In this embodiment, before charging, the PFD of the phase-locked loop (PLL) is first suspended, and the PLL is in an open circuit, thereby avoiding interference from the PFD during the charging process. Then, the loop filter of the PLL is charged based on characteristic data at the operating frequency. For example, when the characteristic data at the operating frequency is the tuning voltage value at the operating frequency locked by the PLL in this operation, charging the loop filter based on this characteristic data includes: generating an analog current signal based on the tuning voltage value, and charging the loop filter based on the analog current signal. Charging based on an analog current signal is merely an example; other signals suitable for charging the loop filter of the PLL may be used instead of this analog current signal in this embodiment.

[0103] After confirming that the phase-locked loop (PLL) has relocked to the operating frequency, charging of the PLL's loop filter can be stopped. For example, after stopping charging, the PLL's PFD needs to be restarted. This switches the PLL from an open circuit to a closed circuit, allowing it to continue the phase-locking process, i.e., tracking the phase that needs to be locked. The phase-locking process will not be elaborated upon here.

[0104] In an exemplary embodiment, the timing for stopping the charging of the loop filter is determined as follows: during the charging of the loop filter of the phase-locked loop based on the characteristic data at the operating frequency, the characteristic data of the phase-locked loop is collected, and the charging of the loop filter is stopped when the difference between the collected characteristic data and the characteristic data at the operating frequency is less than a threshold.

[0105] In some implementations, the feature data at the operating frequency and the acquired feature data are collected at the same location within the phase-locked loop, thereby avoiding errors and reduced accuracy caused by different collection locations. The process of acquiring feature data, and determining the difference between the feature data at the operating frequency and the acquired feature data, can be performed multiple times during charging. This allows for timely cessation of charging the loop filter when the difference is less than a threshold. This not only avoids wasting electrical energy but also further shortens the time required to lock the operating frequency.

[0106] For example, the feature data at the operating frequency is the stored digital signal form of the feature data at the operating frequency. After acquiring the feature data in analog signal form, the analog signal form of the feature data is converted into digital signal form of feature data, and then the difference between the digital signal form of the feature data at the operating frequency and the acquired digital signal form of the feature data is determined.

[0107] The control method of the phase-locked loop provided in the embodiments of this application has been generally introduced through steps 801 and 802. Next, see... Figure 9The control method will be illustrated with an example.

[0108] After starting the work, first determine whether the frequency to be locked in this task differs from the frequencies locked in previous tasks. If they differ, proceed to... Figure 9 The left branch is shown. If they are the same, proceed to the next step. Figure 9 The right-hand branch is shown.

[0109] exist Figure 9 The left branch shown represents the frequency at which normal locking is required for this task. Normal locking refers to locking according to... Figure 1 If locking is performed using the method described in the corresponding instructions, the VCO needs to update the frequency multiple times, making the normal locking process time-consuming. After normally locking the frequency required for this operation, the phase is also locked to complete the locking. Then, it operates normally according to the locked frequency and phase until an interrupt signal is received. After receiving the interrupt signal, the characteristic data of the phase-locked loop at the frequency required for this operation is collected and stored according to the method described in step 801. After completing the collection and storage process, the current operation is interrupted.

[0110] exist Figure 9 In the right-hand branch shown, the frequency required for this operation is quickly locked. Quick locking, i.e., locking the frequency as described in step 802, eliminates the need for the VCO to update the frequency multiple times, resulting in a shorter locking process. After quickly locking the required frequency, the phase is also locked, thus completing the locking. Then, the system operates normally according to the locked frequency and phase until an interrupt signal is received. Upon receiving the interrupt signal, no data acquisition or storage process is required; the current operation is simply terminated.

[0111] In summary, this application collects and stores characteristic data of the operating frequency locked by the phase-locked loop (PLL) during the current operation. Therefore, the PLL can be controlled to relock the operating frequency based on the characteristic data of the operating frequency, without having to lock the operating frequency through multiple frequency update processes. This shortens the time it takes for the PLL to lock the operating frequency, enabling the PLL to quickly relock after an interruption.

[0112] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.

[0113] It should be noted that all information, data (including but not limited to feature data) and signals (including but not limited to voltage signals and error voltage control signals) involved in this application have been authorized by the user or by all parties in full, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the feature data of the operating frequency and the feature data collected in this application were obtained with full authorization.

[0114] The above description is merely an embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A control device (10) for a phase-locked loop, characterized in that, The control device (10) includes a data collector (11), a memory (12), and a controller (13). The input terminal of the data collector (11) is connected to the phase-locked loop (20), the output terminal of the data collector (11) is connected to the input terminal of the memory (12), the output terminal of the memory (12) is connected to the input terminal of the controller (13), and the output terminal of the controller (13) is connected to the phase-locked loop (20). The memory (12) is configured to store the first operating frequency locked by the phase-locked loop (20) before this operation and the corresponding feature data at the first operating frequency. The collector (11) is configured to acquire the stored first operating frequency before the current operation of the phase-locked loop (20) is interrupted, compare the first operating frequency with the second operating frequency locked by the phase-locked loop (20) in this operation, and if the second operating frequency is different from the first operating frequency, collect feature data at the second operating frequency. The memory (12) is also configured to store the second operating frequency and the corresponding feature data at the second operating frequency; The controller (13) is configured to, after the current operation of the phase-locked loop (20) is interrupted, if the phase-locked loop (20) needs to relock the second operating frequency, query the second operating frequency from the stored first operating frequency and the second operating frequency, read the feature data of the second operating frequency stored in the memory (12) corresponding to the second operating frequency, and control the phase-locked loop (20) to relock the second operating frequency based on the feature data of the second operating frequency.

2. The control device (10) according to claim 1, characterized in that, The controller (13) includes an analog-to-digital converter (AD / DA) and a comparator (15). The output terminal of the data acquisition unit (11) is connected to the analog input terminal of the AD / DA converter (14); The digital output terminal of the AD / DA converter (14) is connected to the first input terminal of the comparator (15), and the output terminal of the memory (12) is connected to the second input terminal of the comparator (15). The output of the comparator (15) is connected to the digital input of the AD / DA converter (14); The analog output terminal of the AD / DA converter (14) is connected to the phase-locked loop (20).

3. The control device (10) according to claim 2, characterized in that, The digital output of the AD / DA converter (14) is connected to the input of the memory (12).

4. The control device (10) according to claim 2 or 3, characterized in that, The comparator (15) is integrated into the AD / DA converter (14); Alternatively, the AD / DA converter (14) may be integrated into the memory (12).

5. A phase-locked loop control system, characterized in that, The control system includes a control device (10) for the phase-locked loop according to any one of claims 1-4 and the phase-locked loop (20) connected to the control device (10).

6. A control method for a phase-locked loop, characterized in that, The method includes: Before the current operation of the phase-locked loop is interrupted, a first operating frequency is acquired and stored. The first operating frequency is compared with the second operating frequency locked by the phase-locked loop during the current operation. If the second operating frequency is different from the first operating frequency, feature data under the second operating frequency is collected, and the second operating frequency and the feature data under the second operating frequency are stored accordingly. The first operating frequency is the operating frequency locked before the current operation of the phase-locked loop, and the first operating frequency and the feature data under the first operating frequency are stored accordingly. After the current operation of the phase-locked loop is interrupted, if the phase-locked loop needs to relock the second operating frequency, the second operating frequency is retrieved from the stored first and second operating frequencies, the characteristic data corresponding to the second operating frequency is read, and the phase-locked loop is controlled to relock the second operating frequency based on the characteristic data of the second operating frequency.

7. The method according to claim 6, characterized in that, The step of controlling the phase-locked loop to relock the second operating frequency based on the feature data at the second operating frequency includes: The loop filter of the phase-locked loop is charged based on the characteristic data at the second operating frequency, so that the phase-locked loop relocks to the second operating frequency.

8. The method according to claim 7, characterized in that, The method further includes: During the charging process of the loop filter of the phase-locked loop based on the characteristic data at the second operating frequency, the characteristic data of the phase-locked loop is collected. When the difference between the collected characteristic data and the characteristic data at the second operating frequency is less than a threshold, the charging of the loop filter is stopped.

9. The method according to claim 7, characterized in that, The characteristic data at the second operating frequency is the tuning voltage value of the phase-locked loop at the second operating frequency; The charging of the loop filter of the phase-locked loop based on the feature data at the second operating frequency includes: An analog current signal is generated based on the tuning voltage value, and the loop filter of the phase-locked loop is charged based on the analog current signal.

10. The method according to any one of claims 6-9, characterized in that, After acquiring the feature data at the second operating frequency, the method further includes: converting the feature data at the second operating frequency into a digital signal form suitable for storage. The step of controlling the phase-locked loop to relock the second operating frequency based on the feature data at the second operating frequency includes: controlling the phase-locked loop to relock the second operating frequency based on the feature data at the second operating frequency converted from digital signal form to analog signal form.

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