Component carrier and method for producing a component carrier

Abstract

A component carrier is provided, comprising: (a) a base structure having a main surface with a surface profile; (b) a first dielectric layer formed on the main surface of the base structure and having a first main surface with a first surface profile, wherein the first main surface is correspondingly remote from the main surface of the base structure and wherein the first surface profile corresponds to the surface profile of the base structure; and (c) a second dielectric layer formed on the first main surface and having a second main surface with a second surface profile, wherein the second main surface is correspondingly remote from the main surface of the base structure and wherein the second surface profile is different from the surface profile of the base structure. A method for manufacturing such a component carrier is also provided, wherein the first dielectric layer is pressed onto the main surface using an auxiliary sheet. The auxiliary sheet is removed before the second dielectric layer is pressed onto the first dielectric layer.

Description

Technical Field

[0001] The present invention relates to the technical field of component carriers on which electronic components can be mounted to form electronic assemblies. In particular, the present invention relates to a component carrier comprising a pressed laminate stack comprising, in addition to at least one patterned metal layer, a base structure and a dielectric layer, and a method for producing such a component carrier. Background Art

[0002] A component carrier, such as a printed circuit board (PCB), is a support structure for at least one electronic component that forms an electronic assembly or electronic circuit. The component carrier comprises a stack of at least one electrically insulating or dielectric layer structure and at least one electrically conductive layer structure, typically made of a metal such as copper. The conductor traces representing the interconnecting wiring are formed by appropriately structuring or patterning the electrically conductive layer structure disposed on top of or below the electrically insulating layer of the component carrier. The electronic components can be mounted on the upper or lower surface of the component carrier. In some applications, the electronic components are at least partially embedded within (the volume of) the component carrier.

[0003] A multilayer component carrier is a laminated stack comprising a plurality of electrically insulating or dielectric layer structures and a plurality of (patterned) electrically conductive layer structures arranged alternately. In order to electrically connect the different electrically conductive layer structures, metallized vias extending through at least one electrically insulating layer may be used.

[0004] A "thick" multilayer component carrier can comprise, for example, 38 layers. Typically, in particular internally patterned electrically conductive layer structures have a relatively thick copper thickness of, for example, 70 μm. This means that there are free spaces or gaps between the conductor tracks. In order not to reduce the quality of the component carrier (e.g. mechanical stability), the gaps must be filled during the lamination process. This can be achieved by applying high voltage. However, high voltage levels can easily lead to undesirable image transfer in the thickness direction of the component carrier, for example in the range of 100 μm. In this context, image transfer is a surface deformation at one surface of the dielectric layer structure, which is caused by a surface deformation at the opposite surface of the dielectric layer structure. In addition, high voltage levels - in particular when combined with a pronounced image transfer - can lead to undesirable warping of the final component carrier. Consequently, each dielectric layer of a multilayer component carrier can lead to such undesirable warping.

[0005] There is a need for a component carrier that exhibits only a small warpage. Summary of the Invention

[0006] This need can be met by a component carrier according to one aspect of the invention and a method for producing the component carrier. Advantageous embodiments of the invention are described by the other aspects of the invention.

[0007] According to a first aspect of the present invention, a component carrier is provided, comprising: (a) a base structure having a main surface with a surface contour (in a three-dimensional shape); (b) a first dielectric layer formed on the main surface of the base structure and having a first main surface with a first surface contour (in a three-dimensional shape). The first main surface faces away from the main surface of the base structure, and the first surface contour (in terms of its three-dimensional shape) corresponds to the surface contour of the base structure. The component carrier described further comprises (c) a second dielectric layer formed on the first main surface and having a second main surface with a second surface contour (in a three-dimensional shape). The second main surface faces away from the main surface of the base structure, and the second surface contour (in terms of its three-dimensional shape) is different from the surface contour of the base structure.

[0008] The component carrier described is based on the idea that by separating a dielectric layer—on which an electrically conductive layer or any other (multi-layer) laminate structure can subsequently be formed—into two sub-layers, namely a first dielectric layer and a second dielectric layer, the flatness of the outer surface of the (combined) dielectric layer can be improved. This applies to (i) the flatness on a spatially larger scale, which can be degraded by undesirable warping of the entire component carrier, and (ii) the flatness on a spatially smaller scale, which can be degraded by undesirable ridges and indentations that can be caused by so-called "image transfer" during the lamination process. As already mentioned above in the introductory part of this document, image transfer is a surface deformation at one surface of a dielectric layer structure that is caused by surface deformation at the opposite surface of the dielectric layer structure due to the pressure required for any lamination process of an (at least partially cured) dielectric layer structure, such as a so-called prepreg layer structure.

[0009] To achieve maximum flatness of the component carrier's outer surface as described for each dielectric layer, separate process parameters can be used. Specifically, a relatively high pressure can be used to form the first dielectric layer formed on the base structure. A lower pressure can be used to form the second dielectric layer formed on the first dielectric layer. This can allow for the "closing" or smoothing of bumps and indentations created by the image transfer on the outer surface of the first dielectric layer.

[0010] The described component carrier can exhibit the following advantages:

[0011] (1) The warpage of the entire component carrier will be very small.

[0012] (2) Voids in the dielectric layer can be avoided.

[0013] (3) The component carrier can be used as a base for forming at least one further high-quality build-up structure on the component carrier. This can allow the production of thicker printed circuit boards with a higher number of layers and of higher quality.

[0014] (4) The component carrier allows the formation of electronic circuits with a high integration density.

[0015] According to an embodiment of the present invention, the base structure comprises a core and a stack comprising at least one electrically conductive layer structure and / or at least one electrically insulating layer structure.

[0016] The core together with the stack may be a laminate formed in particular by applying mechanical pressure and / or thermal energy.The term "layer structure" or simply "layer" may in particular denote a continuous layer, a patterned layer or a plurality of discontinuous islands in a common plane.

[0017] The described component carrier, if applicable, together with additional layers or layer structures, can be formed as a plate. This can facilitate a compact design, wherein the component carrier still provides a large base for mounting components on the component carrier. Furthermore, bare chips (dies), as an example of embedded electronic components, can be easily embedded in thin boards, such as printed circuit boards, due to their low thickness.

[0018] In an embodiment, the at least one electrically insulating layer (structure) comprises at least one of the following: a resin (e.g., a reinforced resin or a non-reinforced resin, such as an epoxy resin or a bismaleimide-triazine resin), a cyanate resin, a polyphenylene derivative, a glass (particularly a glass fiber, a multilayer glass, a glass-like material), a prepreg material (e.g., FR-4 or FR-5), a polyimide, a polyamide, a liquid crystal polymer (LCP), an epoxy-based laminate film, a polytetrafluoroethylene (PTFE, Teflon), a Ceramics, and metal oxides. Reinforcement structures made of, for example, glass (multilayer glass) such as meshes, fibers, or spheres may also be used. Although prepregs, particularly FR4, are generally preferred for rigid PCBs, other materials, particularly epoxy-based laminates or photosensitive dielectric materials, may also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers and / or cyanate ester resins, low-temperature co-fired ceramics (LTCC), or other low, very low, or ultra-low DK materials may be implemented as electrically insulating layer structures in the component carrier.

[0019] In an embodiment, the at least one electrically conductive layer (structure) comprises at least one of the following: copper, aluminum, nickel, silver, gold, palladium and tungsten. Although copper is generally preferred, other materials or coated variations thereof, in particular coated with superconducting materials such as graphene, are also possible.

[0020] According to another embodiment of the present invention, the stack includes a patterned electrically conductive layer defining a major surface of the base structure, wherein the surface contours of the base structure are defined by the patterned electrically conductive layer.

[0021] In this embodiment, the base structure provides at least one inner electrically conductive layer structure of the multilayer component carrier. This allows a high integration density of the electronic assembly to be achieved.

[0022] According to another embodiment of the present invention, the patterned electrically conductive layer is a patterned metal layer, in particular, a patterned copper layer. Conventional PCB materials and PCB processing techniques can be used to form the entire base structure. Thus, the described component carrier can be manufactured efficiently by relying on recognized and approved manufacturing processes.

[0023] According to another embodiment of the invention, the component carrier further comprises an outer electrically conductive layer formed on the second dielectric layer. The outer electrically conductive layer can also be patterned in a suitable manner to form conductive traces and / or conductor pads for contacting at least one (surface mounted) electronic component.

[0024] According to another embodiment of the present invention, the first dielectric layer has a first thickness and the second dielectric layer has a second thickness, wherein the first thickness is identical to the second thickness. This can achieve high-quality results, particularly with respect to warpage and flatness of the component carrier. In an alternative embodiment, the first thickness is different from the second thickness.

[0025] According to another embodiment of the present invention, at least one of the first dielectric layer and the second dielectric layer includes a resin and a solid object located within the resin.

[0026] The solid objects may influence the characteristic features of the corresponding dielectric layer, such as mechanical stability / rigidity, flow behavior during curing (in particular during lamination), dielectric constant, impedance, etc. Therefore, by selecting an appropriate number, material and / or size of solid objects, suitable application-specific properties of the entire component carrier can be achieved.

[0027] According to another embodiment of the present invention, the first dielectric layer comprises solid objects that are unevenly distributed across (or along) the first major surface. Alternatively or in combination, the second dielectric layer comprises solid objects that are evenly distributed across (or along) the second major surface.

[0028] By selecting an appropriately uneven distribution of solid objects within the first dielectric layer (before forming the second dielectric layer on the first dielectric layer), a substantially uniform or flat first major surface of the first dielectric layer can be achieved. This flatness can be particularly related to the flatness on the larger scales described above. Undesirable smaller-scale unevenness, which may be caused by the aforementioned "image transfer" during the lamination process, can be compensated by the second dielectric layer of the component carrier described above.

[0029] It should be noted that solid objects are generally harder than the surrounding resin material. Therefore, the compressibility of the first and / or second dielectric layers depends on the amount of solid objects embedded in the resin material of the respective layer. Therefore, by selecting an appropriate uneven distribution of solid objects on the first dielectric layer, the local compressibility of the first dielectric layer can be specifically adjusted with respect to the (expected) surface contour of the main surface of the base structure. As a result, a significant surface flattening can be achieved using only the first dielectric layer.

[0030] The described uniform distribution of solid objects on the second major surface may allow for an improvement in the mentioned flatness at smaller scales.

[0031] According to another embodiment of the present invention, the solid object is a reinforcing fiber and / or a filler particle. In PCB manufacturing technology, reinforcing fibers and filler particles, such as glass spheres, are proven and mature materials for achieving the required application-specific properties of the corresponding dielectric layer in an efficient and reliable manner.

[0032] According to another embodiment of the invention, the variation of the thickness of the component carrier divided by the average thickness of the component carrier is less than 5%, in particular the variation of the thickness of the component carrier divided by the average thickness of the component carrier is less than 3%.

[0033] A component carrier with a precisely defined thickness (as an intermediate product) facilitates virtually any further processing of the component carrier to produce high-quality printed circuit boards, in particular multilayer PCBs. Furthermore, the small thickness variations described have the effect of stabilizing the impedance across the entire surface of the circuit board. This allows for the formation of stable and reliable electronic circuits on the component carrier, resulting in electronic assemblies with excellent performance, particularly for high-frequency (HF) applications.

[0034] According to another embodiment of the present invention, the base structure has an additional main surface having an additional surface profile (in a three-dimensional shape), wherein the additional main surface is opposite to the main surface. The component carrier according to this embodiment also includes (a) a third dielectric layer, which is formed on the additional main surface of the base structure and has a third main surface, which has a third surface profile (in a three-dimensional shape). The third main surface corresponds to the additional main surface remote from the base structure, and the third surface profile (in terms of its three-dimensional shape) corresponds to the additional surface profile of the base structure. The component carrier also includes (b) a fourth dielectric layer, which is formed on the third main surface and has a fourth main surface with a fourth surface profile (in a three-dimensional shape). Thus, the fourth main surface corresponds to the additional main surface remote from the base structure, and the fourth surface profile (in terms of its three-dimensional shape) is different from (does not correspond to) the additional surface profile of the base structure. This embodiment of the component carrier can be implemented as a (completely) symmetrical multilayer PCB, which, due to its symmetry, can exhibit excellent performance, especially in terms of minimal warping.

[0035] It should be noted that this symmetry is not only related to the size or thickness of the dielectric layer, but also to the possible additional layer structures that may be formed on the opposite sides of the base structure. In addition, the mentioned symmetry may also be related to the material and / or other characteristics: such as mechanical stability / rigidity, flow behavior during curing (especially lamination), dielectric constant, impedance, etc.

[0036] According to another embodiment, the component carrier comprises at least one component surface-mounted on the component carrier and / or embedded in the component carrier, wherein the at least one component is in particular selected from: electronic components, non-electrically conductive and / or electrically conductive inlays, heat transfer units, light-conducting elements, optical elements, bridges, energy harvesting units, active electronic components, passive electronic components, electronic chips, memory devices, filters, integrated circuits, signal processing components, power management components, optoelectronic interface elements, voltage converters, cryptographic components, transmitters and / or receivers, electromechanical transducers, actuators, microelectromechanical systems, microprocessors, capacitors, resistors, inductors, batteries, switches, cameras, antennas, magnetic elements, further component carriers and logic chips.

[0037] According to a further embodiment, the component carrier comprises at least one electrically conductive layer structure, the electrically conductive layer structure of the component carrier comprising at least one of copper, aluminum, nickel, silver, gold, palladium and tungsten, any of the above materials optionally being coated with a superconducting material, for example graphene.

[0038] According to another embodiment, the component carrier includes at least one dielectric layer, and the electrically insulating layer structure includes at least one of the following: resin (in particular reinforced resin or non-reinforced resin, such as epoxy resin or bismaleimide-triazine resin), FR-4, FR-5, cyanate resin, polyphenylene derivative, glass, prepreg material, polyimide, polyamide, liquid crystal polymer, epoxy-based laminate film, polytetrafluoroethylene, ceramic and metal oxide.

[0039] According to a further embodiment, the component carrier is formed as a plate.

[0040] According to another embodiment, the component carrier is configured as one of the group consisting of a printed circuit board, a substrate, and an interposer.

[0041] According to a further embodiment, the component carrier is designed as a laminate component carrier.

[0042] According to another aspect of the present invention, a method for manufacturing a component carrier is provided. The method includes: (a) providing a base structure having a major surface; (b) pressing an at least partially uncured first dielectric layer together with an auxiliary sheet onto the major surface of the base structure; (c) removing the auxiliary sheet from the first dielectric layer; and (d) pressing an at least partially uncured second dielectric layer onto the first dielectric layer.

[0043] This aspect of the invention is based on the idea that a single pressing cycle, in which a stack of a metal layer and an (at least partially uncured) dielectric layer is directly or indirectly laminated onto or at a base structure, is subdivided into two sub-cycles. Thus, each sub-cycle can be completed with specific and appropriate parameters for each sub-cycle. These parameters may include process parameters (e.g., pressure, temperature, etc.) as well as layer-specific parameters (e.g., material, thickness, degree of curing, etc.) of the first dielectric layer, the auxiliary sheet, and the second dielectric layer.

[0044] The primary goal of the first pressing sub-cycle can be to ensure good filling of the inner layer while minimizing the level of image transfer. Thus, a relatively high pressure can allow for full filling of the inner first dielectric layer, while the auxiliary sheet will act as a strong boundary condition to prevent excessive image transfer on the next outer second dielectric layer. Consequently, image transfer may be limited to, for example, 20 microns.

[0045] After completion of the first pressing sub-cycle, the auxiliary sheet can be removed, in particular by etching, in order to prepare a corresponding intermediate product for the second pressing sub-cycle.

[0046] The primary goal of the second pressing sub-cycle is to at least partially eliminate any unwanted image transfer and ultimately obtain a structure with no or only negligible warpage. The semi-finished product thus formed can be provided with an additional outer electrically conductive layer that can be further processed in a known manner. This processing can include, for example, appropriate patterning to form outer conductor tracks and / or outer conductor pads for contacting the mounted electronic components.

[0047] The auxiliary sheet can be made of any material or combination of materials that is sufficiently rigid to evenly distribute the pressure or stress applied to the stack comprising the base structure and the at least partially uncured first dielectric layer. Furthermore, the material or combination of materials should allow the auxiliary sheet to be removed with little or no residue. The auxiliary sheet can also comprise a stack of layers of different materials.

[0048] According to another embodiment of the present invention, the auxiliary sheet includes at least one of a copper sheet, a ceramic sheet, and a glass sheet. The materials described for the auxiliary sheet are particularly suitable for equalizing the pressure acting on the first dielectric layer during the lamination process. In addition, copper, in particular, and the other mentioned materials, can allow for easy removal of the auxiliary sheet before forming / laminating the second dielectric layer onto the first dielectric layer. Furthermore, the described materials are well-known materials used in PCB manufacturing processes and facilitate the implementation of the described method using known process equipment.

[0049] In some embodiments, the auxiliary sheet comprises a (thin) copper foil applied or attached to a steel support structure. This attachment can be achieved using an adhesive material. The adhesive material can be any adhesive layer, such as a glue layer and / or tape / foil.

[0050] According to a preferred embodiment, the auxiliary sheet has a thickness of at least 50 μm and in particular at least 100 μm.

[0051] According to another embodiment of the invention, an outer electrically conductive layer is pressed onto the first dielectric layer together with the second dielectric layer. Thus, the outer electrically conductive layer may be a copper structure, in particular having a thickness of less than 40 μm and more in particular less than 20 μm.

[0052] According to another embodiment of the present invention, the base structure has an additional major surface, wherein the additional major surface is opposite to the first major surface. The method according to this embodiment further comprises: (a) pressing an at least partially uncured third dielectric layer together with an additional auxiliary sheet onto the additional major surface of the base structure while pressing the at least partially uncured first dielectric layer; (b) removing the additional auxiliary sheet from the third dielectric layer; and (c) pressing an at least partially uncured fourth dielectric layer onto the third dielectric layer while pressing the at least partially uncured second dielectric layer.

[0053] The described method can provide the advantage that the resulting component carrier can be realized as a (completely) symmetrical multilayer PCB. The advantages and possible further features of such a symmetrical component carrier have already been described above and also apply, mutatis mutandis, to the described (symmetrical) method.

[0054] It should be noted that embodiments of the present invention have been described with reference to different subject matters. In particular, some embodiments have been described with reference to method-type claims, while other embodiments have been described with reference to apparatus-type claims. However, as will be apparent to those skilled in the art from the foregoing and following descriptions, any combination of features relating to different subject matters, in particular any combination of features from method-type claims and features from apparatus-type claims, in addition to any combination of features belonging to one type of subject matter, is considered to be disclosed with this document unless otherwise indicated.

[0055] Before describing exemplary embodiments in more detail with reference to the accompanying drawings, some basic considerations based on which exemplary embodiments of the present invention have been developed will be summarized.

[0056] In the context of this document, the term "component carrier" may particularly denote any supporting structure capable of accommodating one or more components on and / or in the component carrier to provide mechanical support and / or electrical connection. In other words, the component carrier may be configured as a mechanical carrier and / or an electronic carrier for the components. In particular, the component carrier may be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. The component carrier may also be a hybrid board combining different types of component carriers of the types mentioned above.

[0057] In an embodiment, the component carrier is configured as one of the group consisting of a printed circuit board, a substrate (in particular an IC substrate) and an interposer.

[0058] In the context of this document, the term "printed circuit board" (PCB) may particularly denote a plate-like component carrier formed by laminating a plurality of electrically conductive layer structures with a plurality of electrically insulating layer structures, for example by applying pressure and / or by supplying heat. As a preferred material for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may comprise resin and / or glass fiber, so-called prepreg, or FR4 material. The individual electrically conductive layer structures may be connected to each other in a desired manner by forming through-holes through the laminate, for example by laser drilling or mechanical drilling, and by filling these through-holes with electrically conductive material (particularly copper) to form vias serving as through-hole connections. In addition to being able to embed one or more components in the printed circuit board, the printed circuit board is typically configured to accommodate one or more components on one surface or two opposite surfaces of the plate-like printed circuit board. The one or more components may be connected to the corresponding main surface by soldering. The dielectric portion of the PCB may be composed of a resin with reinforcing fibers (e.g., glass fibers).

[0059] In the context of this document, the term "substrate" can particularly refer to a small component carrier. Relative to a PCB, a substrate can be a relatively small component carrier on which one or more components can be mounted and which can serve as a connecting medium between one or more chips and another PCB. For example, a substrate can have approximately the same dimensions as the components (particularly electronic components) to be mounted on the substrate (for example, in the case of a chip-scale package (CSP)). More specifically, a substrate can be understood as a component carrier that is used for electrical connectors or power grids and a component carrier that has a relatively high density of horizontal and / or vertical connectors, comparable to a PCB but with a higher density. Horizontal connectors are, for example, conductive channels, while vertical connectors can be, for example, drilled holes. These horizontal and / or vertical connectors are arranged within the substrate and can be used to provide electrical, thermal, and / or mechanical connections between accommodated or unaccommodated components (such as bare chips), in particular IC chips, and a printed circuit board or an intermediate printed circuit board. Therefore, the term "substrate" also includes an "IC substrate." The dielectric portion of the substrate may be composed of a resin with reinforcing particles, such as reinforcing spheres, particularly glass spheres.

[0060] The substrate or interposer may include or be composed of at least one layer of: glass; silicon (Si); a photosensitive or dry-etchable organic material, such as an epoxy-based laminate material (e.g., an epoxy-based laminate film); or a polymer compound, such as polyimide, polybenzoxazole, or benzocyclobutene-functional polymer.

[0061] After the formation of the stack having the electrically insulating layer structure and the electrically conductive layer structure is completed, the obtained layer structure or component carrier can be subjected to surface treatment. In particular, in terms of surface treatment, an electrically insulating solder resist can be applied to one main surface or two opposite main surfaces of the layer stack or component carrier. For example, a solder resist can be formed on the entire main surface and then the solder resist layer can be patterned to expose one or more electrically conductive surface portions, which will be used to electrically couple the component carrier to the electronic peripheral. The surface portions of the component carrier that remain covered with the solder resist, in particular the surface portions containing copper, can be effectively protected from oxidation or corrosion.

[0062] In terms of surface treatment, a surface finishing portion can also be selectively applied to the exposed electrically conductive surface portions of the component carrier. Such a surface finishing portion can be an electrically conductive covering material on the exposed electrically conductive layer structure (such as a pad, a conductive trace, etc., in particular comprising or consisting of copper) on the surface of the component carrier. If such an exposed electrically conductive layer structure is not protected, the exposed electrically conductive component carrier material (in particular copper) will be oxidized, thereby making the reliability of the component carrier lower. The surface finishing portion can then be formed as a joint between, for example, a surface mounted component and a component carrier. The surface finishing portion has the function of protecting the exposed electrically conductive layer structure (in particular copper circuits), and the surface finishing portion can realize a joining process with one or more components, for example by welding. Examples of suitable materials for the surface finishing portion are organic solderability preservatives (OSP), electroless nickel immersion gold (ENIG), gold (in particular hard gold), chemical tin, nickel gold, nickel palladium, electroless nickel immersion palladium immersion gold (ENIPIG), etc.

[0063] The component carrier described can be provided with at least one embedded component that is at least partially housed within a recess formed in the component carrier structure. The at least one component can be selected from the group consisting of a non-electrically conductive inlay (e.g., a ceramic inlay or an aluminum nitride inlay), an electrically conductive inlay (e.g., a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (e.g., a heat pipe), a light-guiding element (e.g., an optical waveguide or optical conductor connector), an optical element (e.g., a lens), an electronic component, or a combination thereof. For example, the component can be an active electronic component, a passive electronic component, an electronic chip, a memory device (e.g., a DRAM or other data memory), a filter, an integrated circuit, a signal processing component, a power management component, an optoelectronic interface element, a light-emitting diode, an optocoupler, a voltage converter (e.g., a DC / DC converter or an AC / DC converter), a cryptographic component, a transmitter and / or receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductor, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components can also be embedded in the component carrier. For example, a magnetic element can be used as a component. This magnetic element can be a permanent magnetic element (e.g., a ferromagnetic element, an antiferromagnetic element, a multiferroic element, or a ferrimagnetic element, such as a ferrite core) or a paramagnetic element. However, the component can also be a substrate, an interposer, or other component carrier, such as a plate-in-plate configuration. The component can be surface-mounted on the component carrier and / or embedded in the interior of the component carrier. In addition, other components, in particular components that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation transmitted from the environment, can also be used as components.

[0064] After processing the internal layer structure of the component carrier, one or both main surfaces of the processed layer structure can be covered symmetrically or asymmetrically with one or more further electrically insulating and / or electrically conductive layer structures (in particular by lamination). In other words, the layer buildup can be continued until the desired number of layers is achieved.

[0065] The aspects defined above and further aspects of the invention are apparent from the examples of embodiment described hereinafter and are explained with reference to the examples of embodiment.The invention will be described in more detail hereinafter with reference to examples of embodiment but to which the invention is not limited. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 (a) to (e) show a method for producing a component carrier according to an embodiment of the present invention.

[0067] Figure 2 (a) to (e) show a method for producing a component carrier according to another embodiment of the present invention, wherein the component carrier comprises an intermediate multi-core stack having a plurality of inner cores and dielectric layers. DETAILED DESCRIPTION

[0068] The illustrations in the figures are schematic. Note that in different figures, similar or identical elements or features are provided with the same reference numerals or reference numerals that differ from the corresponding reference numerals only within the first digit. To avoid unnecessary repetition, elements or features that have already been explained with respect to previously described embodiments will not be explained again later in the specification.

[0069] Figure 1 (a) to (e) show a method according to an embodiment of the present invention for producing a component carrier 100. The production method begins with preparing the various layer structures for a first lamination process, wherein the layer structures are laminated together in a known manner by applying pressure and heat.

[0070] Figure 1 (a) shows the various layer structures before being arranged together. Figure 1 As can be seen in (a), the layer structure is arranged in a symmetrical manner, wherein the base structure 110 is arranged in the middle of the symmetrical arrangement structure. The base structure 110 includes a core 112, on which are formed two patterned electrically conductive layers 114 and 116. According to the exemplary embodiment described herein, the patterned electrically conductive layers 114 and 116 are made of copper.

[0071] A patterned electrically conductive layer 114 is formed on the upper surface of the base structure 110, while another patterned electrically conductive layer 116 is formed on the lower surface of the base structure 110. In the final product / component carrier 100, both patterned electrically conductive layers 116, 114 represent internal conductor traces. The final product is therefore a multi-layer component carrier 100.

[0072] The base structure 110 comprises a three-dimensional surface contour at the upper major surface 110a due to the thickness of the patterned electrically conductive layers 114, 116. Correspondingly, the base structure 110 comprises an additional three-dimensional surface contour at the lower major surface 110b.

[0073] In the layered arrangement to be laminated, there is also provided a first dielectric layer 120 above the base structure 110 and a third dielectric layer 160 below the base structure 110. Figure 1 As seen in (a) of FIG, an auxiliary sheet 125 is provided above the first dielectric layer 120 and a further auxiliary sheet 165 is provided below the third dielectric layer 160. According to the embodiment described here, the two auxiliary sheets 125, 165 are relatively thick copper layers with a thickness of, for example, 105 μm.

[0074] Figure 1 (b) shows the layer arrangement structure after the first lamination process described above. Figure 1 Indicated by arrow L1.

[0075] As can be seen, lamination results in a so-called image transfer. This means that the three-dimensional surface profile 110a is at least partially pushed through the first dielectric layer 120. Consequently, the first main surface 120a of the first dielectric layer 120 exhibits a three-dimensional first surface profile. Depending on the process conditions, in particular the pressure applied during the first lamination process L1, the height variations of the first surface profile 120a correspond more or less to the surface profile 110a. Of course, a corresponding further image transfer also occurs on the underside of the base structure 110. This further image transfer results in a three-dimensional third surface profile on the third main surface 160a of the third dielectric layer 160, which at least substantially corresponds to the further surface profile 110b.

[0076] In a subsequent production step, the (copper) auxiliary sheet 125 and the (copper) further auxiliary sheet 165 are removed by known etching procedures. Figure 1 The result of the etching process indicated by arrow E in Figure 1 is shown in (c).

[0077] As from Figure 1As can be seen in (d), a plurality of further layers are provided after the etching process E. This arrangement is indicated by the arrow P.

[0078] According to the exemplary embodiment described herein, the plurality of further layers comprises a first double layer stack and a second double layer stack. The first double layer stack comprises a second dielectric layer 130 and an outer electrically conductive layer 140. The second double layer stack comprises a fourth dielectric layer 170 and an additional outer electrically conductive layer 180.

[0079] It is mentioned that the second dielectric layer 130 and the outer electronically conductive layer 140 may also be separate layers before being laminated together with the other layers. The same applies to the fourth dielectric layer 170 and the further outer electronically conductive layer 180.

[0080] Thereafter, a second lamination process indicated by arrow L2 is performed. This second lamination process L2 produces Figure 1 Component carrier 100 shown in (e).

[0081] Due to the pressure required for the second lamination process L2, there is now again an image transfer from the three-dimensional first surface profile 120a to the three-dimensional second surface profile of the second main surface of the second dielectric layer 130. However, the process conditions of the first lamination process L1 and the second lamination process L2, as well as the material properties of the layer structures involved in these lamination processes L1 and L2, are selected so that the height variations of the second surface profile 130a are significantly smaller than the height variations of the first surface profile 120a. According to the embodiment described here, the height variations of the second surface profile 130a are so small that they can be ignored and thus Figure 1 Not shown in (e).

[0082] Due to the symmetrical layer structure arrangement, a corresponding further image transfer also occurs on the lower side of the base structure 110. This further image transfer occurs between the third surface profile 160a and the fourth surface profile 170a at the fourth major surface of the fourth dielectric layer 170.

[0083] It is mentioned that the component carrier 100 depicted can of course also be further processed, for example to form a printed circuit board (PCB), which is Figure 1 Such further processing may include, for example, appropriate patterning of the outer electrically conductive layer 140 and / or the further outer electrically conductive layer 180. Thus, further conductor traces may be formed within the PCB. Furthermore, such processing may include build-up with further layer structures to increase the number of layers of the PCB.

[0084] Figure 2 (a) to (e) show a method for producing a component carrier 200 according to another embodiment of the present invention.

[0085] The component carrier 200 comprises an intermediate multi-core stack 211. Figure 2 As can be seen from the exploded view of FIG. 2 ( a ), the intermediate multi-core layer stack 211 includes a multi-layer stack including a plurality of cores 212 and a plurality of inner dielectric layers 215 .

[0086] Specifically, the middle multi-core stack 211 includes two (outer) dielectric layers, a first dielectric layer 220 and a third dielectric layer 260. The core 212 is on one side, and the dielectric layers 215, 220, 260 are arranged in an alternating order on the other side. The core 212 and the dielectric layers 215, 220, 260 can be any suitable layer structure well known in PCB manufacturing. The inner dielectric layer 215 and / or the dielectric layers 220, 260 can be a prepreg layer structure.

[0087] Furthermore, a non-depicted patterned electrically conductive layer is provided on top of the upper core 212 (and below the first dielectric layer 220), the non-depicted patterned electrically conductive layer corresponding to Figure 1 Thus, below the lower core 212 (and above the third dielectric layer 260) there is provided a further patterned electrically conductive layer, not depicted, corresponding to Figure 1 (a) Another patterned electrically conductive layer 116 .

[0088] from Figure 2 It can also be seen in (b) that an auxiliary sheet 225 is provided above the middle multi-core layer stack 211. Another auxiliary sheet 265 is provided below the middle multi-core layer stack 211. Again, these auxiliary sheets 225 and 265 may be copper foil having a thickness of, for example, 105 μm.

[0089] Figure 2 (b) shows the result of the first lamination process L1. Thus, by appropriate lamination process conditions, the auxiliary sheets 225, 265 and especially the first dielectric layer 220 and the third dielectric layer 260 are attached to the other layer structures of the intermediate multi-core layer stack 211.

[0090] Thereafter, the two auxiliary sheets 225 and 265 are removed by a suitable and per se well-known etching process E. The intermediate product obtained is shown in FIG. Figure 2 (c) of the .

[0091] The manufacturing method continues to provide further layer structures. Figure 2In the method shown, a second dielectric layer 230 is provided above the middle multi-core stack 211 and an outer electrically conductive layer 240 is provided above the second dielectric layer 230. Correspondingly, a fourth dielectric layer 270 is provided below the middle multi-core stack 211 and an additional outer electrically conductive layer 280 is provided below the fourth dielectric layer 270. Figure 2 is shown in (d).

[0092] Thereafter, a second lamination process L2 is performed. This second lamination process L2 produces Figure 2 Component carrier 200 shown in (e). In the component carrier 200 described, the ridges and / or recesses caused by the image transfer effect become smaller and smaller with each additional (outer) dielectric layer of the multilayer component carrier 200 being formed.

[0093] It should be noted that the term "comprising" does not exclude other elements or steps, and the use of the article "a" or "an" does not exclude a plurality. Elements described in connection with different embodiments may also be combined. It should also be noted that reference signs in the claims should not be construed as limiting the scope of the claims.

[0094] List of reference numerals:

[0095] 100 component carriers

[0096] 110 base structure

[0097] 110a Main surface / surface contour

[0098] 110b Additional main surface / additional surface contour

[0099] 112 cores

[0100] 114 Patterned conductive layer

[0101] 116 Additional patterned electrically conductive layer

[0102] 120 first dielectric layer

[0103] 120a First major surface / first surface contour

[0104] 125 auxiliary sheet

[0105] 130 second dielectric layer

[0106] 130a Second major surface / second surface contour portion

[0107] 140 outer electrically conductive layer

[0108] 160 third dielectric layer

[0109] 160a Third major surface / third surface contour portion

[0110] 165 Additional auxiliary sheets

[0111] 170 fourth dielectric layer

[0112] 170a Fourth major surface / fourth surface contour portion

[0113] 180 Additional outer electrically conductive layer

[0114] L1 First Lamination Process

[0115] Etching process

[0116] P Set up additional layer structure

[0117] L2 Second Lamination Process

[0118] 200 component carriers

[0119] 211 Intermediate multi-core stack

[0120] 215 inner dielectric layer / prepreg layer

[0121] 220 first dielectric layer

[0122] 225 auxiliary sheet

[0123] 230 second dielectric layer

[0124] 240 External electrical conductive layer

[0125] 260 third dielectric layer

[0126] 265 Additional auxiliary sheets

[0127] 270 fourth dielectric layer

[0128] 280 Additional outer electrically conductive layer

[0129] 290 Multi-core stack-up.

Claims

1. A component carrier (100), comprising: a base structure (110) having a major surface (110a) with a surface contour; a first dielectric layer (120), the first dielectric layer (120) being formed on the main surface (110a) of the base structure (110), and the first dielectric layer (120) having a first main surface (120a) having a first surface contour, wherein the first main surface (120a) corresponds to the main surface (110a) away from the base structure (110), and wherein the first surface contour corresponds to the surface contour of the base structure (110); and a second dielectric layer (130), the second dielectric layer (130) being formed on the first major surface (120a), and the second dielectric layer (130) having a second major surface (130a) having a second surface profile, wherein the second major surface (130a) corresponds to the major surface (110a) remote from the base structure (110), wherein the second surface profile is different from the surface profile of the base structure, and The process conditions of the first lamination process (L1) for forming the first dielectric layer (120) on the main surface (110a) of the base structure (110) and the second lamination process (L2) for forming the second dielectric layer (130) on the first main surface (120a) and / or the material properties of the layer structures involved in the first lamination process (L1) and the second lamination process (L2) are selected so that: the height variation of the second surface contour portion is significantly smaller than the height variation of the first surface contour portion.

2. The component carrier (100) according to claim 1, wherein The base structure (110) comprises a core (112) and a stack comprising at least one electrically conductive layer structure and / or at least one electrically insulating layer structure.

3. The component carrier (100) according to claim 2, wherein The stack includes a patterned electrically conductive layer (114) defining the major surface (110a) of the base structure (110), wherein the surface contour of the base structure (110) is defined by the patterned electrically conductive layer (114).

4. The component carrier (100) according to claim 3, wherein The patterned electrically conductive layer (114) is a patterned metal layer.

5. The component carrier (100) according to claim 1, further comprising: An outer electrically conductive layer (140) is formed on the second dielectric layer (130).

6. The component carrier (100) according to claim 1, wherein The first dielectric layer (120) has a first thickness and the second dielectric layer (130) has a second thickness, wherein the first thickness is the same as the second thickness, or wherein the first thickness is different from the second thickness.

7. The component carrier according to claim 1, wherein: At least one of the first dielectric layer (120) and the second dielectric layer (130) includes a resin and a solid object within the resin.

8. The component carrier (100) according to claim 7, in, The first dielectric layer (120) comprises the solid objects unevenly distributed on the first major surface (120a), and / or The second dielectric layer (130) includes the solid objects uniformly distributed on the second main surface (130a).

9. The component carrier (100) according to claim 7 or 8, wherein The solid objects are reinforcing fibers and / or filler particles.

10. The component carrier (100) according to claim 1, wherein The variation of the thickness of the component carrier (100) divided by the average thickness of the component carrier (100) is less than 5%.

11. The component carrier (100) according to claim 1, wherein The base structure (110) has a further main surface (110b) with a further surface contour, wherein the further main surface (110b) is opposite to the main surface (110a); The component carrier (100) further comprises: a third dielectric layer (160), the third dielectric layer (160) being formed on the further main surface (110b) of the base structure (110), and the third dielectric layer (160) having a third main surface (160a) with a third surface contour, wherein the third main surface (160a) corresponds to the further main surface (110b) away from the base structure (110), and wherein the third surface contour corresponds to the further surface contour of the base structure (110); and A fourth dielectric layer (170) is formed on the third major surface (160a), and the fourth dielectric layer (170) has a fourth major surface (170a) with a fourth surface profile, wherein the fourth major surface (170a) corresponds to the additional major surface (110b) away from the base structure (110), and wherein the fourth surface profile is different from the additional surface profile of the base structure (110).

12. A method for producing a component carrier (100) according to any one of claims 1 to 11, the method comprising: providing a base structure (110) having a major surface (110a); pressing an at least partially uncured first dielectric layer (120) together with an auxiliary sheet (125) onto the main surface (110a) of the base structure (110); removing the auxiliary sheet (125) from the first dielectric layer (120); as well as An at least partially uncured second dielectric layer (130) is pressed onto the first dielectric layer (120).

13. The method according to claim 12, wherein: The auxiliary sheet (125) includes at least one of a copper sheet, a ceramic sheet, and a glass sheet.

14. The method according to claim 12, wherein: An outer electrically conductive layer (140) is pressed onto the first dielectric layer (120) together with the second dielectric layer (130).

15. The method according to claim 14, wherein The outer electrically conductive layer (140) is a copper structure.

16. The method according to claim 15, wherein The copper structure has a thickness of less than 40 μm.

17. The method according to claim 12, wherein: The base structure (110) has a further main surface (110b), wherein the further main surface (110b) is opposite to the main surface (110a); The method further comprises: Pressing an at least partially uncured third dielectric layer (160) together with an additional auxiliary sheet (165) onto the additional main surface (110b) of the base structure (110) while pressing the at least partially uncured first dielectric layer (120); removing the further auxiliary sheet (165) from the third dielectric layer (160); and While pressing the at least partially uncured second dielectric layer (130), the at least partially uncured fourth dielectric layer (170) is pressed onto the third dielectric layer (160).

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