Voltage regulating integrated circuits (ICs) having circuit components in integrated three-dimensional (3D) inductor cores and related methods of manufacture

Abstract

Space occupied by an inductor is shared with other circuit components and structural layers of a voltage regulation integrated circuit (IC) by implementing the inductor as a 3D inductor having windings formed by conductive elements integrated into a lower substrate, a circuit layer, and an upper substrate, and positioning other components within a core space of the 3D inductor in the circuit layer. The space occupied by the inductor is shared with other circuit components and structural layers of a voltage regulation IC. The voltage regulation IC can be a switch mode power supply (SMPS) including an inductor with a capacitor and / or a switching circuit. The inductor is implemented as an upper horizontal trace in an upper substrate, a lower horizontal trace in a lower substrate, and a vertical interconnect in a circuit layer between the upper substrate and the lower substrate, and these conductive elements form a 3D inductor as a rectangular coil.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to non-provisional application No. 16 / 804474, filed on February 28, 2020, entitled “VOLTAGE REGULATION INTEGRATE DCIRCUIT (IC) WITH CIRCUIT COMPONENTS IN AN INTEGRATED THREEDIMENSIONAL (3D) INDUCTOR CORE AND RELATED METHODS OF FABRICATION”, which has been assigned to the assignee of this application and is hereby expressly incorporated herein by reference. Technical Field

[0003] The scope of this disclosure relates to the miniaturization of electronic circuits, and more specifically, to reducing the amount of space occupied by integrated circuits used for voltage regulation. Background Technology

[0004] In response to consumer demand, electronic devices have become smaller, faster, and more energy-efficient over time. This trend has been made possible by technological improvements to the integrated circuits (ICs) within electronic devices. ICs are designed to operate at a specific operating voltage for normal function. ICs consume power based on several factors, including the voltage at which they operate. ICs receive power from a power source in the electronic device, such as a battery or an adapter connected to an alternating current (AC) power supply. The power source provides power at a specific voltage, but the voltage required by a particular IC from the power supply may differ from the voltage provided by the power source. Therefore, electronic devices include voltage regulation circuitry to convert the power signal from a first voltage at the power supply to a second voltage required by the IC.

[0005] A type of voltage regulation circuit used to convert power to direct current (DC) power supplies with a desired voltage level is called a switch-mode power supply (SMPS). Different types of SMPS have been developed to convert AC signals to DC signals, and to convert DC signals at a first voltage level to DC signals at a higher or lower voltage level. Voltage regulation circuits include capacitors and switching circuits, which, like other circuits in electronic devices, may need to be miniaturized according to trends. The physical size of circuit components depends on circuit requirements, and as technology advances, these requirements allow for a gradual reduction in the size of components specific to a particular technology. However, in electronic devices, the need to reduce the size of voltage regulation circuits may require changes to existing component technologies. Summary of the Invention

[0006] The aspects disclosed herein include a voltage-regulating integrated circuit (IC) having circuit components arranged within an integrated three-dimensional (3D) inductor core. Related methods for manufacturing the voltage-regulating IC are also disclosed. Reducing the space occupied by the voltage-regulating IC, including the inductor, is achieved through a two-part approach. Instead of positioning the surface-mount inductor on the top surface of the substrate (e.g., in a package layer), the inductor is implemented as a 3D inductor having a winding formed by conductive elements integrated into a lower substrate, a circuit layer, and an upper substrate. Furthermore, instead of mounting other circuit components of the voltage-regulating IC near the surface-mount inductor on the substrate, the other components are positioned within the core space of the 3D inductor in the circuit layer. In this respect, the space occupied by the inductor is shared with other circuit components and the structural layers of the voltage-regulating IC, resulting in a smaller footprint width and a smaller height.

[0007] In one example, the voltage regulating IC may be a switch-mode power supply (SMPS) that converts a received power supply signal into a direct current (DC) signal having the voltage required to power an IC in an electronic device. The voltage regulating IC includes an inductor and other circuit components such as capacitors and / or switching circuitry. In an exemplary aspect disclosed herein, the inductor is implemented as a 3D inductor formed of conductive elements including an upper horizontal trace in an upper substrate, a lower horizontal trace in a lower substrate, and vertical interconnects in a circuit layer. The vertical interconnects extend between the upper and lower substrates, and these conductive elements together form a 3D inductor as a rectangular coil extending longitudinally between the upper and lower substrates in a first direction.

[0008] By employing a 3D inductor integrated into a voltage regulator IC and arranging other circuit components within the core space of the integrated 3D inductor, the inductor cross-section can be increased to provide the desired inductance increase, while reducing the height and footprint of the voltage regulator IC. Inductance can be further increased by incorporating magnetic materials to enhance the permeability of the 3D inductor's core space. For this purpose, a magnetic layer is arranged on the sides of the circuit components within the core space, and a magnetic thin film can be integrated into the upper substrate within the core space.

[0009] In this regard, on the one hand, a voltage regulation IC is disclosed. The voltage regulation IC includes: an upper substrate including a plurality of upper horizontal traces; a lower substrate below the upper substrate and including a plurality of lower horizontal traces; and a circuit layer between the upper and lower substrates. The circuit layer includes: a plurality of first vertical interconnects, each first vertical interconnect coupled to a first end of one of the plurality of upper horizontal traces and a first end of one of the plurality of lower horizontal traces; and a plurality of second vertical interconnects, each second vertical interconnect coupled to a second end of one of the plurality of upper horizontal traces and a second end of one of the plurality of lower horizontal traces. The circuit layer also includes one or more circuit components and a 3D inductor, the one or more circuit components being disposed on the lower substrate, the 3D inductor being electrically coupled to at least one of the one or more circuit components. The 3D inductor includes a coil extending along a longitudinal axis, the cross-section of the coil orthogonal to the longitudinal axis including at least one of the one or more circuit components.

[0010] On the other hand, a method for manufacturing a voltage regulation IC is disclosed. The method includes: forming an upper substrate including a plurality of upper horizontal traces; forming a lower substrate including a plurality of lower horizontal traces; and forming a circuit layer. Forming the circuit layer includes: arranging one or more circuit components on the surface of the lower substrate, in a region including the plurality of lower horizontal traces; forming a molding compound over the one or more circuit components; and forming a plurality of first vertical interconnects and a plurality of second vertical interconnects in the molding compound, wherein the bottom end of each of the plurality of first and second vertical interconnects is coupled to one of the plurality of lower horizontal traces in the lower substrate. The method further includes: arranging the upper substrate on the circuit layer such that each of the plurality of upper horizontal traces is coupled to one of the plurality of first vertical interconnects and one of the plurality of second vertical interconnects in the circuit layer, and the plurality of upper horizontal traces, the plurality of first vertical interconnects, the plurality of lower horizontal traces, and the plurality of second vertical interconnects form a 3D inductor. Attached Figure Description

[0011] Figure 1 This is a cross-sectional side view of a conventional switch-mode power supply (SMPS) voltage regulation circuit, which includes capacitors, inductors, and switching circuitry mounted on a substrate on a printed circuit board (PCB).

[0012] Figure 2This is a cross-sectional side view of another SMPS voltage regulation circuit, which includes a switching circuit and an inductor mounted on the top surface of the substrate, wherein a capacitor is mounted on the bottom surface of the substrate to interact with... Figure 1 Compared to the SMPS voltage regulation circuit, it occupies less area.

[0013] Figure 3 yes Figure 2 A cross-sectional side view of the SMPS voltage regulation circuit, which uses an inductor smaller than usual to achieve the maximum height target for the SMPS voltage regulation circuit;

[0014] Figure 4 This is a perspective view of an example rectangular coil that forms a three-dimensional (3D) inductor not integrated into a layer of an integrated circuit (IC).

[0015] Figure 5 This is a perspective view of another example of a rectangular coil forming a 3D inductor;

[0016] Figure 6 yes Figure 5 A perspective view of a rectangular coil, which includes a plate of magnetic material in the core space of the rectangular coil to increase inductance;

[0017] Figure 7 This is a cross-sectional side view of an exemplary voltage regulation IC, which includes active circuit components and capacitors arranged within the core space of a 3D inductor, which is integrated into the layers of the voltage regulation IC to reduce height and footprint width.

[0018] Figure 8 The diagram illustrates the manufacturing process. Figure 7 A flowchart of the voltage regulation IC method in the process;

[0019] Figure 9 yes Figure 7 The illustration shows an exemplary voltage regulation IC in the longitudinal direction of a 3D inductor through a cross section of vertical interconnects, each of which forms one side of a winding of a rectangular coil.

[0020] Figure 10 yes Figure 7 The voltage regulation IC is shown as a cross-sectional side view of a field-replaceable unit mounted on a PCB with solder ball connectors.

[0021] Figure 11 This is a block diagram of an exemplary processor-based system that may include: a voltage regulation IC having a 3D inductor integrated into a structural layer of the voltage regulation IC; and circuit elements arranged within the core space of the 3D inductor to reduce height and footprint width, such as... Figure 7 and 10 Any one of them shown; and

[0022] Figure 12 This is a block diagram of an exemplary wireless communication device, which includes a radio frequency (RF) component formed by an IC, including: a voltage regulation IC having a 3D inductor integrated into a structural layer of the voltage regulation IC; and circuit elements arranged within the core space of the 3D inductor to reduce height and occupied area width, such as... Figure 7 and 10 Any one of them is shown. Detailed Implementation

[0023] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0024] The aspects disclosed herein include a voltage-regulating integrated circuit (IC) having circuit components arranged within an integrated three-dimensional (3D) inductor core. Related methods for manufacturing the voltage-regulating IC are also disclosed. Reducing the space occupied by the voltage-regulating IC, including the inductor, is achieved through a two-part approach. Instead of positioning the surface-mount inductor on the top surface of the substrate (e.g., in a package layer), the inductor is implemented as a 3D inductor having a winding formed by conductive elements integrated into a lower substrate, a circuit layer, and an upper substrate. Furthermore, instead of mounting other circuit components of the voltage-regulating IC near the surface-mount inductor on the substrate, the other components are positioned within the core space of the 3D inductor in the circuit layer. In this respect, the space occupied by the inductor is shared with other circuit components and with the structural layers of the voltage-regulating IC, resulting in a smaller footprint width and a smaller height.

[0025] In one example, the voltage regulating IC may be a switch-mode power supply (SMPS) that converts a received power supply signal into a direct current (DC) signal having the voltage required to power an IC in an electronic device. The voltage regulating IC includes an inductor and other circuit components such as capacitors and / or switching circuitry. In an exemplary aspect disclosed herein, the inductor is implemented as a 3D inductor formed of conductive elements including: a plurality of upper horizontal traces in an upper substrate, a plurality of lower horizontal traces in a lower substrate, and a plurality of vertical interconnects in a circuit layer. The plurality of vertical interconnects extend between the upper and lower substrates, and these conductive elements together form a 3D inductor as a rectangular coil extending longitudinally between the upper and lower substrates in a first direction.

[0026] By employing a 3D inductor integrated into the voltage regulator IC and arranging other circuit components within the core space of the integrated 3D inductor, the inductor cross-section can be increased to provide the desired increase in inductance, while reducing the height and footprint of the voltage regulator IC. Inductance can be further increased by incorporating magnetic materials to increase the permeability of the 3D inductor's core space. For this purpose, a magnetic layer is arranged on the sides of the circuit components within the core space, and a magnetic thin film can be integrated into the upper substrate within the core space.

[0027] Figures 1 to 3 It is shown that the inductor size requirement is an important factor in determining the dimensions of the SMPS voltage regulation circuits 100, 200, and 300, and these dimensions cannot be reduced without a solution to effectively address the space occupied by the inductors.

[0028] Figure 1 This is an illustration of a cross-sectional side view of an SMPS voltage regulation circuit (“SMPS circuit”) 100, which includes a switching circuit 102, a capacitor 104, and an inductor 106 as discrete circuit components attached to a substrate 108 via, for example, a surface mount technology (SMT) process. The substrate 108 includes vertical and horizontal interconnects between the circuit components and interconnects to a printed circuit board (PCB) 110 on which the substrate 108 is mounted. The dimensions of the capacitor 104 and the inductor 106 are determined at least in part by the electrical requirements of the SMPS circuit 100. Therefore, the vertical height H of the SMPS circuit 100... 100 The thickness T of substrate 108 SUB1 and the height H of the inductor 106 mounted on the substrate 108 IND1 Confirmed. The area width W occupied by the SMPS circuit 100 is [not specified]. FP1 The width dimensions are determined by the capacitor 104, inductor 106, and switching circuit 102 mounted on substrate 108. The first connector 112 of the SMPS circuit 100 on PCB 110. SRC The device receives a first (e.g., higher) voltage V. IN The DC power supply signal, and the second (e.g., lower) voltage V OUT The DC signal at the location is supplied to the second connector 112 on PCB 110. LD The SMPS circuit 100 can be, for example, a buck converter, a boost converter, or another type of voltage regulation circuit.

[0029] For illustrative purposes, a buck converter is described as an example of an SMPS circuit 100. The buck converter includes a switching circuit and a resonant (LC) circuit formed by an inductor 106 and a capacitor 104. The switching circuit receives an input DC signal at a first (i.e., higher) voltage from a power supply and switches periodically according to a duty cycle to provide or not provide the input DC signal to the LC circuit. The LC circuit provides an output DC signal at a second (i.e., lower) voltage to the load circuit according to the input DC signal and the duty cycle. The operational details of the voltage converter circuit are well known and are not relevant to this disclosure, and therefore will not be presented herein. However, the physical dimensions of the inductor 106 depend on the electrical requirements of the SMPS circuit 100. Although the inductor 106 is discussed in the context of a buck converter, the principles disclosed herein can be applied to other SMPS circuits.

[0030] The required inductance (L) of the inductor in the buck converter can be calculated using the following equation:

[0031] L=((V IN -V OUT )×D CY ) / (f SW ×Δ iL ),in:

[0032] V IN =Input voltage;

[0033] V OUT = Output voltage;

[0034] D CY =Duty cycle;

[0035] f SW = Switching frequency; and

[0036] Δ iL = Changes in inductor current.

[0037] According to the above equation, the inductance (L) of the inductor in the buck converter and the switching frequency (f) at which the buck converter switches at that point are related. SW It is inversely proportional to the switching frequency (f) of the processing circuit. That is, as the switching frequency (f) of the processing circuit increases... SW As the switching frequency (f) increases, the inductance required in the buck converter supplying DC voltage to the processing circuit decreases. Therefore, assuming other variables remain constant, as load circuits in electronic devices tend towards faster clock speeds, the inductance requirement of the buck converter supplying DC voltage to the load circuit will decrease. Since the inductance of an inductor depends directly on the diameter and number of its windings or turns (i.e., a larger diameter and more windings provide greater inductance), and the inductance requirement increases with the switching frequency (f... SWThe diameter and length of the inductor decrease over time as the overall size increases, allowing for the use of smaller inductors in the future. Nevertheless, the diameter and length (i.e., the overall volume) of the inductor remain important factors in the size of existing voltage regulation ICs.

[0038] Based on the above equation regarding inductance (L), when the IC clock frequency increases from approximately 3.2 MHz to approximately 30 MHz, the required inductance in the SMPS circuit 100 will decrease from approximately 500 nanohenries (nH) to approximately 50 nH. However, at the current clock frequency, the height H of the inductor 106 used in the SMPS circuit 100... IND1 Within a range of approximately one millimeter (1 mm). It is only when much higher circuit switching frequencies become possible that the height H of inductor 106 can be significantly reduced. IND1 Therefore, the total height of the SMPS circuit 100 is well over 600 micrometers (μm), which is the design target for the voltage regulation IC.

[0039] Figure 2 This is a cross-sectional side view of the SMPS circuit 200, which is another configuration of the voltage regulation IC. Figure 1 and Figure 2 The illustrations are at different scales, as shown by the corresponding sizes of switch circuits 102 and 202. At this point, it can be recognized that the SMPS circuit 200 has the same... Figure 1 The SMPS circuit 100 occupies a width W of area. FP1 Compared to the reduced occupied area width W FP2 .

[0040] exist Figure 2 In the middle, the switching circuit 202 and the inductor 204 are mounted on the top surface 206 of the substrate 206. TOP Meanwhile, capacitor 208 is disposed between substrate 206 and PCB 210 on the bottom surface 206 of substrate 206. BOT Above. In Figure 2 In the configuration, by means of the top surface 206 of the substrate 206 TOP and bottom surface 206 BOT Install components on top to make more efficient use of space. Therefore, it has... Figure 1 The voltage-regulated SMPS circuit 200 of the SMPS circuit 100 can utilize a ratio Figure 1 The occupied area width W FP1 Smaller footprint width W FP2 To achieve this. However, Figure 2 The minimum height H of the SMPS circuit 200 in 200 The height H of inductor 204 is still at least IND2 With the thickness T of substrate 206 SUB2The sum of . Therefore, with Figure 1 Compared to the SMPS circuit 100, the SMPS circuit 200 has a smaller footprint but does not have a reduced height.

[0041] Figure 3 This is a cross-sectional side view of an SMPS circuit 300 having an inductor 302, a switching circuit 304, and a capacitor 306. Figure 3 Also with Figure 1 Draw at different scales. Figure 3 The SMPS circuit 300 in the middle includes a reduced footprint width W on the PCB 310. FP3 The substrate 308 is similar to Figure 2 The SMPS circuit 200 in the middle. Additionally, with... Figure 2 In comparison, the height H of inductor 302 IND3 The height is reduced, therefore, according to the design objectives, the SMPS circuit 300 can have the desired height H. 300 However, due to the height H of inductor 302 IND3 The inductance of inductor 302 is reduced, and it is insufficient to meet the circuit requirements at the current switching frequency of the electronic circuit.

[0042] therefore, Figures 1 to 3 This demonstrates that it is impossible to achieve this in circuits that can still provide sufficient functionality in current electronic circuits. Figure 1 The SMPS circuit 100 in the middle occupies less area and has a smaller height.

[0043] The solution disclosed in this article involves replacing the 3D inductor. Figures 1 to 3 The surface-mount inductor shown is a 3D inductor that can provide the inductance required by the SMPS circuit and has the ability to be integrated into the reference below. Figure 7 The structure of the voltage regulation IC in the layers is described. In the discussion... Figure 7 Before discussing the details of the voltage regulation IC, in Figures 4 to 6 An example of a 3D inductor is introduced in the paper.

[0044] When a conductor is formed into a circle, the inductance of a straight conductor (such as a wire) increases. A conductor that is continuously wound in a tubular shape around a core has a strong inductance and is referred to herein as a 3D inductor, and may also be called a 3D solenoid inductor. Figure 4This is a perspective view of a rectangular coil 400 used to form a 3D inductor 402 (“inductor 402”). The rectangular coil 400 is formed by windings 404 having a rectangular cross-section with an approximately tubular structure. Each winding 404 of the rectangular coil 400 extends one turn around the core space CS4 of the rectangular coil 400, and the axis A4 of the core space CS4 extends in the longitudinal direction. The rectangular coil 400 is a series of conductive horizontal traces and vertical interconnects electrically coupled to form a single continuous conductor starting at a first terminal 407. The first terminal 407 is connected to the top end of a left vertical interconnect 408A(1). The bottom end of the left vertical interconnect 408A(1) is coupled to the left end of a lower horizontal trace 410L(1). The right end of the lower horizontal trace 410L(1) is coupled to the bottom end of a right vertical interconnect 408B(1). The top end of the right vertical interconnect 408B(1) is coupled to the right end of the upper horizontal trace 410U(1), and the left end of the upper horizontal trace 410U(1) is coupled to the left vertical interconnect 408A(2) adjacent to the first terminal 407, thus completing the first winding 404.

[0045] The next winding 404 of the rectangular coil 400 is formed by a next left vertical interconnect 408A(2), a next lower horizontal trace 410L(2), a next right vertical interconnect 408B(2), and a next upper horizontal trace 410U(2). The left vertical interconnects 408A(1) to 408A(N) are arranged parallel to each other in the left vertical row 408A. The lower horizontal traces 410L(1) to 410L(N) are arranged parallel to each other in the lower horizontal row 410L. The right vertical interconnects 408B(1) to 408B(N) are arranged parallel to each other in the right vertical row 408B, and the upper horizontal traces 410U(1) to 410U(N) are arranged parallel to each other in the upper horizontal row 410U. Each of rows 408A, 410L, 408B, and 410U extends longitudinally along axis A4 of rectangular coil 400. The other end of rectangular coil 400 is the second terminal 412 of inductor 402. The inductance of inductor 402 is based on the number of windings 404, the length of rectangular coil 400 along axis A4, the dimensions of windings 404, and other factors. Due to these factors, the inductance is related to the number of windings 404, the length of rectangular coil 400 along axis A4, the dimensions of windings 404, and other factors. Figure 5 Compared to the rectangular coil 500 shown, inductor 402 will have a different inductance. Another factor determining the inductance of inductors 402 and 502 is the permeability of the air occupying the core spaces CS4 and CS5. The permeability of the core material is a factor determining the strength of the magnetic field generated by the inductor, which in turn determines the inductance of the inductor.

[0046] Figure 6 It shows the relationship with Figure 5The rectangular coil 500 is similar to the rectangular coil 600, in which magnetic material plates 602A and 602B replace some of the air in the core space CS6. Compared to the air occupying the core space CS5, the magnetic material of plates 602A and 602B has a higher permeability. Therefore, Figure 6 The inductor 602, which includes magnetic material plates 602A and 602B, will have a higher performance than... Figure 5 The inductor 502, which has an air core, has a larger inductance. Therefore, adding magnetic material to the core space of an inductor can be used to increase the inductance of a rectangular coil of a given size, or to reduce the size of the inductor coil but still provide the same inductance as a larger coil.

[0047] Figure 7 This is a cross-sectional side view of an exemplary voltage regulation IC 700, including a switching circuit 702 and a capacitor 704. The voltage regulation IC 700 is an example of a 3D inductor integrated into the structural layer of the voltage regulation IC, wherein other circuit components are arranged within the core space of the 3D inductor to provide a voltage regulation circuit with a smaller footprint and lower height compared to a functionally equivalent circuit of discrete components mounted on a substrate.

[0048] Switching circuit 702 and capacitor 704 are collectively referred to as "circuit components 702, 704". Switching circuit 702 can be a circuit used to control the switching of a power supply signal to an LC circuit according to a duty cycle. In this respect, controlling the power supply signal means switching between providing and not providing a power supply signal. Switching circuit 702 can also be any logic circuit used in a voltage regulation circuit. To reduce the size of voltage regulation IC 700, the space occupied by switching circuit 702, capacitor 704 and 3D inductor 706 is overlapped by arranging circuit components 702, 704 within the core space CS7 of 3D inductor 706. This can be achieved by integrating 3D inductor 706 into layer 708, which is the structural layer of voltage regulation IC 700. Figure 7 This is a cross-sectional side view of the voltage regulator IC 700 in a plane including the horizontal X-axis and the vertical Y-axis, wherein the vertical axis A7 of the voltage regulator IC 700 is in the Z-axis direction.

[0049] Figure 1 The height H of the SMPS circuit 100 in the middle 100 Including the height H of inductor 106 IND1 and the thickness T of the substrate 108 on which the inductor 106 is mounted. SUB1 In contrast, Figure 7 In the voltage regulation IC 700, the 3D inductor 706 is integrated into the lower substrate 708L below the circuit components 702 and 704. The height H of the inductor 706 is... IND7Thickness T of the lower substrate 708L SUB7 Vertical overlap. Therefore, the height H of the voltage regulation IC 700 is... 700 The thickness T can be less than that of the lower substrate 708L. SUB7 Height H of inductor 706 IND7 The sum of. Therefore, if the inductor height H in the voltage regulation IC 700 IND7 and Figure 1 The height H of the inductor 106 in the SMPS circuit 100 IND1 If they are the same, then the height H of the voltage regulation IC 700 is... 700 The height H can be less than 100 of the SMPS circuit. 100 Alternatively, if the inductor height H in the voltage regulation IC 700 is made... IND7 Compare Figure 1 The height H of the inductor 106 in the SMPS circuit 100 is... IND1 Much larger, to provide a larger inductance, the height H of the voltage regulation IC 700 700 It can be used with the height H of the SMPS circuit 100 100 same.

[0050] also, Figure 1 The SMPS circuit 100 occupies a width W of area. FP1 Based on the combined width of the respective circuit components 102, 104, and 106 mounted on the substrate 108. In contrast, Figure 7 The switching circuit 702 and capacitor 704 are arranged within the core space CS7 of the 3D inductor 706, which is integrated into layer 708 of the voltage regulator IC 700. Therefore, the occupied area width W of the voltage regulator IC 700 is... FP7 Based on the width of the switching circuit 702 and capacitor 704, plus a slight increase in the width of the vertical segment for the 3D inductor 706, the core space CS7 of the 3D inductor 706 in the voltage regulator IC 700 can thus have a larger cross-section (providing greater inductance) than that of the inductor 106, while the occupied area width W of the voltage regulator IC 700 is reduced. FP7 equal to or less than Figure 1 The SMPS circuit 100 occupies a width W of area. FP1 .

[0051] therefore, Figure 7 The voltage regulation IC 700, which includes an integrated 3D inductor 706, can have different ratios. Figure 1 The height H of the SMPS circuit 100 in the middle 100 and the area occupied by the width W FP1 Small height H 700 and the area occupied by the width W FP7However, this does not reduce the inductance.

[0052] Structurally, the voltage regulation IC 700 includes: an upper substrate 708U, including a plurality of upper horizontal traces 710U; a lower substrate 708L, located below the upper substrate 708U, including a plurality of lower horizontal traces 710L; and a circuit layer 708C, located between the upper substrate 708U and the lower substrate 708L. The circuit layer 708C includes a plurality of first vertical interconnects 712A and a plurality of second vertical interconnects 712B. Each of the plurality of first vertical interconnects 712A is coupled to a first end of an upper horizontal trace in the upper horizontal trace 710U and to a first end of a lower horizontal trace in the lower horizontal trace 710L. Each of the plurality of second vertical interconnects 712B is coupled to a second end of an upper horizontal trace in the upper horizontal trace 710U and to a second end of a lower horizontal trace in the lower horizontal trace 710L.

[0053] Circuit layer 708C also includes one or more circuit components of circuit assemblies 702 and 704. 3D inductor 706 is electrically coupled to at least one of the circuit components 702 and 704. 3D inductor 706 includes a coil 716 extending along a longitudinal axis A7. A cross-section of coil 716 orthogonal to the longitudinal axis A7 includes at least one of the circuit components 702 and 704. Coil 716 includes a winding 718 surrounding circuit assemblies 702 and 704 (i.e., above, below, and on both sides of circuit assemblies 702 and 704). Winding 718 is formed by an upper horizontal trace 710U, a first vertical interconnect 712A, a lower horizontal trace 710L, and a second vertical interconnect 712B. Contact 714U is formed in the upper substrate 708U to contact the bottom surface 708U of the upper substrate 708U at the end of the upper horizontal trace 710U. BOT They extend vertically between each other. Contact 714L is also formed at the end of the lower horizontal trace 710L and on the top surface 708L of the lower substrate 708L. TOP In the lower substrate 708L between.

[0054] The lower substrate 708L includes contacts 714L to provide access to the top surface 708L. TOP The connector between capacitor 704 and switching circuit 702. Bottom surface 708L BOTThis includes connectors configured to couple circuit components 702, 704 to external circuitry (such as a PCB). Upper horizontal trace 710U and lower horizontal trace 710L are conductive and can be formed within upper substrate 708U and lower substrate 708L, respectively. Upper horizontal trace 710U and lower horizontal trace 710L can be linear and planar, but can also be non-planar and / or non-linear conductive traces. Upper horizontal trace 710U and lower horizontal trace 710L, as well as upper contact 714U and lower contact 714L, can be formed of a metal (such as aluminum or copper) or another metal or conductive material. Upper horizontal trace 710U and lower horizontal trace 710L can be formed from copper layers in the upper and lower substrates using, for example, known photolithography processes.

[0055] Each of the first vertical interconnects 712A couples an end of an upper horizontal trace in the upper horizontal trace 710U to an end of a lower horizontal trace in the lower horizontal trace 710L. Each of the second vertical interconnects 712B couples the other end of an upper horizontal trace in the upper horizontal trace 710U to the other end of a lower horizontal trace in the lower horizontal trace 710L. More specifically, the first vertical interconnects 712A and the second vertical interconnects 712B extend between a contact 714U in the upper substrate 708U and a contact 714L in the lower substrate 708L. Therefore, the first vertical interconnects 712A and the second vertical interconnects 712B are coupled to the upper horizontal trace 710U and the lower horizontal trace 710L via contacts 714U and 714L.

[0056] Vertical interconnects 712A and 712B, upper horizontal trace 710U, lower horizontal trace 710L, and contacts 714U and 714L are sequentially connected to form coil 716, similar to... Figures 4 to 6 The coil shown is coil 716. Coil 716 is formed by winding 718 and has a core space CS7. The longitudinal axis A7 of the core space CS7 is... Figure 7The winding 718 extends in the Z-axis direction. Specifically, the winding 718 can be formed starting from one of the vertical interconnects 712A. The first vertical interconnect 712A is coupled to a first end (e.g., the left end) of the first upper horizontal trace 710U via a first contact 714U and to a first end of the first lower horizontal trace 710L via a contact 714L. One of the vertical interconnects 712B is coupled to a second end (e.g., the right end) of the first lower horizontal trace 710L via a second contact 714L and to a second end of the second upper horizontal trace 710U (not shown) via a second contact 714U. The second upper horizontal trace 710U is adjacent to the first upper horizontal trace 710U. In this respect, "adjacent to" means the next upper horizontal trace 710U corresponding to the next winding 718 of the coil 716 in the longitudinal axis A7 direction. The first end of the second upper horizontal trace 710U is coupled to another vertical interconnect (not shown) in the first vertical interconnect 712A, and so on.

[0057] Circuit components 702 and 704 can be arranged within the core space CS7 of the 3D inductor 706 in a cross-section orthogonal to the vertical axis A7. The cross-section of the 3D inductor 706 may include the capacitor 704 and the switching circuit 702. Alternatively, circuit components 702 and 704 can be arranged within the core space CS7 of the 3D inductor 706 in a first cross-section parallel to the vertical axis A7. In other words, the cross-section of the 3D inductor 706 may include only one of the capacitor 704 and the switching circuit 702.

[0058] The core space CS7 of the 3D inductor 706 in the voltage regulation IC 700 occupies space within each of the upper substrate 708U, the lower substrate 708L, and the circuit layer 708C. The core space CS7 within the lower substrate 708L includes metal traces and interconnects for coupling circuit components 702 and 704 to each other, to the 3D inductor 706, and to external circuitry or a PCB (not shown). Figure 10 (As shown in the diagram). Because of the presence of these traces and interconnects in the lower substrate 708L, it will be difficult to add magnetic material to the lower substrate 708L for the purpose of increasing magnetic permeability.

[0059] In circuit layer 708C, switching circuit 702 and capacitor 704 are mounted on the top surface 708L of the lower substrate 708L. TOPThe circuit components 702 and 704 are mounted onto the lower substrate 708L, and occupy some of the core space in the core space CS7. After mounting the circuit components 702 and 704 onto the lower substrate 708L, a molding compound MC is added to form the circuit layer 708C. The molding compound MC is provided for structural support and is not a magnetic material. Therefore, to increase the permeability of the core space CS7 within the circuit layer 708C, some of the molding compound MC can be replaced by a magnetic material. In this regard, before adding the molding compound MC, a magnetic layer 720C is formed on the top and vertical sides of the capacitor 704 within the circuit layer 708C, and a magnetic layer 720S is formed on the top and vertical sides of the switching circuit 702. After the molding compound MC is added and planarized, a first vertical interconnect 712A and a second vertical interconnect 712B are formed as vias through the molding compound MC. The first vertical interconnect 712A and the second vertical interconnect 712B can be formed using known processes for via formation.

[0060] The upper substrate 708U includes the upper horizontal trace 710U, but does not include the upper horizontal trace 710U and the bottom surface 708U of the upper substrate 708U. BOT Any traces or interconnects between them. The upper substrate 708U is not formed of magnetic material. Therefore, the permeability of the core space CS7 can be further increased by including a magnetic thin film layer 722 formed of at least one layer of magnetic material within the upper substrate 708U. The magnetic thin film layer 722 is formed on the upper row of the upper horizontal traces 710U and coupled to the bottom surface 708U of the upper substrate 708U. BOT Between the circuit layers 708C. The magnetic thin film layer 722 can be formed of one or more magnetic materials, including cobalt tantalum zirconium (CoTaZr) and nickel iron (NiFe) separated by silicon dioxide (SiO2) or other oxide thin film layers. The magnetic thin film layer 722 can be covered with a polymer planarization layer (not shown).

[0061] Figure 8 The diagram illustrates the manufacturing process. Figure 7 A flowchart of an exemplary method 800 for a voltage regulation IC 700 is provided. Method 800 includes: forming an upper substrate 708U (block 802) including a plurality of upper horizontal traces 710U; and forming a lower substrate 708L (block 804) including a plurality of lower horizontal traces 710L. The method includes forming a circuit layer 708C (block 806), the circuit layer 708C including: on the top surface 708L of the lower substrate 708L... TOPThe method 800 further includes: arranging one or more circuit components 702, 704 on a region including a plurality of lower horizontal traces 710L (box 808); forming a molding compound MC above the one or more circuit components 702, 704 (box 810); and forming a plurality of first vertical interconnects 712A and a plurality of second vertical interconnects 712B in the molding compound MC, the bottom end of each of the plurality of first vertical interconnects 712A and the plurality of second vertical interconnects 712B being coupled to one of the plurality of lower horizontal traces 710L in the lower substrate 708L (box 812). The method 800 also includes: arranging an upper substrate 708U on a circuit layer 708C such that each of the plurality of upper horizontal traces 710U is coupled to one of the plurality of first vertical interconnects 712A and the plurality of second vertical interconnects 712B in the circuit layer 708C. Arranging an upper substrate 708U on circuit layer 708C includes coupling each of a plurality of upper horizontal traces 710U to one of a plurality of first vertical interconnects 712A and to one of a plurality of second vertical interconnects 712B, such that the plurality of upper horizontal traces 710U, the plurality of first vertical interconnects 712A, the plurality of lower horizontal traces 710L, and the plurality of second vertical interconnects 712B form a 3D inductor 706 (block 814). The 3D inductor 706 includes a coil 716 extending along a longitudinal axis A7, and a cross section of the coil 716 orthogonal to the longitudinal axis A7 includes at least one of circuit components 702 and 704.

[0062] Forming the upper substrate 708U further includes forming parallel upper horizontal traces 710U in the upper row of the upper substrate 708U, the upper row extending in the direction of the vertical axis A7 of the 3D inductor 706. Forming the lower substrate 708L further includes forming parallel lower horizontal traces 710L in the lower row of the lower substrate 708L, the lower row extending in the direction of the vertical axis A7. Forming the upper substrate 708U further includes forming a magnetic thin film layer 722 in the region of the upper substrate 708U including the upper horizontal traces 710U. A magnetic thin film layer 722 is formed on the top surface 708L of the lower substrate 708L. TOP The circuit assembly 702, 704 includes: a capacitor 704 and a switching circuit 702 disposed on a lower substrate 708L. Disposing of the capacitor 704 on the lower substrate 708L includes: mounting the capacitor 704 on the lower substrate 708L, and disposing of the switching circuit 702 on the lower substrate 708L includes: mounting the switching circuit 702 onto the lower substrate 708L. Forming the circuit layer 708C includes: forming a first magnetic layer 720C on the side surface of the capacitor 704 and forming a second magnetic layer 720S on the side surface of the switching circuit 702. The longitudinal axis A7 of the 3D inductor 706 extends in a first direction and is located on the top surface 708L of the lower substrate 708L. TOPThe upper arrangement of circuit components 702 and 704 includes arranging a capacitor 704 and a switching circuit 702 in a cross section of the 3D inductor 706 orthogonal to the vertical axis A7. Alternatively, on the top surface 708L of the lower substrate 708L... TOP The circuit components 702 and 704 are arranged in a cross section of the 3D inductor 706 that is parallel to the vertical axis A7.

[0063] Figure 9 yes Figure 7 Example of a cross-section of the voltage regulation IC 700 in a plane that extends vertically along the Y-axis and horizontally along the Z-axis (i.e., along the direction of the longitudinal axis A7). Figure 9 The cross-sectional diagram in the image shows one side of coil 716, similar to... Figure 4 The left row of vertical interconnects 408A(1) to 408A(N) is 408A. The first vertical interconnect 712A is coupled to the lower horizontal trace 710L in the lower substrate 708L via contact 714L and to the upper horizontal trace 710U in the upper substrate 708U via contact 714U. Figure 9 In the example shown, the first vertical interconnect 712A and contacts 714L and 714U have a conical shape, which represents a via formed in the IC by a known process. However, when formed by a different process, the first vertical interconnect 712A and contacts 714L and 714U may have other shapes.

[0064] Figure 10 yes Figure 7 A cross-sectional view of the voltage regulation IC 700 shows a 3D inductor integrated into the structural layer of the voltage regulation IC, with other circuit components arranged within the core space of the 3D inductor to provide a voltage regulation circuit with a smaller footprint and lower height compared to the functionally equivalent circuit of discrete components mounted on a substrate on a PCB1000. Figure 10 The image shows a cross-section 1002 of the core space CS7. The lower substrate 708L includes metal traces 1004 and interconnects 1006 for electrically coupled circuit components 702 and 704. Figure 10 As shown, the voltage regulator IC 700 is electrically coupled to the PCB 1000 via solder balls 1008; however, the voltage regulator IC 700 is not limited to this type of PCB connection. By integrating the 3D inductor 706 into the structural layer 708 and arranging the switching circuit 702 and capacitor 704 within the core space CS7 of the 3D inductor 706, the volume occupied by the voltage regulator IC 700 on the PCB 1000 is reduced compared to... Figure 1 The SMPS circuit 100 in the middle will occupy a smaller volume.

[0065] A voltage regulation IC can be provided in or integrated into any processor-based device. The voltage regulation IC includes a switching circuit and a capacitor disposed within a core space of a 3D inductor, the core space being integrated into the structural layer of the voltage regulation IC to implement, according to any aspect disclosed herein, […]. Figure 7 and Figure 10 The reduced height and footprint width are illustrated in any of the examples. Non-limiting examples include set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, tablet-phone computers, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-rotor helicopters.

[0066] On this point, Figure 11 An example of a processor-based system 1100 is shown, which includes a 3D inductor integrated into the structural layer of a voltage regulation IC, wherein other circuit components are arranged within the core space of the 3D inductor for use in... Figure 7 and Figure 10 The voltage regulation circuit shown herein has a smaller footprint and lower height compared to the functional equivalent circuit of discrete components mounted on a substrate, and conforms to any aspect disclosed herein. In this example, the processor-based system 1100 includes one or more central processing unit (CPU) units 1102, which may also be referred to as CPUs or processor cores, each including one or more processors 1104. The CPU(s) 1102 may have a cache memory 1106 coupled to the processor(s) 1104 for fast access to temporarily stored data. As an example, the processor(s) 1104 may include a 3D inductor integrated into the structural layer of the voltage regulation IC, wherein other circuit components are arranged within the core space of the 3D inductor for use such as Figure 7 and Figure 10Each of the circuits shown has a smaller footprint and narrower width compared to the functionally equivalent circuit of a discrete component mounted on a substrate, and a voltage regulation circuit according to some aspects disclosed herein. Multiple CPUs 1102 are coupled to a system bus 1108 and can be coupled to master and slave devices included in the processor-based system 1100. It is known that the multiple CPUs 1102 communicate with these other devices by exchanging address, control, and data information on the system bus 1108. For example, the multiple CPUs 1102 can transmit bus transaction requests to a memory controller 1110, which is an example of a slave device. Although... Figure 11 It is not shown in the figure, but multiple system buses 1108 can be provided, each of which constitutes a different structure.

[0067] Other master and slave devices can be connected to system bus 1108. For example... Figure 11 As shown, as an example, these devices may include: a memory system 1112 including a memory controller 1110 and one or more memory arrays 1114; one or more input devices 1116; one or more output devices 1118; one or more network interface devices 1120; and one or more display controllers 1122. Each of the memory system 1112, the one or more input devices 1116, the one or more output devices 1118, the one or more network interface devices 1120, and the one or more display controllers 1122 may include a 3D inductor integrated into the structural layer of a voltage regulation IC, wherein other circuit components are arranged within the core space of the 3D inductor for use with Figure 7 and Figure 10 Any of the circuits shown herein has a smaller footprint and smaller height compared to a functionally equivalent circuit of discrete components mounted on a substrate, and a voltage regulation circuit according to any aspect disclosed herein. Multiple input devices 1116 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Multiple output devices 1118 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Multiple network interface devices 1120 may be any device configured to allow data exchange with network 1124. Network 1124 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth. TM Networks and the Internet. Multiple network interface devices 1120 can be configured to support any type of communication protocol desired.

[0068] The (multiple) CPUs 1102 can also be configured to access (multiple) display controllers 1122 via system bus 1108 to control information sent to one or more displays 1126. The (multiple) display controllers 1122 send information to the (multiple) displays 1126 for display via one or more video processors 1128, which process the information to be displayed into a format suitable for the one or more displays 1126. The (multiple) displays 1126 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc. The (multiple) display controllers 1122, (multiple) displays 1126, and / or (multiple) video processors 1128 can include 3D inductors integrated into the structural layer of a voltage regulation IC, wherein other circuit components are arranged within the core space of the 3D inductor for use such as Figure 7 and Figure 10 Any of the circuits shown herein has a smaller footprint and a smaller height compared to the functional equivalent circuit of a discrete component mounted on a substrate, and a voltage regulation circuit according to any aspect disclosed herein.

[0069] Figure 12 An exemplary wireless communication device 1200 is shown, which includes a radio frequency (RF) component formed by an IC 1202, wherein any component in the IC 1202 may include a 3D inductor integrated into a structural layer of a voltage regulation IC, wherein other circuit components are arranged within the core space of the 3D inductor for use in... Figure 7 and Figure 10 Any of the circuits shown herein has a smaller footprint and a smaller height compared to the functionally equivalent circuit of a discrete component mounted on a substrate, and a voltage regulation circuit according to any aspect disclosed herein. As an example, wireless communication device 1200 may include or be incorporated in any of the foregoing devices. Figure 12 As shown, the wireless communication device 1200 includes a transceiver 1204 and a data processor 1206. The data processor 1206 may include memory for storing data and program code. The transceiver 1204 includes a transmitter 1208 and a receiver 1210 supporting bidirectional communication. Generally, the wireless communication device 1200 may include any number of transmitters 1208 and / or receivers 1210 for any number of communication systems and frequency bands. All or part of the transceiver 1204 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0070] Transmitter 1208 or receiver 1210 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between RF and baseband in multiple stages, for example, from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for receiver 1210. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 12 In the wireless communication device 1200, the transmitter 1208 and the receiver 1210 are implemented using a direct conversion architecture.

[0071] In the transmission path, the data processor 1206 processes the data to be transmitted and provides I-analog output signals and Q-analog output signals to the transmitter 1208. In the exemplary wireless communication device 1200, the data processor 1206 includes digital-to-analog converters (DACs) 1212(1) and 1212(2) for converting digital signals generated by the data processor 1206 into I-analog output signals and Q-analog output signals (e.g., I-output current and Q-output current) for further processing.

[0072] Within transmitter 1208, low-pass filters 1214(1) and 1214(2) filter the I analog output signal and the Q analog output signal, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1216(1) and 1216(2) amplify the signals from low-pass filters 1214(1) and 1214(2), respectively, and provide I baseband and Q baseband signals. Upconverter 1218 uses the I transmit (TX) local oscillator (LO) signal and the Q transmit (TX) local oscillator (LO) signal from TX LO signal generator 1222, through mixers 1220(1) and 1220(2), to upconvert the I baseband and Q baseband signals to provide upconverted signal 1224. Filter 1226 filters upconverted signal 1224 to remove unwanted signals caused by frequency upconversion and noise in the receiving band. Power amplifier (PA) 1228 amplifies the up-converted signal 1224 from filter 1226 to obtain the desired output power level and provide the transmitted RF signal. The transmitted RF signal is routed via duplexer or switch 1230 and transmitted via antenna 1232.

[0073] In the receiving path, antenna 1232 receives the signal transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1230 and provided to low-noise amplifier (LNA) 1234. Duplexer or switch 1230 is designed to operate at a specific receive (RX) to TX ((RX)-to-TX) duplexer frequency interval, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1234 and filtered by filter 1236 to obtain the desired RF input signal. Downconversion mixers 1238(1) and 1238(2) mix the output of filter 1236 with the I RX LO signal and Q RX LO signal (i.e., LO_I and LO_Q) from RX LO signal generator 1240 to generate I baseband signal and Q baseband signal. The I-baseband signal and Q-baseband signal are amplified by AMPs 1242(1) and 1242(2) and further filtered by low-pass filters 1244(1) and 1244(2) to obtain the I-analog input signal and Q-analog input signal, which are then provided to the data processor 1206. In this example, the data processor 1206 includes analog-to-digital converters (ADCs) 1246(1) and 1246(2) for converting the analog input signal into a digital signal for further processing by the data processor 1206.

[0074] exist Figure 12 In the wireless communication device 1200, a TX LO signal generator 1222 generates I TX LO and Q TX LO signals for up-conversion, while an RX LO signal generator 1240 generates I RX LO and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1248 receives timing information from a data processor 1206 and generates a control signal for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1222. Similarly, an RX PLL circuit 1250 receives timing information from the data processor 1206 and generates a control signal for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1240.

[0075] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the master and slave devices described herein can be employed, for example, in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in accordance with their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this invention.

[0076] The various illustrative logic blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a DSP with a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other combination of such configurations).

[0077] The aspects disclosed herein can be implemented in hardware and by instructions stored in hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0078] It should also be noted that the operational steps described in any exemplary aspect of this document are described to provide examples and discussion. The described operations can be performed in many different orders besides the order stated. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps shown in the flowcharts can be modified in many different ways, as will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or light particles, or any combination thereof.

[0079] The foregoing description of this disclosure is intended to enable those skilled in the art to make or use it. Various modifications to this disclosure will readily be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A voltage regulating integrated circuit (IC) comprising: an upper substrate comprising a plurality of upper horizontal traces; a lower substrate located below the upper substrate and comprising a plurality of lower horizontal traces; and a circuit layer between the upper substrate and the lower substrate, the circuit layer comprising: a plurality of first vertical interconnects, each first vertical interconnect coupled to a first end of one of the plurality of upper horizontal traces and a first end of one of the plurality of lower horizontal traces; a plurality of second vertical interconnects, each second vertical interconnect coupled to a second end of one of the plurality of upper horizontal traces and a second end of one of the plurality of lower horizontal traces; one or more circuit components disposed on the lower substrate; and a three-dimensional (3D) inductor electrically coupled to at least one of the one or more circuit components, the 3D inductor comprising a coil extending along a longitudinal axis, a cross-section of the coil orthogonal to the longitudinal axis comprising the at least one of the one or more circuit components.

2. The voltage regulating integrated circuit (IC) of claim 1, wherein the coil comprises a winding formed by the plurality of upper horizontal traces, the plurality of first vertical interconnects, the plurality of lower horizontal traces, and the plurality of second vertical interconnects.

3. The voltage regulating integrated circuit (IC) of claim 1, wherein the at least one of the one or more circuit components comprises a switching circuit and at least one other of the one or more circuit components comprises a capacitor.

4. The voltage regulating integrated circuit (IC) of claim 3, wherein the circuit layer further comprises: a first magnetic layer on a side of the capacitor; and a second magnetic layer on a side of the switching circuit. a plurality of upper horizontal traces parallel to each other; and a magnetic thin film layer between the plurality of upper horizontal traces and the circuit layer.

5. The voltage regulating integrated circuit (IC) of claim 1, wherein the upper substrate further comprises:

6. The voltage regulating integrated circuit (IC) of claim 3, wherein: the longitudinal axis of the 3D inductor extends in a first direction; the cross-section of the coil of the 3D inductor orthogonal to the longitudinal axis comprises the capacitor and the switching circuit.

7. The voltage regulating integrated circuit (IC) of claim 3, wherein: the longitudinal axis of the 3D inductor extends in a first direction; the cross-section of the coil of the 3D inductor orthogonal to the longitudinal axis comprises only one of the capacitor and the switching circuit.

8. The voltage regulating integrated circuit (IC) of claim 3, wherein the lower substrate further comprises: a first surface comprising connections to the capacitor and the switching circuit; and a second surface comprising connections configured to couple at least one of the one or more circuit components to a printed circuit board (PCB).

9. The voltage regulating integrated circuit (IC) of claim 1, wherein: the longitudinal axis of the 3D inductor extends in a first direction; ​ ​ ​ the plurality of upper horizontal traces are arranged in an upper row in the upper substrate that is parallel to each other, the upper row extending in the first direction; the plurality of lower horizontal traces are arranged in a lower row in the lower substrate that is parallel to each other, the lower row extending in the first direction; and the plurality of first vertical interconnects are arranged in a first row that is parallel to each other, the plurality of second vertical interconnects are arranged in a second row that is parallel to each other, and the first row and the second row extend in the first direction.

10. The voltage regulating integrated circuit (IC) of claim 9, wherein the winding of the 3D inductor comprises: a first one of the plurality of first vertical interconnects is coupled to a first end of a first one of the plurality of upper horizontal traces and to a first end of a first one of the plurality of lower horizontal traces; and a first one of the plurality of second vertical interconnects is coupled to a second end of the first one of the plurality of lower horizontal traces and to a second end of another one of the plurality of upper horizontal traces that is proximate to the first one of the plurality of upper horizontal traces in the upper row.

11. The voltage regulating integrated circuit (IC) of claim 3, wherein the lower substrate further comprises a molding compound.

12. The voltage regulating integrated circuit (IC) of claim 1, the voltage regulating IC is integrated in an integrated circuit (IC).

13. The voltage regulating integrated circuit (IC) of claim 1, the voltage regulating IC is integrated into a device selected from a group consisting of: a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cell phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multi-copter.

14. A method of manufacturing a voltage regulating integrated circuit (IC), the method comprising: forming an upper substrate, the upper substrate comprising a plurality of upper horizontal traces; forming a lower substrate, the lower substrate comprising a plurality of lower horizontal traces; and forming a circuit layer, comprising: arranging one or more circuit components on a surface of the lower substrate on an area comprising the plurality of lower horizontal traces; forming a molding compound over the one or more circuit components; forming a plurality of first vertical interconnects and a plurality of second vertical interconnects in the molding compound, a bottom end of each vertical interconnect of the plurality of first vertical interconnects and the plurality of second vertical interconnects being coupled to one of the plurality of lower horizontal traces in the lower substrate; and arranging the upper substrate on the circuit layer includes coupling each of the plurality of upper horizontal traces to one of the plurality of first vertical interconnects and to one of the plurality of second vertical interconnects such that the plurality of upper horizontal traces, the plurality of first vertical interconnects, the plurality of lower horizontal traces, and the plurality of second vertical interconnects form a three-dimensional (3D) inductor.

15. The method of claim 14, wherein: forming the upper substrate further includes forming a plurality of upper horizontal traces parallel to each other in an upper row in the upper substrate, the upper row extending in a first direction of a longitudinal axis of the 3D inductor; and forming the lower substrate further includes forming a plurality of lower horizontal traces parallel to each other in a lower row in the lower substrate, the lower row extending in the first direction.

16. The method of claim 14, wherein: the 3D inductor includes a coil extending along a longitudinal axis; and a cross-section of the coil orthogonal to the longitudinal axis includes at least one of the one or more circuit components.

17. The method of claim 14, wherein forming the upper substrate further comprises: forming a magnetic thin film layer in a region of the upper substrate including the plurality of upper horizontal traces.

18. The method of claim 14, wherein disposing the one or more circuit components on a surface of the lower substrate further comprises: arranging a capacitor and a switching circuit on the lower substrate.

19. The method of claim 18, further comprising: forming a first magnetic layer on a side of the capacitor; and forming a second magnetic layer on a side of the switching circuit.

20. The method of claim 18, wherein: a longitudinal axis of the 3D inductor extends in a first direction; and arranging the one or more circuit components on a surface of the lower substrate further includes arranging the capacitor and the switching circuit in a cross-section of the 3D inductor orthogonal to the longitudinal axis.

21. The method of claim 18, wherein: a longitudinal axis of the 3D inductor extends in a first direction; and arranging the one or more circuit components on a surface of the lower substrate further includes arranging the capacitor and the switching circuit in a cross-section of the 3D inductor parallel to the longitudinal axis.

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