Gate driving device

Abstract

A gate drive device is provided. A detection section (11, 32, 52, 72) detects a peak value or a rate of change of an element voltage in a change period in which the element voltage of one semiconductor switching element (5A, 5B) changes. A discrimination section (12, 33, 53) discriminates whether energization to the semiconductor switching element in the change period is forward energization or reverse energization. An operation section (13, 34, 54, 74, 82, 92) operates a target command value corresponding to a switching speed, such that the peak value or the rate of change becomes a value or a rate of change that is equal to or lower than a permissible value determined based on a detection value of the detection section in a change period in which the energization is discriminated as forward energization and a permissible value according to a specification of the semiconductor switching element. A drive section (14, 35, 55, 75) changes a gate resistance value or a gate current value of the semiconductor switching element and drives a gate of the semiconductor switching element based on the target command value operated by the operation section.

Description

[0001] Cross-reference to related applications: This application is based on Japanese Patent Application No. 2020-035779, filed on March 3, 2020, for the reasons described herein. Technical Field

[0002] This invention relates to a gate driving device for driving the gates of semiconductor switching elements that constitute the upper and lower arms of a half-bridge circuit. Background Technology

[0003] In a gate driving device that drives the gates of semiconductor switching elements constituting the upper and lower arms of a half-bridge circuit, a malfunction may occur when the surge applied to the main terminal of the semiconductor switching element exceeds the withstand voltage of the semiconductor switching element, i.e., the element withstand voltage. Therefore, countermeasures are required. Furthermore, in this specification, the semiconductor switching element constituting the upper arm of the half-bridge circuit is sometimes referred to as the upper element, and the semiconductor switching element constituting the lower arm of the half-bridge circuit is sometimes referred to as the lower element. Additionally, in this specification, the flow of forward current relative to the semiconductor switching element is sometimes referred to as forward current, and the flow of reverse current relative to the semiconductor switching element is sometimes referred to as reverse current.

[0004] For example, during the period when the upper component is forward-energized and the lower component is reverse-energized, a surge voltage is applied to the main terminal of the upper component when it is turned off. This surge voltage is called a turn-off surge. The turn-off surge is determined by the product of the slope of the component current flowing in the upper component (i.e., the rate of change of the component current) and the parasitic inductance of the current path determined by the system configuration; the greater the rate of change of the component current, the larger the turn-off surge. Therefore, conventionally, the gate resistor of the upper component at turn-off is selected in a way that the turn-off surge does not exceed the component's withstand voltage, and is installed using chip resistors or the like.

[0005] However, the switching losses of a semiconductor switching element during turn-off are proportional to the resistance value of the gate resistor during turn-off. Therefore, when the gate resistor value during turn-off is set to a fixed value as described in the conventional method, the suppression effect of turn-off surge becomes excessive under operating conditions with relatively low turn-off surge, and the increase in switching losses becomes problematic. Thus, there is a trade-off between suppressing turn-off surge and reducing switching losses.

[0006] On the other hand, in Patent Literature 1, there is disclosed a configuration in which a drain-source voltage of a semiconductor switching element that is a MOSFET is measured, and a timing of a gate signal applied to a gate of the semiconductor switching element is adjusted on the basis of a measurement result thereof. In addition, although there is no description in Patent Literature 1 regarding a specific method of adjusting the timing of the gate signal, such adjustment of the timing can be achieved by changing a gate resistance value or a gate current value. Thus, it can be considered that the configuration of Patent Literature 1 is such that a surge voltage applied to a main terminal of the semiconductor switching element is measured, and a gate resistance value or the like at the time of turning off is adjusted in accordance with a measurement result thereof.

[0007] Prior Art Documents

[0008] Patent Literature

[0009] Patent Literature 1: Japanese Patent Application Publication No. 2019-57757 SUMMARY

[0010] Among surges applied to main terminals of semiconductor switching elements of upper and lower arms that constitute a half-bridge circuit, not only the above-mentioned turn-off surge but also a recovery surge is included. The recovery surge is generated due to a reverse recovery characteristic of a backflow diode such as a body diode reverse-parallel connected with respect to the semiconductor switching element, and is, for example, a surge applied to a main terminal of an upper-side element at the time of turning on of a lower-side element during a period in which the upper-side element is reverse energized and the lower-side element is forward energized.

[0011] Like the turn-off surge, such a recovery surge is determined by a product of a rate of change of current and a parasitic inductance. However, the current in this case corresponds to a recovery current in the backflow diode. The recovery surge, unlike the turn-off surge, can be operated in accordance with a gate resistance value at the time of turning on of the lower-side element, regardless of a gate resistance value at the time of turning off of the upper-side element.

[0012] In the prior art disclosed in Patent Literature 1, there is no specific description of a timing of measuring a drain-source voltage of a semiconductor switching element, that is, a surge voltage applied to a main terminal of the semiconductor switching element. Therefore, in the prior art, a gate resistance value or the like is adjusted on the basis of a measurement result of a surge voltage including both a turn-off surge and a recovery surge, and as a result, it can be impossible to appropriately control the turn-off surge.

[0013] An object of the present application is to provide a gate drive device capable of appropriately controlling a turn-off surge.

[0014] In one embodiment of the present application, a gate drive device that drives gates of two semiconductor switching elements that constitute upper and lower arms of a half-bridge circuit includes a detection section, a discrimination section, a calculation section, and a drive section. The detection section detects a peak value of an element voltage or a rate of change of the element voltage in a change period in which the element voltage changes, in a main terminal of one of the semiconductor switching elements. The peak value of the element voltage and the rate of change of the element voltage in the change period are values corresponding to the magnitude of a surge applied to the main terminal of the semiconductor switching element. Therefore, in this case, it can be said that the detection section detects the magnitude of the surge applied to the main terminal of the one semiconductor switching element.

[0015] The discrimination section discriminates whether the energization of the one semiconductor switching element in the change period is forward energization in which a forward current flows or reverse energization in which a reverse current flows. As described above, there are an off surge and a recovery surge in the surge applied to the main terminal of the semiconductor switching element, the off surge is generated when the energization of the semiconductor switching element as a target is forward energization, and the recovery surge is generated when it is reverse energization. Therefore, in this case, it can be said that the discrimination section discriminates whether the generated surge is the off surge or the recovery surge.

[0016] The calculation section calculates a target command value corresponding to the switching speed of the semiconductor switching element, such that the peak value or the rate of change becomes equal to or lower than a permissible value, based on the detection value of the detection section in the change period in which the discrimination section discriminates that the energization of the one semiconductor switching element is forward energization, and the permissible value of the peak value or the rate of change determined according to the specifications of the semiconductor switching element. That is, the calculation section calculates a target command value such that the peak value or the rate of change of the element voltage becomes equal to or lower than the permissible value, based on the detection value corresponding to the magnitude of the surge in the change period in which the discrimination is made that the generated surge is the off surge, and the permissible value.

[0017] The drive section changes the gate resistance value or the gate current value of the one semiconductor switching element based on the target command value calculated by the calculation section, and drives the gate of the semiconductor switching element. That is, the drive section changes the gate resistance value or the gate current value based on the target command value calculated using the detection result of the surge voltage including only the off surge. According to this configuration, the following excellent effects can be obtained: the magnitude of the off surge can be controlled so that the peak value or the rate of change of the element voltage does not exceed the permissible value and the switching loss does not excessively increase, in other words, the off surge can be appropriately controlled. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above objects and other objects, features, and advantages of the present application will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1Fig. 1 is a diagram schematically showing an outline configuration of a gate drive device and a half-bridge circuit of Embodiment 1;

[0020] Figure 2 Fig. 2 is a diagram schematically showing waveforms of a load current and currents and voltages associated with semiconductor switching elements of Embodiment 1;

[0021] Figure 3 Fig. 3 is a diagram schematically showing waveforms of each part at the time of turn-off of the semiconductor switching elements of Embodiment 1;

[0022] Figure 4 Fig. 4 is a diagram schematically showing each function of the gate drive device of Embodiment 1;

[0023] Figure 5 Fig. 5 is a diagram schematically showing a flow of processing performed by each function of the gate drive device of Embodiment 1;

[0024] Figure 6 Fig. 6 is a diagram schematically showing a specific configuration example of the gate drive device of Embodiment 1;

[0025] Figure 7 Fig. 7 is a timing chart for explaining timings of each control performed by the gate drive device of Embodiment 1;

[0026] Figure 8 Fig. 8 is a diagram showing a first modification example related to detection of a drain current;

[0027] Figure 9 Fig. 9 is a diagram showing a second modification example related to detection of a drain current;

[0028] Figure 10 Fig. 10 is a diagram schematically showing a specific configuration example of a gate drive device of Embodiment 2;

[0029] Figure 11 Fig. 11 is a diagram schematically showing a relationship between a threshold value and a drain current of Embodiment 2;

[0030] Figure 12 Fig. 12 is a timing chart for explaining timings of each control performed by the gate drive device at the time of forward energization of Embodiment 2;

[0031] Figure 13 Fig. 13 is a timing chart for explaining timings of each control performed by the gate drive device at the time of reverse energization of Embodiment 2;

[0032] Figure 14 Fig. 14 is a diagram schematically showing a specific configuration example of a gate drive device of Embodiment 3;

[0033] Figure 15is a diagram schematically showing a specific configuration example of the gate drive device of the 4th embodiment;

[0034] Figure 16 is a diagram schematically showing each function that the gate drive device of the 5th embodiment has;

[0035] Figure 17 is a diagram schematically showing each function that the gate drive device of the 6th embodiment has. DETAILED DESCRIPTION

[0036] Hereinafter, a plurality of embodiments will be described with reference to the drawings. In addition, in each embodiment, the same symbols are attached to substantially the same configurations and the description is omitted.

[0037] (1st Embodiment)

[0038] Hereinafter, a plurality of embodiments will be described with reference to the drawings. In addition, in each embodiment, the same symbols are attached to substantially the same configurations and the description is omitted. Figures 1-9 The 1st embodiment will be described.

[0039] <Outline Configuration of Gate Drive Device>

[0040] As shown in Figure 1 , the gate drive device 1A of the present embodiment drives a semiconductor switching element 5A that constitutes an upper arm of a half-bridge circuit 4 connected between a pair of direct-current power supply lines 2, 3. Further, the gate drive device 1B of the present embodiment drives a semiconductor switching element 5B that constitutes a lower arm of the half-bridge circuit 4. In this case, the gate drive devices 1A, 1B are the same configuration, and the semiconductor switching elements 5A, 5B are the same configuration. Therefore, in the present specification, in a case where it is not necessary to distinguish the gate drive devices 1A, 1B and the semiconductor switching elements 5A, 5B respectively, the last letter is omitted and a general term is used.

[0041] The half-bridge circuit 4 is included in an inverter that drives a motor not shown. For example, a power supply voltage Va is supplied to the half-bridge circuit 4 from a direct-current power supply not shown such as a battery via the direct-current power supply lines 2, 3. The semiconductor switching element 5 is a power element, and in this case, is configured to include an N-channel type MOSFET, and a diode for backflow connected to a source side as an anode between a drain and a source of the MOSFET, that is, reverse-parallel to the MOSFET. In addition, in this case, the diode for backflow is provided as an element different from the MOSFET, but the body diode of the MOSFET can be utilized as the diode for backflow.

[0042] The drain of the upper component 5A is connected to the DC power supply line 2 on the high-potential side. The source of the upper component 5A is connected to the drain of the lower component 5B. The source of the lower component 5B is connected to the DC power supply line 3 on the low-potential side. The interconnection node N1 between the upper component 5A and the lower component 5B is connected to the motor (not shown). Thus, the output current IL of the half-bridge circuit 4, i.e., the load current IL, is supplied to the motor. The controller 6 controls the operation of the half-bridge circuit 4, which constitutes the inverter, thereby controlling the drive of the motor.

[0043] The controller 6 is supplied with a detection signal Sc, representing the detected value of the load current IL, output from a current detection unit (not shown). Based on the detection signal Sc, the controller 6 generates and outputs a command signal Sa instructing the operation of the gate drive device 1A and a command signal Sb instructing the operation of the gate drive device 1B, so that the load current IL is aligned with the desired target current. The gate drive device 1A performs PWM control on the drive of the upper component 5A based on the command signal Sa supplied from the controller 6. Furthermore, the gate drive device 1B performs PWM control on the drive of the lower component 5B based on the command signal Sb supplied from the controller 6.

[0044] In this configuration, the upper element 5A and the lower element 5B are complementaryly switched on and off. Therefore, the lower element 5B is switched off while the upper element 5A is on, and vice versa. In this configuration, during the period when the load current IL flows from node N1 to the motor, the upper element 5A is driven to make the current flow forward from the drain to the source, and the lower element 5B is driven to make the current flow backward from the source to the drain. Furthermore, in this configuration, during the period when the load current IL flows from the motor to node N1, the lower element 5B is driven to make the current flow forward from the drain to the source, and the upper element 5A is driven to make the current flow backward from the source to the drain.

[0045] like Figure 2 As shown, the load current IL becomes a sinusoidal current. To achieve this load current IL, the drain current Id, drain-source voltage Vds, and gate-source voltage Vgs of the lower component 5B become... Figure 2 The waveforms are as shown. In addition, although the diagrams for the drain current Id, drain-source voltage Vds, and gate-source voltage Vgs of the upper element 5A are omitted, the waveforms relative to the lower element 5B are the same except that they are inverted.

[0046] In this case, the drain-source voltage Vds is the voltage at the main terminal of the semiconductor switching element 5, equivalent to the element voltage. Furthermore, in this case, the drain current Id is the current flowing in the semiconductor switching element 5, equivalent to the element current. Additionally, in this specification, the drain current Id, drain-source voltage Vds, and gate-source voltage Vgs are sometimes simply referred to as current Id, voltage Vds, and voltage Vgs, respectively.

[0047] The waveforms of each part when the semiconductor switching element 5 is turned off become Figure 3 The waveform shown. Additionally, in Figure 3 The waveforms corresponding to each part of the lower component 5B are illustrated, but the same waveforms are also shown for the upper component 5A. The disconnect voltage Vds_off when the lower component 5B is turned off is approximately equal to the power supply voltage Va. In this case, the peak value Vds_p of the off-state voltage, i.e., the difference between the peak voltage and the disconnect voltage Vds_off, i.e., ΔVds, is equivalent to the surge voltage superimposed on the lower component 5B. In this case, the slope of the voltage Vds variation is equivalent to the rate of change of the component voltage. In addition, in this specification, the slope of the voltage Vds variation is sometimes referred to as dV / dt, and the slope of the current Id variation is sometimes referred to as dI / dt.

[0048] <Functions of the gate drive device>

[0049] Next, the functions of the gate driving device 1 will be described with reference to the accompanying drawings. Figure 4 In the above, the functions of the gate driving device 1 are represented in the form of functional blocks. The specific implementation methods of each function will be described later. Furthermore, in the following description, the semiconductor switching element 5 that is driven by this device is referred to as the semiconductor switching element 5 of this arm, and the semiconductor switching element that will be driven by a gate driving device 1 different from this device is referred to as the semiconductor switching element 5 of the opposing arm. Additionally, the semiconductor switching element 5 of this arm corresponds to one of the semiconductor switching elements in the scope of the patent claim, and the semiconductor switching element 5 of the opposing arm corresponds to the other semiconductor switching element in the scope of the patent claim.

[0050] The detection section 11 detects the peak value Vds_p of the voltage Vds in the variation period in which the voltage Vds of the semiconductor switching element 5 of the own arm, i.e., the semiconductor switching element 5 that becomes a drive object of the gate drive device 1, varies. The discrimination section 12 discriminates whether the energization to the semiconductor switching element 5 of the own arm in the above variation period is forward energization or reverse energization. In the present embodiment, the discrimination section 12 directly or indirectly detects the current Id of the semiconductor switching element 5 of the own arm, and discriminates that the above energization is forward energization in a period in which the current Id flows forward, and discriminates that the above energization is reverse energization in a period in which the element current flows reverse.

[0051] The operation section 13 operates the target command value corresponding to the switching speed of the semiconductor switching element 5. In this case, the target command value becomes a value indicating the gate resistance value of the semiconductor switching element 5. The operation section 13 operates the target command value in which the peak value Vds_p of the voltage Vds becomes a value or less on the basis of the detection value of the detection section 11, i.e., the detection value of the peak value Vds_p of the voltage Vds, in the variation period in which the discrimination section 12 discriminates that the energization to the semiconductor switching element 5 of the own arm is forward energization, and the allowable value of the peak value Vds_p of the voltage Vds.

[0052] The allowable value of the peak value of the voltage Vds is decided in accordance with the specifications of the semiconductor switching element 5, and specifically becomes a value as follows. That is, the allowable value is set to a value that is lower than the withstand voltage of the semiconductor switching element 5 by a prescribed margin, and is a value in which the semiconductor switching element 5 is not likely to fail even if the voltage of the value is applied to the main terminal, but the semiconductor switching element 5 is likely to fail when a voltage that exceeds the above margin is applied to the main terminal. In the present embodiment, the operation section 13 operates the target command value so that the deviation between the detection value of the detection section 11 and the allowable value decided in advance becomes zero.

[0053] The drive section 14 drives the gate of the semiconductor switching element 5 of the own arm. In this case, the drive section 14 changes the gate resistance value Rg_off at the time of the turn-off of the semiconductor switching element 5 of the own arm on the basis of the target command value operated by the operation section 13. Further, in this case, the drive section 14 completes the change of the gate resistance value Rg_off before the semiconductor switching element 5 of the own arm is next turned off. In the present embodiment, the drive section 14 continuously switches the gate resistance value Rg_off of the semiconductor switching element 5 of the own arm on the basis of the target command value.

[0054] <Summary of the processing based on each function>

[0055] Next, a summary of the processing performed by each function of the gate drive device 1 having the above configuration will be described with reference to FIG. 8. Figure 5 Figure 5 ​As shown, after the start of the processing, in the step S100 which is initially executed, the gate resistance value Rg_off of the own arm is set to an initial value. In this case, the initial value is set to a comparatively high value which is sufficiently lower than the withstand voltage of the semiconductor switching element 5. After the execution of the step S100, the processing proceeds to the step S200. In the step S200, the detected value of the peak value Vds_p of the voltage Vds, that is, the peak voltage of the surge is acquired.

[0056] In the step S300, it is judged whether or not the energization to the semiconductor switching element 5 of the own arm is judged to be the forward energization. Here, in the case where the energization is judged to be the reverse energization, that is, in the case where it is judged to be the period during which the recovery surge is generated, in the step S300, "No" is made, and the processing returns to the step S200. On the other hand, in the case where the energization is judged to be the forward energization, that is, in the case where it is judged to be the period during which the turn-off surge is generated, in the step S300, "Yes" is made, and the processing proceeds to the step S400.

[0057] In the step S400, the gate resistance value Rg_off is adjusted on the basis of the detected value of the peak value Vds_p and the allowable value. After the execution of the step S400, the processing proceeds to the step S500. In the step S500, it is judged whether or not the end instruction is given. The above-mentioned end instruction is given from the control device of the upper stage of the gate drive device 1 at the time of the disconnection of the power supply of the device, at the time of the system stop in conjunction with the detection of some kind of abnormality, and the like. Here, in the case where the end instruction is given, in the step S500, "Yes" is made, and the processing proceeds to the step S600.

[0058] On the other hand, in the case where the end instruction is not given, in the step S500, "No" is made, and the processing returns to the step S200, and the processing after the step S200 is repeated. In the step S600, each processing at the time of the end is implemented. As each processing at the time of the end, there are included the processing for setting the gate resistance value Rg_off to a prescribed value on the safe side, the processing for resetting the integrator in the case where the arithmetic portion 13 is constituted with an integrator, and the like. In addition, as the prescribed value on the safe side of the gate resistance value Rg_off, a comparatively high value which is sufficiently lower than the withstand voltage of the semiconductor switching element 5 is set. After the execution of the step S600, the present processing is ended.

[0059] <Specific Configuration of Gate Drive Device>

[0060] As the specific configuration of the gate drive device 1 having each function as mentioned above, for example, the configuration example as shown in FIG. 1 can be adopted. In addition, in the case where the gate drive device 1 is constituted with a plurality of gate drive devices 1, the configuration example as shown in FIG. 2 can be adopted. Figure 6 Figure 6 ​The specific configuration of the gate drive device 1 will be described taking the gate drive device 1B that drives the lower-side element 5B as an example, but the same configuration can be adopted for the gate drive device 1A that drives the upper-side element 5A. In this case, a shunt resistor Rs for detecting the current Id is inserted in series between the source of the semiconductor switching element 5B and the direct-current power supply line 3.

[0061] In Figure 6 In the gate drive device 1 shown in the figure, the detection section 11 is configured by the peak holding circuit 15 and the switch 16, the discrimination section 12 is configured by the comparator 17 and the sample-and-hold circuit 18, and the operation section 13 is configured by the memory 19, the subtracter 20, and the controller 21. The voltage of the node N1, that is, the drain voltage of the lower-side element 5B is input to the peak holding circuit 15. The peak holding circuit 15 is a circuit that inputs the drain voltage of the lower-side element 5B, that is, the voltage Vds with the source potential of the lower-side element 5B as a reference, and holds the peak value Vds_p thereof.

[0062] That is, the peak holding circuit 15 is provided in order to obtain the peak voltage of the surge applied to the main terminal of the lower-side element 5B. The peak holding circuit 15 obtains the peak value Vds_p every time the voltage Vds of the lower-side element 5B changes, that is, every time the lower-side element 5B switches, and outputs the updated value at all times. The peak holding circuit 15 outputs a detection voltage Vb that represents the detection value of the peak value Vds_p. In this case, the detection voltage Vb output from the peak holding circuit 15 is applied to the operation section 13 in the subsequent stage via the switch 16. Although the details will be described later, the on-off of the switch 16 is controlled by a signal SW output from the discrimination section 12.

[0063] The non-inverting input terminal of the comparator 17 is connected to the node N2, that is, the node at which the lower-side element 5B and the shunt resistor Rs are connected to each other. Thus, the voltage Vse obtained by voltage conversion of the current Id flowing in the lower-side element 5B by the shunt resistor Rs is input to the non-inverting input terminal of the comparator 17. The inverting input terminal of the comparator 17 is connected to the direct-current power supply line 3 to which the reference potential of the circuit, that is, 0 V is applied. Thus, the comparator 17 compares the voltage Vse corresponding to the current Id with 0 V, and outputs a signal Sd that represents the binary of the comparison result.

[0064] According to the above-described configuration, based on the level of the signal Sd output from the comparator 17, it is possible to discriminate whether the current Id is flowing from the drain toward the source, that is, forward flow, or the current Id is flowing from the source toward the drain, that is, reverse flow. Specifically, in the case where the signal Sd is at a high level, it is discriminated that the current Id is forward flow and the energization to the lower-side element 5B is forward energization.

[0065] Further, in the case where the signal Sd is at the low level, it is determined that the current Id is flowing in the reverse direction and that the energization to the lower arm element 5B is reverse energization. In addition, the threshold value at which the comparator 17 makes the determination can not be limited to 0 V, but can be appropriately changed as long as it is a range in which the direction of the current Id can be determined. Further, the comparator 17 can be configured to have a hysteresis in detection and recovery.

[0066] The sample-and-hold circuit 18 inputs the signal Sd output from the comparator 17 and outputs a signal SW of a binary value of the input signal. In the above configuration, during the on period of the semiconductor switching element 5 of the opposite arm, i.e., the upper arm element 5A, the current Id flowing in the semiconductor switching element 5 of the own arm, i.e., the lower arm element 5B, is necessarily zero, and thus the level of the signal Sd output from the comparator 17 can not become a level corresponding to the direction of the current Id.

[0067] Therefore, the sample-and-hold circuit 18 samples the signal Sd during the on period of the lower arm element 5B, i.e., the own arm energization, and interpolates by holding the sampling result in the opposite arm energization. According to this configuration, based on the level of the signal SW output from the sample-and-hold circuit 18, the direction of the current Id can be reliably determined, and further, it can be reliably determined whether the energization to the lower arm element 5B is forward energization or reverse energization.

[0068] When the energization to the lower arm element 5B is forward energization, the signal SW output from the sample-and-hold circuit 18 becomes the high level, and thus the switch 16 is on and the detection voltage Vb output from the peak value holding circuit 15 is input to the operation section 13. In contrast, when the energization to the lower arm element 5B is reverse energization, the signal SW output from the sample-and-hold circuit 18 becomes the low level, and thus the switch 16 is off and the detection voltage Vb output from the peak value holding circuit 15 is not input to the operation section 13. That is, in the above configuration, the detection voltage Vb indicating the detected value of the peak value Vds_p at the time when the energization to the lower arm element 5B is forward energization, i.e., at the time of the turn-off surge, is input to the operation section 13.

[0069] The above allowable value, i.e., the allowable value of the peak value Vds_p determined in accordance with the specifications of the semiconductor switching element 5, is stored in the memory 19. The memory 19 outputs an allowable voltage Vc indicating the stored allowable value. In addition, it can also be configured that, instead of such a memory 19, the allowable voltage Vc is input to the operation section 13 from the outside of the gate drive device 1. The allowable voltage Vc is given to the + input of the subtracter 20, and the detection voltage Vb is given to the - input thereof. The subtracter 20 obtains a deviation AV corresponding to the difference between the detected value and the allowable value of the peak value Vds_p by subtracting the detection voltage Vb from the allowable voltage Vc, and outputs the deviation AV to the controller 21.

[0070] The controller 21 is a digital PID controller that performs a PID operation with respect to the deviation AV to generate a command signal Se that indicates a target command value. The command signal Se is output to the drive section 14. In addition, as the controller 21, a controller that performs a PI operation, a controller that performs a P operation, another feedback controller, or the like can be used. In the present embodiment, the operation of the PID controller 21 is performed during a period in which the detection voltage Vb is input to the operation section 13, and is stopped during a period in which the detection voltage Vb is not input to the operation section 13.

[0071] The drive section 14 is configured to perform constant voltage drive on the gate of the lower element 5B, and includes a buffer 22, a transistor Ql that is a P-channel MOSFET, a transistor Q2 that is an N-channel MOSFET, and resistors Rl and R2. The buffer 22 inputs a command signal Sb and outputs a signal corresponding to the input signal. The output terminal of the buffer 22 is connected to each of the gates of the transistors Ql and Q2. The source of the transistor Ql is connected to a direct current power supply line 23 to which a power supply voltage Vd is supplied. The power supply voltage Vd is a voltage with respect to the potential of the direct current power supply line 3, and is a voltage that is sufficiently higher than the threshold voltage of the gate of the lower element 5B.

[0072] The drain of the transistor Ql is connected to a node N3 via the resistor Rl. The node N3 is connected to the gate of the lower element 5B. The resistor Rl functions as a gate resistance when the lower element 5B is turned on, together with the wiring resistance and the like of a path from the direct current power supply line 23 to the gate of the lower element 5B. The resistor Rl is configured to have a certain resistance value. The source of the transistor Q2 is connected to the direct current power supply line 3. The drain of the transistor Q2 is connected to the node N3 via the resistor R2.

[0073] The resistor R2 functions as a gate resistance when the lower element 5B is turned off, together with the wiring resistance and the like of a path from the direct current power supply line 3 to the gate of the lower element 5B. The resistor R2 is configured to be able to change its resistance value based on the command signal Se from the operation section 13. That is, in the above configuration, the gate resistance value Rg off when the lower element 5B is turned off is changed based on the command signal Se. In addition, the change in the resistance value of the resistor R2 can be performed by various methods, such as a method using a variable resistor, a method using switching of a resistance ladder, a method of operating the on resistance of the transistor Q2, and the like.

[0074] Next, the operation of the gate drive device 1B will be described with reference to FIG. 6. Figure 7 The timing of each control based on the above configuration will be described. In addition, here, the control with the gate drive device IB side as the main body will be described, but the control with the gate drive device IA side as the main body is the same content. In the following description, the state of the switch 16 will be described as "ON" for the state in which the switch 16 is turned on, and "OFF" for the state in which the switch 16 is turned off. Figure 7 In the above configuration, the command signal Se is output to the drive section 14 when the detection voltage Vb is input to the operation section 13. In addition, the command signal Se is not output to the drive section 14 when the detection voltage Vb is not input to the operation section 13.Figure 7 The diagram shows dashed lines extending longitudinally in a manner consistent with the timing of the drop in voltage Vgs, but the spacing between these dashed lines corresponds to the drive cycle of semiconductor switching element 5.

[0075] In this case, the period Ta during which the current Id is positive, i.e., the period when the current Id flows in the positive direction, is the period during which the semiconductor switching element 5 of this arm, i.e., the lower element 5B, is positively energized. Therefore, a turn-off surge is generated during the period Ta. During the period Ta, since the signal SW is at a high level, the switch 16 is in the on state. During this period Ta, the detection voltage Vb, which represents the peak value Vds_p of the voltage Vds, is applied to the arithmetic unit 13.

[0076] Therefore, the arithmetic unit 13 calculates and generates an instruction signal Se such that the peak value Vds_p is below the allowed value based on the detected voltage Vb and the allowable voltage Vc. Then, the drive unit 14 switches the gate resistance value Rg_off at any time based on the instruction signal Se. In this case, the drive unit 14 completes the change of the gate resistance value Rg_off during the period from the start of the off-time of a predetermined drive cycle to the start of the off-time of the next drive cycle.

[0077] Conversely, during the period Tb when the current Id is negative, i.e., when the current Id flows in reverse, the energization of the lower component 5B becomes reverse energization. Therefore, a recovery surge occurs during period Tb. During period Tb, the signal SW becomes low, so switch 16 is in the off state. During this period Tb, the detection voltage Vb is not applied to the arithmetic unit 13. Therefore, the arithmetic unit 13 does not perform the operation on the instruction signal Se, and consequently, the drive unit 14 does not switch the gate resistor value Rg_off.

[0078] Therefore, during period Tb, the gate resistance value Rg_off is maintained at a constant value. The gate resistance value Rg_off during period Tb can be set to the following value: That is, as... Figure 7 As shown, the gate resistance value Rg_off in period Tb can be set to a value set immediately preceding that period Tb. Alternatively, the gate resistance value Rg_off in period Tb can be set to a predetermined setting value. In this case, the setting value can be set to a value that represents a relatively high resistance value, i.e., a safe-side value, indicating that surges are less likely to occur.

[0079] Thus, the following effects can be obtained. That is, in the period Ta immediately after the period Tb, the magnitude of the turn-off surge initially generated corresponds to the value of the gate resistance Rg_off in the period Tb. Thus, if the value of Rg_off in the period Tb is set to the value on the safe side as described above, the turn-off surge initially generated in the period Ta can be reliably prevented from becoming an excessively large surge that exceeds the element withstand voltage of the semiconductor switching element 5.

[0080] According to the present embodiment described above, the following effects can be obtained.

[0081] The detection section 11 detects the peak value Vds_p of the voltage Vds in the change period in which the voltage Vds of the semiconductor switching element 5 of the own arm changes. The peak value Vds_p of the voltage Vds in the change period becomes a value corresponding to the magnitude of the surge applied to the main terminal of the semiconductor switching element 5. Therefore, in this case, it can be said that the detection section 11 detects the magnitude of the surge applied to the main terminal of the semiconductor switching element 5 of the own arm.

[0082] The discrimination section 12 discriminates whether the energization to the semiconductor switching element 5 of the own arm in the change period is forward energization or reverse energization. There are the turn-off surge and the recovery surge in the surge applied to the main terminal of the semiconductor switching element 5, the turn-off surge is generated when the energization to the semiconductor switching element 5 as the object is forward energization, and the recovery surge is generated when it is reverse energization. Therefore, in this case, it can be said that the discrimination section 12 discriminates whether the generated surge is the turn-off surge or the recovery surge.

[0083] The operation section 13 operates the target command value in which the peak value Vds_p becomes the value or less on the basis of the detection value of the detection section 11 in the change period in which the discrimination section 12 discriminates that the energization to the semiconductor switching element 5 of the own arm is forward energization, and the allowable value of the peak value Vds_p decided in accordance with the specifications of the semiconductor switching element 5, which corresponds to the switching speed of the semiconductor switching element 5. That is, the operation section 13 operates the target command value in which the peak value Vds_p of the voltage Vds becomes the value or less on the basis of the detection value corresponding to the magnitude of the surge in the change period in which the discrimination is made that the generated surge is the turn-off surge, and the allowable value.

[0084] The drive section 14 changes the gate resistance value Rg_off of the semiconductor switching element 5 of the local arm on the basis of the target command value calculated by the arithmetic section 13, and drives the gate of the semiconductor switching element 5 of the local arm. That is, the drive section 14 changes the gate resistance value Rg_off on the basis of the target command value calculated using the detection result of the surge voltage including only the turn-off surge. According to this configuration, the following excellent effect can be obtained: the magnitude of the turn-off surge can be controlled so that the peak value Vds_p of the voltage Vds does not exceed the allowable value and the switching loss does not excessively increase, in other words, the turn-off surge can be appropriately controlled.

[0085] In this case, the drive section 14 completes the change of the gate resistance value Rg_off before the semiconductor switching element 5 of the local arm is next turned off. That is, in the present embodiment, when the target command value is calculated on the basis of the detected value of the peak value Vds_p of the voltage Vds in the prescribed drive period, the result of the calculation is actually reflected in the gate resistance value Rg_off at the time when the semiconductor switching element 5 of the local arm is next turned off. According to this control, the optimization of the gate resistance value Rg_off can be more reliably and more quickly achieved, that is, the above-described effect can be maximized.

[0086] In this case, the discrimination section 12 detects the direction of the current Id flowing in the semiconductor switching element 5 of the local arm, and determines that it is forward energization during the period when the current Id flows forward, and determines that it is reverse energization during the period when the current Id flows backward. Specifically, the discrimination section 12 of the present embodiment is provided with a comparator 17 that compares the voltage Vse corresponding to the current Id with 0 V.

[0087] According to this configuration, during the period when the semiconductor switching element 5 of the local arm is on, that is, during the local arm energization, the level of the signal Sd output from the comparator 17 becomes the level corresponding to the direction in which the current Id flows, and thus it is possible to accurately discriminate whether the energization of the semiconductor switching element 5 of the local arm is forward energization or reverse energization. However, in this case, during the period when the semiconductor switching element 5 of the opposing arm is on, that is, during the opposing arm energization, the current Id flowing in the semiconductor switching element 5 of the local arm is necessarily zero, and thus the level of the signal Sd can not become the level corresponding to the direction in which the current Id flows.

[0088] Therefore, the discrimination section 12 is provided with a sample-and-hold circuit 18 that samples the signal Sd during the local arm energization, and interpolates by holding the result of the sampling during the opposing arm energization, and the discrimination section 12 discriminates the above-described energization on the basis of the level of the signal SW output from the sample-and-hold circuit 18. According to this configuration, it is possible to reliably discriminate the direction of the current Id, and further, it is possible to reliably discriminate whether the energization of the semiconductor switching element 5 of the local arm is forward energization or reverse energization.

[0089] In this case, the arithmetic unit 13 calculates and generates an instruction signal Se representing the target instruction value, so that the deviation ΔV between the detection voltage Vb representing the detection value of the detection unit 11 and the allowable voltage Vc representing the allowable value of the peak value Vds_p becomes zero. The drive unit 14 continuously switches the gate resistance value Rg_off of the semiconductor switching element 5 of this arm based on the instruction signal Se. In this way, detailed settings can be made to make the gate resistance value Rg_off when the semiconductor switching element 5 of this arm is turned off the optimal value, and as a result, the turn-off surge can be controlled in more detail.

[0090] <Variations related to the detection of current Id>

[0091] exist Figure 6 In the specific configuration example shown, the discrimination unit 12 is configured to directly detect the current Id of the semiconductor switching element 5 of this arm based on the terminal voltage of the shunt resistor Rs connected in series between the semiconductor switching element 5 and the DC power line 3. However, the discrimination unit 12 can also be configured, for example, as in the following two variations, to indirectly detect the current Id of the semiconductor switching element 5 of this arm.

[0092] [1] First variation

[0093] exist Figure 8 In the first modified example shown, the semiconductor switching element 5, i.e., the lower element 5B, which serves as the main arm, is an element having a main unit 24 and a sensing unit 25. Furthermore, in Figure 8 The diagram of the return diode is omitted. The main unit 24 and the sensing unit 25 are formed on the same semiconductor chip, and the size of the sensing unit 25 is several hundred to several thousandths of the size of the main unit 24.

[0094] The drain of the main unit 24 is connected to node N1, and its source is connected to the DC power supply line 3. The sensing unit 25 detects the current Id flowing in the main unit 24 and supplies a current corresponding to the current Id flowing in the main unit 24 at a predetermined shunt ratio. This shunt ratio is determined based on the size ratio of the main unit 24 and the sensing unit 25. The drain of the sensing unit 25 is connected to node N1, and its source is connected to the DC power supply line 3 via a shunt resistor Rs1.

[0095] In this case, comparator 17 compares the voltage Vse1 obtained by voltage conversion of the current flowing in sensing unit 25 using shunt resistor Rs1 with 0V, and outputs a binary signal Sd1 representing the comparison result. This signal Sd1 is compared with... Figure 6The signal Sd in the configuration shown is the same, becoming a level corresponding to the direction of the current Id during the energization of this arm. Therefore, according to this first modification, the discrimination unit 12 can also accurately determine whether the energization of the semiconductor switching element 5 of this arm during the change period is forward or reverse.

[0096] [2] Second variation

[0097] like Figure 1 As shown, the controller 6 is given a detection signal Sc representing the detected value of the load current IL. Based on the detection signal Sc, the controller 6 can determine the direction of the load current IL, specifically, whether the load current IL flows from node N1 to the motor or from the motor to node N1. Furthermore, based on this direction of the load current IL, the direction of the current Id flowing in each of the semiconductor switching elements 5 constituting the upper and lower arms can be deduced.

[0098] Therefore, in Figure 9 In the second variation shown, the controller 6 infers the direction of the current Id flowing in the upper element 5A and the direction of the current Id flowing in the lower element 5B based on the detection signal Sc. Then, the controller 6 sends a signal Sf indicating the direction of the current Id flowing in the upper element 5A to the gate drive device 1A, and sends a signal Sg indicating the direction of the current Id flowing in the lower element 5B to the gate drive device 1B.

[0099] In this case, signals Sf and Sg are the same as signal SW, and are binary signals with levels corresponding to the direction of current Id. Therefore, each discrimination unit 12 of the gate drive devices 1A and 1B determines the direction of the current Id flowing in the semiconductor switching element 5 of its own arm based on these signals Sf and Sg. Thus, according to this second modification, the discrimination unit 12 can also determine with high accuracy whether the energization of the semiconductor switching element 5 of its own arm during the change period is forward or reverse.

[0100] (Second Implementation)

[0101] The following is for reference Figures 10-13 The second embodiment will be described.

[0102] In this embodiment, the specific configuration of the gate driving device differs from that in the first embodiment. That is, as shown in the following example... Figure 10 As shown, the gate driving device 31 of this embodiment is relative to Figure 6 The gate driving device 1B of the first embodiment shown has modified the specific configuration of the detection unit, the discrimination unit, the arithmetic unit, and the driving unit. Furthermore, in Figure 10The configuration for driving the lower-side element 5B is exemplified, but the same configuration can be employed for the configuration for driving the upper-side element 5A.

[0103] The gate drive device 31 includes a detection section 32, a discrimination section 33, an arithmetic section 34, and a drive section 35. The detection section 32 is a configuration in which a sample-and-hold circuit 36 is added to the detection section 11. The discrimination section 33 is a configuration including a comparator 37 and a timing circuit 38. The arithmetic section 34 is a configuration including a threshold value output section 39 and a comparator 40. The drive section 35 is configured so as to differ from the drive section 14 in that, instead of the resistor R2, resistors R21 and R22 and a switch 41 are included.

[0104] In this case, the discrimination section 33 discriminates that the energization of the lower-side element 5B is forward energization during a period until a timing at which a prescribed discrimination time elapses from the start timing of the turn-off of the semiconductor switching element 5, i.e., the lower-side element 5B, and discriminates that the energization of the lower-side element 5B is reverse energization during a period after the timing at which the discrimination time elapses. The specific configuration for achieving such discrimination is as follows.

[0105] That is, the non-inverting input terminal of the comparator 37 is connected to the node N3, i.e., the gate of the lower-side element 5B. A threshold voltage Vth that is decided in advance is input to the inverting input terminal of the comparator 37. The threshold voltage Vth is a voltage with respect to the potential of the direct-current power supply line 3, and is, for example, a voltage value that is the same degree as the gate threshold voltage of the semiconductor switching element 5. Thus, the comparator 37 compares the voltage Vgs of the lower-side element 5B with the voltage Vth, and outputs a signal Sh of a binary value that indicates the result of the comparison.

[0106] According to the above-described configuration, the turn-on and turn-off of the lower-side element 5B can be determined on the basis of the level of the signal Sh output from the comparator 37. Specifically, when the signal Sh is at a high level, it can be determined that the lower-side element 5B is turned on, i.e., the gate is turned on, and when the signal Sh is at a low level, it can be determined that the lower-side element 5B is turned off, i.e., the gate is turned off. In this way, on the basis of the signal Sh that becomes a level corresponding to the gate turn-on or the gate turn-off, the start timing of the turn-off of the lower-side element 5B can be grasped. In addition, instead of this configuration, the start timing of the turn-off of the lower-side element 5B can be grasped on the basis of another signal such as the command signal Sb.

[0107] The signal Sh output from the comparator 37 is input to the timing circuit 38. The timing circuit 38 outputs a signal Si of a binary value that becomes a high level for a certain time corresponding to the above-described discrimination time from the timing at which the signal Sh changes from a high level to a low level, i.e., the start timing of the turn-off of the lower-side element 5B. In this case, the turn-on and turn-off of the switch 16 is controlled by the signal Si output from the timing circuit 38.

[0108] According to the above configuration, during the period when the signal Si is at the high level, that is, before the timing at which the determination time elapses from the start timing of the turn-off of the lower-side element 5B, the switch 16 is on and the detection voltage Vb is input to the sample-and-hold circuit 36. In contrast, during the period when the signal Si is at the low level, that is, after the timing at which the determination time elapses from the start timing of the turn-off of the lower-side element 5B, the switch 16 is off and the detection voltage Vb is not input to the sample-and-hold circuit 36.

[0109] The detection voltage Vb input to the sample-and-hold circuit 36 is a detection value that represents the peak Vds_p at the time when the turn-off surge is generated when the conduction to the lower-side element 5B is forward conduction, and is a detection value that does not represent the peak Vds_p at the time when the turn-off surge is generated when the conduction to the lower-side element 5B is reverse conduction, and becomes substantially 0 V. Therefore, the sample-and-hold circuit 36 determines that it is the detection voltage Vb at the time of reverse conduction when the input detection voltage Vb is below a prescribed determination voltage that is set to a value higher than 0 V, and does not sample and hold the detection voltage Vb.

[0110] In contrast, the sample-and-hold circuit 36 determines that it is the detection voltage Vb at the time of forward conduction when the input detection voltage Vb exceeds the above determination voltage, and samples and holds the detection voltage Vb to hold and output to the operation section 34. According to this configuration, the detection voltage Vb that represents the detection value of the peak Vds_p at the time when the conduction to the lower-side element 5B is forward conduction, that is, at the time when the turn-off surge is generated, is input to the operation section 34.

[0111] In this case, the operation section 34 compares the detection value of the detection section 32 and a threshold value that is set corresponding to the allowable value of the peak Vds_p of the voltage Vds, and operates a value that represents the result of the comparison as a target command value. The specific configuration for realizing this operation is as follows. That is, a detection signal Sj corresponding to the detection value of a current detection section 42 that detects the current Id of the lower-side element 5B is input to a threshold value output section 39. The current detection section 42 can adopt various configurations such as the configuration using a shunt resistor Rs as shown in FIG. 6, Figure 6 the configuration using the sensor unit 25 and the shunt resistor Rsl as shown in FIG. 7, and the like. Figure 8 The threshold value output section 39 has a storage device such as a memory in which mapping data that is made based on the relationship between the threshold value and the current Id flowing in the semiconductor switching element 5 is stored. The relationship between the threshold value and the current Id becomes, for example, the relationship as shown in FIG. 8. Simulation, experiments, and the like can be performed in advance, and such mapping data can be made in advance based on the results thereof. In addition, the threshold value is set to a value that can control the size of the turn-off surge to the desired degree.

[0112] Figure 11 The threshold value output section 39 has a storage device such as a memory in which mapping data that is made based on the relationship between the threshold value and the current Id flowing in the semiconductor switching element 5 is stored. The relationship between the threshold value and the current Id becomes, for example, the relationship as shown in FIG. 8. Simulation, experiments, and the like can be performed in advance, and such mapping data can be made in advance based on the results thereof. In addition, the threshold value is set to a value that can control the size of the turn-off surge to the desired degree.​

[0113] The threshold output section 39 acquires the current value of the current Id based on the detection signal Sj, and acquires the threshold value corresponding to the current value of the current Id from the mapping data with reference to the above-described mapping data, and outputs the threshold voltage Ve corresponding to the acquired threshold value. The threshold voltage Ve output by the threshold output section 39 is input to the inverting input terminal of the comparator 40, and the detection voltage Vb output by the sample-and-hold circuit 36 is input to the non-inverting input terminal thereof.

[0114] The comparator 40 compares the threshold voltage Ve with the detection voltage Vb, and outputs a signal Sk indicating the result of the comparison as a binary signal to the drive section 35. That is, in this case, the signal Sk indicates a value indicating the gate resistance value of the lower side element 5B, and becomes a signal indicating the target command value corresponding to the switching speed of the semiconductor switching element 5. In the case where the detection voltage Vb is greater than the threshold voltage Ve, that is, in the case where the detection value of the voltage Vds_p at the time of generation of the turn-off surge is greater than the threshold value, the signal Sk becomes a high level. Further, in the case where the detection voltage Vb is less than the threshold voltage Ve, that is, in the case where the detection value of the voltage Vds_p at the time of generation of the turn-off surge is less than the threshold value, the signal Sk becomes a low level. In addition, the comparator 40 can also be configured to have hysteresis by detection and recovery. However, in this case, two threshold values need to be input to the comparator 40.

[0115] In this case, the drive section 35 switches the gate resistance value Rg_off of the semiconductor switching element 5, that is, the lower side element 5B of the main arm, in stages based on the signal Sk corresponding to the target command value. The specific configuration for achieving such switching of the gate resistance value Rg_off is as follows. That is, in the drive section 35, the drain of the transistor Q2 is connected to the node N3 via the resistance R21, and is connected to the node N3 via the resistance R22 and the switch 41.

[0116] The resistances R21, R22 are each a configuration having a certain resistance value, and function as the gate resistance at the time of turn-off of the lower side element 5B together with the wiring resistance of the path from the direct current power supply line 3 to the gate of the lower side element 5B and the like. In other words, the drive section 35 is configured so that two resistances R21, R22 functioning as the gate resistance at the time of turn-off are connected in parallel between the direct current power supply line 3 and the node N3. The on-off of the switch 41 is controlled by the signal Sk output from the operation section 34. Specifically, the switch 41 is turned off when the signal Sk is a high level, and is turned on when the signal Sk is a low level.

[0117] According to the above configuration, the switch 41 is turned off in a case where the detected value of the voltage Vds_p at the time of generation of the turn-off surge is greater than the threshold value, and thus the gate resistance value Rg_off at the time of turn-off becomes a value corresponding to the resistance value of the resistance R21, that is, a relatively large value, and the turn-off surge is suppressed. Further, according to the above configuration, the switch 41 is turned on in a case where the detected value of the voltage Vds_p at the time of generation of the turn-off surge is less than the threshold value, and thus the gate resistance value Rg_off at the time of turn-off becomes a value corresponding to the resistance value of the parallel combination of the resistances R21, R22, that is, a relatively small value, and high-speed switching is achieved.

[0118] Next, the timing of each control based on the above configuration will be described with reference to Figure 12 and Figure 13 In addition, the control of the gate drive device 31 side for driving the lower-side element 5B is described as an example, but the control of the gate drive device side for driving the upper-side element 5A is the same content. In Figure 12 and Figure 13 In addition, the command signals Sa, Sb are expressed as binary signals indicating on at a high level and off at a low level.

[0119] First, the timing of each control at the time of forward conduction of the energization of the semiconductor switching element 5, that is, the lower-side element 5B of the present arm will be described with reference to Figure 12 In this case, when the command signal Sb is changed from a low level to a high level at time t1, the voltage Vgs starts to rise. In this case, as the voltage Vgs rises, the current Id rises and the voltage Vds falls. Then, when the voltage Vgs reaches the threshold voltage Vth at time t2, the signal Sh is changed from a low level to a high level.

[0120] After that, when the command signal Sb is changed from a high level to a low level at time t3, the voltage Vgs starts to fall. Then, when the voltage Vgs reaches the threshold voltage Vth at time t4, the signal Sh is changed from a high level to a low level. Although not shown, the signal Si is a high level during a period from time t4 to the elapse of the determination time. In this case, the energization of the lower-side element 5B is forward conduction, and thus a surge is generated immediately after the turn-off start timing of the lower-side element 5B, that is, at time t3, and the voltage Vds exceeds the off voltage Vds_off and sharply rises.

[0121] Therefore, the detection voltage Vb higher than 0 V is input to the sample-and-hold circuit 36. Therefore, the sample-and-hold circuit 36 samples the detection voltage Vb at the time t5 when a prescribed time elapses from the time t4. Thereby, the detection voltage Vb representing the detection value of the peak value Vds_p at the time when the off surge is generated is input to the operation section 34. The operation section 34 generates the signal Sk using such detection voltage Vb. Then, in the drive section 35, the switching of the gate resistance value Rg_off is performed based on the signal Sk imparted from the operation section 34. At the time t6 when a prescribed time elapses from the time t5, the output of the peak holding circuit 15 is reset.

[0122] Next, the operation of the semiconductor switching element 5 will be described with reference to FIG. 6. Figure 13 The timing of the control at the time of the reverse conduction of the semiconductor switching element 5, i.e., the lower side element 5B of the present arm will be described. In this case, also, when the command signal Sb is turned from the low level to the high level at the time t1, the voltage Vgs starts to rise. However, in this case, since the lower side element 5B performs the backflow operation, the current Id and the voltage Vds do not change greatly and the voltage Vds is maintained at 0 V. Then, when the voltage Vgs reaches the threshold voltage Vth at the time t2, the signal Sh is turned from the low level to the high level.

[0123] After that, when the command signal Sb is turned from the high level to the low level at the time t3, the voltage Vgs starts to fall. Then, when the voltage Vgs reaches the threshold voltage Vth at the time t4, the signal Sh is turned from the high level to the low level. Although not shown, the signal Si becomes the high level during the period from the time t4 to when the prescribed time elapses. In this case, the conduction of the lower side element 5B is the reverse conduction, and therefore, no surge is generated immediately after the off start timing of the lower side element 5B, i.e., the time t3, and the voltage Vds is maintained at 0 V.

[0124] Therefore, the detection voltage Vb of 0 V is input to the sample-and-hold circuit 36. Therefore, the sample-and-hold circuit 36 does not sample and hold the detection voltage Vb, and does not input the detection voltage Vb to the operation section 34, and therefore, the generation of the signal Sk is not performed. Thus, the drive section 35 does not perform the switching of the gate resistance value Rg_off. At the time t6 when a prescribed time elapses from the time t5, the output of the peak holding circuit 15 is reset. In this case, also, a recovery surge is generated immediately after the conduction start timing of the upper side element 5A of the semiconductor switching element 5 of the opposite arm side, i.e., the time t7, when the command signal Sa is turned from the low level to the high level, and the voltage Vds exceeds the off voltage Vds_off and sharply rises.

[0125] The configuration of this embodiment, as described above, is the same as that of the first embodiment. The gate resistance value Rg_off is changed based on a target command value calculated using only the surge voltage that controls the shutdown surge. Therefore, the same effect as the first embodiment can be obtained, namely, the ability to appropriately control the shutdown surge. Furthermore, in this embodiment, the calculation using only the surge voltage that controls the shutdown surge is performed with the following considerations.

[0126] That is, when the semiconductor switching element 5 of this arm is forward-biased, a turn-off surge is generated immediately after the gate of the semiconductor switching element 5 is turned off. Therefore, if the detection voltage Vb corresponding to the detection value of the peak value Vds_p after a predetermined time from the start of the turn-off of the semiconductor switching element 5 of this arm is sampled, held, and output to the arithmetic unit 34, the arithmetic unit 34 can use the detection voltage Vb, which represents the detection result of the surge voltage including only the turn-off surge, to calculate the target command value. In this embodiment, by adopting the above-described configuration, such calculation of the target command value is possible.

[0127] In this case, the calculation unit 34 compares the detection voltage Vb, which represents the detection value of the detection unit 11, with a threshold value set corresponding to the allowable value of the peak value Vds_p, and calculates a value representing the comparison result as a target command value. Then, the drive unit 35 switches the gate resistance value Rg_off of the semiconductor switching element 5 of this arm in stages based on the signal Sk corresponding to the target command value. In this way, compared with the configuration of continuously switching the gate resistance value Rg_off as in the first embodiment, the configuration and control can be simplified.

[0128] <Variations related to switching of gate resistance>

[0129] exist Figure 10 In the specific configuration example shown, the driving unit 35 is configured to switch the gate resistance value Rg_off of the semiconductor switching element 5 of this arm in two stages based on the signal Sk corresponding to the target command value. However, the driving unit 35 can also be configured to switch the gate resistance value Rg_off in three stages based on the signal Sk. In this configuration, the arithmetic unit 34 needs to compare the detected voltage Vb with multiple thresholds and calculate the value representing the comparison result as the target command value. Therefore, in this configuration, the amount of pre-stored mapping data, the number of comparators, and the number of switches used to switch the gate resistance value Rg_off will increase.

[0130] (Third Implementation)

[0131] The following is for reference Figure 14 The third embodiment will be described.

[0132] In this embodiment, the specific configuration of the gate drive device is different from that of the first embodiment. That is, as shown in FIG. 5, the gate drive device 51 of this embodiment is different from the gate drive device IB of the first embodiment shown in FIG. 4 in that the detection section, the discrimination section, the operation section, and the drive section are changed in specific configuration. Figure 14 Figure 6 Figure 14

[0133] The gate drive device 51 has a detection section 52, a discrimination section 53, an operation section 54, and a drive section 55. The detection section 52 has a configuration in which a rate-of-change detection section 56, a switching section 57, switches 58, 59 are provided. The discrimination section 53 has a configuration in which a comparator 60 and a sample-and-hold circuit 61 are provided. The operation section 54 has a configuration in which sample-and-hold circuits 62, 63, a polarity inverting section 64, a threshold value output section 65, and comparators 66, 67 are provided. The drive section 55 is configured so as to have resistors R31, R32 and a switch 68 instead of the resistor Rl, and resistors R41, R42 and a switch 69 instead of the resistor R2, unlike the drive section 14.

[0134] In this case, the detection section 52 detects the rate of change of the voltage Vds, i.e., dV / dt, in the change period of the voltage Vds of the semiconductor switching element 5, i.e., the lower-side element 5B, of the present arm. The specific configuration for achieving such detection is as follows. That is, the voltage of the node Nl, i.e., the drain voltage of the lower-side element 5B, is input to the rate-of-change detection section 56. The rate-of-change detection section 56 is configured to input the drain voltage of the lower-side element 5B, i.e., the voltage Vds, with the source potential of the lower-side element 5B as a reference, and to detect dV / dt thereof.

[0135] The rate-of-change detection section 56 outputs a detection voltage Vf representing the detected value of dV / dt. In addition, the rate-of-change detection section 56 outputs a binary signal Sm that becomes a high level when the detected value of dV / dt is a positive value and becomes a low level when the detected value of dV / dt is 0 V or a negative value. The detection voltage Vf is imparted to the input terminal of the switching section 57. The switching section 57 switches which of the one output terminal and the other output terminal outputs the input detection voltage Vf based on the level of the signal Sm output from the rate-of-change detection section 56. Specifically, the switching section 57 outputs the input detection voltage Vf from the one output terminal when the signal Sm is a high level, and outputs the input detection voltage Vf from the other output terminal when the signal Sm is a low level.

[0136] ​​​According to this configuration, the detected value of dV / dt when the lower element 5B is off becomes a positive value, and therefore the detection voltage Vf is output from the output terminal of one side of the switching section 57, and the detected value of dV / dt when the lower element 5B is on becomes a negative value, and therefore the detection voltage Vf is output from the output terminal of the other side of the switching section 57. That is, the detection voltage Vf output from the output terminal of one side of the switching section 57 indicates dV / dt when the lower element 5B is off, and is supplied to the arithmetic section 54 in the subsequent stage via the switch 58. Further, the detection voltage Vf output from the output terminal of the other side of the switching section 57 indicates dV / dt when the lower element 5B is on, and is supplied to the arithmetic section 54 in the subsequent stage via the switch 59. The on / off of the switches 58, 59 is controlled identically in accordance with the signal Sn output from the discrimination section 53.

[0137] In the case where the voltage Vds during the on period when the lower element 5B is on is a positive voltage value, it can be considered that the energization to the lower element 5B is forward energization. Further, in the case where the voltage Vds during the on period when the lower element 5B is on is a negative voltage value, it can be considered that the energization to the lower element 5B is reverse energization. Therefore, the discrimination section 53 detects the voltage Vds during the on period when the lower element 5B is on, and discriminates that the energization to the lower element 5B is forward energization during the period when the detected value of the voltage Vds is a positive value, and discriminates that the energization to the lower element 5B is reverse energization during the period when the detected value of the voltage Vds is a negative value. The specific configuration for realizing this discrimination is as follows.

[0138] That is, the non-inverting input terminal of the comparator 60 is connected to the node Nl, and the inverting input terminal thereof is connected to the direct current power supply line 3. That is, the drain voltage of the lower element 5B is input to the non-inverting input terminal of the comparator 60, and the source voltage of the lower element 5B is input to the inverting input terminal thereof. According to this configuration, the binary signal Sl output from the comparator 60 is high level when the voltage Vds is a positive value, that is, "Vds > 0", and is low level when the voltage Vds is a negative value, that is, "Vds < 0".

[0139] The signal Sl output from the comparator 60 is input to the sample-and-hold circuit 61. The sample-and-hold circuit 61 samples the signal Sl at an arbitrary timing during the period when the lower element 5B is on. In addition, as explained in the 2nd embodiment, the period when the lower element 5B is on can be grasped on the basis of the voltage Vgs, the command signal Sb, and the like. The sample-and-hold circuit 61 outputs the binary signal Sn obtained by sampling and holding the signal Sl.

[0140] According to the above configuration, when the energization to the lower-side element 5B is forward energization, the signal Sn becomes high, and thus the switches 58, 59 are turned on and the detection voltage Vf is input to the operation section 54. In contrast, when the energization to the lower-side element 5B is reverse energization, the signal Sn becomes low, and thus the switches 58, 59 are turned off and the detection voltage Vf is not input to the operation section 54. That is, in the above configuration, the detection voltage Vf, which indicates the detection value of dV / dt at the time of turn-off and each detection value of dV / dt at the time of turn-on during the period in which the energization to the lower-side element 5B is forward energization, is input to the operation section 54. In addition, in the following description and Figure 14 the detection voltage Vf indicating the detection value of dV / dt at the time of turn-off is referred to as a detection voltage Vf off, and the detection voltage indicating the detection value of dV / dt at the time of turn-on is referred to as a detection voltage Vf on.

[0141] In this case, the operation section 54 operates a target command value in which the detection value of dV / dt becomes a permissible value or less, on the basis of the detection value of dV / dt detected by the detection section 52 during the period in which the energization to the lower-side element 5B is forward energization, which is discriminated by the discrimination section 53, and the permissible value of dV / dt. The permissible value of dV / dt is the same as the permissible value of the peak value of the voltage Vds, and is determined in accordance with the specifications of the semiconductor switching element 5. The target command value in this case is also the same as in each of the above embodiments, and becomes a value indicating the gate resistance value of the semiconductor switching element 5. However, in the target command value in this case, not only a value indicating the gate resistance value Rg off at the time of turn-off, but also a value indicating the gate resistance value Rg on at the time of turn-on is included.

[0142] The specific configuration for realizing such operation is as follows. That is, the detection voltage Vf off is input to a sample-and-hold circuit 62, and the detection voltage Vf on is input to a sample-and-hold circuit 63. The sample-and-hold circuit 62 samples and holds the input detection voltage Vf off and holds it, and outputs it to a non-inverting input terminal of a comparator 66. The sample-and-hold circuit 63 samples and holds the input detection voltage Vf on and holds it, and outputs it to a non-inverting input terminal of a comparator 67. However, the detection voltage Vf on is a negative voltage value, and thus, after the polarity is reversed by a polarity reversal section 64, it is output to the comparator 67.

[0143] The threshold output section 65 has the same configuration as the threshold output section 39 in the second embodiment, and includes a storage device such as a memory in which mapping data is stored. In this case, the threshold values include a turn-off threshold value corresponding to the gate resistance Rg off and an on threshold value corresponding to the gate resistance Rg on. In addition, the turn-off threshold value and the on threshold value can each be set to different values, or can be set to the same value. Although not shown, the threshold output section 65 has the same configuration as the threshold output section 39, and can obtain the current value of the current Id.

[0144] The threshold output section 65 obtains the current value of the current Id, and refers to the mapping data described above to obtain the threshold value corresponding to the current value of the current Id from the mapping data, and outputs a threshold voltage corresponding to the obtained threshold value. In this case, the threshold output section 65 outputs two threshold voltages, specifically, a threshold voltage Vg off corresponding to the turn-off threshold value and a threshold voltage Vg on corresponding to the on threshold value.

[0145] The threshold voltage Vg off output from the threshold output section 65 is input to the inverting input terminal of the comparator 66. The comparator 66 compares the threshold voltage Vg off with the detection voltage Vf off, and outputs a signal So indicating a binary value of the comparison result to the drive section 55. That is, in this case, the signal So is a signal indicating a value indicating the gate resistance value Rg off of the lower element 5B, and indicating a target command value corresponding to the switching speed of the semiconductor switching element 5.

[0146] In the case where the detection voltage Vf off is greater than the threshold voltage Vg off, that is, in the case where the detected value of dV / dt at the time of forward conduction and at the time of turn-off is greater than the allowable value, the signal So becomes high. In addition, in the case where the detection voltage Vf off is less than the threshold voltage Vg off, that is, in the case where the detected value of dV / dt at the time of forward conduction and at the time of turn-off is less than the allowable value, the signal So becomes low.

[0147] The threshold voltage Vg on output from the threshold output section 65 is input to the inverting input terminal of the comparator 67. The comparator 67 compares the threshold voltage Vg on with the detection voltage Vf on after the polarity is reversed, and outputs a signal Sp indicating a binary value of the comparison result to the drive section 55. That is, in this case, the signal Sp is a signal indicating a value indicating the gate resistance value Rg on of the lower element 5B, and indicating a target command value corresponding to the switching speed of the semiconductor switching element 5.

[0148] The signal Sp becomes a high level in a case where the detection voltage Vf_on after the polarity inversion is greater than the threshold voltage Vg_on, that is, in a case where the detected value of dV / dt at the time of the forward conduction and the conduction is greater than the allowable value. Further, the signal Sp becomes a low level in a case where the detection voltage Vf_on after the polarity inversion is less than the threshold voltage Vg_on, that is, in a case where the detected value of dV / dt at the time of the forward conduction and the conduction is less than the allowable value. In this case, the voltage after the polarity inversion of the detection voltage Vf_on is input to the comparator 67, but instead, the voltage after the polarity inversion of the threshold voltage Vg_on can be input to the comparator 67.

[0149] In this case, the drive section 55 switches the gate resistance value Rg_off of the semiconductor switching element 5, that is, the lower side element 5B of the main arm, on a stage-by-stage basis on the basis of the signal So corresponding to the target command value. Further, in this case, the drive section 55 switches the gate resistance value Rg_on of the lower side element 5B on a stage-by-stage basis on the basis of the signal Sp corresponding to the target command value. Furthermore, in this case, the drive section 55 completes the change of the gate resistance values Rg_on, Rg_off before the next time the lower side element 5B is switched. Specifically, the drive section 55 completes the change of the gate resistance value Rg_off before the next time the lower side element 5B is turned off, and completes the change of the gate resistance value Rg_on before the next time the lower side element 5B is turned on.

[0150] The specific configuration for realizing such switching of the gate resistance values Rg_off, Rg_on is as follows. That is, in the drive section 55, the drain of the transistor Q1 is connected to the node N3 via the resistance R31, and is connected to the node N3 via the resistance R32 and the switch 68. The resistances R31, R32 are each a configuration having a certain resistance value, and function as the gate resistance at the time of the conduction of the lower side element 5B together with the wiring resistance and the like of the path from the direct current power supply line 23 to the gate of the lower side element 5B.

[0151] In other words, the drive section 55 is configured so that two resistances R31, R32 that function as the gate resistance at the time of the conduction are connected in parallel between the direct current power supply line 23 and the node N3. The on-off of the switch 68 is controlled by the signal Sp output from the arithmetic section 54. Specifically, the switch 68 is turned off when the signal Sp is a high level, and is turned on when the signal Sp is a low level.

[0152] Further, in the drive section 55, the drain of the transistor Q2 is connected to the node N3 via the resistance R41, and is connected to the node N3 via the resistance R42 and the switch 69. The resistances R41, R42 are each a configuration having a certain resistance value, and function as the gate resistance at the time of the turn-off of the lower side element 5B together with the wiring resistance and the like of the path from the direct current power supply line 3 to the gate of the lower side element 5B.

[0153] In other words, the drive section 55 is configured so that two resistors R41, R42 that function as gate resistance at the time of turning off are connected in parallel between the direct-current power supply line 3 and the node N3. The on-off of the switch 69 is controlled by the signal So output from the operation section 54. Specifically, the switch 69 is turned off when the signal So is at a high level, and is turned on when the signal So is at a low level.

[0154] According to the present embodiment described above, the following effects can be obtained.

[0155] In the above configuration, in the case where the detected value of dV / dt is greater than the allowable value, the switch 68 is turned off in the drive section 55, and thus the gate resistance value Rg_on becomes a value corresponding to the resistance value of the resistor R31, i.e., a relatively large value, and dV / dt at the time of turning on is suppressed to a relatively small value. Further, in the above configuration, in the case where the detected value of dV / dt is less than the allowable value, the switch 68 is turned on in the drive section 55, and thus the gate resistance value Rg_on becomes a value corresponding to the combined resistance value of the resistors R31, R32, i.e., a relatively small value, and dV / dt at the time of turning on becomes a relatively large value, and a high-speed switch can be realized.

[0156] According to the above configuration, in the case where the detected value of dV / dt is greater than the allowable value, the switch 69 is turned off in the drive section 55, and thus the gate resistance value Rg_off becomes a value corresponding to the resistance value of the resistor R41, i.e., a relatively large value, and dV / dt at the time of turning off is suppressed to a relatively small value. Further, in the above configuration, in the case where the detected value of dV / dt is less than the allowable value, the switch 69 is turned on in the drive section 55, and thus the gate resistance value Rg_off becomes a value corresponding to the combined resistance value of the resistors R41, R42, i.e., a relatively small value, and dV / dt at the time of turning off becomes a relatively large value, and a high-speed switch can be realized.

[0157] Thus, according to the configuration of the present embodiment, it is possible to control dV / dt at the time of turning on and at the time of turning off of the semiconductor switching element 5 of the own arm to an optimum value, specifically, to a value that does not exceed the allowable value and enables a high-speed switch. Further, according to the configuration of the present embodiment, the same effects as those of the first embodiment and the like can be obtained as follows.

[0158] That is, the detection section 52 detects dV / dt at the time of turning off in the change period of the voltage Vds change of the semiconductor switching element 5 of the own arm. dV / dt at the time of turning off in the change period becomes a value corresponding to the magnitude of the surge applied to the main terminal of the semiconductor switching element 5. Therefore, in this case, it can be said that the detection section 52 detects the magnitude of the surge applied to the main terminal of the semiconductor switching element 5 of the own arm.

[0159] The discrimination section 53 discriminates whether the energization of the semiconductor switching element 5 of the own arm during the change period is forward energization or reverse energization. That is, in this case, it can also be said that the discrimination section 53 discriminates whether the generated surge is an off surge or a recovery surge. The operation section 54 operates a target command value corresponding to the switching speed of the semiconductor switching element 5, such that the dV / dt becomes a value or less of the allowable value, based on the detection value of the detection section 52 during the change period in which the discrimination section 53 discriminates that the energization of the semiconductor switching element 5 of the own arm is forward energization, and the allowable value of the dV / dt determined in accordance with the specifications of the semiconductor switching element 5. That is, the operation section 54 operates a target command value such that the detection value of the dV / dt becomes a value or less of the allowable value, based on the detection value corresponding to the magnitude of the surge during the change period in which it is discriminated that the generated surge is an off surge, and the allowable value.

[0160] The drive section 55 changes the gate resistance value Rg_off of the semiconductor switching element 5 of the own arm based on the target command value operated by the operation section 54, and drives the gate of the semiconductor switching element 5 of the own arm. That is, the drive section 55 changes the gate resistance value Rg_off based on the target command value operated using the detection result of the surge voltage containing only the off surge. According to this configuration, the following excellent effect can be obtained: it is possible to control the magnitude of the off surge such that the detection value of the dV / dt does not exceed the allowable value and the switching loss does not excessively increase, in other words, it is possible to appropriately control the off surge.

[0161] In this case, the discrimination section 53 detects the voltage Vds during the on period in which the semiconductor switching element 5 of the own arm is on, discriminates that the energization of the semiconductor switching element 5 of the own arm is forward energization during a period in which the detection value of the voltage Vds is a positive value, and discriminates that the above energization is reverse energization during a period in which the detection value of the voltage Vds is a negative value. As described above, it can be considered that the voltage Vds during the on period changes depending on the direction of the energization of the semiconductor switching element 5. Thus, according to the above configuration, it is possible to accurately discriminate whether the energization of the semiconductor switching element 5 of the own arm is forward energization or reverse energization.

[0162] (4th Embodiment)

[0163] Hereinafter, the 4th embodiment will be described with reference to Figure 15 The 4th embodiment will be described.

[0164] In each of the above embodiments, the detection result of the surge voltage becomes a configuration in which it is possible to divide into a portion containing the off surge and a portion containing the recovery surge, but does not become a configuration in which the detection result of the surge voltage containing the recovery surge is effectively utilized. Therefore, in the present embodiment, a configuration in which the detection result of such surge voltage containing the recovery surge is effectively utilized will be described.

[0165] As described above, in the present embodiment, the detection result of the surge voltage containing the off surge and the recovery surge isFigure 15 The gate drive devices 71A, 71B of this embodiment are configured as shown in FIG. 7A and FIG. 7B, respectively, with respect to the Figure 6 The gate drive device 1B of the first embodiment shown in FIG. 7B is changed in the specific configuration of the detection section, the discrimination section, the operation section, and the drive section. Also, here, regarding the gate drive device 71A for driving the upper-side element 5A, although the illustration and explanation of the specific configuration are omitted, the same configuration as the gate drive device 71B is adopted.

[0166] The gate drive device 71B is provided with the detection section 72, the discrimination section 33 which is the same as that of the second embodiment, the operation section 74, and the drive section 75. The detection section 72 is configured such that the difference from the detection section 11 is that the switching section 76 is provided in place of the switch 16. The input terminal of the switching section 76 is given the detection voltage Vb. The switching section 76 switches which of the one output terminal and the other output terminal outputs the input detection voltage Vb based on the level of the signal Si output from the discrimination section 33.

[0167] As explained in the second embodiment, the signal Si is a signal which becomes the high level during the period from the start timing of the turn-off of the semiconductor switching element 5 of the home arm to the timing at which the determination time elapses, and becomes the low level during other periods. That is, the period during which the signal Si is the high level is a period during which the turn-off surge is likely to occur, and the period during which the signal Si is the low level is a period during which the recovery surge is likely to occur. In this case, the switching section 76 outputs the input detection voltage Vb from the one output terminal when the signal Si is the high level, and outputs the input detection voltage Vb from the other output terminal when the signal Si is the low level.

[0168] According to this configuration, the detection voltage Vb output from the one output terminal of the switching section 76 indicates the detection value of the peak value Vds_p at the time of the occurrence of the turn-off surge, and is given to the operation section 74 of the subsequent stage. Also, according to the above configuration, the detection voltage Vb output from the other output terminal of the switching section 76 indicates the detection value of the peak value Vds_p at the time of the occurrence of the recovery surge, and is given to the operation section 74 of the gate drive device 71A of the opposite arm side. Also, in the following explanation and Figure 15 , the detection voltage Vb corresponding to the turn-off surge which is output from the one output terminal of the switching section 76 is referred to as the detection voltage Vbo, and the detection voltage Vb corresponding to the recovery surge which is output from the other output terminal of the switching section 76 is referred to as the detection voltage Vbr.

[0169] The arithmetic unit 74 is configured to differ from the arithmetic unit 13 in that a subtracter 77 and a controller 78 are added. The arithmetic unit 74, like the arithmetic unit 13, operates the target command value such that the peak value Vds_p becomes the allowable value or less, based on the detection value of the detection section 72 and the allowable value of the peak value Vds_p in the change period in which the energization of the semiconductor switching element 5, i.e., the lower element 5B, is determined by the discrimination section 33 to be forward energization. Further, the arithmetic unit 74 operates the target command value such that the peak value Vds_p becomes the allowable value or less, based on the peak value Vds_p detected by the detection section 72 and the allowable value in the change period in which the energization of the lower element 5B is determined by the discrimination section 33 to be reverse energization. The specific configuration for achieving such operation is as follows.

[0170] That is, the allowable voltage Vc is given to the + input of the subtracter 20, and the detection voltage Vbo is given to the - input thereof. The subtracter 20 obtains the deviation AV that corresponds to the difference between the detection value of the peak value Vds_p at the time of generation of the off surge and the allowable value, by subtracting the detection voltage Vbo from the allowable voltage Vc, and outputs the deviation AV to the controller 21. Further, the allowable voltage Vc is given to the + input of the subtracter 77, and the detection voltage Vbr output from the detection section 72 of the gate drive device 71A is given to the - input thereof.

[0171] The subtracter 77 obtains the deviation AV that corresponds to the difference between the detection value of the peak value Vds_p at the time of generation of the recovery surge and the allowable value, by subtracting the detection voltage Vbr from the allowable voltage Vc, and outputs the deviation AV to the controller 78. The controller 78 is configured the same as the controller 21, and generates the command signal Sq that indicates the target command value, by performing the PID operation on the deviation AV. The command signal Sq is output to the drive section 75.

[0172] The drive section 75, like the drive section 14, changes the gate resistance value Rg_off at the time of off of the semiconductor switching element 5 of the home arm, based on the target command value operated by the arithmetic unit 74. Further, the drive section 75 changes the gate resistance value Rg_on at the time of on of the semiconductor switching element 5 of the home arm, based on the target command value operated by the arithmetic unit 74 of the gate drive device 71A of the opposite arm side. Further, in this case, the drive section 75 completes the change of the gate resistance value Rg_on before the semiconductor switching element 5 of the home arm is turned on next time. In the present embodiment, the drive section 75 continuously switches the gate resistance value Rg_on based on the target command value. The specific configuration for achieving such drive is as follows.

[0173] That is, the drive section 75 is configured so as to differ from the drive section 14 in that the resistor R51 is provided instead of the resistor Rl. The resistor R51 is configured so as to be able to change its resistance value based on the command signal Sq imparted from the operation section 74. That is, in the above-described configuration, the gate resistance value Rg_on at the time when the lower-side element 5B is turned on is changed based on the command signal Sq. In addition, the change in the resistance value of the resistor R51 can be performed by the same method as the change in the resistance value of the resistor R2.

[0174] According to the configuration of the present embodiment described above, as with the first embodiment, the change in the gate resistance value Rg_off is performed based on the target command value calculated using the detection result of the surge voltage including only the turn-off surge, and thus the same effects as the first embodiment, i.e., the effects that the turn-off surge can be appropriately controlled, can be obtained. In this case, the detection voltage Vbr corresponding to the detection result of the surge voltage including only the recovery surge is transmitted between the gate drive devices 71A and 71B.

[0175] Then, the gate drive devices 71A and 71B calculate the target command value using the detection voltage Vbr transmitted from the gate drive device on the opposite arm side, i.e., the detection result of the surge voltage including only the recovery surge, and perform the change in the gate resistance Rg_on based on the target command value. According to this configuration, the following excellent effects can be obtained: the size of the recovery surge can be controlled so that the peak value Vds_p of the voltage Vds does not exceed the allowable value and the switching loss does not excessively increase, in other words, the recovery surge can be appropriately controlled.

[0176] In this case, the drive section 75 completes the change in the gate resistance value Rg_on before the semiconductor switching element 5 on the home arm is next turned on. That is, in the present embodiment, when the target command value is calculated based on the detected value of the peak value Vds_p of the voltage Vds in the prescribed drive period, the calculated result thereof is actually reflected in the gate resistance value Rg_on at the time when the semiconductor switching element 5 on the home arm is next turned on. According to this control, the optimization of the gate resistance value Rg_on can be more reliably and more quickly achieved, i.e., the above-described effects can be maximally obtained.

[0177] (Fifth Embodiment)

[0178] Hereinafter, the fifth embodiment will be described with reference to Figure 16 The fifth embodiment will be described.

[0179] In the present embodiment, a part of each function of the gate drive device differs from the first embodiment. That is, as shown in FIG. 8, the gate drive device 81 differs from the gate drive device 1 in that the operation section 82 is provided instead of the operation section 13. Figure 16 In the present embodiment, the operation section 82 is configured so as to be able to calculate the target command value based on the detection result of the surge voltage including only the turn-off surge.

[0180] Generally, the element withstand voltage of the semiconductor switching element 5, that is, the surge resistance, depends on the temperature around the semiconductor switching element 5. Specifically, the higher the temperature around, the higher the element withstand voltage, and the lower the temperature around, the lower the element withstand voltage. Further, in a case where the semiconductor switching element 5 is driven with a prescribed gate resistance value, when the load current IL varies, the surge voltage also varies depending on the variation thereof. Specifically, if the gate resistance value is constant, when the load current IL increases, the peak value of the surge voltage rises, and when the load current IL decreases, the peak value of the surge voltage falls. In addition, the same can be said for the current Id flowing in the semiconductor switching element 5 as the load current IL.

[0181] Further, in a case where the semiconductor switching element 5 is driven with a prescribed gate resistance value, when the power supply voltage Va varies, the surge voltage also varies depending on the variation thereof. Specifically, if the gate resistance value is constant, when the power supply voltage Va increases, the peak value of the surge voltage rises, and when the power supply voltage Va decreases, the peak value of the surge voltage falls. In addition, the same can be said for the off voltage Vds off of the semiconductor switching element 5 as the power supply voltage Va.

[0182] In a state where the gate resistance value is optimized, when the surge voltage rises with the change of the above-mentioned temperature around, the load current IL, the power supply voltage Va, and the like, it is possible that a voltage exceeding the element withstand voltage is applied to the main terminal of the semiconductor switching element 5. Further, in a state where the gate resistance value is optimized, when the surge voltage falls with the change of the above-mentioned temperature around, the load current IL, the power supply voltage Va, and the like, the gate resistance value is set too high, and the switching loss accordingly increases.

[0183] In view of this, the operation section 82 acquires at least one of the temperature around, the load current IL, and the power supply voltage Va as a variation parameter, and changes the allowable value of the peak value Vds p based on the relationship between the acquired variation parameter and the detection value of the detection section 11. Thus, even in a case where the temperature around, the load current IL, and the power supply voltage Va vary, it is possible to optimize the gate resistance value on the basis of taking into account the variation thereof, that is, external disturbance. Thus, according to the present embodiment, it is possible to appropriately control the off surge regardless of the variation of the temperature around, the load current, and the power supply voltage Va, and the like.

[0184] (6th Embodiment)

[0185] Hereinafter, the 6th embodiment will be described with reference to Figure 17 The 6th embodiment will be described.

[0186] In the present embodiment, a part of each function that the gate drive device has is different from the 3rd embodiment. That is, as Figure 17As shown, the difference between the gate drive device 91 and the gate drive device 51 is that the gate drive device 91 is provided with the operation section 92 instead of the operation section 54.

[0187] The temperature of the surroundings, the load current IL, and the variation of the power supply voltage Va have the same effect on dV / dt as the surge voltage. In addition, in general, the allowable value of dV / dt for the semiconductor switching element 5 depends on the atmospheric pressure of the surroundings. Specifically, the higher the atmospheric pressure of the surroundings, the higher the allowable value.

[0188] In the state where the gate resistance value is optimized, when dV / dt rises with the change in the temperature of the surroundings, the atmospheric pressure of the surroundings, the load current IL, the power supply voltage Va, and the like, dV / dt can exceed the allowable value. In addition, in the state where the gate resistance value is optimized, when dV / dt falls with the change in the temperature of the surroundings, the load current IL, the power supply voltage Va, and the like, the gate resistance value can be set too high, and the switching loss can accordingly increase.

[0189] In view of this, the operation section 92 acquires at least one of the temperature of the surroundings, the atmospheric pressure of the surroundings, the load current IL, and the power supply voltage Va as a variation parameter, and changes the allowable value of dV / dt based on the relationship between the acquired variation parameter and the detection value of the detection section 52. In this way, even when the temperature of the surroundings, the atmospheric pressure of the surroundings, the load current IL, and the power supply voltage Va vary, the gate resistance value can be optimized in consideration of the variation, that is, external disturbance. Thus, according to the present embodiment, dV / dt can be appropriately controlled regardless of the variation in the temperature of the surroundings, the atmospheric pressure of the surroundings, the load current, and the power supply voltage Va, and the like.

[0190] (Other Embodiments)

[0191] In addition, the present application is not limited to each of the embodiments described above and illustrated in the drawings, and can be arbitrarily modified, combined, or expanded without departing from the gist thereof.

[0192] The numerical values and the like shown in each of the embodiments described above are examples, and are not limited thereto.

[0193] The drive section 14, 35, 55, 75 is configured to change the gate resistance value of the semiconductor switching element 5 of the robot arm based on the calculated target command value, but can instead be configured to change the gate current value of the semiconductor switching element 5 of the robot arm based on the calculated target command value. In the case where the configuration is changed to this, the same effects as those of each of the embodiments described above can be obtained.

[0194] The gate drive device in each of the above-described embodiments is not limited to the N-channel MOSFET, and can take various semiconductor switching elements such as a P-channel MOSFET and an IGBT as a drive object.

[0195] Although the present application is described based on the embodiment, it should be understood that the present application is not limited to the embodiment, the configuration. The present application also includes various modifications, modifications within the equivalent scope. Also, various combinations and modes, even other combinations, modes including only one element, above or below thereof fall within the scope, the idea range of the present application.

Claims

1. A gate drive device that drives gates of two semiconductor switching elements that constitute upper and lower arms of a half-bridge circuit, comprising: a detection section that detects a peak value of an element voltage that is a voltage of a main terminal of one of the semiconductor switching elements or a rate of change of the element voltage in a change period in which the element voltage changes; a discrimination section that discriminates whether energization of the one of the semiconductor switching elements in the change period is forward energization in which a forward current flows or reverse energization in which a reverse current flows; a calculation section that calculates a target command value corresponding to a switching speed of the semiconductor switching element, in which the peak value or the rate of change becomes a value or less, based on a detection value of the detection section in the change period in which the discrimination section discriminates that the energization of the one of the semiconductor switching elements is the forward energization and an allowable value of the peak value or the rate of change that is determined according to a specification of the semiconductor switching element; and a drive section that changes a gate resistance value or a gate current value of the one of the semiconductor switching elements based on the target command value calculated by the calculation section and drives the gate of the semiconductor switching element.

2. The gate drive device according to claim 1, wherein the detection section detects the peak value of the element voltage in the change period, the calculation section calculates the target command value corresponding to the switching speed of the semiconductor switching element, in which the peak value becomes the allowable value or less, based on the peak value detected by the detection section in the change period in which the discrimination section discriminates that the energization of the one of the semiconductor switching elements is the forward energization and the allowable value, and the drive section changes the gate resistance value or the gate current value at the time when the one of the semiconductor switching elements is turned off based on the target command value calculated by the calculation section.

3. The gate drive device according to claim 2, wherein the drive section completes the change of the gate resistance value or the gate current value before the one of the semiconductor switching elements is next turned off.

4. The gate drive device according to claim 1 or 2, wherein the calculation section calculates the target command value corresponding to the switching speed of the semiconductor switching element, in which the peak value becomes the allowable value or less, based on the peak value detected by the detection section in the change period in which the discrimination section discriminates that the energization of the one of the semiconductor switching elements is the reverse energization and the allowable value, and the drive section changes the gate resistance value or the gate current value at the time when the other of the semiconductor switching elements is turned on based on the target command value calculated by the calculation section.

5. The gate drive device according to claim 4, wherein the drive section completes the change of the gate resistance value or the gate current value before the other of the semiconductor switching elements is next turned on.

6. The gate drive device according to claim 1, wherein the detection section detects the rate of change of the element voltage in the change period, the calculation section calculates the target command value corresponding to the switching speed of the semiconductor switching element, in which the rate of change becomes a value or less, based on the rate of change detected by the detection section in the change period in which the discrimination section discriminates that the energization of the one of the semiconductor switching elements is the forward energization or the reverse energization and an allowable value of the rate of change that is determined according to a specification of the semiconductor switching element, and the drive section changes the gate resistance value or the gate current value of the one of the semiconductor switching elements based on the target command value calculated by the calculation section. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The operation section operates a target command value corresponding to a switching speed of the semiconductor switching element, which becomes equal to or lower than the allowable value, based on the rate of change detected by the detection section during the change period in which the energization of the one semiconductor switching element is determined by the determination section to be the forward energization and the allowable value. The drive section changes the gate resistance value or the gate current value when the one semiconductor switching element is switched, based on the target command value operated by the operation section.

7. The gate drive device according to claim 6, wherein The drive section completes the change of the gate resistance value or the gate current value before the one semiconductor switching element is switched next time.

8. The gate drive device according to any one of claims 1, 2, and 6, wherein The determination section determines that the energization is the forward energization during a period until a predetermined determination time elapses from a start timing of the turn-off of the one semiconductor switching element, and determines that the energization is the reverse energization during a period after the determination time elapses.

9. The gate drive device according to any one of claims 1, 2, and 6, wherein The determination section directly or indirectly detects a direction of a current flowing in the one semiconductor switching element, that is, an element current, and determines that the energization is the forward energization during a period in which the element current flows forward, and determines that the energization is the reverse energization during a period in which the element current flows backward.

10. The gate drive device according to any one of claims 1, 2, and 6, wherein The determination section detects the element voltage during the turn-on of the one semiconductor switching element, and determines that the energization is the forward energization during a period in which a detected value of the element voltage is a positive value, and determines that the energization is the reverse energization during a period in which the detected value of the element voltage is a negative value.

11. The gate drive device according to any one of claims 1, 2, and 6, wherein The operation section compares a detected value of the detection section with one or a plurality of threshold values set corresponding to the peak value or the allowable value of the rate of change, and operates a value indicating a result of the comparison as the target command value, The drive section switches the gate resistance value or the gate current value of the semiconductor switching element in stages based on the target command value.

12. The gate drive device according to any one of claims 1, 2, and 6, wherein The operation section operates the target command value so that a deviation between the detected value of the detection section and the peak value or the allowable value of the rate of change becomes zero, The drive section continuously switches the gate resistance value or the gate current value of the semiconductor switching element based on the target command value.

13. The gate drive device according to any one of claims 1, 2, and 6, wherein The operation section obtains at least one of the temperature of the surroundings, the atmospheric pressure of the surroundings, the output current of the half-bridge circuit, and the power supply voltage supplied to the half-bridge circuit as a variation parameter, and varies the allowable value of the peak value or the rate of change based on a relationship between the obtained variation parameter and the detection value of the detection section.

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