Copy command for memory system

Abstract

This application relates to a copy command for a memory system. A method may include storing data associated with one or more first addresses in an address space within the memory system. The method may further include receiving a copy command for the memory system regarding the data from a host. In response to the copy command, the memory system may associate the data with one or more second addresses in the address space.

Description

[0001] Cross-citation of related applications

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 717,762, filed April 11, 2022, entitled “COPY COMMAND FOR A MEMORY SYSTEM”, by Gyllenskog et al., which claims the benefit of U.S. Provisional Patent Application No. 63 / 180,441, filed April 27, 2021, entitled “COPY COMMAND FOR A MEMORY SYSTEM”, both of which are assigned to the assignee and are expressly incorporated herein by reference in their entirety. Technical Field

[0003] The technical field relates to copy commands for memory systems. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any one of the two possible states. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically updated by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even in the absence of an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include one or more memory devices. The apparatus may also include a controller coupled to the one or more memory devices and configured to cause the apparatus to: store data associated with one or more first addresses in an address space within the one or more memory devices; receive a copy command for the data in the one or more memory devices from a host; and, in response to the copy command, associate the data with one or more second addresses in the address space.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: store data associated with one or more first addresses in an address space within one or more memory devices; receive from a host a copy command for the data in the one or more memory devices; and, in response to the copy command, associate the data with one or more second addresses in the address space.

[0008] A method is described for execution by a memory system including one or more memory devices. The method may include: storing data associated with one or more first addresses in an address space within the one or more memory devices; receiving a copy command for the data from a host for the one or more memory devices; and, in response to the copy command, associating the data with one or more second addresses in the address space.

[0009] Describe an apparatus. The apparatus may include a controller configured to be coupled to a memory system. The controller may be configured to cause the apparatus to identify data associated with one or more first addresses within an address space of the memory system; issue a copy command to the memory system, wherein the copy command instructs the memory system to associate the data with one or more second addresses within the address space; and, after issuing the copy command, issue an access command for at least a portion of the data to the memory system, wherein the access command is associated with a second address among the one or more second addresses.

[0010] A non-transitory computer-readable medium containing code including instructions is described. When executed by a processor of an electronic device, the code containing instructions causes the electronic device to: identify data associated with one or more first addresses in an address space associated with a memory system; issue a copy command to the memory system, wherein the copy command instructs the memory system to associate the data with one or more second addresses in the address space; and, after issuing the copy command, issue an access command for at least a portion of the data to the memory system, wherein the access command is associated with a second address among the one or more second addresses.

[0011] A method executed by a host for a memory system is described. The method may include identifying data associated with one or more first addresses within an address space of the memory system; issuing a copy command to the memory system, wherein the copy command instructs the memory system to associate the data with one or more second addresses within the address space; and, after issuing the copy command, issuing an access command for at least a portion of the data to the memory system, wherein the access command is associated with a second address among the one or more second addresses. Attached Figure Description

[0012] Figure 1 This document describes an example of a system that supports copy commands for memory systems, based on the examples disclosed herein.

[0013] Figure 2 This document describes examples of copy commands used in memory systems, based on the examples disclosed herein.

[0014] Figure 3 This document describes an example of a list of copy parameters for a copy command used with a memory system, based on the examples disclosed herein.

[0015] Figure 4 This document describes instances of copy block descriptors that support copy commands for memory systems, based on the examples disclosed herein.

[0016] Figure 5 This document describes an example of a system that supports copy commands for memory systems, based on the examples disclosed herein.

[0017] Figure 6 This document describes an example of a system that supports copy commands for memory systems, based on the examples disclosed herein.

[0018] Figure 7 A block diagram of a memory system supporting copy commands for a memory system, based on examples disclosed herein, is shown.

[0019] Figure 8 A block diagram of a host system supporting copy commands for a memory system, based on the examples disclosed herein, is shown.

[0020] Figure 9 and 10 A flowchart illustrating one or more methods for supporting copy commands for a memory system, based on the examples disclosed herein. Detailed Implementation

[0021] Memory systems can be used to store data for a host system in an electronic system. In some instances, the host system can reference data stored in the memory system using addresses within its address space. The address referenced by the host system (e.g., data used by the host system to identify data subject to associated commands, such as read or write commands) may be referred to as a logical address, and the address space containing said logical address may be referred to as a logical address space.

[0022] In some cases, a host system for a memory system may determine to copy data from a first address (e.g., a first location or source location) to a second address (e.g., a second location or destination location) via an address space (e.g., a logical address space). In some memory systems, to achieve this copying, the host system may issue a read command for the data (e.g., a read command referencing or otherwise associated with the first address) to the memory system. The memory system may, in response to the read command, read the data from a first storage location within the memory system associated with the first address and issue the data to the host system (e.g., via an interface external to the memory system and coupled to the host system). The host system may then issue the data back to the memory system (e.g., via the same external interface) along with an associated write command for the memory system (e.g., a write command referencing or otherwise associated with the second address), which writes the data to a second storage location within the memory device associated with the second address. The memory system may write the data to the second address based on the receipt of the write command. In some cases, the host system may perform various additional processing on the data between receiving data from the memory system and sending the data back to the memory system (e.g., decrypting and then re-encrypting, decoding and then re-encoding, etc.). Transmitting data between the host system and the memory system (e.g., via an external interface) to repeatedly copy data from a first address to a second address can increase latency and degrade system performance. That is, the memory system may perform several read and write operations and repeatedly transmit data to and receive data from the host system to move or copy data from a first location to a second location.

[0023] This document describes systems, techniques, and apparatuses for copying commands, in which a host system issues the copy command to a memory system to copy data associated with a first address to a second address by associating the data with a second location. For example, the memory system may store data associated with a first logical block address (e.g., an LBA) and associate the data with a second LBA in response to receiving a copy command from the host system. In some cases, the memory device may not send data to the host system in connection with executing the copy command (e.g., it may not send it on an interface external to the memory system). In some such instances, the memory system may also maintain the association between the data and the first address.

[0024] In some instances, the memory system can associate data with a second address by reading data from a first address and writing data to a second address, but without sending data to or receiving data from the host device in connection with a copy command. That is, the memory system can copy data from a first physical location in the memory system to a second physical location in the memory system in response to a copy command.

[0025] Alternatively, in some instances, the memory system can associate data with a second address by updating one or more mapping tables within the memory system. For example, the memory system can add an entry to a logical-to-physical table (L2P table) indicating that the second LBA is also associated with data; for instance, the second LBA may also be associated with the physical location where the data is stored. In such instances, the memory system can maintain the association between the first LBA address and the data in the L2P table. Additionally, the memory system can maintain a second table that associates the first LBA with the second LBA; for example, the second table may indicate to the memory system that data associated with the first LBA is also associated with the second LBA, and vice versa.

[0026] Therefore, in response to a copy command for data associated with a first address as described herein, the memory system can copy data by associating it with a second address without transmitting data back and forth through the host system. That is, the memory system can copy data without transmitting data from the first address to the host system in response to a read command and without receiving the same data to write to the second address in response to a write command. Thus, the techniques described herein can reduce the latency associated with copying data within the address space and improve the overall performance of the system (e.g., by reducing the amount of processing overhead or time associated with copying data for the host, by reducing or eliminating the amount of communication overhead between the host system and the memory system via one or more interfaces, or by means of other benefits that are apparent to those skilled in the art).

[0027] Initially, as referenced Figure 1 Features of this disclosure are described in the context of the systems, apparatus, and circuits described herein. (Refer to...) Figure 2-6 The features of this disclosure are described within the context of the copy command, the copy parameter list, the copy block descriptor, and the system. References to this document are also included. Figure 7-10 These and other features of this disclosure are further illustrated and described in the context of the device diagrams and flowcharts for copy commands for memory systems.

[0028] Figure 1 This document describes an instance of system 100 that supports copy commands for a memory system, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0029] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Form-factor DIMM (SO-DIMM), or a Non-volatile DIMM (NVDIMM), and other possibilities.

[0030] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or any other computing device containing memory and processing means.

[0031] System 100 may include a host system 105 that can be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed via the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0032] Host system 105 may be coupled to memory system 110 via at least one physical host interface (e.g., an external interface, which may be at least partially external to memory system 110). In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in or otherwise supported therebetween the host system controller 106 of host system 105 and the memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0033] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0034] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0035] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0036] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0037] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that stores operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. In some cases, memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0039] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0040] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding block set 170, wherein each block 170 may include a corresponding page set 175, and each page 175 may include a set of memory cells.

[0041] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0042] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may have one or more limitations, such as the same operation being performed on memory cells within different pages 175 with the same page address within the corresponding plane 165 (e.g., involving command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0043] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0044] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0045] System 100 may include any number of non-transitory computer-readable media that support copy commands for the memory system. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access storage instructions (e.g., firmware) to perform one or more non-transitory computer-readable media that pertain to the functions of host system 105, memory system controller 115, or memory device 130 herein. For example, such instructions, when executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0046] As described herein, host system 105 may issue a copy command to memory system 110, enabling memory system 110 to copy data by associating data associated with a first location with a second location (e.g., without external data transfer between memory system 110 and host system 105, such as via a physical host interface). For example, memory system 110 may store data associated with a first LBA and associate the data with a second LBA in response to a copy command. In one instance, memory system 110 may associate data with a second LBA by internally reading data from the first LBA and writing the data to the second LBA. In other instances, memory system 110 may associate data with a second location by updating a mapping table (e.g., an L2P table) and associating the second LBA with the physical address associated with the data and the first LBA, for example by associating the second LBA and the first LBA with the same physical address using a new entry in the L2P table. By utilizing copy commands and internally copying data, memory system 110 can reduce latency and power consumption.

[0047] Figure 2 This document describes an example of a copy command 200 that supports copy commands for a memory system, based on the examples disclosed herein. The copy command 200 can be transmitted via a host system (e.g., reference...). Figure 1 The described host system 105) is transmitted to the memory system (e.g., reference). Figure 1 The memory system 110 described herein. Copy command 200 may contain a number of bytes 205 (e.g., bytes 205-a to 205-j). Copy command 200 may also contain bits 210-a to 210-h, for example, each byte 205 of command 200 may contain eight (8) bits 210. In some instances, copy commands as described herein (e.g., copy command 200) may be specified by a standard relating to communication with the memory system or communication performed by the memory system (e.g., the UFS standard or other standards).

[0048] In some instances, the host system (e.g., reference) Figure 1 The described host system 105 can send copy command 200 to the storage system (e.g., reference...). Figure 1 The memory system 110 described herein. In some instances, the memory system may be an instance of a UFS device. In some cases, the memory system may be an instance of a managed NAND system (e.g., an mNAND system). In such instances, the memory system may be located within an mNAND system controller (e.g., referenced...). Figure 1 The memory system controller 115 receives a copy command 200. In response to the copy command 200, the memory system can copy data stored at a first address to a reference address. Figure 5and 6 The described second address is associated. In some cases, the memory system may issue a response to copy command 200. In such instances, the response issued by the memory system may indicate to the host system that the memory system is ready to receive the reference. Figure 3 The described replication parameter list may be associated with replication command 200. Additionally, replication command 200 may include operation code 215, reservation 220, anchor 225, most significant bit (MSB) 230, least significant bit (LSB) 235, group number 240, parameter list length 245, and control 250.

[0049] Operation code 215 can be configured as a unique operation code specific to a copy command (e.g., copy command 200). That is, operation code 215 can be a unique code indicating that the command received by the memory system is copy command 200 (e.g., operation code 215 may not be included as an operation code in any command that is not a copy command). In some instances, operation code 215 may be received in the first byte 205-a.

[0050] Reserved 220 can be configured to indicate bits reserved for future use. That is, Reserved 220-a, Reserved 220-b, and Reserved 220-c may contain bits 210 that are not currently associated with any operation or function but may be defined and associated with an operation or function later. In some instances, bit 210 associated with Reserved 220-a may be transmitted in byte 205-b, bit 210 associated with Reserved 220-b may be transmitted in bytes 205-c through 205-f, and bit 210 associated with Reserved 220-c may be transmitted in byte 205-g. In some instances, bytes 205-c through 205-f that transmit Reserved 220-b may also contain MSB 230-a and LSB 235-a. In other words, bit 210-a associated with bytes 205-c to 205-f can be LSB 235-a and bit 210-h associated with bytes 205-c to 205-f can be MSB 230-a.

[0051] Anchor 225 can be configured to be associated with value 0b in the UFS device. In some instances, if anchor 225 is associated with value 1 (1), the memory system can terminate copy command 200, for example, for a check condition state where the sensing keyword is set to illegal request and the additional sensing code is set to invalid field. 1 That is, if the memory system receives copy command 200 with anchor 225 set to one (1), the memory system may terminate the command. In some instances, anchor 225 may be transmitted as bit 210-a in byte 205-b.

[0052] Group number 240 can be configured to indicate to the device whether system data is labeled or associated with a contextID. For example, group number 240 can match storage characteristics with system data characteristics. In some instances, copy command 200 may include the group number 240 value "00000b". In some cases, if group number 240 is set to a reserved value, the operation may fail. In some instances, group number 240 may be emitted in bytes 205-g using bits 210-a to 210-e.

[0053] The parameter list length 245 can be configured to indicate the length of the list of replication parameters to be transmitted to the memory system. That is, the host system can transmit the replication parameter list to the memory system after transmitting the replication command 200, as shown in the reference. Figure 3 As described. Copy command 200 may include a parameter list length 245 indicating the length (e.g., in bytes) of an associated (e.g., subsequently issued) copy parameter list. In some instances, parameter list length 245 may be issued in bytes 205-h through 205-i. In some cases, parameter list length 245 may include MSB 230-b and LSB 235-b; for example, bits 210-h and 210-a of bytes 205-g and 205-i may be MSB 230-b and LSB 235-b, respectively.

[0054] Control 250 can be configured to indicate the end of copy command 200. That is, control 250 can be a flag indicating to the memory system that copy command 200 has been fully issued. In some cases, control 250 can have the value "00h". In some cases, control 250 can be issued in bytes 205-j (e.g., the last byte 205 of copy command 200).

[0055] Figure 3 This describes an example of a list of copy parameters 300 for copy commands used with storage systems, based on the examples disclosed herein. In some instances, the host system (e.g., reference...) Figure 1 The described host system 105 can issue replication commands (e.g., refer to...) Figure 2 The copy command 200 described above is followed by the issuance of the copy parameter list 300. In such instances, the memory system (e.g., reference...) Figure 1 The described memory system 110 can be used in a memory system controller (e.g., reference 110). Figure 1 The memory system controller 115 described herein receives a list of copy parameters 300. Figure 3The replication parameter list 300 described herein may contain bytes 305-a to 305-z. It should be noted that a certain number of bytes 305 are described for illustrative purposes only, and the replication parameter list 300 may contain more than... Figure 3 The diagram shows more or fewer bytes 305. Each byte 305 may additionally contain bits 310-a to 310-h. Each byte 305 may also have an MSB 320 and an LSB 325. For example, byte 305-a may contain an MSB 320-a associated with bit 310-h and an LSB 325-a associated with bit 310-a. The replication parameter list 300 may contain a replication data length 315, a replication block descriptor data length 330, a reservation 335, a destination LBA 340, and a replication block descriptor 345.

[0056] The copy data length 315 can be configured to indicate the amount of information contained in the copy parameter list 300 other than the copy data length 315 itself. For example, the copy data length 315 can indicate the number of bytes 305 contained in the copy parameter list 300 other than the byte 305 used for the copy data length 315. That is, the copy data length 315 can indicate a number of bytes 305-z—bytes 305-a and 305-b, for example, more generally, n-1, where byte 305-a is zero (0) and byte 305-z is n. In some instances, the copy data length 315 can be emitted in two (2) bytes (e.g., bytes 305-a and 305-b).

[0057] The replication block descriptor data length 330 can be configured to indicate the amount of information allocated to one or more block descriptors. That is, the replication block descriptor data length 330 can indicate the amount of information used to transmit the replication block descriptor 345. For example, the replication block descriptor data length 330 can indicate the number of bytes used to transmit replication block descriptors 345-a through 345-n. That is, the replication block descriptor data length 330 can indicate the number of bytes 305-z through byte 305-h, for example, more generally, n-15, where byte 305-a is zero (0) and sixteen (15) bytes 305 are used to transmit the replication data length 315, the replication block descriptor data length 330, the reservation 335, and the destination LBA 340. In some instances, the replication block descriptor data length 330 can be transmitted in two (2) bytes (e.g., bytes 305-c and 305-d).

[0058] Reserve 335 (for example, refer to) Figure 2 The described reservation 220 can be configured to indicate that byte 305 (and its corresponding bit 310) is reserved for future use. In some instances, reservation 335 can be issued in four (4) bytes (e.g., bytes 305-e to byte 305-f).

[0059] Destination LBA 340 can be configured to indicate the start address in a set of destination addresses that can be associated with data by the memory system, such as the start address in a sequential set of destination addresses to which data will be copied. For example, the start address may be the lowest address contained in the sequential set (e.g., the sequential set of destination addresses may contain destination LBA 340 and zero or more LBAs following it). The memory system may store data associated with one or more first addresses and associate the data with one or more second addresses in response to a copy command. Destination LBA 340 can be configured to indicate the start address of one or more second addresses. In some instances, the memory system may associate data with a sequential set of addresses that begins at the start address indicated in destination LBA 340. In some instances, destination LBA 340 may be transmitted in eight (8) bytes (e.g., bytes 305-g to 305-h).

[0060] The copy block descriptor 345 can be configured as a block indicator. That is, the stored data associated with one or more first addresses may also contain one or more data blocks. In the context of block descriptor 345, a block can refer to a data group of any size and therefore may contain, for example, any number of blocks 170. The copy parameter list 300 may contain any number (e.g., one or more) of copy block descriptors 345. Reference Figure 4 Additional details are described for the individual copy block descriptor 345. In some instances, each copy block descriptor 345 may be emitted in sixteen (16) bytes (e.g., bytes 305-i to 305-j or bytes 305-n to 305-z).

[0061] Figure 4 This document describes an example of a copy block descriptor 400 that supports copy commands for a memory system, based on the examples disclosed herein. In some instances, the copy block descriptor 400 may be a reference... Figure 3 The described instance of replication block descriptor 345. That is, in some instances, replication block descriptor 400 may be included via the host system (e.g., reference...). Figure 1 The host system 105 described herein transmits data to the memory system (e.g., reference 105). Figure 1 The memory system 110 described herein has a list of replication parameters (e.g., replication parameter list 300). The memory system controller can be configured in the memory system controller (e.g., reference 300). Figure 1The memory system controller 115 described herein receives a replication parameter list and a replication block descriptor 400. The replication block descriptor 400 may contain bytes 405; for example, each replication block descriptor 400 may contain sixteen bytes 405-a to 405-p. Each byte 405 may additionally contain bits 410-a to 410-h. Each byte 405 may also have an MSB 420 and an LSB 425. For example, byte 405-a may contain an MSB 320-a associated with bit 410-h and an LSB 425-a associated with bit 410-a. The replication block descriptor 400 may contain a replication logical block address 415, a logical block number 430, and a reservation 435.

[0062] The replication logical block address 415 can be configured to indicate the corresponding start address (e.g., logical address) of a data block that passes through the replication block descriptor 400. For example, a data block may span multiple LBAs (containing data associated with multiple LBAs), and the replication logical block address 415 may indicate the start address of the data block. For example, in the case where a data block spans one or more LBAs, the replication logical block address 415 may indicate the lowest or initial LBA contained in that one or more LBAs. In some instances, the replication logical block address 415 may be emitted over eight (8) bytes (e.g., bytes 405-a to 405-h).

[0063] The number of logical blocks 430 can be configured to indicate the size of the corresponding blocks of data that pass through the copy block descriptor 400. That is, the number of logical blocks 430 can indicate the number of LBAs (or indicate the number of data or data units passing through the copy block descriptor 400). For example, the copy logical block address 415 can indicate the first LBA, and the number of logical blocks 430 can indicate the total number of LBAs of the data blocks passing through the copy block descriptor 400. For example, if the value of the number of logical blocks 430 is four (4), then the memory system can associate the first LBA (as indicated by the copy logical block address 415), the second LBA following the first LBA, the third LBA following the second LBA, and the fourth LBA following the third LBA with the copy block descriptor 400. For example, the memory system can copy data from LBAs 1-4 to one or more corresponding second (e.g., destination) addresses based on the copy logical block address 415 indicating starting with LBA 1 (1) and the number of logical blocks 430 indicating the four (4) blocks associated with or copied from there. In some instances, the number of logic blocks 430 can be emitted in four (4) bytes (e.g., bytes 405-i to 405-l).

[0064] Reserve 435 (for example, refer to) Figure 2The described reservation 220 can be configured to indicate that bytes 405-m to 405-p (and their corresponding bits 410) are reserved for future use. In some instances, reservation 435 can be emitted in four (4) bytes (e.g., bytes 405-m to byte 405-p).

[0065] Figure 5 This describes an example of a system 500 that supports copy commands for a memory system, based on the examples disclosed herein. System 500 may include a memory system 510 (e.g., referenced...). Figure 1 The memory system 510 described herein may include a memory system controller 515 (e.g., an mNAND controller or a reference controller). Figure 1 The described memory system controller 115, and memory locations 520 (e.g., source location) and 525 (e.g., destination location). In some instances, memory locations 520 and 525 may be located in different memory devices (e.g., reference memory devices). Figure 1 The different memory devices 130 described may reside in the same memory device (e.g., the same memory device 130). System 500 further describes a mapping table, such as a logic-to-physical table (L2P table) 530. In some instances, the L2P table 530 may be stored at the memory system controller 515. In other instances, the L2P table 530 may be stored in one or more memory devices, and the memory system controller 515 may retrieve the L2P table 530 associated with the operation to be performed. The L2P table 530 may contain entries associated with corresponding logical block addresses (LBAs) 535. In some instances, each LBA 535 may also be associated with a physical address in the memory system 510 (e.g., pointing to a physical address, indicating a physical address, or mapping from an LBA to a physical address).

[0066] In some instances, the host system (e.g., reference) Figure 1 The described host system 105 can identify data associated with one or more first addresses (e.g., source addresses) within the address space of the memory system 510. In some cases, the host system can also copy commands (e.g., reference...) Figure 2 The described copy command 200 is issued to memory system 510 to instruct memory system 510 to associate data with one or more second addresses (e.g., destination addresses) within the address space. For example, a host system may identify data associated with one or more LBAs 535 and issue a copy command to memory system 510 to instruct the memory system to associate data with one or more second LBAs 535. The copy command may include references... Figure 2The fields and parameters described. In some cases, the memory system 510 may receive a copy command at the memory system controller 515. Additionally, the memory system may transmit signaling in response to the copy command; for example, the memory system 510 may transmit a response instructing the host system that it is ready to execute the copy command. In some cases, the host system may transmit a list of copy parameters (e.g., refer to...) in response to receiving signaling from the memory system. Figure 3 The described list of copy parameters (300). In some cases, the list of copy parameters may include lengths as indicated in the copy command, such as the number of bytes indicated in the copy command.

[0067] The memory system 510 may receive a copy parameter list from the memory system controller 515. In some instances, the copy parameter list may indicate the start address of one or more second address blocks, such as the start destination LBA. For example, the copy parameter list may indicate the start LBA address at LBA 535-s to the memory system 510. In some cases, the copy parameter list may also contain one or more copy block descriptors (e.g., reference...). Figure 4 The described copy block descriptor 400. For example, each copy block descriptor can indicate a corresponding start address (e.g., see reference 400). Figure 4 The described copy logical block address (415) and the corresponding block size (e.g., reference) Figure 4 The number of logical blocks described is 430. That is, the copy block descriptor can indicate the number of blocks associated with one or more first addresses starting from the first LBA 535 and associated with one or more second addresses.

[0068] For example, a first copy block descriptor may indicate a first start LBA 535-a to memory system 510. In some cases, the first copy block descriptor may also indicate five (5) associated LBAs to memory system 510. In such cases, memory system controller 515 may initiate a copy command received from the host system by associating LBA 535-a (e.g., source LBA) with LBA 535-s (e.g., destination LBA). For example, memory system controller 515 may read data stored at a first set of memory cells in memory location 520 (e.g., from the physical address associated with LBA 535-a in the L2P table) and write the data to a second set of memory cells in memory location 525, for example, to a second physical address. In such instances, memory system controller 515 may update L2P table 530 to associate the second physical address of the second set of memory cells with LBA 535-a, for example, associating the destination LBA 535-s with the second physical address of the data. Additionally, the memory system controller 515 may maintain the data stored at the first set of memory cells; for example, the memory system controller 515 may prevent the erasure of the data stored at the first set of memory cells. In such an example, the memory system 510 may have data stored at memory location 520 and a copy of the data stored at memory location 525. In some cases, the memory system controller 515 may continue to read data from a source block address and write data to a destination block address based on the number of blocks or addresses indicated in the number of logical blocks. For example, the memory system controller may then read data associated with the next sequential source block (e.g., LBA 535-b) and write the data to the next sequential destination block (e.g., LBA 535-t), and so on, until, for example, data associated with the fifth source block (e.g., LBA 535-e) is read and written to the fifth destination block (e.g., LBA 535-w) based on five (5) LBAs indicated in the number of logical blocks.

[0069] In some instances, the replication parameter list may also include a second replication block descriptor. In such instances, the memory system controller 515 may determine different start source LBAs. For example, the memory system controller 515 may determine that the replication parameter list includes a start LBA-g and several logical blocks associated with three (3) LBAs; for instance, the second replication block descriptor may contain a set of three (3) source LBAs. In such instances, the memory system controller may read data stored at a third set of memory cells in memory location 520 associated with LBA 535-i and write data to a fourth set of memory cells in memory location 525 associated with LBA 535-x. That is, the memory system controller 515 may continue to write sequentially to destination blocks; for example, a first write operation associated with the second replication block descriptor may be located at a destination block following the second destination block written during the last write operation associated with the first replication block descriptor. For example, if the memory system controller 515 writes to LBA 535-w at the end of the first copy block descriptor, then the memory system controller 515 can write to the next sequential LBA 535-x at the beginning of the second copy block descriptor. The memory system controller 515 can continue to associate the source LBA of the second copy block descriptor with the destination LBA of the second copy block descriptor based on the indicated number of logical blocks (e.g., three). For example, the memory system controller 515 can complete the copy operation associated with the second block descriptor by reading data from a first physical location in memory location 520 associated with LBA 535-i and writing the data to a second physical location in memory location 525 associated with LBA 535-z. The memory system controller 515 can continue similar operations for any remaining copy block descriptors in the copy parameter list, such as for the third copy block descriptor, the fourth copy block descriptor, and so on.

[0070] In some instances, the memory system controller 515 may also indicate to the host system attributes of the memory system 510 associated with a copy command. For example, memory system 510 attributes may be stored in registers at the memory system 510. The memory system controller 515 may, in response to one or more related requests from the host system or as part of an initialization routine for the memory system, and other possibilities, send signaling indicating values ​​from registers to the host system. In some cases, the memory system 510 may indicate that it supports copy commands by, for example, indicating the value of a corresponding attribute (e.g., dExtendedUFSFeaturesSupport) representing such support. Alternatively or concurrently, the memory system 510 may indicate, for example, by indicating the value of a corresponding attribute (e.g., bMaximumCopyLbaCount) to indicate the maximum amount of data that the memory system supports copying in response to a single copy command. For example, the memory system 510 may indicate the total amount of data that the memory system can copy from all copy block descriptors (e.g., expressed in terms of the total number of corresponding LBAs), such as the maximum sum of the number of logical blocks across all copy block descriptors. Alternatively, the memory system 510 may indicate, for example, the maximum number of block descriptors (e.g., the maximum number of copy block descriptors 345) supported by the memory system for a single copy command by indicating the value of a corresponding attribute (e.g., bMaximumCopyBlockDescriptorCount). That is, the memory system 510 may indicate the maximum number of copy block descriptors that the memory system 510 can process in a single copy command. Alternatively, the memory system 510 may indicate, for example, the maximum amount of data associated with a single block descriptor (e.g., the maximum value for a single logical block number 430) supported by the memory system 510 by indicating the value of a corresponding attribute (e.g., bMaximumCopyBlockDescriptorSize). That is, the memory system 510 may indicate the maximum size for a single logical block number in the copy block descriptor.

[0071] In some cases, for at least some commands, the memory system 510 may also be allowed to issue a busy state to the host system relating to the execution of the command for only a limited duration (which may be referred to as a busy timeout period). In some instances, copy commands as described herein may experience a busy timeout period, in which case the memory system 510 may return a busy state for only the given copy command for the duration corresponding to the duration of the busy timeout period. In such instances, the memory system 510 may terminate the copy command if the duration of execution of the copy command exceeds a busy timeout period value (e.g., duration).

[0072] Figure 6This document describes an example of a system 600 that supports copy commands for a memory system, based on the examples disclosed herein. In some instances, system 600 may be a reference. Figure 1 The system 100 or reference described Figure 5 An example of the described system 500. System 600 may include a memory system 610 (e.g., reference...). Figure 1 The memory system 610 described herein may include a memory system controller 615 (e.g., an mNAND controller or a reference controller). Figure 1 The memory system controller 115 described herein and memory location 620. In some instances, memory location 620 may be located in a memory device (e.g., reference 115). Figure 1 The memory device 130 described is included. System 600 further describes a mapping table, such as a logic-to-physical table (L2P table) 630. In some instances, L2P table 630 may be stored at memory system controller 615. In other instances, L2P table 630 may be stored in one or more memory devices, and memory system controller 615 may retrieve L2P table 630 associated with an operation to be performed. L2P table 630 may contain entries associated with corresponding logical block addresses (LBAs) 635. In some instances, each LBA 635 may also be associated with a physical address in memory system 610 (e.g., pointing to a physical address, indicating a physical address, mapping from an LBA to a physical address). System 600 also describes table 645. Table 645 may also be stored at memory system controller 615. Table 645 may contain entries 650.

[0073] refer to Figure 5 Description, host system (e.g., reference) Figure 1 The described host system 105 may, after identifying data associated with one or more first addresses (e.g., source LBAs) within the address space associated with the memory system 610, send a copy command (e.g., reference) to the memory system 610. Figure 2 The described copy command 200 is issued to memory system 610. The host system may issue the copy command to memory system 610 to instruct memory system 610 to associate data with one or more second addresses (e.g., destination LBAs) within the address space. Memory system 610 may issue signaling in response to the copy command and, in response to issuing the signaling, receive a list of copy parameters (e.g., reference...) from the host system. Figure 3 The replication parameter list described is 300. The replication parameter list issued by the host system may contain one or more second addresses (e.g., reference...). Figure 3 The described destination (LBA340) and one or more block indicators (e.g., references) Figure 3The described copy block descriptor 345). The memory system controller 615 can determine the start address in each corresponding block descriptor (e.g., refer to...). Figure 4 The described copy logical block address (415) and the size of the corresponding block (e.g., reference) Figure 4 The number of logical blocks described is 430.

[0074] For example, memory system 610 may receive a copy command with a start address LBA 635-a indicating one or more first addresses and a logical block number having a value of six (6). In some instances, memory system 610 may also receive a destination LBA with one or more second addresses associated with an address LBA 635-u. In some cases, memory system controller 615 may update L2P table 630 by associating LBA 635-u with the physical address associated with LBA 635-a. That is, memory system controller 615 may execute copy commands and operations associated with copy block descriptors by mapping LBA 635-u having the same physical location associated with LBA 635-a without actually transferring data from a first physical location to a second physical location, for example, LBA 635-a and LBA 635-u may be associated with the same set of memory cells that already physically store data before issuing a copy command. In such instances, the memory system controller 615 can also maintain the association between the source LBA and the physical address of the data. For example, the memory system controller 615 can maintain the association between the LBA 635-a of a memory cell set and its physical address.

[0075] In some instances, the memory system controller 615 may indicate an LBA 635 associated with data stored in memory location 620. For example, the memory system controller may indicate in metadata 625 that LBA 635-a is associated with data in memory location 620. In some cases, the memory system controller 615 may indicate associated LBA 635 to reduce errors. Therefore, in addition to updating L2P table 630, the memory system controller 615 may also maintain table 645 that associates one or more first addresses with one or more second addresses. That is, the memory system controller 615 may maintain table 645 that associates source LBAs with destination LBAs sharing the same physical address. For example, the memory system controller 615 may update entry 650-a that indicates LBA 635-a is associated with LBA 635-u, such as LBA 635-a and LBA 635-u sharing the same physical address. In some instances, the memory system controller 615 may write flags 640-a (e.g., bits or fields), flags 640-b, or both, to indicate that a corresponding LBA 635-a or LBA 635-u is associated with a shared physical address and to check table 645 accordingly. In other instances, the memory system controller may store flags in metadata 625 to indicate that a physical address is shared by multiple LBAs 635-a and 635-u and to check table 645 accordingly, wherein metadata 625 may be associated with data stored in memory location 620.

[0076] For example, the host system may issue an access command associated with at least a portion of data stored at memory location 620 to memory system 610, such as an access command associated with data stored at a physical address associated with both LBA 635-a and LBA 635-u. In some instances, the memory system controller may read L2P table 630 in response to receiving an access command. In instances where the memory system controller 615 stores flags in LBA 635-a (e.g., storing flag 640-a) or stores flags in LBA 635-u (e.g., storing flag 640-b), the memory system controller 615 may first check table 645 and entry 650-a. In other words, regardless of whether the access command is associated with LBA 635-a or LBA 635-u, the memory system controller 615 can check table 645 to determine, based on flag 640, whether the correct LBA 635 is associated with a physical address in memory location 620. For example, if the memory system controller 615 receives an access command associated with LBA 635-u, then the memory system controller 615 can check entry 650-a in table 645 based on flag 640-b (e.g., a flag). In such an instance, the memory system controller 615 can determine that the physical address of memory location 620 is associated with both LBA 635-u and 635-a. Therefore, the memory system controller 615 can continue the access operation with the association with LBA 635-a or LBA 635-u stored in metadata 625.

[0077] In other instances, where the memory system controller 615 stores flags in metadata 625, the memory system controller 615 may first read the LBA 635 (e.g., LBA 635-a or LBA 635-u) associated with the access command to determine the physical address at memory location 620, and then read the metadata 625. The memory system controller 615 may then check table 645 based on the flags stored in the metadata 625 and continue the access operation if the metadata 625 indicates LBA 635-a or LBA 635-u.

[0078] In some instances, the memory system controller 615 may perform a similar update in the L2P table 630 for one or more remaining first addresses in one or more second addresses. For example, the memory system controller may associate LBA 635-v with a second physical location associated with LBA 635-b, and so on, until a certain number of logical blocks are satisfied, such as until a sixth destination LBA 635-z and a sixth source block LBA 635-f are associated with the same physical address. The memory system controller 615 may perform a similar process for any number of copy block descriptors contained in a copy command.

[0079] In some cases, the memory system controller 615 may receive an unmapping command after executing a copy command received from the host system. For example, the unmapping command may be associated with unmapping LBA 635-a or LBA 635-u. In some instances, if the memory system controller 615 receives an unmapping command for 635-a, then the memory system controller 615 may unmapping LBA 635-a from the physical address associated with memory location 620 but retain entry 650-a in table 645. That is, the memory system controller may unmapping LBA 635-a from the physical address but maintain the association between LBA 635-u and the physical address; for example, the memory system controller may erase entry LBA 635-a but prevent the erasure of data stored in memory location 620. Because metadata 625 indicates the association between the physical address at memory location 620 and LBA 635-a, the memory system controller 615 can maintain entry 650-a and flag 640-b or the flag in metadata 625. Therefore, the memory system controller 615 can check table 645 using flag 640-b in entry LBA 635-u or metadata 625 in response to a subsequent access command for at least a portion of the data stored at memory location 620. For example, the memory system controller 615 can check entry 650-a and continue the access operation associated with LBA 635-u if metadata 625 indicates the association with LBA 635-a as indicated in entry 650-a. In other instances, if the memory system controller receives an unmapping command for 635-u, the memory system controller can unmapping LBA 635-u from the physical address associated with memory location 620 and also delete entry 650-a from table 645. In other words, metadata 625 can indicate the association between memory location 620 and LBA 635-a, and the behavior of checking entry 650-a will be redundant.

[0080] It should be noted that, as a reference Figure 5As described, the memory system 610 can also indicate to the host system the attributes of the memory system 610 associated with the copy command. For example, the memory system 610 may indicate the values ​​of one or more attributes as described herein (e.g., dExtendedUFSFeaturesSupport, bMaximumCopyLbaCount, bMaximumCopyBlockDescriptorCount, or bMaximumCopyBlockDescriptorSize), and as referenced Figure 5 As described, the copy command may experience a busy timeout period on the host system.

[0081] Figure 7 A block diagram 700 illustrates a memory system 720 supporting copy commands for a memory system, according to an example disclosed herein. The memory system 720 may be as described in the references... Figures 1 to 6 Examples of aspects of the described memory system. Memory system 720 or its various components may be examples of means for executing various aspects of copy commands for a memory system as described herein. For example, memory system 720 may include storage component 725, receiving component 730, association component 735, transmitting component 740, operation component 745, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0082] Storage component 725 may be configured or otherwise support means for storing data associated with one or more first addresses in an address space within a memory system. In some cases, storage component 725 may be configured or otherwise support means for continuing to store data at a set of memory cells having one or more physical addresses, wherein the one or more first addresses include one or more first logical addresses, and after data is associated with one or more second addresses, one or more mapping tables associate the one or more physical addresses with both the one or more second logical addresses and the one or more first logical addresses. In some cases, the data stored by storage component 725 comprises one or more data blocks. In some instances, the memory system and storage component 725 include a Universal Flash Memory (UFS) device. In some instances, the one or more second addresses at storage component 725 comprise one or more second logical addresses. In some cases, the data at storage component 725 remains stored at the first memory cell set after a copy of the data has been written to the second memory cell set. In some cases, the one or more second addresses of storage component 725 comprise one or more second logical addresses. In some cases, the data at storage component 725 is stored at a set of memory cells with one or more physical addresses before a copy command is received.

[0083] The receiving component 730 may be configured or otherwise support means for receiving a copy command for data from a host for a memory system. In some instances, the receiving component 730 may be configured or otherwise support means for receiving a list of copy parameters associated with a copy command from a host, wherein the list of copy parameters indicates one or more first addresses, one or more second addresses, or both. In some cases, the receiving component 730 may be configured or otherwise support means for receiving an access command for at least a portion of data. In some cases, the copy command received by the receiving component 730 includes an indication of the length of the copy parameter list. In some instances, the copy parameter list received by the receiving component 730 includes one or more block indicators, each for a corresponding block in one or more blocks.

[0084] In some cases, the block indicator among one or more block indicators received by the receiving component 730 includes an indication of a corresponding start address for the corresponding block within the address space, an indication of the size of the corresponding block, or both. In some cases, the replication parameter list received by the receiving component 730 includes an indication of the amount of information assigned to one or more block indicators. In some cases, the replication parameter list received by the receiving component 730 includes an indication of the amount of information contained in the replication parameter list, wherein the amount of information does not include an indication of quantity. In some instances, the replication parameter list received by the receiving component 730 includes an indication of a start address within one or more second addresses. In some cases, the replication command received by the receiving component 730 includes operation codes specific to the replication command.

[0085] Association component 735 may be configured or otherwise support means for associating data with one or more second addresses within an address space in response to a replication command. In some instances, to support associating data with one or more second addresses, association component 735 may be configured or otherwise support means for associating data with a sequential set of addresses starting from a start address indicated by a replication parameter list. In some cases, association component 735 may be configured or otherwise support means for one or more first addresses to contain one or more first logical addresses. In some cases, association component 735 may be configured or otherwise support means for one or more mapping tables to associate one or more physical addresses with both one or more second logical addresses and one or more first logical addresses after data has been associated with one or more second addresses.

[0086] In some cases, the association component 735 may be configured or otherwise support means for maintaining one or more second tables that associate one or more first logical addresses with one or more second logical addresses. In some cases, the association component 735 may be configured or otherwise support means for checking one or more second tables at least in part based on received access commands, wherein the checking is at least in part based on flags stored in one or more mapping tables associated with a first logical address among one or more first logical addresses or associated with a second logical address among one or more second logical addresses, or wherein the checking is at least in part based on metadata stored in association with at least said portion of the data. In some cases, associating data with one or more second addresses via the association component 735 includes updating one or more mapping tables within the memory system to associate one or more second logical addresses with one or more physical addresses. In some cases, associating data with one or more second addresses via the association component 735 includes updating one or more mapping tables within the memory system to associate one or more second logical addresses with one or more second physical addresses corresponding to a second set of memory cells.

[0087] In some cases, the transmission component 740 may be configured or otherwise support means for transmitting signaling in response to a copy command from the memory system to the host, wherein receiving the copy parameter list is at least partially based on transmitting the signaling in response to the copy command. In some cases, the transmission component 740 may be configured or otherwise support means for instructing the host via the memory system on the memory system's support for a copy command, the maximum amount of data that the memory system supports for copying in response to a single copy command, the maximum number of block indicators that the memory system supports for a single copy command when the data includes one or more data blocks, each associated with a corresponding block indicator, the maximum amount of data associated with a single block indicator supported by the memory system, or any combination thereof.

[0088] In some cases, the operation component 745 may be configured or otherwise support means for reading data from a first set of memory cells associated with one or more first addresses in response to a copy command. In some instances, the operation component 745 may be configured or otherwise support means for writing a copy of data to a second set of memory cells associated with one or more second addresses in response to a copy command. In some cases, the operation component 745 is allowed to send a busy status to the host for a limited duration in response to receiving a copy command.

[0089] Figure 8 A block diagram 800 illustrates a host system 820 supporting copy commands for a memory system, according to an example disclosed herein. The host system 820 may be as described in the reference... Figures 1 to 6Examples of aspects of the described host system. Host system 820 or its various components may be examples of means for executing various aspects of copy commands for a memory system as described herein. For example, host system 820 may include an identifier manager 825, a send manager 830, a receive manager 835, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0090] The identifier manager 825 may be configured or otherwise support means for identifying data associated with one or more first addresses within the address space of a memory system. In some instances, the data identified by the identifier manager 825 comprises one or more data blocks. In some instances, the copy parameter list contains one or more block indicators, each for a corresponding block within one or more blocks. In some cases, the one or more second addresses identified by the identifier manager 825 comprise a sequential set of addresses starting from a start address indicated by the copy parameter list. In some cases, the one or more first addresses identified by the identifier manager 825 comprise one or more first logical block addresses (LBAs). In some instances, the one or more second addresses comprise one or more second LBAs.

[0091] The issue manager 830 may be configured or otherwise support means for issuing a copy command to a memory system, wherein the copy command instructs the memory system to associate data with one or more second addresses within an address space. In some cases, the issue manager 830 may be configured or otherwise support means for issuing an access command for at least a portion of the data to the memory system after issuing the copy command, wherein the access command is associated with a second address among one or more second addresses. In some cases, the issue manager 830 may be configured or otherwise support means for issuing a copy parameter list associated with the copy command to the memory system, wherein the copy parameter list indicates one or more first addresses, one or more second addresses, or both. In some cases, the copy command issued by the issue manager 830 further indicates that after the data is associated with one or more second addresses, the data will remain associated with one or more first addresses. In some cases, the copy command issued by the issue manager 830 includes operation code specific to the copy command. In some cases, the copy command issued by the issue manager 830 includes an indication of the length of the copy parameter list. In some cases, the block indicator in one or more block indicators issued by the sender manager 830 includes an indication of the corresponding start address for the corresponding block within the address space, an indication of the size of the corresponding block, or both. In some instances, the replication parameter list issued by the sender manager 830 includes an indication of the amount of information assigned to one or more block indicators. In some cases, the replication parameter list issued by the sender manager 830 includes an indication of the amount of information contained in the replication parameter list, wherein the amount of information does not include an indication of quantity. In some cases, the replication parameter list issued by the sender manager 830 includes an indication of the start address within one or more second addresses.

[0092] In some instances, the receive manager 835 may be configured or otherwise support means for receiving signaling from the memory system in response to a copy command, wherein the transmission of a copy parameter list is at least partially based on receiving the signaling in response to the copy command. In some cases, the receive manager 835 may be configured or otherwise support means for receiving signaling from the memory system indicating the memory system's support for a copy command, the maximum amount of data the memory system supports copying in response to a single copy command, the maximum number of block indicators the memory system supports for a single copy command when the data includes one or more data blocks each associated with a corresponding block indicator, the maximum amount of data associated with a single block indicator supported by the memory system, or any combination thereof. In some cases, the receive manager 835 receives a busy state, wherein the memory system is allowed to transmit a busy state to the host system for a limited duration in response to receiving a copy command.

[0093] Figure 9 A flowchart illustrating a method 900 for supporting copy commands for a memory system according to an example disclosed herein is shown. Operation of method 900 may be implemented by a memory system (e.g., one or more memory devices) or its components as described herein. For example, operation of method 900 may be performed by, as referenced... Figures 1 to 7 The memory system described herein performs the functions described. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the functions described below. Alternatively, the memory system may use dedicated hardware to perform aspects of the functions described below.

[0094] At 905, the method may include storing data associated with one or more first addresses in the address space within the one or more memory devices. The operation at 905 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The described storage component 725 performs the operation of 905.

[0095] At 910, the method may include receiving from a host a copy command for the data of the one or more memory devices. The operation of 910 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The described aspect of the receiving component 730 performing the operation of 910.

[0096] At 915, the method may include, in response to the copy command, associating the data with one or more second addresses within the address space. The operation at 915 can be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 7 The described associated component 735 performs the operation of 915.

[0097] In some cases, the device as described herein may perform one or more methods, such as method 900. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: storing data associated with one or more first addresses in an address space within one or more memory devices; receiving a copy command for the data from a host for the one or more memory devices; and, in response to the copy command, associating the data with one or more second addresses in the address space.

[0098] Some examples of the method 900 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for receiving a list of replication parameters associated with the replication command from the host, wherein the list of replication parameters indicates the one or more first addresses, the one or more second addresses, or both.

[0099] In some instances of the method 900 and device described herein, the copy command includes an indication of the length of the copy parameter list.

[0100] In some cases of the method 900 and apparatus described herein, the data comprises one or more data blocks, and the replication parameter list comprises one or more block indicators, each for a corresponding block in the one or more blocks.

[0101] In some examples of the method 900 and apparatus described herein, the block indicator in one or more block indicators includes an indication of a corresponding start address for the corresponding block within the address space, an indication of the size of the corresponding block, or both.

[0102] In some cases of the method 900 and apparatus described herein, the replication parameter list contains an indication of the number of information assigned to the one or more block indicators.

[0103] In some examples of the method 900 and apparatus described herein, the replication parameter list includes an indication of the number of information contained in the replication parameter list, the number of information not including the indication of the number.

[0104] In some cases of the method 900 and apparatus described herein, the copy parameter list includes an indication of the start address within the one or more second addresses.

[0105] In some examples of the method 900 and apparatus described herein, associating the data with the one or more second addresses may include operations, features, circuitry, logic, means, or instructions for associating the data with a sequential set of addresses starting at the start address indicated by the copy parameter list.

[0106] Some aspects of the method 900 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for transmitting signaling in response to a copy command from a memory system to a host, wherein receiving a copy parameter list may be based at least in part on transmitting the signaling in response to the copy command.

[0107] Examples of the methods 900 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: instructing a host via a memory system to support a copy command by one or more memory devices; supporting a maximum amount of data to be copied in response to a single copy command by one or more memory devices; supporting a maximum number of block indicators for a single copy command by one or more memory devices when the data contains one or more data blocks each associated with a corresponding block indicator; supporting a maximum amount of data associated with a single block indicator by one or more memory devices; or any combination thereof.

[0108] In some cases of the method 900 and device described herein, the copy command includes operation code that may be specific to the copy command.

[0109] In some examples of the method 900 and apparatus described herein, a memory system may be allowed to transmit a busy state to the host for a finite duration, at least in part, based on receiving a copy command (e.g., in response to a copy command, performing one or more operations based on the copy command).

[0110] In some cases of the methods 900 and apparatus described herein, the memory system may be a Universal Flash Storage (UFS) device.

[0111] Some examples of the methods 900 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: reading data from a first set of memory cells associated with one or more first addresses in response to a copy command, and writing a copy of the data to a second set of memory cells associated with one or more second addresses in response to a copy command, wherein the association is at least partially based on the write.

[0112] In some cases of the method 900 and apparatus described herein, one or more second addresses comprise one or more second logical addresses, and associating data with one or more second addresses comprises updating one or more mapping tables within the memory system to associate one or more second logical addresses with one or more second physical addresses corresponding to a second set of memory cells.

[0113] In some cases of the method 900 and apparatus described herein, the data remains stored at the first memory cell set after a copy of the data can be written to the second memory cell set.

[0114] In some cases of the method 900 and apparatus described herein, one or more second addresses comprise one or more second logical addresses, and the data may be stored at a set of memory cells having one or more physical addresses prior to receiving the copy command. Associating the data with the one or more second addresses includes updating one or more mapping tables within the memory system to associate the one or more second logical addresses with the one or more physical addresses.

[0115] Some examples of the methods 900 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for continuing to store data at a set of memory cells having one or more physical addresses, wherein the one or more first addresses include one or more first logical addresses, and after the data may be associated with one or more second addresses, one or more mapping tables associate the one or more physical addresses with both the one or more second logical addresses and the one or more first logical addresses.

[0116] Some examples of the methods 900 and devices described herein may additionally include operations, features, circuit systems, logic, devices, or instructions for maintaining one or more second tables that associate one or more first logical addresses with one or more second logical addresses.

[0117] Examples of the methods 900 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: receiving an access command for at least a portion of data and checking one or more second tables at least in part based on the received access command, wherein the checking may be at least in part based on flags stored in one or more mapping tables associated with a first logical address among one or more first logical addresses or associated with a second logical address among one or more second logical addresses, or wherein the checking may be at least in part based on metadata stored associated with at least said portion of the data.

[0118] Figure 10 A flowchart illustrating a method 1000 for supporting copy commands for a memory system according to an example disclosed herein is shown. The operation of method 1000 may be implemented by a host system or its components as described herein. For example, the operation of method 1000 may be implemented by a reference... Figures 1 to 6 The host system described in section 8 performs the functions described herein. In some instances, the host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0119] At 1005, the method may include identifying data associated with one or more first addresses within the address space of the memory system. The operation at 1005 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 8 The described aspect of the identifier manager 825 performing operation 1005.

[0120] At 1010, the method may include issuing a copy command to a memory system, wherein the copy command instructs the memory system to associate data with one or more second addresses within an address space. The operation of 1010 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 8 The described aspects of the launch manager 830 performing the operation of 1010.

[0121] At 1015, the method may include, after issuing the copy command, issuing an access command for at least a portion of the data to the memory system, wherein the access command is associated with a second address among the one or more second addresses. The operation at 1015 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 8 The described aspects of the operation performed by the launch manager 830 are 1015.

[0122] In some cases, the device as described herein may perform one or more methods, such as method 1000. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: identifying data associated with one or more first addresses within an address space associated with the memory system; issuing a copy command to the memory system, wherein the copy command instructs the memory system to associate the data with one or more second addresses within the address space; and, after issuing the copy command, issuing an access command for at least a portion of the data to the memory system, wherein the access command is associated with a second address among the one or more second addresses.

[0123] Some aspects of the method 1000 and apparatus described herein may additionally include operations, features, circuit systems, logic, devices, or instructions for transmitting a copy parameter list associated with a copy command to a memory system, wherein the copy parameter list indicates one or more first addresses, one or more second addresses, or both.

[0124] In some examples of the method 1000 and device described herein, the copy command includes an indication of the length of the copy parameter list.

[0125] In some instances of the method 1000 and apparatus described herein, the data comprises one or more data blocks, and the replication parameter list comprises one or more block indicators, each for a corresponding block in the one or more blocks.

[0126] In some instances of the method 1000 and apparatus described herein, the block indicator in one or more block indicators includes an indication of a corresponding start address for the corresponding block within the address space, an indication of the size of the corresponding block, or both.

[0127] In some instances of the method 1000 and apparatus described herein, the replication parameter list contains an indication of the number of information assigned to the one or more block indicators.

[0128] In some cases of the method 1000 and apparatus described herein, the replication parameter list includes an indication of the number of information contained in the replication parameter list, the number of information not including the indication of the number.

[0129] In some examples of the method 1000 and device described herein, the copy parameter list includes an indication of the start address within one or more second addresses.

[0130] In some instances of the method 1000 and device described herein, one or more second addresses comprise a sequential set of addresses starting with a start address indicated by a list of replication parameters.

[0131] Some aspects of the method 1000 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for receiving signaling in response to a copy command from a memory system, wherein transmitting a copy parameter list may be based at least in part on receiving the signaling in response to the copy command.

[0132] Some examples of the methods 1000 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: receiving signaling from a memory system indicating that the memory system supports a copy command, that the memory system supports a maximum amount of data to be copied in response to a single copy command, that the memory system supports a maximum number of block indicators for a single copy command when the data contains one or more data blocks each associated with a corresponding block indicator, that the memory system supports a maximum amount of data associated with a single block indicator, or any combination thereof.

[0133] In some cases of the method 1000 and device described herein, the copy command further indicates that after the data can be associated with one or more second addresses, the data can remain associated with one or more first addresses.

[0134] In some cases of the method 1000 and device described herein, the copy command includes operation code that may be specific to the copy command.

[0135] In some examples of the method 1000 and device described herein, one or more first addresses contain one or more first LBAs and one or more second addresses contain one or more second LBAs.

[0136] In some cases of the method 1000 and apparatus described herein, the memory system may be allowed to transmit a busy state to the host for a finite duration, at least in part, based on a copy command (e.g., in response to receiving a copy command, performing one or more operations based on the copy command).

[0137] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0138] Describe an apparatus. The apparatus may include one or more memory devices and a controller coupled to the one or more memory devices. The controller may be configured to cause the apparatus to: store data associated with one or more first addresses in an address space within the one or more memory devices; receive a copy command for the data in the one or more memory devices from a host; and, in response to the copy command, associate the data with one or more second addresses in the address space.

[0139] In some cases, the controller may be further configured to cause the device to receive from the host a list of replication parameters associated with the replication command, wherein the list of replication parameters indicates the one or more first addresses, the one or more second addresses, or both.

[0140] In some instances of the device, the copy command includes an indication of the length of the copy parameter list.

[0141] In some examples of the device, the data comprises one or more data blocks, and the replication parameter list comprises one or more block indicators, each for a corresponding block in the one or more blocks.

[0142] In some cases of the device, the block indicator in one or more block indicators includes an indication of the corresponding start address for the corresponding block within the address space, an indication of the size of the corresponding block, or both.

[0143] In some cases of the device, the copy parameter list includes an indication of the number of information assigned to the one or more block indicators.

[0144] In some cases of the device, the copy parameter list includes an indication of the number of information items contained in the copy parameter list, where the number of items does not include the indication of the number of items.

[0145] In some examples of the device, the replication parameter list includes an indication of the start address within one or more second addresses.

[0146] In some instances, to associate the data with the one or more second addresses, the controller may be further configured to cause the device to associate the data with a sequential set of addresses starting from the starting address indicated by the copy parameter list.

[0147] In some cases, the controller may be further configured to cause the device to transmit signaling in response to a copy command to the host, wherein receiving the copy parameter list may be based at least in part on transmitting the signaling in response to the copy command.

[0148] In some examples, the controller may be further configured to indicate to the host one or more memory devices support for a copy command, one or more memory devices support a maximum amount of data to be copied in response to a single copy command, one or more memory devices support a maximum number of block indicators for a single copy command when the data contains one or more data blocks each associated with a corresponding block indicator, one or more memory devices support a maximum amount of data associated with a single block indicator, or any combination thereof.

[0149] In some cases of the device, the copy command contains operation codes specific to (e.g., dedicated to, exclusive to) the copy command.

[0150] In some examples of the device, the controller may be configured to allow the device to send a busy status to the host for a limited duration, at least in part, based on receiving the replication command (e.g., afterward).

[0151] In some instances of the device, one or more memory devices may be or be included in a Universal Flash Memory (UFS) device.

[0152] In some cases, the controller may be further configured to cause the device to read the data from a first set of memory cells associated with the one or more first addresses in response to the copy command; and to write a copy of the data to a second set of memory cells associated with the one or more second addresses in response to the copy command.

[0153] In some examples of the device, one or more second addresses include one or more second logical addresses, and associating data with one or more second addresses includes updating one or more mapping tables within the memory array to associate one or more second logical addresses with one or more second physical addresses corresponding to a second set of memory cells.

[0154] In some instances of the device, the data remains stored in the first memory set after a copy of the data has been written to the second memory set.

[0155] In some cases of the device, one or more second addresses comprise one or more second logical addresses, and the data may be stored at a set of memory cells having one or more physical addresses before the copy command is received. Associating the data with the one or more second addresses includes updating one or more mapping tables within the memory array to associate the one or more second logical addresses with the one or more physical addresses.

[0156] In some examples, the controller may be further configured to cause the device to continue storing data at a set of memory cells with one or more physical addresses (e.g., after the data is associated with one or more second addresses), wherein the one or more first addresses include one or more first logical addresses, and after the data can be associated with one or more second addresses, one or more mapping tables associate one or more physical addresses with both one or more second logical addresses and one or more first logical addresses.

[0157] In some cases, the controller may be further configured to cause the device to maintain one or more second tables that associate one or more first logical addresses with one or more second logical addresses.

[0158] In some instances, the controller may be further configured to cause the device to receive an access command for at least a portion of the data and to check one or more second tables at least in part based on the received access command, wherein the controller may be further configured to cause the device to perform the check at least in part based on a flag stored in one or more mapping tables associated with a first logical address among one or more first logical addresses or a second logical address among one or more second logical addresses, or wherein the controller may be further configured to cause the device to perform the check at least in part based on metadata stored associated with at least said portion of the data.

[0159] Another device is described. The device may include a controller configured to be coupled to a memory system (e.g., one or more memory devices), wherein the controller is configured to cause the device to identify data associated with one or more first addresses within an address space of the memory system; issue a copy command to the memory system, wherein the copy command instructs the memory system to associate the data with one or more second addresses within the address space; and, after issuing the copy command, issue an access command for at least a portion of the data to the memory system, wherein the access command is associated with a second address among the one or more second addresses.

[0160] In some instances, the controller may be further configured to cause the device to transmit a list of copy parameters associated with a copy command to the memory system, wherein the list of copy parameters indicates one or more first addresses, one or more second addresses, or both.

[0161] In some cases of the device, the copy command includes an indication of the length of the copy parameter list.

[0162] In some examples of the device, the data comprises one or more data blocks, and the replication parameter list comprises one or more block indicators, each for a corresponding block in the one or more blocks.

[0163] In some cases of the device, the block indicator in one or more block indicators includes an indication of the corresponding start address for the corresponding block within the address space, an indication of the size of the corresponding block, or both.

[0164] In some cases of the device, the copy parameter list includes an indication of the number of information assigned to the one or more block indicators.

[0165] In some cases of the device, the copy parameter list includes an indication of the number of information items contained in the copy parameter list, where the number of items does not include the indication of the number of items.

[0166] In some examples of the device, the replication parameter list includes an indication of the start address within one or more second addresses.

[0167] In some cases of the device, one or more second addresses comprise a sequential set of addresses starting with a start address indicated by the copy parameter list.

[0168] In some instances, the controller may be further configured to cause the device to receive signaling from the memory system in response to a copy command, wherein the transmit copy parameter list may be based at least in part on the signaling received in response to the copy command.

[0169] In some cases, the controller may be further configured to receive signaling from the memory system indicating the memory system's support for copy commands, the maximum amount of data that the memory system supports copying in response to a single copy command, the maximum number of block indicators that the memory system supports for a single copy command when the data contains one or more data blocks each associated with a corresponding block indicator, the maximum amount of data that the memory system supports associated with a single block indicator, or any combination thereof.

[0170] In some examples of the device, the copy command further indicates that after the data can be associated with one or more second addresses, the data can remain associated with one or more first addresses.

[0171] In some instances, the copy command includes operation code that can be specific to the copy command.

[0172] In some instances of the device, one or more first addresses contain one or more first LBAs, and one or more second addresses contain one or more second LBAs.

[0173] In some cases of the device, the memory system may be allowed to send a busy status to the device for a limited duration, at least in part, based on receiving a copy command.

[0174] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, signals may represent buses of signals, which may have various bit widths.

[0175] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0176] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If a component, such as a controller, couples other components together, then the component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0177] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0178] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0179] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0180] Additionally, the terms "directly in response to" or "directly responding to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly responding to" such other condition or action.

[0181] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0182] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, for example, degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., most charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., most charge carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0183] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0184] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0185] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0186] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0187] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list followed by phrases such as "at least one of..." or "one or more of..."), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0188] Computer-readable media includes both non-transitory computer storage media and communication media that include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0189] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system comprising: One or more memory devices; and Processing circuitry, coupled to the one or more memory devices and configured to cause the memory system to: Data associated with one or more first addresses in an address space is stored in one or more memory devices; The host receives a copy command for the data of the one or more memory devices, wherein the copy command includes a numerical value representing a number of bytes, the number of bytes being the length of a copy parameter list associated with the copy command, and the copy parameter list is subsequently received by the memory system after the copy command is received; After receiving the copy command, the copy parameter list is received from the host, wherein the copy parameter list includes one or more first addresses and one or more second addresses, and wherein the length of the copy parameter list is equal to the number of bytes represented by the value contained in the copy command; and In response to the copy command, the data is associated with one or more second addresses within the address space.

2. The memory system according to claim 1, wherein: The data includes one or more data blocks; and The list of replication parameters includes one or more block indicators, each for a corresponding block in the one or more blocks.

3. The memory system of claim 2, wherein the block indicator in the one or more block indicators includes an indicator of the corresponding start address of the corresponding block within the address space, an indicator of the size of the corresponding block, or both.

4. The memory system of claim 2, wherein the copy parameter list includes an indication of the number of information assigned to the one or more block indicators.

5. The memory system of claim 1, wherein the copy parameter list includes an indication of the number of information contained in the copy parameter list, the number of information excluding the indication of the number.

6. The memory system of claim 1, wherein the copy parameter list includes an indication of a start address within the one or more second addresses.

7. The memory system of claim 6, wherein, in order to associate the data with the one or more second addresses, the processing circuitry is configured to cause the memory system to: The data is associated with a sequential set of addresses that begin at the starting address indicated by the list of replication parameters.

8. The memory system of claim 1, wherein the copy command includes operation code specific to the copy command.

9. The memory system of claim 1, wherein the processing circuitry is configured to allow the memory system to send a busy status to the host for a finite duration after receiving the copy command.

10. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: In response to the copy command, the data is read from a first set of memory cells associated with the one or more first addresses; and In response to the copy command, a copy of the data is written to a second set of memory cells associated with the one or more second addresses.

11. The memory system according to claim 10, wherein: The one or more second addresses include one or more second logical addresses; and Associating the data with the one or more second addresses includes updating one or more mapping tables within the memory system to associate the one or more second logical addresses with one or more second physical addresses corresponding to the second set of memory cells.

12. The memory system of claim 10, wherein after the copy of the data is written to the second set of memory cells, the data remains stored in the first set of memory cells.

13. The memory system according to claim 1, wherein: The one or more second addresses include one or more second logical addresses; Prior to receiving the copy command, the data is stored in a set of memory cells with one or more physical addresses; and Associating the data with the one or more second addresses includes updating one or more mapping tables within the memory system to associate the one or more second logical addresses with the one or more physical addresses.

14. The memory system of claim 13, wherein the processing circuitry is further configured to cause the memory system to: The data continues to be stored at the set of memory cells having the one or more physical addresses, wherein: The one or more first addresses include one or more first logical addresses; and After the data is associated with the one or more second addresses, the one or more mapping tables associate the one or more physical addresses with both the one or more second logical addresses and the one or more first logical addresses.

15. A non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of an electronic device, cause the electronic device to: Storing data associated with one or more first addresses in an address space within one or more memory devices; The host receives a copy command for the data of the one or more memory devices, wherein the copy command includes a numerical value representing a number of bytes, the number of bytes being the length of a copy parameter list associated with the copy command, the copy parameter list being received by the memory system after the copy command is received; After receiving the copy command, the copy parameter list is received from the host, wherein the copy parameter list includes one or more first addresses and one or more second addresses, and wherein the length of the copy parameter list is equal to the number of bytes represented by the value contained in the copy command; and In response to the copy command, the data is associated with one or more second addresses within the address space.

16. The non-transitory computer-readable medium according to claim 15, wherein: The data includes one or more data blocks; and The list of replication parameters includes one or more block indicators, each for a corresponding block in the one or more blocks.

17. The non-transitory computer-readable medium of claim 16, wherein the block indicator in the one or more block indicators includes an indication of a corresponding start address for the corresponding block within the address space, a size indication of the corresponding block, or both.

18. The non-transitory computer-readable medium of claim 16, wherein the copy parameter list includes an indication of the amount of information assigned to the one or more block indicators.

19. The non-transitory computer-readable medium of claim 15, wherein the copy parameter list includes an indication of the number of information contained in the copy parameter list, the number of information excluding the indication of the number.

20. The non-transitory computer-readable medium of claim 15, wherein the list of copying parameters includes an indication of a start address within the one or more second addresses.

21. The non-transitory computer-readable medium of claim 20, wherein, in order to associate the data with the one or more second addresses, the instructions, when executed by the one or more processors of the electronic device, further cause the electronic device to: The data is associated with a sequential set of addresses that begin at the starting address indicated by the list of replication parameters.

22. A method performed by a memory system including one or more memory devices, the method comprising: Data associated with one or more first addresses in an address space is stored in one or more memory devices; The host receives a copy command for the data of the one or more memory devices, wherein the copy command includes a numerical value representing a number of bytes, the number of bytes being the length of a copy parameter list associated with the copy command, and the copy parameter list is subsequently received by the memory system after the copy command is received; After receiving the copy command, the copy parameter list is received from the host, wherein the copy parameter list includes one or more first addresses and one or more second addresses, and wherein the length of the copy parameter list is equal to the number of bytes represented by the value contained in the copy command; and In response to the copy command, the data is associated with one or more second addresses within the address space.

23. An apparatus comprising: Processing circuitry configured to be coupled to a memory system, wherein the processing circuitry is configured to cause the device to: Identify data associated with one or more first addresses within the address space of the memory system; A copy command is issued to the memory system, wherein the copy command instructs the memory system to associate the data with one or more second addresses within the address space, and wherein the copy command includes a value representing the number of bytes, the number of bytes being the length of a copy parameter list associated with the copy command, and the copy parameter list is subsequently issued to the memory system after the copy command is issued; After the copy command is issued, the copy parameter list is issued to the memory system, wherein the copy parameter list includes one or more first addresses and one or more second addresses, and wherein the length of the copy parameter list is equal to the number of bytes represented by the value contained in the copy command; and After the copy command is issued, an access command for at least a portion of the data is issued to the memory system, wherein the access command is associated with a second address among the one or more second addresses.

24. The device according to claim 23, wherein: The data includes one or more data blocks; and The list of replication parameters includes one or more block indicators, each for a corresponding block in the one or more blocks.

25. The device of claim 24, wherein the block indicator in the one or more block indicators includes an indication of a corresponding start address for the corresponding block within the address space, a size indication of the corresponding block, or both.

26. The device of claim 24, wherein the copy parameter list includes an indication of the number of information assigned to the one or more block indicators.

27. The device of claim 23, wherein the list of replication parameters includes an indication of a start address within the one or more second addresses.

28. A non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of an electronic device, cause the electronic device to: Identify data associated with one or more first addresses within the address space of the memory system; A copy command is issued to the memory system, wherein the copy command instructs the memory system to associate the data with one or more second addresses within the address space, and wherein the copy command includes a value representing the number of bytes, the number of bytes being the length of a copy parameter list associated with the copy command, and the copy parameter list is subsequently issued to the memory system after the copy command is issued; After the copy command is issued, the copy parameter list is issued to the memory system, wherein the copy parameter list includes one or more first addresses and one or more second addresses, and wherein the length of the copy parameter list is equal to the number of bytes represented by the value contained in the copy command; and After the copy command is issued, an access command for at least a portion of the data is issued to the memory system, wherein the access command is associated with a second address among the one or more second addresses.

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