Phase change memory and manufacturing method thereof

Abstract

An embodiment of the present application proposes a phase change memory and a manufacturing method thereof, wherein the phase change memory comprises: a phase change memory unit, wherein the phase change memory unit comprises at least a first electrode, a gating layer, and a second electrode stacked in sequence; the gating layer comprises a first sub-gating layer and a second sub-gating layer stacked alternately; the material of the first sub-gating layer comprises at least germanium, a chalcogen element, and a first doping element; wherein the chalcogen element comprises sulfur and / or selenium; the material of the second sub-gating layer comprises a preset metal element; when the first electrode and the second electrode receive a voltage, the first doping element and the preset metal element are used to provide metal ions for the gating layer.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a phase change memory and a method for manufacturing the same. Background Art

[0002] 3D Phase Change Memory (3D PCM) is a new type of non-volatile memory device that has the advantages of high speed and long life of Dynamic Random Access Memory (DRAM) and low cost and non-volatility of Flash Memory. In addition, it can be used in mobile devices due to its low power consumption and high integration.

[0003] In the related art, phase change memory cells (PCM cells) can be stacked vertically to the substrate to improve the bit density and integration of the phase change memory. How to improve the bit density and integration of the phase change memory while improving the driving capability and reducing the holding voltage has become an urgent problem to be solved. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a phase change memory and a method for manufacturing the same.

[0005] According to a first aspect of an embodiment of the present application, a phase change memory is provided, including:

[0006] A phase-change memory unit, the phase-change memory unit at least comprising a first electrode, a gating layer, and a second electrode stacked in sequence; the gating layer comprises a first sub-gating layer and a second sub-gating layer stacked alternately;

[0007] The material of the first sub-selection layer at least includes germanium, chalcogen, and a first doping element; wherein the chalcogen includes sulfur and / or selenium;

[0008] The material of the second sub-gating layer includes a preset metal element;

[0009] When the first electrode and the second electrode receive a voltage, the first doping element and the preset metal element are used to provide metal ions for the gating layer.

[0010] In the above scheme, the first doping element is the same as or different from the preset metal element, and the first doping element and the preset metal element both include at least one of Ti, As, Te, Sb, Zr, Hf, Sc, Y, La, Ce, and Ho.

[0011] In the above scheme, the chemical formula of the material of the first sub-selection layer is Ge x My Q 100-x-y , M includes sulfur element and / or selenium element, Q includes a first doping element; wherein x and y refer to the atomic percentage of the element, 0<x<40, 0<y<60, and 0≤100-xy≤10.

[0012] In the above solution, the material of the second sub-selection layer includes a single substance of the preset metal element or a compound of the preset metal element.

[0013] In the above solution, the material of the second sub-selection layer includes titanium or titanium telluride.

[0014] In the above solution, the material of the first sub-selection layer also includes a second doping element; the second doping element includes at least one of C, Si, N, and P.

[0015] In the above scheme, the chemical formula of the material of the first sub-selection layer is Ge x M y Q z R 100-x-y-z , M includes sulfur element and / or selenium element, Q includes a first doping element, and R includes a second doping element; wherein x, y, and z all refer to the atomic percentage of the element, wherein x, y, and z all refer to the atomic percentage of the element, 0<x<40, 0<y<60, 0<z≤10, 0<100-xyz≤1.

[0016] In the above solution, the phase change memory unit further includes: a phase change memory layer and a third electrode which are sequentially stacked and arranged above the second electrode or below the first electrode.

[0017] According to a second aspect of an embodiment of the present application, a method for manufacturing a phase change memory is provided, comprising:

[0018] A phase-change memory unit is formed, wherein the phase-change memory unit at least comprises a first electrode, a gating layer, and a second electrode which are stacked in sequence; the gating layer comprises a first sub-gating layer and a second sub-gating layer which are stacked alternately;

[0019] The material of the first sub-selection layer at least includes germanium, sulfur and / or selenium and a first doping element;

[0020] The material of the second sub-gating layer includes a preset metal element;

[0021] When the first electrode and the second electrode receive a voltage, the first doping element and the preset metal element are used to provide metal ions for the gating layer.

[0022] In the above scheme, the method further comprises:

[0023] A first doping element is formed in the first sub-selection layer through a thermal diffusion process or a doping process.

[0024] An embodiment of the present application provides a phase change memory and a method for manufacturing the same, wherein the phase change memory comprises: a phase change memory unit, wherein the phase change memory unit comprises at least a first electrode, a gating layer, and a second electrode stacked in sequence; the gating layer comprises a first sub-gating layer and a second sub-gating layer stacked alternately; the material of the first sub-gating layer comprises at least germanium, a chalcogen, and a first doping element; wherein the chalcogen comprises sulfur and / or selenium; the material of the second sub-gating layer comprises a preset metal element; when the first electrode and the second electrode receive a voltage, the first doping element and the preset metal element are used to provide metal ions for the gating layer. In each embodiment of the present application, a gating structure is formed by a plurality of alternately stacked first sub-gating layers and second sub-gating layers. The gating structure has a lower thermal conductivity and a higher electrical conductivity, which can improve the stability of the gating structure and further improve the ability of the gating structure to drive current; and by introducing doped ions or metal ions as another form of carriers into the first sub-gating layer and the second sub-gating layer, under the action of the electric field, electrons and metal ions act together as two types of carriers, which can greatly improve the driving current and switching ratio of the gating structure, reduce the holding voltage of the gating structure, and thereby optimize the performance of the phase change memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of a phase change memory according to an exemplary embodiment;

[0026] Figure 2a to Figure 2c is a schematic diagram showing different transition states of a gating structure according to an exemplary embodiment;

[0027] Figures 3a to 3d is a schematic diagram of some phase change memories according to an exemplary embodiment;

[0028] Figures 4a to 4f is a schematic diagram showing another gating structure in different transition states according to an exemplary embodiment;

[0029] Figure 5 is a schematic diagram of another phase change memory according to an exemplary embodiment;

[0030] Figure 6 is a schematic diagram of another phase change memory according to an exemplary embodiment;

[0031] Figures 7a to 7c is a schematic cross-sectional view showing a manufacturing process of yet another phase change memory according to an exemplary embodiment. DETAILED DESCRIPTION

[0032] The technical solution of the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation method of the present application is shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0033] In the following paragraphs, various embodiments of the present application are described in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present application will become more apparent from the following description and claims. It should be noted that the accompanying drawings are in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present application.

[0034] It will be understood that the meaning of “on,” “over,” and “over” in this application should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0035] In the embodiments of the present application, the term "A is connected to B" includes the situation where A and B are connected to each other in contact with each other, or the situation where A is connected to B in a non-contact manner with other components interposed between A and B.

[0036] In the embodiments of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0037] In the embodiment of the present application, the term "layer" refers to a material portion including an area with a thickness. The layer may extend over the entirety of the lower or upper structure, or may have a range that is smaller than the range of the lower or upper structure. In addition, the layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. For example, the layer may be located between the top surface and the bottom surface of the continuous structure, or the layer may be between any horizontal faces at the top surface and the bottom surface of the continuous structure. The layer may extend horizontally, vertically and / or along an inclined surface. The layer may include multiple sublayers. For example, the interconnect layer may include one or more conductors and contact sublayers (where interconnects and / or via contacts are formed), and one or more dielectric sublayers.

[0038] It should be noted that the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0039] With the continuous miniaturization of process nodes, the difficulties encountered in the continuation of Moore's Law have become increasingly arduous, so it is difficult to continue Moore's Law by relying on device size reduction. For three-dimensional phase change memory, it has become very difficult to obtain performance improvement by reducing the size of the phase change memory unit (including the memory unit (Resistor Cell) and the gate structure (Selector Cell)). On the other hand, the process difficulty of size miniaturization has also increased significantly, further increasing the difficulty of improving the performance of phase change memory. Therefore, finding new ways to improve performance has become a new trend to continue Moore's Law. In addition, the development of new phase change materials and device structures has the disadvantages of long cycle and high cost. Optimizing the stacking structure and thin film material of the gate structure film of the phase change memory unit (memory unit and gate structure) as a new way to improve performance can optimize device performance without changing the main structure, such as improving the driving ability of the gate structure and reducing the holding voltage of the gate structure, thereby improving the performance of the gate device.

[0040] However, the carrier type of the conventional carrier-based gating device is single, and it is difficult to provide a high driving current; the switching ratio (Roff / Ron) of the conventional carrier-based gating device is low; the conventional carrier-based gating device has a high holding voltage. Specifically:

[0041] For ease of description, the first direction and the second direction in the embodiment of the present application are represented as two orthogonal directions in the stacking plane, that is, two directions in which each stacked layer extends laterally in the stacking plane; the third direction is a direction perpendicular to the stacking plane, that is, the third direction is the thickness direction of the stack. The first direction can be represented as the X direction in the drawings; the third direction can be represented as the Z direction in the drawings.

[0042] Figure 1 is a schematic diagram of a phase change memory according to an exemplary embodiment. Figure 1 As shown, the phase change memory 10 includes: a bit line BL, a first electrode 101, a gating layer 102, a second electrode 103, a phase change memory layer 104, a third electrode 105, and a word line WL that are stacked in sequence. The phase change memory cell 100 coupled between the word line WL and the bit line BL in the stacking direction is a structure including a gating structure S (Selector) and a storage structure R (Resistor) (1S1R). The gating structure S includes a first electrode 101, a gating layer 102, and a second electrode 103; the storage structure R includes a second electrode 103, a phase change memory layer 104, and a third electrode 105.

[0043] refer to Figure 2a to Figure 2cThe phase change memory unit 100 includes a gating structure, which includes a gating layer 102 and a first electrode 101 and a second electrode 103 located on the upper and lower surfaces of the gating layer 102 in the stacking direction; the material of the gating layer 102 is an amorphous chalcogenide material (such as GeSe, GeS), and the material of the first electrode 101 and the second electrode 103 is tungsten (W).

[0044] like Figure 2a to Figure 2c As shown, under the action of the electric field, some carrier electrons first gain energy and their energy levels are in the conduction band. These carriers can move freely, but the gate is still in a subthreshold state. When the voltage is greater than the threshold voltage, more carrier electrons are in a free-moving state. At this time, the electrons move freely between the electrodes, and the gate device is in an on state, providing a driving current for the phase change memory device.

[0045] like Figure 2a As shown, when the first electrode 101 and the second electrode 103 do not receive voltage, no current flows through the gating layer 102. Figure 2b As shown, when the first electrode 101 and the second electrode 103 begin to receive voltage, the first electrode 101 and the second electrode 103 containing W cannot provide additional metal ions for the gating layer 102 to increase its operating current, and only the electron E carrier conducts electricity, and the electron E passes through the gating layer 102 under the action of the voltage. Figure 2c As shown, when the first electrode 101 and the second electrode 103 receive voltage, the electrons E pass through the selection layer 102 under the action of the voltage. Since only a single electron carrier provides current, the ability of the selection layer 102 to drive current is low, which is not conducive to the selection layer 102 providing driving current for the phase change memory device.

[0046] The gating structure in a common phase-change memory cell is an amorphous sulfur-based material, which provides a large on-state current by causing the transition of carrier electrons under the action of an electric field, thereby providing a driving current for the phase-change structure. To further improve the driving capability and switching ratio of the gating structure, it is difficult to achieve significant results only by miniaturization.

[0047] In some embodiments, by optimizing the stacking structure and / or material type of the gating structure, the driving capability and switching ratio of the gating structure can be improved, the holding voltage of the gating structure can be reduced, and the performance of the phase change memory can be optimized.

[0048] Figures 3a to 3d FIG. 1 is a schematic diagram of several phase change memories according to an exemplary embodiment. Figures 3a to 3d As shown, the phase change memory comprises:

[0049] A phase change memory unit 200, wherein the phase change memory unit 200 at least comprises a first electrode 201, a gating layer 202, and a second electrode 203 which are stacked in sequence; the gating layer 202 comprises a first sub-gating layer 2021 and a second sub-gating layer 2022 which are stacked alternately;

[0050] The material of the first sub-selection layer 2021 at least includes germanium, chalcogen and a first doping element; wherein the chalcogen includes sulfur and / or selenium;

[0051] The material of the second sub-gating layer 2022 includes a preset metal element;

[0052] When the first electrode 201 and the second electrode 203 receive a voltage, the first doping element and the preset metal element are used to provide metal ions for the gating layer 202 .

[0053] It should be noted that Figure 3a and Figure 3b The number of the first sub-gating layers 2021 and the second sub-gating layers 2022 is different; Figure 3c and Figure 3d The number of the first sub-selection layers 2021 and the number of the second sub-selection layers 2022 are the same.

[0054] For example, Figure 3a As shown, the gating layer 202 includes a first sub-gating layer 2021 and a second sub-gating layer 2022 which are alternately stacked, and the gating layer 202 is in contact with and electrically connected to the first electrode 201 and the second electrode 203 through the second sub-gating layer 2022 in the stacking direction.

[0055] For example, Figure 3b As shown, the gating layer 202 includes a first sub-gating layer 2021 and a second sub-gating layer 2022 that are alternately stacked, and the gating layer 202 is in contact with and electrically connected to the first electrode 201 and the second electrode 203 through the first sub-gating layer 2021 in the stacking direction.

[0056] For example, Figure 3c , Figure 3d As shown, the gating layer 202 includes a first sub-gating layer 2021 and a second sub-gating layer 2022 which are alternately stacked, and the gating layer 202 is respectively in contact with and electrically connected to the second electrode 203 and the first electrode 201 through the first sub-gating layer 2021 and the second sub-gating layer 2022 in the stacking direction, or the first sub-gating layer 2021 and the second sub-gating layer 2022 are respectively in contact with and electrically connected to the first electrode 201 and the second electrode 203.

[0057] It should be noted that Figures 3a to 3d The first sub-selection layer 2021 and the second sub-selection layer 2022 shown in the figure are only used for illustration, and are not used to limit the thickness relationship and / or quantity relationship of the first sub-selection layer 2021 and the second sub-selection layer 2022 alternately stacked in the embodiment of the present application.

[0058] In some embodiments, the first sub-gating layer 2021 and the second sub-gating layer 2022 provide layers with the same or different thicknesses. In practical applications, the thickness can be selected according to actual needs; specifically, the thickness of the first sub-gating layer 2021 can be greater than the thickness of the second sub-gating layer 2022.

[0059] In some specific embodiments, the thickness of the first sub-gating layer 2021 is 2 to 10 times the thickness of the second sub-gating layer 2022. Exemplarily, the thickness of the first sub-gating layer 2021 ranges from 1 nm to 100 nm, and the thickness of the second sub-gating layer 2022 ranges from 1 nm to 40 nm.

[0060] In the above embodiment, one of the first sub-selection layer 2021 and one of the second sub-selection layer 2022 constitute a periodic stack, and the selection layer 202 includes a plurality of the periodic stacks alternately stacked; the number of the periodic stacks may be 2 to 100, and the thickness of each of the periodic stacks may be 1 nm to 100 nm. It should be noted that the number of the plurality of periodic stacks and the thickness of each of the first sub-selection layer 2021 and each of the second sub-selection layer 2022 may be adjusted according to the actual process requirements.

[0061] The first doping element can provide metal ion carriers, so that the first sub-selection layer 2021 has the combined effect of two carriers (electrons and metal ions); at the same time, the preset metal element can further provide metal ion carriers, so that the selection layer 202 has the combined effect of abundant carriers (electrons and metal ions), and the combined effect of these carriers can greatly enhance the driving current capability of the selection layer.

[0062] Here, the first doping element and the preset metal element may be the same or different. In some embodiments, the first doping element and the preset metal element may include at least one of: semi-metallic elements (such as As, Te, Sb), transition metal elements (such as Ti, Zr, Hf), and rare earth elements (such as Sc, Y, La, Ce, Ho).

[0063] In some specific embodiments, the first doping element is the same as or different from the preset metal element, and the first doping element and the preset metal element both include at least one of titanium (Ti), arsenic (As), tellurium (Te), antimony (Sb), zirconium (Zr), hafnium (Hf), scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), and holmium (Ho).

[0064] In some embodiments, the chemical formula of the material of the first sub-gating layer is Ge x M y Q 100-x-y , M includes sulfur element and / or selenium element, Q includes a first doping element; wherein x and y refer to the atomic percentage of the element, 0<x<40, 0<y<60, and 0≤100-xy≤10.

[0065] Here, the atomic percentage of the first doping element in the first sub-gating layer is in the range of 0-10%. In this way, the driving current capability of the gating layer can be improved as much as possible under the premise of improving the stability of the gating layer.

[0066] In some embodiments, the material of the second sub-gating layer includes a single substance of the preset metal element or a compound of the preset metal element.

[0067] In some embodiments, the material of the second sub-selection layer includes titanium or titanium telluride. In some specific embodiments, the titanium telluride may include TiTe, TiTe 2 、Ti 5 Te 8 、Ti 2 Te 3 Preferably, the material of the second sub-gating layer comprises TiTe 2 .

[0068] Titanium subgroup tellurides have lower thermal conductivity and higher electrical conductivity. Thus, titanium subgroup tellurides can reduce the energy loss of the gate structure in the open or closed state, thereby improving the switching ratio of the gate structure. Under a larger turn-on current, the turn-on resistance is lower, thereby improving the switching ratio.

[0069] In some embodiments, the material of the first sub-selection layer further includes a second doping element; the second doping element includes at least one of carbon (C), silicon (Si), nitrogen (N), and phosphorus (P).

[0070] Here, the second doping element includes a non-metallic element, such as a P-type doping element or an N-type doping element. Exemplarily, the second doping element includes an N-type doping element N.

[0071] By doping a certain amount of non-metallic material elements into the first sub-gating layer, the thermal stability of the gating layer can be improved.

[0072] In some embodiments, the material of the first sub-gating layer has a chemical formula of Ge x M y Q z R 100-x-y-z , M includes sulfur element and / or selenium element, Q includes a first doping element, and R includes a second doping element; wherein x, y, and z all refer to the atomic percentage of the element, wherein x, y, and z all refer to the atomic percentage of the element, 0<x<40, 0<y<60, 0<z≤10, 0<100-xyz≤1.

[0073] Here, the atomic percentage of the second doping element in the first sub-gating layer is in the range of 0-1%. In this way, the stability of the gating layer can be improved while satisfying the driving current capability of the gating layer.

[0074] Exemplarily, the chemical formula of the material of the first sub-selection layer is (GeSe) a (Ti 2 Te) b R 100-a-b , wherein 0<a<40, 0≤b≤10, 0≤100-ab≤1; the material of the second sub-selection layer includes TiTe 2 Here, GeSe and Ti 2 Te constitutes the main material of the first sub-gating layer, which can stabilize the gating layer. 2 The material constituting the second sub-gating layer can improve the switching ratio of the gating layer.

[0075] Exemplarily, the chemical formula of the material of the first sub-selection layer is (GeSe) a (GeTi 2 ) b R 100-a-b , wherein 0<a+b<40, 0≤2b≤10, 0≤100-ab≤1; the material of the second sub-selection layer includes TiTe 2 Here, GeSe and GeTi 2 The main material constituting the first sub-gating layer can stabilize the gating layer. 2 The material constituting the second sub-gating layer can improve the switching ratio of the gating layer.

[0076] Exemplarily, the chemical formula of the material of the first sub-selection layer is (GeSe) a (GeTe 6 ) b R100-a-b , wherein 0<a+b<40, 0≤6b≤10, 0≤100-ab≤1; the material of the second sub-selection layer includes TiTe 2 Here, GeSe and GeTe 6 The main material constituting the first sub-gating layer can stabilize the gating layer. 2 The material constituting the second sub-gating layer can improve the switching ratio of the gating layer.

[0077] It can be understood that the gating layer 202 can realize an instantaneous transition from a high resistance state to a low resistance state under the operation of an electrical signal, and instantaneously return to a high resistance state when the electrical signal is removed; that is, the gating layer 202 can realize a transition from a high resistance state to a low resistance state when the threshold voltage is reached under the action of an external electric field, and the gating structure is opened, thereby providing a larger on-state current and thus providing a driving current to the phase change structure. When the effect of the external electric field is removed or the applied voltage is less than the threshold voltage, a transition from a low resistance state to a high resistance state can be realized, and the gating structure is closed, so that no current is provided to the phase change structure or an extremely low off-state current is provided to the phase change structure. Specifically:

[0078] A voltage is applied to the gating layer 202 through the first electrode 201 and the second electrode 203. When the threshold voltage is reached, the gating layer 202 is in a relatively low resistance state, the gating structure is opened, and an on-state current is provided for the phase change structure; when the applied voltage is removed or when the applied voltage is less than the threshold voltage, the gating layer 202 maintains a relatively high resistance state, the gating structure is closed, and an off-state current is provided for the phase change structure. In this way, in the 1S1R structure (1 gating structure and 1 storage structure), an external electric field is applied to the storage structure through the opening or closing state of the gating structure; further, the crystalline and amorphous properties of the phase change storage layer in the storage structure are used to store data, and the change of the crystalline and amorphous states of the phase change storage layer can represent a bit of data "1" or "0", and two logical states can be defined.

[0079] In the embodiment of the present application, in the first aspect, the gating layer 202 is composed of a plurality of the periodic stacks arranged by alternating stacking, wherein each of the periodic stacks includes a first sub-gating layer 2021 and a second sub-gating layer 2022. The structure of the plurality of periodic stacks introduces a certain number of interfaces between the stacks. Under the effect of interface scattering, the movement of phonons along the stacking growth direction is hindered, resulting in additional interface phonon impedance. In semiconductors, phonons are the main heat flow carriers, and the macroscopic thermal conductivity of semiconductor materials is mainly determined by phonons. Therefore, the interface phonon impedance will produce obvious interface thermal resistance, thereby reducing the thermal conductivity of the material. The reduction in the thermal conductivity of the material means a reduction in the heat diffusion of the material, and the ability to accumulate heat will be greatly enhanced. In other words, the reduction in thermal conductivity will improve the thermal properties of the multilayer phase change material, such as the thermal stability of the material. By utilizing this characteristic to manufacture the gating layer of the phase change memory, the materials of the first sub-gating layer 2021 and the second sub-gating layer 2022 have lower thermal conductivity and higher electrical conductivity, which can improve the stability of the gating layer and further improve the ability of the gating layer to drive current.

[0080] Secondly, by introducing metal ions as another form of carriers in the first sub-selection layer and the second sub-selection layer, under the action of the electric field, electrons and metal ions act together as two types of carriers, which can greatly improve the driving current and switching ratio of the selection structure and reduce the holding voltage of the selection structure. Compared with the selection structure in which a single carrier provides current, the performance of the metal ion-optimized selection layer is significantly improved, thereby optimizing the performance of the phase change memory and reducing the dependence on size miniaturization, becoming a low-cost and simple process method, and providing a reliable method for preparing high-performance selection structures in the future.

[0081] Figures 4a to 4f FIG. 1 is a schematic diagram showing another gating structure in different transition states according to an exemplary embodiment. In order to clearly and briefly describe the present application, Figures 4a to 4c Only the schematic diagram of the first sub-gating layer 2021 in the gating layer under different transition states is shown. Figure 4d to Figure 4f Only the schematic diagram of the second sub-gating layer 2022 in the gating layer in different transition states is shown. It can be understood that under the action of the external electric field, the first sub-gating layer and the second sub-gating layer in the gating layer act simultaneously. Figures 4a to 4c The function of the first sub-gating layer 2021 is shown in FIG. Figure 4d to Figure 4f The function of the second sub-selection layer 2022 shown in the figure is only used to clearly and briefly describe the present application, and is not used to limit the embodiments of the present application.

[0082] like Figure 4aAs shown, when the first electrode and the second electrode do not receive a voltage, no current flows through the first sub-selection layer 2021. Figure 4b As shown, when the first electrode and the second electrode receive a voltage, the first sub-selection layer 2021 provides additional metal ions I to increase the operating current. Figure 2b The first sub-gating layer 2021 can provide additional metal ions I to increase the current in the gating layer 202. Figure 4c As shown, compared with the W-containing sub-electrode (ref. Figure 2c In the first electrode 101 and the second electrode 103, the first sub-selection layer 2021 has metal ion I carriers in addition to electron E carriers, thereby improving the driving current capability of the selection layer 202, so that the selection layer 202 can be operated quickly.

[0083] like Figure 4d As shown, when the first electrode and the second electrode do not receive a voltage, no current flows through the second sub-selection layer 2022. Figure 4e As shown, when the first electrode and the second electrode receive a voltage, the second sub-selection layer 2022 provides additional metal ions I to increase their operating current. Figure 2b The first electrode 101 and the second electrode 103 in the gate layer 202 are provided with the second sub-gating layer 2022, which can provide additional metal ions I to increase the current in the gate layer 202. Figure 4f As shown, compared with the W-containing sub-electrode (ref. Figure 2c In the first electrode 101 and the second electrode 103, the second sub-selection layer 2022 has metal ion I carriers in addition to electron E carriers, thereby improving the driving current capability of the selection layer 202, so that the selection layer 202 can be operated quickly.

[0084] The first sub-selection layer 2021 and the second sub-selection layer 2022 contain additional metal ions. When the voltage received by the first electrode and the second electrode exceeds the threshold voltage of the selection structure, they can migrate from the unit cell structure of the first sub-selection layer 2021 and the second sub-selection layer 2022 to between the unit cell structures and undergo electrochemical reactions to form a conductive channel; when the voltage drops below a certain value, they can quickly diffuse into and migrate back to the unit cell structure of the first sub-selection layer 2021 and the second sub-selection layer 2022, thereby breaking the conductive channel.

[0085] On the one hand, the extra metal ions in the first sub-selection layer 2021 and the second sub-selection layer 2022 form an unstable conductive channel. When the voltage drops below a certain value, the first sub-selection layer 2021 and the second sub-selection layer 2022 can more effectively break down and return to the initial high-resistance off state. On the other hand, the first sub-selection layer 2021 and the second sub-selection layer 2022 are in a state of unsaturated metal ions, which can more effectively pull back the metal ions in the conductive channel and promote the rupture of the conductive channel.

[0086] In addition, the first sub-selection layer 2021 and the second sub-selection layer 2022 have a relatively fast transition speed, so their sub-threshold swing is relatively large, and the switching ratio is relatively large. At the same time, the first sub-selection layer 2021 and the second sub-selection layer 2022 are less difficult to etch than the sub-electrode of W with greater hardness (refer to Figure 2a to Figure 2c The first electrode 101 and the second electrode 103 are used in the manufacturing process, and the morphology control is relatively good. In addition, no additional mask is added, the process development difficulty is relatively small, the process development cost is relatively low, and the economic applicability is good.

[0087] At the same time, the gating layer 202 formed by the alternately stacked first sub-gating layer 2021 and the second sub-gating layer 2022 has a lower thermal conductivity and a higher electrical conductivity, which can improve the stability of the gating structure and further improve the ability of the gating structure to drive current.

[0088] In some embodiments, reference Figure 5 As shown, the phase change memory unit 200 further includes: a phase change memory layer 204 and a third electrode 205 which are sequentially stacked and arranged above the second electrode 203 or below the first electrode.

[0089] It should be noted that the first electrode 201, the second electrode 203 and the third electrode 205 represent the electrode layers in the phase change memory unit 200, and the material of the electrode layer may include amorphous carbon, such as α-phase carbon. The electrode layer is used to conduct electrical signals. It should be emphasized that the materials included in the first electrode 201, the second electrode 203 and the third electrode 205 can be the same or different, and the different reference numerals are only used to distinguish the differences in the positions of the electrode layers, and are not necessarily used to describe a specific order or sequence.

[0090] Here, the material of the phase change memory layer 204 may include: germanium antimony tellurium (Ge-Sb-Te, GST) alloy, or a mixture formed by doping at least one element of sulfur (S), nitrogen (N), oxygen (O) and silicon (Si) in the GST alloy. The material of the phase change memory layer 204 may also include any other suitable phase change material.

[0091] It should be noted that when the phase change memory layer 204 undergoes a phase change, the resistance of the phase change memory layer 204 changes. The phase change memory can store data according to the change in the resistance state of the phase change memory layer 204.

[0092] In some embodiments, reference Figure 6 As shown, the phase change memory 20 may further include:

[0093] Bit line BL and word line WL; wherein the bit line BL, the phase change memory cell 200 (reference Figure 5 ) and word lines WL are stacked sequentially from bottom to top; the bit lines BL and word lines WL are parallel to the same plane and perpendicular to each other, the phase change memory cell 200 (reference Figure 5 ) is perpendicular to both the bit line BL and the word line WL. It should be noted that the positions of the bit line BL and the word line WL can also be interchanged.

[0094] The material of the bit line BL and the word line WL includes a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, or any combination thereof. The bit line BL and the word line WL may have the same conductive material or different conductive materials.

[0095] It should be emphasized that the first plane on which the bit lines BL are arranged is parallel to the second plane on which the word lines WL are arranged, and the first plane does not overlap with the second plane. Figure 5 ) is located between the first plane and the second plane, and the phase change memory unit 200 (reference Figure 5 ) is perpendicular to both the first plane and the second plane.

[0096] The phase change memory 20 may further include: a substrate (not shown) located below the bit line BL; the material of the substrate (not shown) may include a semiconductor material, such as a silicon (Si) substrate.

[0097] The phase change memory provided in the embodiment of the present application can be formed by the manufacturing method of the phase change memory provided in the following embodiment, referring to Figures 7a to 7c In some embodiments, a method of forming a phase change memory 20 includes:

[0098] A phase change memory unit is formed, wherein the phase change memory unit at least comprises a first electrode 201, a gating layer 202, and a second electrode 203 which are stacked in sequence; the gating layer 202 comprises a first sub-gating layer 2021 and a second sub-gating layer 2022 which are stacked alternately (for details of the gating layer 202, refer to the above Figures 3a to 3dFor understanding, only the selection layer 202 is shown here and below); the material of the first sub-selection layer 2021 includes at least germanium, chalcogen and a first doping element; wherein the chalcogen includes sulfur and / or selenium; the material of the second sub-selection layer 2022 includes a preset metal element; when the first electrode 201 and the second electrode 203 receive a voltage, the first doping element and the preset metal element are used to provide metal ions for the selection layer 202.

[0099] For example, reference Figure 7a Before forming the first electrode 201, a bit line BL may be formed by a deposition process, and the first electrode 201 may be formed on the surface of the bit line BL; Figure 7a And combined with the above Figure 3a , a first sub-gating layer 2021 and a second sub-gating layer 2022 and a second electrode 203 which are stacked and arranged in sequence can be formed on the surface of the first electrode 201 through a deposition process. The deposition process includes but is not limited to a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process or a combination thereof.

[0100] In some embodiments, reference Figure 7b , the phase change memory unit further includes: a phase change memory layer, a third electrode; a reference Figure 7c , the phase change memory further includes a bit line BL and a word line WL; the method for forming the phase change memory 20 further includes:

[0101] After forming the first electrode 201, the gate layer 202, and the second electrode 203, a stacked phase change memory layer 204, a third electrode 205, and a word line WL are sequentially formed; the memory structure includes the second electrode 203, the phase change memory layer 204, and the third electrode 205. It should be noted that: Figures 7a to 7c This is only an example of a manufacturing method and is not intended to limit the manufacturing method of the phase change memory in the embodiment of the present application. It is understandable that the positions of the aforementioned gating layer and the phase change memory structure can be interchanged, the positions of the bit line BL and the word line WL can also be interchanged, and the relationship between the positions of the storage structure and the gating structure in the phase change memory structure is also applicable in manufacturing.

[0102] In some embodiments, the method further comprises:

[0103] A first doping element is formed in the first sub-selection layer 2021 through a thermal diffusion process or a doping process.

[0104] In practical applications, an in-situ doping process is used, which may include but is not limited to a PVD process, a CVD process or an ALD process, and a gas containing the first doping element is introduced while depositing the material of the first sub-select layer 2021 .

[0105] In some specific embodiments, the chemical formula of the material of the first sub-gating layer is Ge x M y Q 100-x-y , M includes sulfur and / or selenium, Q includes a first doping element, and the first doping element includes at least one of Ti, As, Te, Sb, Zr, Hf, Sc, Y, La, Ce, and Ho; wherein x and y refer to the atomic percentage of the element, 0<x<40, 0<y<60, and 0≤100-xy≤10.

[0106] Doping the first sub-gating layer 2021 with a first doping element includes:

[0107] Provide Ge x M y Base material;

[0108] Through the in-situ doping process, the first doping element is in-situ doped while depositing the base material to form the first sub-selection layer 2021.

[0109] In some other specific embodiments, doping the first sub-gating layer 2021 with a first doping element includes:

[0110] Provide Ge x M y Base material;

[0111] First, a seed layer containing a first doping element is formed by a thin film deposition process;

[0112] Then, on the seed layer, through an in-situ doping process, the first doping element is in-situ doped while depositing the base material to form the first sub-selection layer 2021.

[0113] The manufacturing method of the phase change memory provided in the embodiment of the present application is similar to the phase change memory in the above embodiment. For the technical features not fully disclosed in the embodiment of the present application, please refer to the above embodiment for understanding, and no further details will be given here.

[0114] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0115] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0116] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A phase change memory, characterized in that: include: A phase-change memory unit, the phase-change memory unit at least comprising a first electrode, a gating layer, and a second electrode stacked in sequence; the gating layer comprises a first sub-gating layer and a second sub-gating layer stacked alternately; The material of the first sub-selection layer at least includes germanium, chalcogen, and a first doping element; wherein the chalcogen includes sulfur and / or selenium; The material of the second sub-selection layer includes a preset metal element, and the material of the second sub-selection layer includes titanium telluride; When the first electrode and the second electrode receive a voltage, the first doping element and the preset metal element are used to provide metal ions for the gating layer.

2. The phase change memory according to claim 1, characterized in that: The first doping element is the same as or different from the preset metal element, and the first doping element and the preset metal element both include at least one of Ti, Sb, Zr, Hf, Sc, Y, La, Ce, and Ho.

3. The phase change memory according to claim 1, characterized in that: The chemical formula of the material of the first sub-gating layer is Ge x M y Q 100-x-y , M includes sulfur element and / or selenium element, Q includes a first doping element; wherein x and y refer to the atomic percentage of the element, 0<x<40, 0<y<60, and 0≤100-xy≤10.

4. The phase change memory according to claim 1, characterized in that: The material of the first sub-selection layer further includes a second doping element; the second doping element includes at least one of C, Si, N, and P.

5. The phase change memory according to claim 4, characterized in that: The material of the first sub-gating layer has the general chemical formula of Ge x M y Q z R 100-x-y-z , M includes sulfur element and / or selenium element, Q includes a first doping element, and R includes a second doping element; wherein x, y, and z all refer to the atomic percentage of the element, wherein x, y, and z all refer to the atomic percentage of the element, 0<x<40, 0<y<60, 0<z≤10, 0<100-xyz≤1.

6. The phase change memory according to claim 1, characterized in that: The phase-change memory unit further includes: a phase-change memory layer and a third electrode which are sequentially stacked and arranged above the second electrode or below the first electrode.

7. A method for manufacturing a phase change memory, characterized in that: include: A phase change memory unit is formed, the phase change memory unit at least comprising a first electrode, a gating layer, and a second electrode stacked in sequence; the gating layer comprises a first sub-gating layer and a second sub-gating layer stacked alternately; the material of the first sub-gating layer comprises at least germanium, sulfur and / or selenium and a first doping element; the material of the second sub-gating layer comprises a preset metal element, and the material of the second sub-gating layer comprises titanium telluride; when the first electrode and the second electrode receive a voltage, the first doping element and the preset metal element are used to provide metal ions for the gating layer.

8. The method according to claim 7, characterized in that The method further comprises: A first doping element is formed in the first sub-selection layer through a thermal diffusion process or a doping process.

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