Voltage controlled delay buffer with wide tuning range

Abstract

The present disclosure relates to voltage-controlled inverters. A voltage-controlled delay buffer includes a number of inverters configured in a cascade structure to receive an input signal from a source circuit and to output an output signal to an output circuit. The inverters include voltage-controlled inverters controlled by a control signal having a first voltage and a second voltage. The voltage-controlled inverters include a PMOS transistor to assist a low-to-high transition of the output signal and an NMOS transistor to assist a high-to-low transition of the output signal. Two variable capacitors, one connected in a forward direction and the other connected in a reverse direction, are used to adjust a delay of a transition of the input signal. Two other variable capacitors, one connected in a forward direction and the other connected in a reverse direction, are used to adjust a delay of a transition of the output signal according to the first voltage and the second voltage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to voltage-controlled delay buffers, and more particularly to voltage-controlled delay buffers with wide tuning range. BACKGROUND

[0002] It is well known that a typical delay buffer receives an input signal and emits an output signal such that the output signal is nearly identical to the input signal except for a time delay. In practice, the input signal is a logic signal, especially in the present disclosure. In many applications, it is desirable for the delay of the delay buffer to be tunable. A delay buffer with tunable delay is referred to as a variable delay buffer. A variable delay buffer with tunable delay and controllable by a voltage signal is referred to as a voltage-controlled delay buffer.

[0003] In designing a variable delay buffer, many factors need to be considered. First, a variable delay buffer will inevitably contribute additional noise and make the noise of the output signal larger than that of the input signal. Thus, it is desirable to mitigate the additional noise. Second, it is also generally desirable for the variable delay buffer to have a wide tuning range. Third, the interface between the variable delay buffer and the preceding circuit on the input side and the succeeding circuit on the output side needs to be properly handled. In practice, trade-off relationships between various factors need to be considered.

[0004] In one embodiment, the delay of the voltage-controlled delay buffer comprises an inverter powered by a tunable supply voltage, and the supply voltage serves as the voltage signal that controls the delay. The smaller the supply voltage, the longer the delay. This embodiment can have a very wide tuning range, but has the following disadvantages: first, when the delay needs to be very long, the supply voltage needs to be very small, making the output signal very susceptible to additional noise. Second, the supply voltage is variable, and thus can not interface well with the preceding circuit or the succeeding circuit.

[0005] In one embodiment, a voltage-controlled delay buffer includes a tunable current source to charge a capacitor according to an input signal. When the input signal is at a high level, the capacitor is charged by the tunable current source, and when the input signal is at a low level, the capacitor is discharged. The current of the tunable current source is controlled by a bias voltage, which is a voltage signal that controls the delay. The smaller the current of the tunable current source, the longer the delay. This embodiment has a disadvantage in that the tunable current source is prone to low frequency noise, known as "flicker noise," which is often very detrimental.

[0006] Therefore, it is desirable for those skilled in the art to implement a voltage-controlled delay buffer that makes a favorable trade-off between tuning range and noise, and that does not have interface issues. SUMMARY

[0007] In one embodiment, a voltage-controlled delay buffer includes: a first P-channel Metal oxide semiconductor (PMOS) transistor to enable a pull-up of an output signal at an output node according to an input signal at an input node; a second PMOS transistor to perform the pull-up according to the input signal; a third PMOS transistor to assist the pull-up according to a first voltage; a first N-channel Metal oxide semiconductor (NMOS) transistor to enable a pull-down of the output signal according to the input signal; a second NMOS transistor to perform the pull-down according to the input signal; a third NMOS transistor to assist the pull-down according to a second voltage; a first forward-connected variable capacitor and a first reverse-connected variable capacitor controlled by the first voltage and the second voltage, respectively, and to provide a parallel capacitance at the input node; and a second forward-connected variable capacitor and a second reverse-connected variable capacitor controlled by the first voltage and the second voltage, respectively, and to provide a parallel capacitance at the output node.

[0008] In one embodiment, a voltage-controlled delay buffer includes a plurality of inverters. The inverters are configured in a cascade structure. The inverters are configured to receive an input signal from a source circuit and to output an output signal to a load circuit. The inverters include a voltage-controlled inverter. The voltage-controlled inverter is configured to receive an input signal from a preceding circuit and to output an output signal to a succeeding circuit in response to a control signal. The control signal includes a first voltage and a second voltage. The voltage-controlled inverter includes a first PMOS transistor configured to enable a pull-up of the output signal in response to the input signal, a second PMOS transistor configured to perform the pull-up in response to the input signal, a third PMOS transistor configured to assist the pull-up in response to the first voltage, a first NMOS transistor configured to enable a pull-down of the output signal in response to the input signal, a second NMOS transistor configured to perform the pull-down in response to the input signal, a third NMOS transistor configured to assist the pull-down in response to the second voltage, a first forward-connected variable capacitor and a first reverse-connected variable capacitor controlled by the first voltage and the second voltage, respectively, and configured to provide a parallel capacitance at an input node, and a second forward-connected variable capacitor and a second reverse-connected variable capacitor controlled by the first voltage and the second voltage, respectively, and configured to provide a parallel capacitance at an output node.

[0009] In one embodiment, a voltage-controlled delay buffer includes a plurality of inverters. The inverters are configured in a cascade structure. The inverters are configured to receive an input signal from a source circuit and to output an output signal to a load circuit. The inverters include a voltage-controlled inverter. The voltage-controlled inverter is controlled by a control signal. The control signal includes a first voltage and a second voltage. The voltage-controlled inverter includes: a first PMOS transistor having a source, a gate, and a drain connected to a supply node, an input node, and a high-side internal node, respectively; a second PMOS transistor having a source, a gate, and a drain connected to the high-side internal node, the input node, and an output node, respectively; a third PMOS transistor having a source, a gate, and a drain connected to the high-side internal node, the first voltage, and the output node, respectively; a first NMOS transistor having a source, a gate, and a drain connected to a reference ground, the input node, and a low-side internal node, respectively; a second NMOS transistor having a source, a gate, and a drain connected to the low-side internal node, the input node, and the output node, respectively; a third NMOS transistor having a source, a gate, and a drain connected to the low-side internal node, the second voltage, and the output node, respectively; a first forward-connected variable capacitor having a positive terminal and a negative terminal connected to the first voltage and the input node, respectively; a second forward-connected variable capacitor having a positive terminal and a negative terminal connected to the first voltage and the output node, respectively; a first reverse-connected variable capacitor having a positive terminal and a negative terminal connected to the input node and the second voltage, respectively; and a second reverse-connected variable capacitor having a positive terminal and a negative terminal connected to the output node and the second voltage, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 FIG. 1 is a schematic diagram of a voltage-controlled inverter according to one embodiment of the present disclosure.

[0011] Figure 2A FIG. 2 is a schematic diagram of a voltage-controlled delay buffer according to a first embodiment of the present disclosure.

[0012] Figure 2B FIG. 3 is a schematic diagram of a voltage-controlled delay buffer according to a second embodiment of the present disclosure.

[0013] LEGEND

[0014] 100: voltage-controlled inverter

[0015] 101: input node

[0016] 102: output node

[0017] 103: low-side internal node

[0018] 104: high-side internal node

[0019] MP1-3, MN1-3: MOS transistors

[0020] CP1-2, CN1-2: variable capacitances

[0021] VI: input signal

[0022] VO: output signal

[0023] VC+, VC-: voltages

[0024] VDD: power supply node

[0025] 200A: voltage-controlled delay buffer

[0026] 211, 212: voltage-controlled inverters

[0027] 200B: voltage-controlled delay buffer

[0028] 221: voltage-controlled inverter

[0029] 222: inverter DETAILED DESCRIPTION

[0030] The present disclosure relates to voltage-controlled delay buffers. While the specification describes particular embodiments of the present disclosure, and what is described is presently considered to be a preferred way of implementing the application. It is understood, however, that the application can be carried out in various ways and is not limited to the particular examples described below, or to the particular ways of implementing the examples described. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.

[0031] Persons skilled in the art will understand the terminology and underlying concepts used herein in connection with microelectronics, such as "voltage", "signal", "inverter", "circuit node", "reference ground", "power supply node", "metal oxide semiconductor (MOS) transistor", "complementary metal oxide semiconductor (CMOS) technology", "n-channel metal oxide semiconductor (NMOS) transistor", "p-channel metal oxide semiconductor (PMOS) transistor". Such terminology is used in the context of microelectronics, and the relevant concepts will be apparent to persons skilled in the art, and are therefore not explained in detail herein.

[0032] Without further explanation, units such as femto-Farad (fF), micrometer (pm), and the like are understood by those skilled in the art.

[0033] Without further explanation, one skilled in the art can read a circuit schematic containing capacitors, NMOS transistors, and PMOS transistors. One skilled in the art can also recognize the symbols for a reference ground, a capacitor, a varactor or variable capacitor, and the symbols for a PMOS transistor and an NMOS transistor, and can recognize the "source terminal," the "gate terminal," and the "drain terminal" of a PMOS transistor and an NMOS transistor. For brevity in the description, the "source terminal" is referred to as the "source," the "gate terminal" is referred to as the "gate," and the "drain terminal" is referred to as the "drain" for MOS transistors.

[0034] A circuit is a collection of at least one transistor, at least one capacitor, at least one resistor, and / or at least one other electronic device, and they are connected to each other in some manner to achieve a certain function.

[0035] In this document, a "circuit node" is often simply referred to as a "node" when it is clear from the context that the meaning of "node" is "circuit node."

[0036] A signal is a time-varying voltage that carries some information. The level of a signal at a certain time point represents the state of the signal at that time point.

[0037] A differential signal is a signal that contains a first sub-signal and a second sub-signal, and the two sub-signals are distinguished by the "+" and "-" appended to the suffix subscript, respectively. The value of the differential signal is represented by the difference between the two sub-signals. The average value between the first sub-signal and the second sub-signal is referred to as the "common mode" value of the differential signal.

[0038] A logic signal is a voltage signal that has two states: a low state and a high state. The low state is also referred to as the "0" state. The high state is also referred to as the "1" state. With respect to logic signal Q, when it is described that logic signal Q is "high" ("high level") or "low" ("low level"), it means that logic signal Q is in the high state; or logic signal Q is in the low state. Similarly, when it is described that logic signal Q is "1" or "0", it means that logic signal Q is in the "1" state; or logic signal Q is in the "0" state.

[0039] A rising edge occurs when a logic signal transitions from low to high. A falling edge occurs when a logic signal transitions from high to low.

[0040] A first logic signal is said to be logically inverted from a second logic signal if the first logic signal and the second logic signal are always in opposite states. That is, when the first logic signal is "1", the second logic signal is "0"; when the first logic signal is "0", the second logic signal is "1". When the first logic signal is logically inverted from the second logic signal, the first logic signal is said to be complementary to the second logic signal.

[0041] In the present disclosure, a variable capacitance is a two-terminal circuit element with an anode terminal marked with "+" and a cathode terminal marked with "-". When the voltage of the anode terminal rises (falls), the capacitance value of the variable capacitance increases (decreases), and when the voltage of the cathode terminal rises (falls), the capacitance value of the variable capacitance decreases (increases). When the anode terminal is connected to a control voltage used to control the adjustable capacitance, the variable capacitance is said to be forward connected. When the cathode terminal is connected to a control voltage used to control the adjustable capacitance, the variable capacitance is said to be backward connected.

[0042] A logic signal is said to be inverted when the logic signal is logically inverted from another logic signal. A logic signal is said to be inverted when the logic signal is logically inverted from another logic signal. A logic signal is said to be inverted when the logic signal is logically inverted from another logic signal.

[0043] A pull-up of a logic signal occurs when a PMOS transistor is turned on to connect the logic signal to a power supply node. A pull-down of a logic signal occurs when an NMOS transistor is turned on to connect the logic signal to a reference ground node.

[0044] In the present disclosure, a variable delay circuit is a circuit that receives an input signal and outputs an output signal, where both the input signal and the output signal are logic signals. Thus, the waveform of the output signal is nearly identical to the waveform of the input signal, with the difference being that the waveform of the output signal has a time delay, which is variable and controlled by a control signal.

[0045] The core circuit in the present disclosure is a voltage-controlled inverter. Figure 1A schematic diagram of a voltage-controlled inverter 100 according to an embodiment of the present disclosure is shown. The voltage-controlled inverter 100 is referred to as "inverter 100" hereinafter. The inverter 100 is configured to receive an input signal VI from a preceding circuit through an input node 101, and to send an output signal VO to a succeeding circuit through an output node 102. The output signal VO has a delay controlled by a control signal, and the control signal VC includes two voltages in the embodiment of a differential signal. The voltages include a first voltage VC+ and a second voltage VC-. The voltage-controlled inverter 100 includes three PMOS transistors including a first PMOS transistor MP1, a second PMOS transistor MP2, and a third PMOS transistor MP3, three NMOS transistors including a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3, and four variable capacitors including a first forward-connected variable capacitor CP1, a second forward-connected variable capacitor CP2, a first reverse-connected variable capacitor CN1, and a second reverse-connected variable capacitor CN2. In this document, "VDD" represents a power supply node. For the sake of simplicity of the description, the PMOS transistors MP1-MP3 are referred to as MP1-MP3 hereinafter, the NMOS transistors MN1-MN3 are referred to as MN1-MN3 hereinafter, the first forward-connected variable capacitor CP1 and the second forward-connected variable capacitor CP2 are referred to as CP1 and CP2, respectively, hereinafter, the first reverse-connected variable capacitor CN1 and the second reverse-connected variable capacitor CN2 are referred to as CN1 and CN2, respectively, hereinafter, the input signal VI is referred to as VI hereinafter, the output signal VO is referred to as VO hereinafter, and the first voltage VC+ and the second voltage VC- are referred to as VC+ and VC-, respectively, hereinafter.

[0046] The source, gate, and drain of MN1 are connected to a reference ground, the input node 101, and a low-side internal node 103, respectively. The source, gate, and drain of MN2 are connected to the low-side internal node 103, the input node 101, and the output node 102, respectively. The source, gate, and drain of MN3 are connected to the low-side internal node 103, VC-, and the output node 102, respectively. The source, gate, and drain of MP1 are connected to the power supply node VDD, the input node 101, and a high-side internal node 104, respectively. The source, gate, and drain of MP2 are connected to the high-side internal node 104, the input node 101, and the output node 102, respectively. The source, gate, and drain of MP3 are connected to the high-side internal node 104, VC+, and the output node 102, respectively. The anode and cathode of CN1 are connected to the input node 101 and VC-, respectively. The anode and cathode of CN2 are connected to the output node 102 and VC-, respectively. The anode and cathode of CP1 are connected to VC+ and the input node 101, respectively. The anode and cathode of CP2 are connected to VC+ and the output node 102, respectively.

[0047] In embodiments of the differential signal, VC+ and VC- together implement the control signal VC, such that when VC+ rises (falls) by an amount, VC- will fall (rise) by the same amount. Thus, the average value between VC+ and VC- (i.e., the "common-mode" value) remains constant. In an embodiment, the average value between VC+ and VC- (i.e., the "common-mode" value of the control signal VC) is equal to one-half of the voltage of the power supply node VDD.

[0048] VI is a logic signal. When VI is at a low level, VI is pulled down to the potential of the reference ground by a predriver that generates VI. When VI is at a high level, VI is pulled up to the potential of the power supply node VDD by a predriver that generates VI. MN1, MN2, MP1, and MP2 form an inverter. The inverter is used to receive VI and output VO, such that VO is the logical inversion of VI. When VI is at a low level, MP1 enables the pull-up of VO; when VI is at a low level, MP2 enforces the pull-up; and MP3 assists the pull-up according to VC+. On the other hand, when VI is at a high level, MN1 enables the pull-down of VO; when VI is at a high level, MN2 enforces the pull-down; and MN3 assists the pull-down according to VC-. Consider the initial condition, where the initial condition is that VI is at a low level and VO is at a high level. When VI transitions from low to high, MP1, MP2, and MP3 are turned off, while MN1 and MN2 are turned on to pull down VO to the potential of the reference ground with the assistance provided by MN3, such that VO transitions from high to low. When VC- is lowered (raised), the assistance from MN3 will fade (increase), causing the transition of VO from high to low to be slower (faster). When VI transitions from high to low, MN1, MN2, and MN3 are turned off, while MP1 and MP2 are turned on to pull up VO to the potential of the power supply node VDD with the assistance provided by MP3, such that VO transitions from low to high. When VC+ is raised (lowered), the assistance from MP3 will fade (increase), causing the transition of VO from low to high to be slower (faster).

[0049] Furthermore, CP1 and CN1 are used as shunt capacitors at the input node 101, whose capacitance values are controlled by VC+ and VC-. CP2 and CN2 are used as shunt capacitors at the output node 102, whose capacitance values are controlled by VC+ and VC-. When VC+ is raised (lowered) and VC- is lowered (raised) accordingly, the capacitance values of CP1 and CN1 are both increased (decreased), causing the low-to-high transition and the high-to-low transition of VI driven by the preceding circuit to be both slowed (speeded up). Meanwhile, the capacitance values of CP2 and CN2 are both increased (decreased), causing the low-to-high transition and the high-to-low transition of VO sent to the succeeding circuit to be both slowed (speeded up). In short, for both VI and VO, when VC+ is raised (lowered) and VC- is lowered (raised) accordingly, the low-to-high transition and the high-to-low transition are both slowed (speeded up), causing the delay of the voltage-controlled inverter 100 to be lengthened (shortened).

[0050] For example, but not limited to, the voltage-controlled inverter 100 is fabricated on a silicon substrate using a 55 nanometer (nm) CMOS process technology; the voltage of the power supply node VDD is 1.2 volts (V); the "W / L" (which stands for width / length) of MN1 is 32 μm / 120 nm; the "W / L" of MN2 is 6 μm / 150 nm; the "W / L" of MN3 is 96 μm / 150 nm; the "W / L" of MP1 is 64 μm / 120 nm; the "W / L" of MP2 is 12 μm / 150 nm; the "W / L" of MP3 is 192 μm / 150 nm; and CP1, CP2, CN1 and CN2 are all "N-well varactors" with "W / L" of 3 μm / 1 μm, which can provide a variable capacitance between 6 fF and 30 fF.

[0051] The voltage-controlled inverter 100 has many advantages. First, the variable delay is controlled by the driving capability of two MOS transistors MP3 and MN3 and the capacitance values ​​of four variable capacitors CP1, CP2, CN1, and CN2. Therefore, since both control methods are used simultaneously, the tuning range can be very wide. Second, there are no interface problems when the preamplifier and subsequent circuits use the same power supply voltage (the voltage of the power node VDD), because VI and VO are both logic signals, with a low state of 0V and a high state of the power node VDD. Third, regardless of the value of the control signal VC, when VI transitions from low to high, the NMOS transistor MN2 is always turned on to provide driving force to pull down VO, and when VI transitions from high to low, the PMOS transistor MP2 is always turned on to provide driving force to pull up VO. Therefore, extreme cases, such as extremely low driving capability, which are easily affected by the noise of the voltage-controlled inverter 100, can be avoided. Fourthly, the control of the two MOS transistors MP3 and MN3, and the control of the four variable capacitors CP1, CP2, CN2, and CN2, all share the same common-mode voltage, which is half the voltage of the power supply node VDD. Therefore, VI and VO can have symmetrical responses in both low-to-high and high-to-low transitions. In other words, the voltage-controlled inverter 100 is inherently balanced and can have a symmetrical response.

[0052] The voltage-controlled inverter 100 can be used to construct a voltage-controlled delay buffer. In, for example... Figure 2A In the first embodiment shown, the voltage-controlled delay buffer 200A includes a first voltage-controlled inverter 211 and a second voltage-controlled inverter 212. The first voltage-controlled inverter 211 and the second voltage-controlled inverter 212 are configured in a cascade topology to receive an input signal from the source circuit and to output an output signal to the load circuit according to a control signal VC. In the differential signal embodiment, the control signal VC includes two voltages, VC+ and VC-. These two voltage-controlled inverters 211 and 212 are generated by... Figure 1 The voltage-controlled inverter 100 is materialized. Figure 2B In the second embodiment shown, the voltage-controlled delay buffer 200B includes a voltage-controlled inverter 221 and an inverter 222. The voltage-controlled inverters 221 and 222 are configured in a cascaded structure to receive an input signal from the source circuit and to output an output signal to the load circuit according to a control signal VC. In the differential signal embodiment, the control signal VC includes two voltages, VC+ and VC-. The voltage-controlled inverter 221 is...Figure 1 The voltage controlled inverter 100 is embodied as a NOR gate, while the inverter 222 can be implemented from any inverter circuit known from the prior art, depending on the requirements of the circuit designer.

[0053] Several voltage controlled delay buffers can be configured in a cascaded structure to implement a single voltage controlled delay buffer, as will be apparent to the skilled person, and will therefore not be explained in detail here.

[0054] Those skilled in the art will readily observe that numerous modifications and changes in the devices and methods can be made without departing from the teachings of the present disclosure. Accordingly, the above disclosure is not to be construed as being limited only to the embodiments specifically set forth herein.

Claims

1. A voltage-controlled inverter, comprising: a first P-type metal-oxide-semiconductor transistor to enable a pull-up of an output signal at an output node in response to an input signal at an input node; a second P-type metal-oxide-semiconductor transistor to perform the pull-up in response to the input signal; a third P-type metal-oxide-semiconductor transistor to assist the pull-up in response to a first voltage; a first N-type metal-oxide-semiconductor transistor to enable a pull-down of the output signal in response to the input signal; a second N-type metal-oxide-semiconductor transistor to perform the pull-down in response to the input signal; a third N-type metal-oxide-semiconductor transistor to assist the pull-down in response to a second voltage; a first forward-connected variable capacitor and a first reverse-connected variable capacitor controlled by the first voltage and the second voltage, respectively, and to provide a shunt capacitance at the input node; and a second forward-connected variable capacitor and a second reverse-connected variable capacitor controlled by the first voltage and the second voltage, respectively, and to provide a shunt capacitance at the output node.

2. The voltage-controlled inverter of claim 1, wherein the input signal is a logic signal.

3. The voltage-controlled inverter of claim 2, wherein the second voltage decreases when the first voltage increases, and the second voltage increases when the first voltage decreases.

4. The voltage-controlled inverter of claim 3, wherein an average of the first voltage and the second voltage remains constant when a value of the first voltage changes.

5. The voltage-controlled inverter of claim 4, wherein the average is equal to half of a supply voltage of the voltage-controlled inverter. The control signal comprises a first voltage and a second voltage, the voltage-controlled inverter comprising:

6. A voltage-controlled delay buffer, comprising a plurality of inverters configured in a cascade structure, the inverters configured to receive an input signal from a source circuit and to output an output signal to a load circuit, the inverters comprising a voltage-controlled inverter configured to receive an input signal from a preceding circuit and to output an output signal to a succeeding circuit in response to a control signal, wherein, a first P-type metal-oxide-semiconductor transistor to enable a pull-up of an output signal in response to an input signal; a second P-type metal-oxide-semiconductor transistor to perform the pull-up in response to the input signal; a third P-type metal-oxide-semiconductor transistor to assist the pull-up in response to the first voltage; a first N-type metal-oxide-semiconductor transistor to enable a pull-down of the output signal in response to the input signal; a second N-type metal-oxide-semiconductor transistor to perform the pull-down in response to the input signal; a third N-type metal-oxide-semiconductor transistor to assist the pull-down in response to the second voltage; a first forward-connected variable capacitor and a first reverse-connected variable capacitor controlled by the first voltage and the second voltage, respectively, and to provide a shunt capacitance at an input node; and a second forward-connected variable capacitor and a second reverse-connected variable capacitor controlled by the first voltage and the second voltage, respectively, and to provide a shunt capacitance at an output node. ​ a second forward connected variable capacitor and a second reverse connected variable capacitor controlled by the first voltage and the second voltage, respectively, and the first forward connected variable capacitor and the first reverse connected variable capacitor are used to provide a parallel capacitance at an output node.

7. The voltage controlled delay buffer of claim 6, wherein the input signal is a logic signal.

8. The voltage controlled delay buffer of claim 7, wherein the second voltage decreases when the first voltage increases, and the second voltage increases when the first voltage decreases.

9. The voltage controlled delay buffer of claim 8, wherein the average of the first voltage and the second voltage remains constant when the value of the first voltage changes.

10. A voltage controlled delay buffer, comprising a plurality of inverters configured in a cascade structure, the inverters configured to receive an input signal from a source circuit and to output an output signal to a load circuit, the inverters comprising a voltage controlled inverter, the voltage controlled inverter controlled by a control signal, wherein, The control signal includes a first voltage and a second voltage, and the voltage controlled inverter includes: a first P-type metal oxide semiconductor transistor having a source, a gate and a drain connected to a power node, an input node and a high-side internal node, respectively; a second P-type metal oxide semiconductor transistor having a source, a gate and a drain connected to the high-side internal node, the input node and an output node, respectively; a third P-type metal oxide semiconductor transistor having a source, a gate and a drain connected to the high-side internal node, the first voltage and the output node, respectively; a first N-type metal oxide semiconductor transistor having a source, a gate and a drain connected to a reference ground, the input node and a low-side internal node, respectively; a second N-type metal oxide semiconductor transistor having a source, a gate and a drain connected to the low-side internal node, the input node and the output node, respectively; a third N-type metal oxide semiconductor transistor having a source, a gate and a drain connected to the low-side internal node, the second voltage and the output node, respectively; a first forward connected variable capacitor having a positive terminal and a negative terminal connected to the first voltage and the input node, respectively; a second forward connected variable capacitor having a positive terminal and a negative terminal connected to the first voltage and the output node, respectively; a first reverse connected variable capacitor having a positive terminal and a negative terminal connected to the input node and the second voltage, respectively; and a second reverse connected variable capacitor having a positive terminal and a negative terminal connected to the output node and the second voltage, respectively.

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