Clock phasing method, clock phasing circuit and multi-phase switching circuit

Abstract

The application discloses a clock phase separation method, a clock phase separation circuit and a multi-phase switching circuit. A high-frequency clock signal is output according to the comparison result of a first slope signal and a reference voltage, wherein the first slope signal is reset according to the high-frequency clock signal and a standard clock signal; the high-frequency clock signal is frequency-divided to generate a 2nd to (n+1)th phase clock signal; and the size of the reference voltage or the slope of the first slope signal is adjusted according to the (n+1)th phase clock signal and the standard clock signal, so that in a stable state, the absolute value of the phase difference between the (n+1)th phase clock signal and the standard clock signal is less than a preset value, wherein n is an integer greater than or equal to 2. The circuit structure of the clock phase separation circuit is simple, and when the size of the reference voltage is adjusted according to the (n+1)th phase clock signal and the standard clock signal, when n is an integer greater than or equal to 3, the phase difference consistency of the standard clock signal and the 2nd to n-th phase clock signals is good, and the phase separation precision is high.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, specifically to a clock phase splitting method, a clock phase splitting circuit, and a multi-phase switching circuit. Background Technology

[0002] One existing clock phase-splitting method involves counting pulses of a high-frequency clock signal within a standard clock signal cycle, calculating the standard clock signal cycle based on the number of high-frequency clock signal pulses, and then performing phase-splitting based on the calculated standard clock signal cycle and a set number of phases. In this method, the phase-splitting accuracy is affected by the accuracy of the high-frequency clock signal. To obtain a high-precision clock phase-splitting circuit, the accuracy of the high-frequency clock signal needs to be improved, requiring a high-frequency, high-precision clock generation circuit. This results in a complex circuit structure and high design costs. Furthermore, even with a high-precision high-frequency clock signal, counting the pulses within a standard clock signal cycle can easily lead to errors between the two maximum high-frequency clock signal pulses, making it difficult to achieve high phase-splitting accuracy. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a clock phase splitting method, a clock phase splitting circuit, and a multi-phase switching circuit to solve the technical problems of poor phase splitting accuracy and complex circuit structure in the prior art.

[0004] The technical solution of the present invention is to provide a clock phase splitting method for generating the second to nth phase clock signals based on a standard clock signal, wherein the phase splitting method includes:

[0005] A high-frequency clock signal is output based on the comparison result between the first ramp signal and the reference voltage, wherein the first ramp signal is reset based on the high-frequency clock signal and the standard clock signal;

[0006] The high-frequency clock signal is divided to generate the second to (n+1)th phase clock signals;

[0007] The magnitude of the reference voltage or the slope of the first ramp signal is adjusted according to the (n+1)th phase clock signal and the standard clock signal, so that in a stable state, the absolute value of the phase difference between the (n+1)th phase clock signal and the standard clock signal is less than a preset value.

[0008] Where n is an integer greater than or equal to 2.

[0009] Optionally, when adjusting the magnitude of the reference voltage according to the (n+1)th phase clock signal and the standard clock signal, when n is an integer greater than or equal to 3, in a steady state, the phase difference between the standard clock signal and the second phase clock signal is equal to the phase difference between the m-th phase clock signal and the (m+1)th phase clock signal.

[0010] Where m is any integer from 2 to (n-1).

[0011] Optionally, the first ramp signal is reset based on the rising edge of the high-frequency clock signal and the rising edge of the standard clock signal.

[0012] Optionally, the slope of the first ramp signal is related to n.

[0013] Optionally, when adjusting the magnitude of the reference voltage according to the (n+1)th phase clock signal and the standard clock signal, the slope of the first ramp signal is proportional to n.

[0014] Optionally, the magnitude of the reference voltage or the slope of the first ramp signal can be adjusted based on the standard clock signal and the phase difference between the (n+1)th phase clock signal and the standard clock signal.

[0015] Optionally, when n is a fixed integer, the first ramp signal has a fixed slope, and controls the reference voltage to decrease by a fixed value in each period of the standard clock signal;

[0016] When the phase of the (n+1)th phase clock signal leads the phase of the standard clock signal, the reference voltage is increased based on the phase difference between the two.

[0017] Optionally, when n is a fixed integer, the first ramp signal has a fixed slope, and the reference voltage is increased by a fixed value in each period of the standard clock signal.

[0018] When the phase of the (n+1)th phase clock signal lags behind the phase of the standard clock signal, the reference voltage is controlled to decrease based on the phase difference between the two.

[0019] Optionally, the magnitude of the reference voltage or the slope of the first ramp signal can be adjusted based on the phase difference between the (n+1)th phase clock signal and the standard clock signal.

[0020] Optionally, when n is a fixed integer, the first ramp signal has a fixed slope.

[0021] When the phase of the (n+1)th phase clock signal leads the phase of the standard clock signal, the reference voltage is increased according to the phase difference between the two.

[0022] When the phase of the (n+1)th phase clock signal lags behind the phase of the standard clock signal, the reference voltage is controlled to decrease based on the phase difference between the two.

[0023] Optionally, the method of dividing the high-frequency clock signal to generate the second to (n+1) phase clock signals includes:

[0024] A counter is used to count according to the high-frequency clock signal and to reset according to the standard clock signal to output a counting signal;

[0025] The counting signals are logically combined to generate the second to (n+1) phase clock signals.

[0026] Optionally, the method of dividing the high-frequency clock signal to generate the second to (n+1) phase clock signals includes:

[0027] A counter is used to count according to the high-frequency clock signal and to reset according to the standard clock signal to output a counting signal;

[0028] The counting signals are logically combined to generate the second to nth phase clock signals;

[0029] The (n+1)th phase clock signal is generated based on the comparison result between the second ramp signal and the reference voltage, wherein the slope of the second ramp signal is equal to the slope of the first ramp signal, and the second ramp signal is reset according to the nth phase clock signal.

[0030] The present invention also provides a clock phase splitting circuit that generates the second to nth phase clock signals according to a standard clock signal, the clock phase splitting circuit comprising:

[0031] A high-frequency clock generation circuit outputs a high-frequency clock signal based on the comparison result of a first ramp signal and a reference voltage, wherein the first ramp signal is reset based on the high-frequency clock signal and the standard clock signal;

[0032] The frequency divider circuit divides the high-frequency clock signal to generate the 2nd to (n+1)th phase clock signals;

[0033] The phase correction circuit adjusts the magnitude of the reference voltage or the slope of the first ramp signal according to the (n+1)th phase clock signal and the standard clock signal, so that after the clock phase splitting circuit stabilizes, the absolute value of the phase difference between the (n+1)th phase clock signal and the standard clock signal is less than a preset value.

[0034] Where n is an integer greater than or equal to 2.

[0035] Optionally, the phase correction circuit adjusts the magnitude of the reference voltage according to the (n+1)th phase clock signal and the standard clock signal. When n is an integer greater than or equal to 3, after the clock phase splitting circuit stabilizes,

[0036] The phase difference between the standard clock signal and the second phase clock signal is equal to the phase difference between the m-th phase clock signal and the (m+1)-th phase clock signal.

[0037] Where m is any integer from 2 to (n-1).

[0038] Optionally, the phase correction circuit includes:

[0039] The second circuit receives the (n+1)th phase clock signal and the standard clock signal to output a judgment signal;

[0040] The adjustment circuit adjusts the magnitude of the reference voltage or the slope of the first ramp signal according to the judgment signal.

[0041] Optionally, the judgment signal includes a first judgment signal and a second judgment signal, and the second circuit includes:

[0042] The first phase detector circuit is configured to receive the (n+1)th phase clock signal and the standard clock signal, and output the first judgment signal based on the phase difference between the two when the phase of the (n+1)th phase clock signal leads the phase of the standard clock signal.

[0043] The first pulse generation circuit is configured to receive the standard clock signal and output the second judgment signal according to the standard clock signal.

[0044] Optionally, the judgment signal includes a first judgment signal and a second judgment signal, and the second circuit includes:

[0045] The second pulse generation circuit is configured to receive the standard clock signal and output the first judgment signal according to the standard clock signal;

[0046] The second phase detector circuit is configured to receive the (n+1)th phase clock signal and the standard clock signal, and output the second judgment signal based on the phase difference between the (n+1)th phase clock signal and the standard clock signal when the phase of the (n+1)th phase clock signal lags behind the phase of the standard clock signal.

[0047] Optionally, the judgment signal includes a first judgment signal and a second judgment signal, and the second circuit includes:

[0048] The third phase detector circuit is configured to receive the (n+1)th phase clock signal and the standard clock signal, output the first judgment signal based on the phase difference between the two when the phase of the (n+1)th phase clock signal leads the phase of the standard clock signal, and output the second judgment signal based on the phase difference between the two when the phase of the (n+1)th phase clock signal lags the phase of the standard clock signal.

[0049] Optionally, when n is a fixed integer, the first ramp signal has a fixed slope;

[0050] The adjustment circuit controls the reference voltage to increase according to the first judgment signal and controls the reference voltage to decrease according to the second judgment signal.

[0051] Optionally, the reference voltage is a fixed voltage;

[0052] The adjustment circuit controls the slope of the first ramp signal to decrease according to the first judgment signal, and controls the slope of the first ramp signal to increase according to the second judgment signal.

[0053] Optionally, the frequency divider circuit includes:

[0054] The counter receives the high-frequency clock signal and the standard clock signal, counts according to the high-frequency clock signal, and resets according to the standard clock signal to output a count signal;

[0055] The first clock distribution circuit performs logical combination on the counting signals to generate the second to (n+1) phase clock signals.

[0056] Optionally, the frequency divider circuit includes:

[0057] The counter receives the high-frequency clock signal and the standard clock signal, counts according to the high-frequency clock signal, and resets according to the standard clock signal to output a count signal;

[0058] The second clock distribution circuit performs logical combination on the counting signals to generate the second to nth phase clock signals;

[0059] The (n+1)th phase clock generation circuit generates the (n+1)th phase clock signal based on the comparison result of the second ramp signal and the reference voltage, wherein the slope of the second ramp signal is equal to the slope of the first ramp signal, and the second ramp signal is reset according to the nth phase clock signal.

[0060] The present invention also provides a multiphase switching circuit, which includes n switching circuits and the clock phase splitting circuit.

[0061] The standard clock signal and the second to nth phase clock signals generated by the clock phase splitting circuit are respectively used as clock signals for the n switching circuits.

[0062] Compared with the prior art, the present invention has the following advantages: The present invention outputs a high-frequency clock signal based on the comparison result of the first ramp signal and the reference voltage; and divides the high-frequency clock signal to generate the 2nd to (n+1)th phase clock signals; the magnitude of the reference voltage or the slope of the first ramp signal can be adjusted according to the standard clock signal and the phase difference between the (n+1)th phase clock signal and the standard clock signal, or according to the phase difference between the (n+1)th phase clock signal and the standard clock signal, so that after the clock phase splitting circuit stabilizes, the phase between the (n+1)th phase clock signal and the standard clock signal is less than a preset value; when adjusting the magnitude of the reference voltage according to the (n+1)th phase clock signal and the standard clock signal, when n is an integer greater than or equal to 3, the phase difference between the standard clock signal and the 2nd phase clock signal and the phase difference between the mth phase clock signal and the (m+1)th phase clock signal are equal, where m is any integer from 2 to (n-1). The clock phase splitting circuit of the present invention has a simple circuit structure and high phase splitting accuracy. Attached Figure Description

[0063] Figure 1 This is a schematic diagram of the circuit structure of the clock phase splitting circuit according to an embodiment of the present invention;

[0064] Figure 2 This is a schematic diagram of the clock phase splitting circuit according to the first embodiment of the present invention;

[0065] Figure 3 According to Figure 3 A schematic diagram of the waveform after the clock phase splitter circuit has stabilized;

[0066] Figure 4 This is a schematic diagram of the clock phase splitting circuit according to the second embodiment of the present invention;

[0067] Figure 5 According to Figure 4 A schematic diagram of the circuit structure of another embodiment of the second circuit;

[0068] Figure 6 According to Figure 5 A schematic diagram of the waveform after the clock phase splitter circuit has stabilized;

[0069] Figure 7 According to Figure 4 A circuit structure diagram of another embodiment of the second circuit;

[0070] Figure 8 This is a schematic diagram of the clock phase splitting circuit according to the third embodiment of the present invention. Detailed Implementation

[0071] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of the present invention.

[0072] To provide the public with a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the invention, but those skilled in the art can fully understand the invention without these details.

[0073] The invention is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the drawings are in a simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0074] like Figure 1As shown, the clock phase-splitting circuit of this embodiment includes a high-frequency clock generation circuit 10, a frequency divider circuit 20, and a phase correction circuit 30. The high-frequency clock generation circuit 10 outputs a high-frequency clock signal clkH based on the comparison result of the first ramp signal and the reference voltage. The first ramp signal is reset based on the high-frequency clock signal clkH and the clock signal clk1. The frequency divider circuit 20 divides the high-frequency clkH clock signal to generate the second to (n+1) phase clock signals clk2, clk3...clkn+1, where n is an integer greater than or equal to 2. The phase correction circuit 30 adjusts the magnitude of the reference voltage or the slope of the first ramp signal based on the (n+1) phase clock signal clkn+1 and the standard clock signal clk1. This allows the circuit to adjust the time from the reset of the first ramp signal to the reaching of the reference voltage Vref, and thus adjust the period of the high-frequency clock clkH to correct the phase of the second to (n+1) phase clock signals clk2, clk3...clkn+1. This ensures that after the clock phase divider circuit stabilizes, the absolute value of the phase difference between the (n+1) phase clock signal clkn+1 and the standard clock signal clk1 is less than a preset value. In one implementation, the first ramp signal can be reset based on the rising edge of the high-frequency clock signal clkH and the rising edge of the standard clock signal clk1. Specifically, it can be reset once when the rising edge of the high-frequency clock signal clkH arrives or when the rising edge of the standard clock signal clk1 arrives. In one implementation, the high-frequency clock generation circuit 10 also receives a control signal representing the number of phases n, and controls the slope of the first ramp signal according to the control signal, thereby controlling the frequency of the high-frequency clock clkH to be related to n, so that the frequency of the second to nth phase clock signals clk2, clk3...clkn can be quickly locked when the number of phases n changes. For example, in a multi-phase switching circuit including n switching circuits and the clock phase splitting circuit, the standard clock signal clk1 and the second to nth phase clock signals clk2, clk3...clkn generated by the clock phase splitting circuit can be used as the clock signals of the n switching circuits respectively.

[0075] refer to Figure 2 In the clock phase-splitting circuit of the first embodiment of the present invention, the high-frequency clock generation circuit 10 includes a first ramp signal generation circuit 101 and a first comparison circuit U02. The first ramp signal generation circuit 101 generates a first ramp signal Vramp1, and the first comparison circuit U02 compares the first ramp signal Vramp1 with a reference voltage Vref to output a high-frequency clock signal clkH. For example, the first ramp signal generation circuit 101 includes a first controlled current source U01, a first capacitor C01, a first switch K01, and a first circuit 1011, wherein the first controlled current source U01 receives a control signal characterizing the phase number n and a second current I2 to output the first controlled current I1, wherein the second current I2 may be generated by a reference source (…). Figure 2 The current generated (not shown) has a fixed current value. The current value of the first controlled current I1 is proportional to n and proportional to the current value of the second current I2. For ease of understanding, in Figure 2 The value of the first controlled current is represented as n·I2. In other embodiments, the value of the first controlled current can also be k·n·I2, where k is any positive number. The first terminal of the first capacitor C01 is connected to the first controlled current source U01, and the second terminal is grounded. The first switch K01 is connected in parallel with the first capacitor C01. The control terminal of the first switch K01 receives the output signal of the first circuit 1011, and the first terminal of the first capacitor C01 outputs a first ramp signal Vramp1. During the period when the first switch K01 is off, the first controlled current I1 charges the first capacitor C01, and during this period, the first ramp signal Vramp1 is generated. amp1 rises at a slope proportional to the first controlled current I1. In one embodiment, the first circuit 1011 can be configured to receive a high-frequency clock signal clkH and a standard clock signal clk1, and generate a narrow pulse at the rising edge of either the high-frequency clock signal clkH or the standard clock signal clk1, thereby controlling the first switch K01 to conduct briefly at each rising edge of the high-frequency clock signal clkH and each rising edge of the standard clock signal clk1. Correspondingly, each time the first switch K01 conducts, the first ramp signal Vramp1 is reset once. The first input terminal of the first comparison circuit U02 receives the first ramp signal Vramp1, and the second input terminal receives a reference voltage Vref, and compares the two to output the high-frequency clock signal clkH. In this embodiment, when the ramp signal Vramp reaches the reference voltage Vref, the high-frequency clock signal clkH level jumps to an active level, and the waveforms of the first ramp signal Vramp1 and the high-frequency clock signal clkH can be compared with the reference voltage Vref. Figure 3 .

[0076] Please continue to refer to this. Figure 2 The frequency divider circuit 20 in Embodiment 1 includes a counter 201 and a multi-phase clock generation circuit 202. The counter 201 receives a high-frequency clock signal clkH and a standard clock signal clk1, counts according to the high-frequency clock signal clkH, and resets according to the standard clock signal clk1 to output a counting signal. For example, in one embodiment, the counter 201 can be configured to increment the counting signal by 1 whenever the high-frequency clock signal clkH reaches an effective level, and reset the counting signal whenever the standard clock signal clk1 reaches an effective level. The multi-phase clock generation circuit 202 includes a first clock distribution circuit 2021, which performs logical combination on the counting signal and obtains the second to (n+1) phase clock signals clk2, clk3…clkn+1 based on the logical combination result.

[0077] Please refer to this again. Figure 2The phase correction circuit 30 in Embodiment 1 includes a second circuit 301 and an adjustment circuit 302. The second circuit 301 receives a standard clock signal clk1 and an (n+1)th phase clock signal clkn+1, and outputs a judgment signal based on the standard clock signal clk1 and the phase difference between the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1. The adjustment circuit 302 adjusts the magnitude of the reference voltage Vref based on the judgment signal. For example, the second circuit 301 includes a first phase detection circuit 3011 and a first pulse generation circuit 3012. The first phase detection circuit 3011 can be configured to receive the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1, and output a first judgment signal INC based on the phase difference between the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1 when the phase of the (n+1)th phase clock signal clkn+1 leads the phase of the standard clock signal clk1. Further, in one embodiment, the first phase detector circuit 3011 can be configured to control the first judgment signal INC to be valid during the time period when the phase of the (n+1)th phase clock signal clkn+1 leads the phase of the standard clock signal clk1, otherwise control the first judgment signal INC to be invalid. The first pulse generation circuit 3012 can be configured to receive the standard clock signal clk1 and output the second judgment signal DEC according to the standard clock signal clk1. For example, in one embodiment, the first pulse generation circuit 3012 can be configured to output a pulse with a fixed pulse width at each rising edge of the standard clock signal clk1, that is, the second judgment signal DEC is a pulse signal with a fixed pulse width at the same frequency as the standard clock signal clk1. In another embodiment, the first pulse generation circuit 3012 can also be configured to output a pulse with a fixed pulse width at each falling edge of the standard clock signal clk1. Accordingly, the adjustment circuit 302 controls the reference voltage Vref to increase according to the first judgment signal INC and controls the reference voltage Vref to decrease according to the second judgment signal DEC. For example, the specific circuit of the adjustment circuit 302 includes: a second current source U03, a third current source U04, a second switch K02, a third switch K03, and a second capacitor C02. In one embodiment, the current output by the second current source U03 and the current output by the third current source U04 can be set to be equal or equivalent. The control terminal of the second switch K02 receives a first judgment signal INC, and the control terminal of the third switch K03 receives a second judgment signal DEC. The second current source U03 and the second switch K02 are connected in series to form a first series circuit. The third current source U04 and the third switch K03 are connected in series and then in parallel with the second capacitor C02 to form a second parallel circuit. The first series circuit and the second parallel circuit are connected in series, and the connection point serves as the output terminal of the phase correction circuit 30, outputting a reference voltage Vref.When the first judgment signal INC is valid, the second switch K02 is turned on, and the current output by the second current source U03 charges the second capacitor C02, increasing the reference voltage Vref. When the second judgment signal DEC is valid, the third switch K02 is turned on, and the current output by the third current source U04 discharges the second capacitor C02, decreasing the reference voltage Vref. The second judgment signal DEC has a fixed pulse width, meaning that the reference voltage Vref decreases by a fixed value each time it decreases.

[0078] refer to Figure 3 , Figure 3 Taking n=3 as an example, the waveforms of the first ramp signal Vramp1, the high-frequency clock signal clkH, the standard clock signal clk1, the second-phase clock signal clk2, the third-phase clock signal clk3 (i.e., the nth-phase clock signal clkn), and the fourth-phase clock signal clk4 (i.e., the (n+1)th-phase clock signal clkn+1) are shown after the clock phase-splitting circuit in Embodiment 1 has stabilized. Vref represents the reference voltage mentioned earlier. Figure 3 As can be seen, the first ramp signal Vramp1 is reset once when the rising edge of the high-frequency clock signal clkH or the rising edge of the standard clock signal clk1 arrives. The reference voltage Vref decreases by a fixed value each time the rising edge of the standard clock signal clk1 arrives, and increases during the period when the fourth phase clock signal clk4 leads the phase of the standard clock signal clk1. Understandably, before the clock phase splitting circuit stabilizes, when the phase of the fourth phase clock signal clk4 leads the phase of the standard clock signal clk1 by a relatively large amount, the increase in the reference voltage Vref within one standard clock signal clk1 cycle will be greater than its fixed decrease. Therefore, in the next standard clock signal clk1 cycle, the value of the reference voltage Vref will increase, and the time from the reset of the first ramp signal Vramp1 to reaching the reference voltage Vref will increase. Correspondingly, the phases of the second to fourth phase clock signals will be delayed, thus reducing the phase lead of the fourth phase clock signal clk4 over the standard clock signal clk1. Finally, after the clock phase splitter circuit stabilizes, the phase of the fourth phase clock signal clk4 slightly leads the phase of the standard clock signal clk1. The increase in the reference voltage Vref is equal to the fixed decrease in the reference voltage Vref. By controlling the magnitude of the fixed decrease in the reference voltage Vref, the phase difference between the fourth phase clock signal clk4 and the standard clock signal clk1 can be controlled to be less than a preset value. Furthermore, from... Figure 3It can be seen that since the slope of the first ramp signal Vramp1 is always a fixed value, the phase differences between the standard clock signal clk1 and the second-phase clock signal clk2, the second-phase clock signal clk2 and the third-phase clock signal clk3, and the third-phase clock signal clk3 and the fourth-phase clock signal clk4 are all equal. If the phase difference between the fourth-phase clock signal clk4 and the standard clock signal clk1 is denoted as Δphase, then the phase differences between the standard clock signal clk1 and the second-phase clock signal clk2, the second-phase clock signal clk2 and the third-phase clock signal clk3, and the third-phase clock signal clk3 and the fourth-phase clock signal clk4 are all equal. The phase difference between the third-phase clock signal clk3 and the standard clock signal clk1 is: To achieve better phase splitting, the phase difference Δphase between the fourth-phase clock signal clk4 and the standard clock signal clk1 needs to be kept relatively small. This can be achieved by setting the reference voltage Vref to decrease by a relatively small fixed value within each cycle of the standard clock signal clk1. Furthermore, in one embodiment, this can be achieved by... Figure 2 The output current value of the third current source U04 is designed to be of a reasonable magnitude, and the pulse width of the second judgment signal DEC output by the first pulse generation circuit 3012 is set to be relatively small. For example, the pulse width of the second judgment signal DEC can be set to 1-2 ns. It should be noted that in the illustrations of this paper, the high-frequency clock signal clkH, the standard clock signal clk1, and the clock signals of phases 2 to 4 are all active high, but in other examples they can also be active low.

[0079] In this embodiment, when n is a fixed integer, the current value of the first controlled current I1 is a fixed value, and correspondingly, the first ramp signal Vramp1 has a fixed slope. The phase correction circuit 30 adjusts the magnitude of the reference voltage Vref according to the standard clock signal clk1 and the phase difference between the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1. The specific method for adjusting the magnitude of the reference voltage Vref is as follows: within each period of the standard clock signal clk1, the reference voltage Vref is controlled to decrease by a fixed value; when the phase of the (n+1)th phase clock signal clkn+1 leads the phase of the standard clock signal clk1, the reference voltage Vref is controlled to increase according to the phase difference between the two. After the clock phase splitting circuit stabilizes, the phase of the (n+1)th phase clock signal clkn+1 slightly leads the phase of the standard clock signal clk1. By controlling the fixed value by which the reference voltage Vref decreases each time, the phase difference between the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1 can be controlled to be less than a preset value. Furthermore, after the clock phase splitting circuit stabilizes, the phase difference between the standard clock signal clk1 and the second-phase clock signal clk2 is equal to the phase difference between the m-th phase clock signal clkm and the (m+1)-th phase clock signal clkm+1, where m is any integer from 2 to n. The clock phase splitting circuit in this embodiment has a simple circuit structure and high phase splitting accuracy.

[0080] like Figure 4As shown, the clock phase splitting circuit of the second embodiment of the invention is basically the same as that of the first embodiment, and will not be described again here. The difference is that the multi-phase clock generation circuit 202 of this embodiment includes a second clock distribution circuit 2022 and an (n+1)th phase clock generation circuit 2023. The second clock distribution circuit 2022 performs logical combination on the counting signal output by the counter 201, and obtains the 2nd to nth phase clock signals clk2, clk3...clkn according to the result of the logical combination. The (n+1)th phase clock generation circuit 2023 generates the (n+1)th phase clock signal clkn+1 according to the comparison result of the second ramp signal Vramp2 and the reference voltage Vref. The slope of the second ramp signal Vramp2 is equal to the slope of the first ramp signal Vramp1. The second ramp signal Vramp2 is reset according to the nth phase clock signal clkn. For example, the (n+1)th phase clock generation circuit 2023 includes a third capacitor C03, a fourth switch K04, and a second comparator circuit U05. The fourth switch K04 is connected in parallel with the third capacitor C03. The control terminal of the fourth switch K04 receives the nth phase clock signal clkn. The second terminal of the third capacitor C03 is grounded. During the period when the fourth switch K04 is off, the first terminal of the third capacitor C03 receives a third current I3, which charges the third capacitor C03. The ratio of the current value of the third current I3 to the capacitance value of the third capacitor C03 is equal to the first controlled current in the high-frequency clock generation circuit 10. The ratio of the current value of current I1 to the capacitance value of the first capacitor C01 is equal. In one embodiment, the current value of the third current I3 can be set to be equal to the current value of the first controlled current I1, and the capacitance value of the third capacitor C03 can be set to be equal to the capacitance value of the first capacitor C01, so that during the period when the fourth switch K04 is off, the second ramp signal Vramp2 rises with a slope equal to that of the first ramp signal Vramp1; when the rising edge of the nth phase clock signal clkn arrives, the fourth switch K04 is turned on briefly, and the second ramp signal Vramp2 is reset accordingly. The first input terminal of the second comparator circuit U05 receives the second ramp signal Vramp2, and the second input terminal receives the reference voltage Vref, and compares the two to output the (n+1)th phase clock signal clkn+1. The nth phase clock signal clkn (corresponding to Figure 6 clk3), the second ramp signal Vramp2, and the (n+1)th phase clock signal clkn+1 (corresponding to Figure 6 The waveform of clk4 can be referenced. Figure 6 .

[0081] The working principle of the clock phase-splitting circuit in this embodiment is basically the same as that in Embodiment 1, and will not be repeated here. Because the generation methods of the (n+1)th phase clock signal clkn+1 are different in the two embodiments, the waveform of the (n+1)th phase clock signal clkn+1 will be different. Especially before the clock phase-splitting circuit stabilizes, in Embodiment 1, the (n+1)th phase clock signal clkn+1 only has pulses when its phase leads the phase of the standard clock signal clk1; that is, the number of pulses in the (n+1)th phase clock signal clkn+1 may be less than the number of pulses in the nth phase clock signal clkn. However, in this embodiment, regardless of whether the phase of the (n+1)th phase clock signal clkn+1 leads or lags the phase of the standard clock signal clk1, the (n+1)th phase clock signal clkn+1 always has pulses that correspond one-to-one with the pulses of the nth phase clock signal clkn. The clock phase splitting circuit in this embodiment can achieve high-precision phase splitting. Although an (n+1)th phase clock generation circuit is added in this embodiment compared to the first embodiment, the circuit structure of the (n+1)th phase clock generation circuit is basically the same as that of the high-frequency clock generation circuit, and the design difficulty will not increase much.

[0082] like Figure 5 As shown, it is based on Figure 4 The circuit diagram of another embodiment of the second circuit is shown below. The second circuit 301' in this embodiment includes a second pulse generation circuit 3013 and a second phase detection circuit 3014. The second pulse generation circuit 3013 is configured to receive a standard clock signal clk1 and output a first judgment signal INC based on the standard clock signal clk1. For example, in one embodiment, the second pulse generation circuit 3013 can be configured to output a pulse with a fixed pulse width at each falling edge of the standard clock signal clk1, and the first judgment signal INC is a pulse signal with a fixed pulse width and the same frequency as the standard clock signal clk1; in another embodiment, the second pulse generation circuit 3013 can also be configured to output a pulse with a fixed pulse width at each rising edge of the standard clock signal clk1. The second phase detection circuit 3014 is configured to receive the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1, and output a second judgment signal DEC based on the phase difference between the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1. For example, in one embodiment, the second phase detector circuit 3014 may be configured to control the second judgment signal DEC to be in an active state during the time period when the phase of the (n+1)th phase clock signal clkn+1 lags behind the phase of the standard clock signal clk1, and otherwise control the second judgment signal DEC to be in an inactive state.

[0083] refer to Figure 6 , Figure 6 Taking n=3 as an example, the following are examples of how to calculate n=3 based on the following conditions: Figure 5 After the clock phase-splitter circuit stabilizes, the waveform diagrams for the first ramp signal Vramp1, the high-frequency clock signal clkH, the standard clock signal clk1, the second-phase clock signal clk2, the third-phase clock signal clk3 (i.e., the nth-phase clock signal clkn), the second ramp signal Vramp2, and the fourth-phase clock signal clk4 (i.e., the (n+1)th-phase clock signal clkn+1) are shown, where Vref represents the reference voltage mentioned earlier. The second ramp signal Vramp2 and the first ramp signal Vramp1 have the same rising slope. The first ramp signal Vramp1 is reset once when the rising edge of the high-frequency clock signal clkH or the rising edge of the standard clock signal clk1 arrives; the second ramp signal Vramp2 is reset once when the rising edge of the third-phase clock signal clk3 arrives; the reference voltage Vref increases by a fixed value starting from the falling edge of the standard clock signal clk1 each time, and decreases during the time period when the fourth-phase clock signal clk4 lags behind the phase of the standard clock signal clk1. Understandably, before the clock phase splitting circuit stabilizes, when the phase of the 4th phase clock signal clk4 lags significantly behind the phase of the standard clock signal clk1, the decrease in the reference voltage Vref within one standard clock signal clk1 cycle will be greater than its fixed increase each time. Therefore, in the next standard clock signal clk1 cycle, the value of the reference voltage Vref will decrease, and the time for the first ramp signal Vramp1 to reach the reference voltage Vref from reset will decrease. Correspondingly, the phases of the 2nd to 4th phase clock signals will advance slightly, thus reducing the lag between the 4th phase clock signal clk4 and the standard clock signal clk1. Finally, after the clock phase splitting circuit stabilizes, the phase of the 4th phase clock signal clk4 lags slightly behind the standard clock signal clk1, and the decrease in the reference voltage Vref each time is equal to its fixed increase each time. By controlling the magnitude of the fixed increase in the reference voltage Vref each time, the absolute value of the phase difference between the 4th phase clock signal clk4 and the standard clock signal clk1 can be controlled to be less than a preset value. Furthermore, since the slope of the first ramp signal Vramp1 is always a fixed value during its rise, the phase difference between the standard clock signal clk1 and the second-phase clock signal clk2 is equal to the phase difference between the second-phase clock signal clk2 and the third-phase clock signal clk3. To achieve better phase separation, the absolute value of the phase difference between the fourth-phase clock signal clk4 and the standard clock signal clk1 needs to be kept relatively small. This can be achieved by setting the reference voltage Vref to increase by a relatively small fixed value within each cycle of the standard clock signal clk1.

[0084] Combination Figures 4-6 It can be seen that, based on Figure 5In the clock phase-splitting circuit, when n is a fixed integer, the first ramp signal Vramp1 has a fixed slope; the phase correction circuit 30 adjusts the magnitude of the reference voltage Vref according to the standard clock signal clk1 and the phase difference between the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1. Specifically, the method for adjusting the magnitude of the reference voltage Vref is as follows: within each period of the standard clock signal clk1, the reference voltage Vref is increased by a fixed value; when the phase of the (n+1)th phase clock signal clkn+1 lags behind the phase of the standard clock signal clk1, the reference voltage Vref is decreased according to the phase difference between the two. After the clock phase-splitting circuit of this embodiment stabilizes, the phase of the (n+1)th phase clock signal clkn+1 will slightly lag behind the phase of the standard clock signal clk1. By controlling the fixed value by which the reference voltage Vref increases each time, the absolute value of the phase difference between the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1 can be controlled to be less than a preset value. Furthermore, after the clock phase splitting circuit stabilizes, when n is an integer greater than or equal to 3, the phase difference between the standard clock signal and the second phase clock signal and the phase difference between the m-th phase clock signal clkm and the (m+1)-th phase clock signal clkm+1 are equal, where m is any integer from 2 to (n-1).

[0085] like Figure 7 As shown, it is based on Figure 4 A schematic diagram of the circuit structure of another embodiment of the second circuit is shown below. In this embodiment, the second circuit 301″ includes a third phase detector circuit 3015. The third phase detector circuit 3015 can be configured to receive the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1. It outputs a first judgment signal INC based on the phase difference between the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1 when the phase of clkn+1 leads the phase of clk1. It also outputs a first judgment signal INC based on the phase difference between the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1 when the phase of clkn+1 lags the phase of clk1. The second judgment signal DEC is output. For example, in one embodiment, the third phase detector circuit 3015 can be configured to control the first judgment signal INC to be valid during the time period when the phase of the (n+1)th phase clock signal clkn+1 leads the phase of the standard clock signal clk1, otherwise controlling the first judgment signal INC to be invalid; and to control the second judgment signal DEC to be valid during the time period when the phase of the (n+1)th phase clock signal clkn+1 lags the phase of the standard clock signal clk1, otherwise controlling the second judgment signal DEC to be invalid.

[0086] According to Figure 7In the clock phase-splitting circuit, when n is a fixed integer, the first ramp signal Vramp1 has a fixed slope. The phase correction circuit 30 adjusts the magnitude of the reference voltage Vref according to the phase difference between the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1. Specifically, the method for adjusting the magnitude of the reference voltage Vref is as follows: when the phase of the (n+1)th phase clock signal clkn+1 leads the phase of the standard clock signal clk1, the reference voltage Vref is increased based on the phase difference; when the phase of the (n+1)th phase clock signal clkn+1 lags behind the phase of the standard clock signal clk1, the reference voltage Vref is decreased based on the phase difference. It is easy to understand that after the clock phase-splitting circuit stabilizes, the phases of the standard clock signal clk1 and the (n+1)th phase clock signal clkn+1 are equal, and the phase difference between the standard clock signal clk1 and each adjacent pair of clock signals clk2, clk3…clkn is equal.

[0087] In the clock phase-splitting circuits of the above embodiments, the phase correction circuit 30 adjusts the magnitude of the reference voltage Vref based on the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1. It is readily understood that in other embodiments, the phase correction circuit 30 can also be configured to adjust the slope of the first ramp signal Vramp1 based on the (n+1)th phase clock signal and the standard clock signal, thereby adjusting the time it takes for the first ramp signal Vramp1 to reach the reference voltage Vref from reset, thus achieving the purpose of correcting the phase of the 2nd to (n+1)th phase clock signals. In one embodiment, the reference voltage Vref can be set to a fixed voltage; simply by adjusting the reference voltage Vref as shown in the example... Figure 2 and Figure 3 The adjustment circuit 302 in the phase correction circuit 30 shown can be replaced by controlling the slope of the first ramp signal Vramp1 to decrease according to the first judgment signal INC, and controlling the slope of the first ramp signal Vramp1 to increase according to the second judgment signal DEC. The following will illustrate this further. Figure 8 The circuit structure and working principle are introduced using the clock phase splitting circuit of the third embodiment shown as an example.

[0088] like Figure 8 As shown, in this embodiment, the high-frequency clock generation circuit 10 and... Figure 2The high-frequency clock generation circuit of Embodiment 1 shown is basically the same and will not be described again here. The difference is that in the high-frequency clock generation circuit 10 of this embodiment, the reference voltage Vref is a fixed voltage, and the high-frequency clock generation circuit 10 receives the second current I2 output by the phase correction circuit 30; the frequency divider circuit 20 is exactly the same as the frequency divider circuit of Embodiment 1 and will not be described again here; the second circuit 301 in the phase correction circuit 30 is exactly the same as the second circuit in Embodiment 1 and will not be described again here; the adjustment circuit 302 in the phase correction circuit 30 is basically the same as the adjustment circuit of Embodiment 1 and will not be described again here. The difference is that in the adjustment circuit 302 of this embodiment, the control terminal of the second switch K02 receives the second judgment signal DEC, the control terminal of the third switch K03 receives the first judgment signal INC, and the adjustment circuit 302 also includes a voltage-controlled current source U06. The input terminal of the voltage-controlled current source U06 receives the voltage of the second capacitor C02, and the output terminal outputs the second current I2.

[0089] In this embodiment, the reference voltage Vref is a fixed voltage; the phase correction circuit 30 adjusts the magnitude of the second current I2 according to the standard clock signal clk1 and the phase difference between the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1. Since the first controlled current I1 is controlled by the second current I2, the slope of the first ramp signal Vramp1 is proportional to the first controlled current I1, thus achieving the effect of adjusting the slope of the first ramp signal Vramp1. The specific method for adjusting the slope of the first ramp signal Vramp1 is as follows: within each period of the standard clock signal clk1, the second current I2 is increased by a fixed value, thereby increasing the slope of the first ramp signal Vramp1 by a fixed value; when the phase of the (n+1)th phase clock signal clkn+1 leads the phase of the standard clock signal clk1, the second current I2 is decreased according to the phase difference between the two, thereby decreasing the slope of the first ramp signal Vramp1. Understandably, before the clock phase splitting circuit stabilizes, when the phase of the (n+1)th phase clock signal clkn+1 leads the phase of the standard clock signal clk1 by a large margin, within one standard clock signal clk1 cycle, the decrease in the slope of the first ramp signal Vramp1 will be greater than its increase by a fixed value. In the next standard clock signal clk1 cycle, the rise slope of the first ramp signal Vramp1 will decrease, and the time for the first ramp signal Vramp1 to reach the reference voltage Vref from reset will increase. Correspondingly, the phases of the 2nd to (n+1)th phase clock signals will be delayed, thus reducing the phase lead of the (n+1)th phase clock signal clkn+1 over the standard clock signal clk1. Finally, after the clock phase splitting circuit stabilizes, the phase of the (n+1)th phase clock signal clkn+1 slightly leads the phase of the standard clock signal clk1, and the phase differences between the m-th phase clock signal clkm and the (m+1)-th phase clock signal clkm+1 are equal, where m is any integer from 2 to n. The phase differences clk2 between the standard clock signal clk1 and the second phase clock signal, and between the m-th phase clock signal clkm and the (m+1)-th phase clock signal clkm+1 are basically equal. This can be achieved by controlling the slope of the first ramp signal Vramp1 to increase by a relatively small fixed value each time, controlling the phase difference between the (n+1)-th phase clock signal clkn+1 and the standard clock signal clk1 to be less than a relatively small preset value, and controlling the absolute value of the difference between the phase differences between the standard clock signal clk1 and the second phase clock signal clk2 and the phase differences between the m-th phase clock signal clkm and the (m+1)-th phase clock signal clkm+1 to be relatively small.

[0090] In another embodiment, the phase correction circuit 30 can be easily understood to control the slope of the first ramp signal Vramp1 to decrease by a fixed value within each period of the standard clock signal clk1; when the phase of the (n+1)th phase clock signal clkn+1 lags behind the phase of the standard clock signal clk1, the slope of the first ramp signal Vramp1 is increased according to the phase difference between the two. In another embodiment, the phase correction circuit 30 can also be configured to adjust the slope of the first ramp signal Vramp1 according to the phase difference between the (n+1)th phase clock signal clkn+1 and the standard clock signal clk1. Specifically, it can be configured to control the slope of the first ramp signal Vramp1 to decrease according to the phase difference between the two when the phase of the (n+1)th phase clock signal clkn+1 leads the phase of the standard clock signal clk1; and to control the slope of the first ramp signal Vramp1 to increase according to the phase difference between the two when the phase of the (n+1)th phase clock signal clkn+1 lags behind the phase of the standard clock signal clk1. Those skilled in the art can easily obtain the specific circuit structure of the two schemes above and understand their working principle based on the content of this article, so it will not be elaborated here.

[0091] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.

Claims

1. A clock phase splitting method for generating phases 2 to n based on a standard clock signal, characterized in that, include: A high-frequency clock signal is output based on the comparison result between the first ramp signal and the reference voltage, wherein the first ramp signal is reset based on the high-frequency clock signal and the standard clock signal; The high-frequency clock signal is divided to generate the 2nd to (n+1)th phase clock signals; The magnitude of the reference voltage or the slope of the first ramp signal is adjusted according to the standard clock signal and the phase difference between the (n+1)th phase clock signal and the standard clock signal, so that in a stable state, the absolute value of the phase difference between the (n+1)th phase clock signal and the standard clock signal is less than a preset value. Where n is an integer greater than or equal to 2.

2. The clock phase splitting method according to claim 1, characterized in that, When adjusting the reference voltage based on the (n+1)th phase clock signal and the standard clock signal, when n is an integer greater than or equal to 3, in a steady state, the phase difference between the standard clock signal and the second phase clock signal is equal to the phase difference between the m-th phase clock signal and the (m+1)th phase clock signal. Where m is any integer from 2 to (n-1).

3. The clock phase splitting method according to claim 1, characterized in that, The first ramp signal is reset based on the rising edge of the high-frequency clock signal and the rising edge of the standard clock signal.

4. The clock phase splitting method according to claim 1, characterized in that, The slope of the first ramp signal is related to n.

5. The clock phase splitting method according to claim 1, characterized in that, When adjusting the reference voltage based on the (n+1)th phase clock signal and the standard clock signal, the slope of the first ramp signal is proportional to n.

6. The clock phase splitting method according to claim 1, characterized in that, When n is a fixed integer, the first ramp signal has a fixed slope. The reference voltage is reduced by a fixed value during each cycle of the standard clock signal. When the phase of the (n+1)th phase clock signal leads the phase of the standard clock signal, the reference voltage is increased based on the phase difference between the two.

7. The clock phase splitting method according to claim 1, characterized in that, When n is a fixed integer, the first ramp signal has a fixed slope. The reference voltage is increased by a fixed value during each cycle of the standard clock signal. When the phase of the (n+1)th phase clock signal lags behind the phase of the standard clock signal, the reference voltage is controlled to decrease based on the phase difference between the two.

8. The clock phase splitting method according to claim 6, characterized in that, The method for dividing the high-frequency clock signal to generate the 2nd to (n+1)th phase clock signals includes: A counter is used to count according to the high-frequency clock signal and to reset according to the standard clock signal to output a counting signal; The counting signals are logically combined to generate the second to (n+1) phase clock signals.

9. The clock phase splitting method according to claim 6 or 7, characterized in that, The method for dividing the high-frequency clock signal to generate the 2nd to (n+1)th phase clock signals includes: A counter is used to count according to the high-frequency clock signal and to reset according to the standard clock signal to output a counting signal; The counting signals are logically combined to generate the second to nth phase clock signals; The (n+1)th phase clock signal is generated based on the comparison result between the second ramp signal and the reference voltage, wherein the slope of the second ramp signal is equal to the slope of the first ramp signal, and the second ramp signal is reset according to the nth phase clock signal.

10. A clock phase-splitting circuit, generating phases 2 to n based on a standard clock signal, characterized in that, include: A high-frequency clock generation circuit outputs a high-frequency clock signal based on the comparison result of a first ramp signal and a reference voltage, wherein the first ramp signal is reset based on the high-frequency clock signal and the standard clock signal; The frequency divider circuit divides the high-frequency clock signal to generate the 2nd to (n+1)th phase clock signals; The phase correction circuit adjusts the magnitude of the reference voltage or the slope of the first ramp signal according to the standard clock signal and the phase difference between the (n+1)th phase clock signal and the standard clock signal, so that after the clock phase splitting circuit stabilizes, the absolute value of the phase difference between the (n+1)th phase clock signal and the standard clock signal is less than a preset value. Where n is an integer greater than or equal to 2.

11. The clock phase-splitting circuit according to claim 10, characterized in that, The phase correction circuit adjusts the reference voltage based on the (n+1)th phase clock signal and the standard clock signal. When n is an integer greater than or equal to 3, after the clock phase splitting circuit stabilizes... The phase difference between the standard clock signal and the second phase clock signal is equal to the phase difference between the m-th phase clock signal and the (m+1)-th phase clock signal. Where m is any integer from 2 to (n-1).

12. The clock phase-splitting circuit according to claim 10, characterized in that, The phase correction circuit includes: The second circuit receives the (n+1)th phase clock signal and the standard clock signal to output a judgment signal; The adjustment circuit adjusts the magnitude of the reference voltage or the slope of the first ramp signal according to the judgment signal.

13. The clock phase-splitting circuit according to claim 12, characterized in that, The judgment signal includes a first judgment signal and a second judgment signal, and the second circuit includes: The first phase detector circuit is configured to receive the (n+1)th phase clock signal and the standard clock signal, and output the first judgment signal based on the phase difference between the two when the phase of the (n+1)th phase clock signal leads the phase of the standard clock signal. The first pulse generation circuit is configured to receive the standard clock signal and output the second judgment signal according to the standard clock signal.

14. The clock phase-splitting circuit according to claim 12, characterized in that, The judgment signal includes a first judgment signal and a second judgment signal, and the second circuit includes: The second pulse generation circuit is configured to receive the standard clock signal and output the first judgment signal according to the standard clock signal; The second phase detector circuit is configured to receive the (n+1)th phase clock signal and the standard clock signal, and output the second judgment signal based on the phase difference between the (n+1)th phase clock signal and the standard clock signal when the phase of the (n+1)th phase clock signal lags behind the phase of the standard clock signal.

15. The clock phase-splitting circuit according to claim 13 or 14, characterized in that, When n is a fixed integer, the first ramp signal has a fixed slope; The adjustment circuit controls the reference voltage to increase according to the first judgment signal and controls the reference voltage to decrease according to the second judgment signal.

16. The clock phase-splitting circuit according to claim 13 or 14, characterized in that, The reference voltage is a fixed voltage; The adjustment circuit controls the slope of the first ramp signal to decrease according to the first judgment signal, and controls the slope of the first ramp signal to increase according to the second judgment signal.

17. The clock phase-splitting circuit according to claim 13, characterized in that, The frequency divider circuit includes: The counter receives the high-frequency clock signal and the standard clock signal, counts according to the high-frequency clock signal, and resets according to the standard clock signal to output a count signal; The first clock distribution circuit performs logical combination on the counting signals to generate the second to (n+1) phase clock signals.

18. The clock phase-splitting circuit according to claim 13 or 14, characterized in that, The frequency divider circuit includes: The counter receives the high-frequency clock signal and the standard clock signal, counts according to the high-frequency clock signal, and resets according to the standard clock signal to output a count signal; The second clock distribution circuit performs logical combination on the counting signals to generate the second to nth phase clock signals; The (n+1)th phase clock generation circuit generates the (n+1)th phase clock signal based on the comparison result of the second ramp signal and the reference voltage, wherein the slope of the second ramp signal is equal to the slope of the first ramp signal, and the second ramp signal is reset according to the nth phase clock signal.

19. A multiphase switching circuit, comprising n switching circuits, characterized in that, The multiphase switching circuit includes the clock phase splitting circuit as described in any one of claims 10 to 18. The standard clock signal and the second to nth phase clock signals generated by the clock phase splitting circuit are respectively used as the clock signals for the n switching circuits.

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