Plasma processing apparatus

Abstract

To provide a plasma processing apparatus that stabilizes the potential of a wafer under processing and improves the yield of processing, a plasma processing apparatus includes: a processing chamber disposed inside a vacuum vessel to form a plasma inside; a wafer stage disposed inside the processing chamber on which a wafer that is a processing target is placed; an electrostatic chuck including a film-shaped electrostatic chucking electrode disposed inside a film made of a dielectric that covers the upper surface of the wafer stage and used to electrostatically chuck the wafer placed on the film made of a dielectric; a high-frequency electrode disposed inside the wafer stage to be supplied with high-frequency power during processing of the wafer; and a lift pin disposed inside the wafer stage to move up and down to move the wafer up and down, and a lower portion connected to a member made of a conductor, and in the plasma processing apparatus, the resistance value between the electrostatic chucking electrode and the wafer is set to Resc, the resistance between the plasma and a ground electrode across the inner wall surface of the processing chamber is set to Rc, the withstand voltage between the plasma and the vacuum vessel that constitutes the processing chamber is set to Vt, the difference between the actual self-bias voltage Vdc generated by the wafer during processing of the wafer and the expected value Vdcs thereof is set to the expected maximum value δmax, the resistance value Rps between a direct-current power supply and the lower portion of the lift pin electrically connected thereto is set in the range of 100 MΩ > Rps > 1 / {(Vt / ((δmax-Vt)·Rc))-(1 / Resc)}, and the average value of the potential of the electrostatic chucking electrode is set to Eesc, and in processing of the wafer, the voltage value Eps of the lower portion of the lift pin and the average value Eesc of the potential of the electrostatic chucking electrode are adjusted to coincide with the expected value Vdcs of the self-bias voltage of the wafer.

Description

Technical Field

[0001] This invention relates to a plasma processing apparatus for processing semiconductor wafers used in the manufacturing process of semiconductor devices. The apparatus processes a substrate-shaped sample, such as a semiconductor wafer, disposed within a processing chamber in a vacuum chamber using plasma generated within the processing chamber. The apparatus includes: a wafer stage (carrying electrode) disposed within the processing chamber and on its upper surface; and multiple push pins (lifting pins, lifting pins) for the sample that can move vertically between a position where the sample is stored inside a hole disposed on the wafer stage and a position where the sample rests at its front end, protruding upwards from the opening of the hole on the upper surface of the wafer stage. Background Technology

[0002] Inside the processing chamber of a plasma processing apparatus as described above, a substrate such as a semiconductor wafer, which is the sample to be processed, is held on the surface of a wafer stage (electrode carrier) and exposed to plasma formed using a gas supplied to the processing chamber. With the surface of the wafer, on which a film layer for the sample to be processed is pre-formed, in contact with charged particles such as ions and reactive particles such as active species in the plasma, high-frequency power is supplied to the electrodes positioned within the wafer stage. The film layer on the wafer surface is etched or otherwise processed through interaction with these particles. The high-frequency power supplied to the electrodes creates a high-frequency potential on the wafer held above, but this potential is biased negatively by a given value relative to the electrostatic potential of the plasma. The value of the DC component of this negatively biased potential is called the self-bias voltage.

[0003] A potential difference is generated between a wafer with a self-biased potential formed by high-frequency electricity and a conductive component in a processing chamber surrounding the wafer. If this potential difference becomes larger than a certain value, a discharge occurs, damaging the circuitry of the elements on the wafer formed by the pattern created using plasma processing, thus impairing the yield of the processed product. As a technique to suppress this, the solution described in International Patent Publication No. 2003 / 009363 (Patent Document 1) is known. This prior art discloses a technique where, to prevent discharge between the focusing ring surrounding the wafer on the wafer stage and the wafer, the potential of the focusing ring is controlled to match the potential of the wafer; or, the height of the lifting pin on the back of the wafer is finely adjusted to control the gap between the wafer and the upper end of the lifting pin, thereby suppressing discharge at that gap. Furthermore, Japanese Patent Application Publication No. 2001-506808 (Patent Document 2) discloses a technique in which the current flowing from the conductive component of the lifting pin through the substrate lifting device to the ground line is stabilized by using a resistor to prevent component damage. The lifting pin moves upward to raise the substrate (wafer) after plasma processing, thereby bringing its front end into contact with the substrate. The substrate lifting device drives the lifting pin, which is connected to the ground line via an electrical connection. Furthermore, Japanese Patent Application Publication No. 2011-187881 (Patent Document 3) discloses a technique in which an electrostatic adsorption device equipped with a so-called dipole-type electrostatic chuck that imparts different polarities to multiple electrodes of the electrostatically adsorbed wafer is used. During plasma etching, the bias amount of the potential of the positive and negative adsorption electrodes is adjusted based on the leakage current flowing from each electrode through the plasma, corresponding to the self-bias voltage of the wafer. Furthermore, Japanese Patent Publication No. 2002-507326 (Patent Document 4) describes a technique in which the difference between the currents flowing through two electrodes (embedded plates) of an electrostatic chuck is detected while the wafer is charged, and the voltage applied to these electrodes is adjusted accordingly.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: International Publication No. 2003 / 009363

[0007] Patent Document 2: JP Patent No. 2001-506808

[0008] Patent Document 3: JP 2011-187881

[0009] Patent Document 4: JP Patent No. 2002-507326 Summary of the Invention

[0010] The problem that the invention aims to solve

[0011] However, problems arise in the aforementioned prior art due to insufficient consideration of points such as the following.

[0012] That is, in existing plasma processing apparatuses, the following structure is provided: a lifting pin is housed inside a hole pre-positioned in the wafer stage, and the lower part of the lifting pin is connected to a support (also called a support member). This support is connected to a drive device, including a motor and actuator, located in a space situated below or below the wafer stage. Through the operation of the drive device, the support member moves vertically within this space, thereby allowing the front end of the lifting pin to move between its position inside the hole and its position supporting the wafer above the upper surface of the wafer stage. The hole for storing the lifting pin is constructed by penetrating a metal substrate having a cylindrical or circular wafer stage shape and a dielectric material coating covering its upper surface and incorporating electrodes for electrostatic adsorption, or by further penetrating an insulating circular plate member connected to the bottom surface of the wafer stage substrate. This space is located below the wafer stage substrate.

[0013] Furthermore, in plasma processing apparatuses where the inner wall of the processing chamber, which is constructed of metal components and in which plasma is formed, is covered with an insulating material (dielectric), and where the lifting pins are made of dielectric material, a situation arises where a component made of conductive material is exposed below the lifting pins, whose supporting components are made of metal components, in a space below the substrate. In this case, during processes such as etching semiconductor wafers by forming plasma inside the processing chamber and supplying high-frequency power to electrodes inside a metal substrate or dielectric film, power leakage occurs between the conductive components and the wafer. This causes the wafer's self-bias potential to become a value different from the desired processing result, negatively impacting the processing yield.

[0014] The aforementioned existing technology does not take into account the problem of inappropriate potential of the chip, which could lead to the generation of foreign matter.

[0015] The object of the present invention is to provide a plasma processing apparatus that stabilizes the potential of a wafer during processing, thereby improving the yield of the processed product.

[0016] Methods for solving problems

[0017] The above objective is achieved by a plasma processing apparatus comprising: a processing chamber disposed inside a vacuum container, on which plasma is formed; a wafer stage disposed inside the processing chamber, on which a wafer to be processed is placed; an electrostatic chuck comprising a film-shaped electrostatic adsorption electrode disposed within a dielectric film covering the upper surface of the wafer stage and for electrostatically adsorbing the wafer placed on the dielectric film; a high-frequency electrode disposed inside the wafer stage and supplied with high-frequency power during the processing of the wafer; and a lifting pin disposed inside the wafer stage, movable in the vertical direction to move the wafer vertically, and connected at its lower part to a conductive component. The plasma processing apparatus is characterized in that the resistance value between the electrostatic adsorption electrode and the wafer is set to Resc, and the plasma is separated from the wafer by a conductive component. The resistance between the grounding electrodes on the inner wall of the processing chamber is set as Rc, the withstand voltage between the plasma and the vacuum container constituting the processing chamber is set as Vt, the expected maximum value of the difference between the actual self-bias voltage Vdc generated by the wafer during wafer processing and its expected value Vdcs is set as δmax, the resistance value Rps between the DC power supply and the lower part of the lifting pin electrically connected thereto is set in the range of 100MΩ > Rps > 1 / {(Vt / ((δmax-Vt)·Rc))-(1 / Resc)}, and the average value of the potential of the electrostatic adsorption electrode is set as Eesc. During the wafer processing, the voltage value Eps of the lower part of the lifting pin and the average value of the potential of the electrostatic adsorption electrode Eesc are adjusted to be consistent with the expected value Vdcs of the self-bias voltage of the wafer.

[0018] The effects of the invention

[0019] According to the present invention, even if a sudden conduction occurs in the lifting pin during ion etching, an increase in the average potential of the wafer can be prevented. Furthermore, this prevents an increase in the average potential of the plasma, reduces the potential difference applied to the dielectric film between the plasma and the ground wire and the outer metal substrate, prevents abnormal discharges caused by insulation failure of the dielectric film on the inner wall of the processing chamber, and thus prevents the generation of foreign matter. Attached Figure Description

[0020] Figure 1 This is a schematic longitudinal cross-sectional view illustrating the structure of the plasma processing apparatus according to an embodiment of the present invention.

[0021] Figure 2 It is a schematic representation in Figure 1 The illustrated embodiment is a schematic longitudinal cross-sectional view of the structure of the plasma processing apparatus to which the equivalent circuitry and its elements comprising the plasma generated during wafer processing are added.

[0022] Figure 3It is a schematic representation in Figure 1 The illustrated embodiment shows a longitudinal cross-sectional view of an example of a method for detecting the resistance Rc and withstand voltage Vt of the inner wall of the treatment chamber in a plasma treatment apparatus.

[0023] Figure 4 It means to use Figure 3 The graph shows the change in resistance value obtained by the detection method shown, relative to the change in voltage applied to the temporary electrode from a variable DC power supply.

[0024] Figure 5 This is a diagram illustrating the appropriate range of resistance values ​​at the lower part of the lifting pin of the present invention.

[0025] Figure 6 It means and Figure 1 The graph shows the changes in time and the changes in power supply output associated with the processing of the wafer by the plasma processing apparatus involved in the illustrated embodiment.

[0026] Figure 7 This is a chart for determining the lower limit value of the required lower resistance Rps of the lifting pin. Detailed Implementation

[0027] In existing plasma processing apparatuses, there is a mechanism at the lower part of the lifting pin that moves the lifting pin in the vertical direction. In order to maintain the space below the substrate of the mechanism, which is equipped with a metal lifting pin support connected to and supported from below, at a pressure higher than that in the processing chamber (e.g., equivalent to atmospheric pressure), a metal bellows is used around the opening of the lifting pin hole that houses the lifting pin inside. This bellows is used to vacuum seal the space between the lifting pin hole and the interior of the processing chamber connected to it, and the space below the substrate. In such cases, there is a possibility that these metal components are not adequately insulated from the high-frequency electrodes and the wafer in the wafer stage that is supplied with high-frequency power.

[0028] Furthermore, in existing technologies, when using a dielectric material such as indigestible alumina as the material for the lifting pin, it is designed to DC insulate the wafer from the conductive component by a given distance, for example, 5 cm or more. This prevents discharge even when the inner wall of the lifting pin hole is made of a dielectric material and is supplied with the aforementioned high-frequency power. However, if the high-frequency power applied to the electrodes of the wafer stage and the high-frequency power used to generate plasma increase, dielectric barrier discharge will be generated diffusely within the space inside the lifting pin hole. This will cause the wafer and the conductive component below the lifting pin to become conductive. In other words, high-frequency power leaks from the wafer to the conductive component below the lifting pin, reducing the absolute value of the wafer's average potential. That is, the inventors have clarified the situation where the potential of the conductive component below the lifting pin affects the average potential of the wafer.

[0029] The inventors conceived of this invention in order to solve such problems, and the embodiments of this invention have the following structure in order to solve the above-mentioned problems.

[0030] The plasma processing apparatus according to this embodiment includes: a processing chamber disposed inside a vacuum container, wherein plasma is formed inside the chamber; the processing chamber has a cylindrical shape in a portion thereof, surrounding the space in which the plasma is formed; and the inner sidewalls of the processing chamber are covered by a dielectric material of a given thickness. Furthermore, a high-frequency metal electrode within a wafer stage is primarily biased during processing and is connected to a first high-frequency power supply for attracting charged particles in the plasma to the wafer surface, thereby being supplied with first high-frequency power. A second high-frequency power supply is further provided, which supplies second high-frequency power for generating plasma inside the processing chamber.

[0031] Multiple lifting pins that separate the wafer from the wafer stage by lifting it above the upper surface of the wafer stage are at least partially made of a dielectric material. The lower ends of the lifting pins are connected to and supported from below by a lifting pin support disposed in a space below a lifting pin hole in the substrate of the wafer stage. The lifting pin support has a portion (component) made of a conductive material such as metal facing the interior of the space below the substrate.

[0032] In this embodiment, this part (component) is connected to a variable DC power supply via a given resistance value (hereinafter referred to as the lower resistance Rps of the lifting pin), and the output of the variable DC power supply is adjusted so that the potential becomes a given lower voltage Eps of the lifting pin. Furthermore, a bipolar (dipole) electrostatic chuck is provided, which imparts different polarities to the film-like electrodes disposed inside a dielectric film disposed on the upper surface of the wafer stage and used to adsorb multiple wafers.

[0033] Furthermore, the values ​​of the plasma-to-ground withstand voltage Vt and the plasma-to-ground DC resistance Rc of the dielectric covering that constitutes the inner wall of the processing chamber are obtained in advance before the processing of the wafer to be processed begins. When the resistance between the electrode of the electrostatic chuck and the wafer is set as the electrostatic chuck resistance Resc, the lower resistance Rps of the lifting pin is adjusted to the range shown in the following formula.

[0034] 100MΩ>Rps>1 / {(Vt / ((δmax-Vt)×Rc))-(1 / Resc)}

[0035] Furthermore, concurrently, during the process of forming plasma by supplying second high-frequency power from the second high-frequency power source and processing the film layer of the object to be processed on the wafer by supplying first high-frequency power to the wafer stage from the first high-frequency power source, the average voltage (electrostatic chuck average voltage) Eesc of the two electrodes of the electrostatic chuck and the voltage Eps of the lower part of the lifting pin are both adjusted to the estimated value Vdcs of the self-bias potential of the wafer.

[0036] Here, δmax represents the maximum value of the estimated potential difference δ during wafer processing, assuming the possibility that the voltage Eps at the bottom of the lifting pin and the average voltage Eesc of the electrostatic chuck differ from the actual self-bias potential Vdc of the wafer. The maximum potential difference δmax includes the voltage deviation originating from the accuracy of the adjustment of the voltage Eps at the bottom of the lifting pin and the average voltage Eesc of the electrostatic chuck.

[0037] Furthermore, in one example shown below, the estimated value Vdcs of the self-bias potential of the wafer during processing is characterized as a function of the value Vpp of the maximum-minimum amplitude of the voltage (high-frequency voltage) of the first high-frequency power supplied to the metal electrode, i.e., the substrate, of the wafer stage, so as to be approximately consistent with the self-bias potential Vdc obtained in prior experiments, etc. Furthermore, the difference between the actual self-bias potential Vdc and the estimated value Vdcs of the self-bias potential under multiple processing conditions for the wafer is defined as the potential difference δ. Moreover, the maximum potential difference δ obtained in the processing of the wafer under multiple processing conditions using the plasma processing apparatus according to this embodiment, plus the error caused by the control precision, is defined as the maximum value δmax of the potential difference.

[0038] Alternatively, in another example, the maximum-minimum value (amplitude of the high-frequency potential) of the high-frequency potential generated on the wafer by supplying the first high-frequency power from the first high-frequency power source is set as Vppw, and the maximum Vppw used in the processing of the wafer under multiple processing conditions using the plasma processing apparatus according to this embodiment is set as Vppwmax. The estimated value of the self-bias potential Vdcs and the maximum value of the potential difference δ δmax are obtained by the following formula.

[0039] Vdcs = -0.27 × Vppw

[0040] δmax = 0.17 × Vppmax + error due to control precision

[0041] Vppw can be calculated, for example, by the amplitude (vibration) Vpp of the maximum-minimum value of the first high-frequency voltage detected at the outlet of the matching box configured on the power supply path of the first high-frequency power supply electrically connecting the first high-frequency power supply to the substrate of the wafer stage, the matching value of the matching box, and the impedance Z from the point where Vpp is detected on the power supply path to the wafer, omitting harmonics and assuming the fundamental frequency.

[0042] The following uses the accompanying drawings to illustrate the embodiments.

[0043] [Example 1]

[0044] The following uses Figures 1 to 5 The embodiments of the present invention will be described below.

[0045] Figure 1 This is a schematic longitudinal cross-sectional view illustrating the structure of a plasma processing apparatus according to an embodiment of the present invention. The plasma processing apparatus 100 of this embodiment is an etching processing apparatus that uses plasma formed in a processing chamber to process the film layer of a processing object with a film structure, wherein the film structure is obtained by stacking multiple film layers in the vertical direction, including a mask layer pre-formed on the surface of a sample in the form of a substrate such as a semiconductor wafer, which is the processing object disposed in a space inside a vacuum container, and the film layer of the processing object.

[0046] The plasma processing apparatus 100 of this example includes: a processing chamber 101 in which a wafer 107 is disposed and plasma is formed to process it; an exhaust mechanism connected to the bottom of a vacuum container and communicating with the processing chamber 101, wherein a valve or other exhaust flow regulating mechanism (not shown) and a vacuum pump (not shown) are connected in sequence by piping and conduit; and a gas supply line (not shown) including a gas introduction pipe connected to the upper part of the vacuum container to introduce processing gas required for forming plasma for etching the wafer 107, and a flow regulator for the processing gas. In this plasma processing apparatus, the pressure of the processing chamber 101 is maintained within a given range suitable for the processing of the wafer 107 and the operation of the plasma processing apparatus 100 by balancing the flow rate or velocity of the processing gas or dilution gas introduced into the processing chamber 101 from the gas supply line and the flow rate and velocity of the exhaust caused by the operation of the exhaust mechanism communicating with the exhaust port disposed at the bottom of the processing chamber 101.

[0047] Furthermore, the upper part of the vacuum container includes: a microwave generator (not shown) such as a magnetron that forms an electric field for generating plasma inside the processing chamber 101 using a second high-frequency power source at a given frequency (in this example, a microwave band frequency); and a solenoid coil that forms a magnetic field within the processing chamber 101 with a distribution and intensity appropriately matched to the electric field of the microwave. The processing gas supplied to the processing chamber 101 is excited by the electric or magnetic field supplied from them, undergoing ionization and dissociation, thereby generating plasma 102.

[0048] In this embodiment, the processing chamber 101 is surrounded by a metal outer shell 103 that constitutes a vacuum container. To suppress contamination inside the processing chamber 101 caused by interaction between the inner wall surface and the plasma 102, a covering made of a dielectric material is used to prevent the inner wall surface of the outer shell 103 from directly contacting the plasma. The dielectric covering in this example includes: a quartz disc-shaped top plate 104 that forms the top surface of the processing chamber 101; a thermally sprayed film 105 that covers the inner peripheral wall of the annular metal ground electrode 131 surrounding the upper part of the processing chamber 101, and is coated using a ceramic material such as alumina or yttrium oxide via thermal spraying; and an anodic oxide film 106 further formed on the surface of a base material made of aluminum or its alloy.

[0049] The lower part of the space inside the processing chamber 101 is provided with a mounting electrode 108, which serves as a wafer stage on which a wafer 107 is mounted. As described above, a metal substrate 109, which is connected to a first high-frequency power supply, i.e., a high-frequency power supply 112, and has a circular or cylindrical shape, is provided inside the mounting electrode 108. The substrate 109 is electrically connected to the first high-frequency power supply, i.e., the high-frequency power supply 112, via a matching box 111. The high-frequency power supply 112 outputs a first high-frequency power of 400 kHz to form a bias potential on the wafer 107 in order to attract charged particles such as ions in the plasma 102 to the upper surface of the wafer 107 during the processing of the wafer 107. In addition, a detector 110 is provided at the position between the matching box 111 and the substrate 109 on the power supply path of the first high-frequency power for monitoring the amplitude (Vpp) of the maximum-minimum value of the first high-frequency voltage from the high-frequency power supply 112. Furthermore, a dielectric film 113 is disposed around the electrode 108, and an insulating plate 114 made of dielectric (insulator) is disposed below the substrate 109.

[0050] The upper surface of the mounting electrode 108 is roughly circular to match the shape of the wafer 107. The upper surface of the mounting electrode 108 is covered by a film (dielectric film) 122 made of dielectric materials such as alumina and yttrium oxide. An inner electrostatic chuck electrode 115 and an outer electrostatic chuck electrode 116 are disposed inside the film to electrostatically attract and hold the wafer 107 placed on it. The inner electrostatic chuck electrode 115 and the outer electrostatic chuck electrode 116 are each electrically connected to a variable DC power supply 117 and 118 via a low-pass filter (not shown). Corresponding to the voltage formed on these films by the supplied DC power, an electrostatic force is formed between the upper surface of the dielectric film 122 and the wafer 107. This electrostatic force attracts and holds the wafer 107 to the dielectric film 122.

[0051] A plurality of electrodes, including an inner electrostatic chuck electrode 115 and an outer electrostatic chuck electrode 116, disposed within the dielectric film 122 on the upper surface of the mounting electrode 108 constituting this embodiment, constitute a so-called bipolar (dipole) electrostatic chuck. These electrodes are supplied with power from variable DC power supplies 117 and 118, thereby assigning them different polarities. In this example, the average voltage between the positive and negative poles of these bipolar electrostatic adsorption electrodes is set to Eesc. This electrostatic chuck is a JR-type electrostatic chuck that adsorbs the wafer 107 via the Johnsen-Rahbek (JR) effect.

[0052] Inside the mounting electrode 108, through-holes 123 penetrating the substrate 109 and the dielectric film 122 disposed thereon are arranged in three or more locations (three locations in this example, only one location is shown). A lifting pin 124 made of dielectric material is disposed inside each through-hole 123. Driving the lifting pin 124 causes it to move up and down along the vertical axis of the through-hole 123 between a position where its front end is inside the through-hole 123 and a position where its front end is above the upper surface of the dielectric film 122. Through the up-and-down movement of the lifting pin 124, the wafer 107, supported on the front end of each pin, is transferred between a state separated from the upper surface of the mounting electrode 108 and a state placed on the upper surface of the dielectric film 122.

[0053] Inside the through hole 123, a cylindrical sleeve 125 made of an insulating (dielectric) material is inserted into the through hole 123, so that the through hole 123 is covered from top to bottom by the dielectric component. The inner wall of the sleeve 125 has a gap with the lifting pin 124 to a degree that prevents them from contacting each other during vertical movement. The through hole 123 passes through the dielectric film 122 constituting the electrode 108, the substrate 109, and the circular insulating plate 114 disposed below it, and the chassis 134 electrically connected to the ground electrode. The sleeve 125 extends from the upper surface of the substrate 109 to the lower surface of the chassis 134.

[0054] The space 135 below the chassis 134 is the space contained within the wafer mounting electrode 108. A beam 127 with a lifting pin holder 126 is disposed inside the beam 127. The lifting pin holder 126 is connected to and supports the lower end of the lifting pin 124 and is made of a conductive material such as metal. The beam 127, disposed within the space 135, is located at a position where the electric field of the high-frequency potential of the wafer mounting electrode 108 within the space 135 weakens. The lower end of the lifting pin 124 is connected to the upper surface of the front end of the lifting pin holder 126. The root of the beam 127 is connected to a drive mechanism 128 disposed in the center of the space 135. The drive mechanism 128 is configured to extend and retract in the vertical direction shown in the figure. Through this action, the lifting pin holder 126 and the beam 127 move together in the vertical direction within the space 135, thereby moving the lifting pin 124 between a position housed inside the through-hole 123 and a position protruding above the dielectric film 122.

[0055] Furthermore, the beam 127 extends radially outward from its root located at the center of the space 135, and connects to the lower end of the lifting pin 124 on the upper surface of the front end of the lifting pin holder 126, which is made of a conductive material such as metal. Moreover, a bellows (snake-like structure) 136 is provided between the upper surface of the lifting pin holder 126 centered on the lower end of the lifting pin 124 and the surface surrounding the opening at the lower end of the through hole 123, which serves as the bottom surface of the upper chassis 134. This bellows surrounds and covers the lifting pin 124 and the opening at the lower end of the through hole 123, airtightly separating the area below the inner through hole 123 from a portion of the outer space 135, and can extend and retract in response to the vertical movement of the lifting pin holder 126.

[0056] In this embodiment, the interior of the bellows 136 communicates with the interior of the processing chamber 101 via a through hole 123. The metal component of the lifting pin holding the front end portion of 126 inside the bellows 136 is substantially exposed inside the through hole 123 or the processing chamber 101. Inside the bellows 136, the metal component constituting the exposed lifting pin holding the front end portion of 126 is electrically connected to a variable DC power supply 130 via a lower resistor 129Rps of the lifting pin. The power supplied from the variable DC power supply 130 is adjusted so that the potential of the metal component becomes a given lower voltage Eps of the lifting pin.

[0057] During the processing of wafer 107, while supplying high-frequency power from the first high-frequency power source 112 to wafer 107 via substrate 109, it is necessary to suppress fluctuations in the potential of plasma 102 caused by the high-frequency power formed on wafer 107. Therefore, in this embodiment, in order to serve as the ground line for plasma 102 at high frequency, a ground electrode 131 is disposed in the processing chamber 101 as described above. This ground electrode 131 is disposed in the space surrounding the upper part of the processing chamber 101 where plasma 102 is formed, and is equipped with a thermally sprayed film 105. The thermally sprayed film 105 covers its inner peripheral wall facing plasma 102, and is formed by coating a ceramic material such as alumina or yttrium oxide with a thickness of several micrometers to several hundred micrometers using a thermal spraying method. Furthermore, the surface area of ​​the ground electrode 131 facing plasma 102 has an area larger than the bottom area of ​​wafer 107.

[0058] In this embodiment, the ground electrode 131 has an annular shape surrounding a high-density upper region of the plasma 102 formed inside the processing chamber 101. A thermally sprayed film 105 is disposed on the inner peripheral surface of the ground electrode 131 facing the plasma. This thermally sprayed film 105 is formed by thermally spraying a material with yttrium oxide as the main component, which has higher plasma resistance. On the other hand, an anodized film (anodic oxide coating) 106 formed by anodizing is disposed on the inner wall surface of the processing chamber 101 of the outer casing 103 below the ground electrode 131, on the surface of the aluminum material. Corresponding to the quartz top plate 104 disposed above the processing chamber 101 covering it, except for the wafer 107, the inner wall surface of the processing chamber 101 surrounding the plasma 102 and the area around the wafer mounting electrode 108 are covered with a dielectric.

[0059] In this embodiment, as described above, the value of the lower resistance 129 of the lifting pin 124 between the lifting pin 124 and the variable DC power supply 130 is adjusted within a range determined by the relationship between the resistance value Rc and the withstand voltage Vt of the component constituting the inner wall of the processing chamber 101 and the ground electrode. Therefore, the withstand voltage Vt and resistance value Rc of the inner wall of the processing chamber 101 in this embodiment are used... Figure 1 as well as Figure 2 As explained below.

[0060] Figure 2 It is a schematic representation in Figure 1 The illustrated embodiment includes a schematic longitudinal cross-sectional view of the structure of the plasma processing apparatus, which further includes the equivalent circuitry and elements of the plasma generated during wafer processing.

[0061] As shown in these figures, the outer shell 103, which constitutes a vacuum container surrounding the processing chamber 101 of this embodiment, is composed of several parts and is electrically connected to a grounding electrode (not shown) and is set to a grounding potential (ground wire potential). Furthermore, in this embodiment, the electrical resistance value Rc of the inner wall of the processing chamber 101 is considered as the resistance value of the direct current flowing from the entire inner wall surface of the processing chamber 101, which is in contact with the plasma 102, through the outer shell 103 to the grounding electrode. Rc is defined as the electrical resistance value when a voltage equivalent to the withstand voltage Vt (or a voltage value equal to but only slightly smaller than that voltage) is applied between the plasma 102 and the outer shell 103. Figure 2 And the following shown Figures 3 to 5 In the diagram, Rc is shown as a resistor 132, which is considered as an element of the equivalent circuit when a DC voltage is applied between the inner wall of the processing chamber 101 connected to the plasma 102 and a ground electrode through the outer casing 103.

[0062] Furthermore, in this embodiment, when plasma 102 is formed inside the processing chamber 101, the withstand voltage (performance) of the components between the grounding electrode of each part of the outer casing 103 and the plasma 102 is not the same. For example, there are parts with low withstand voltage, such as the corners of the outer casing 103 and the thin dielectric film constituting the covering. In this embodiment, the withstand voltage value of the part with the lowest withstand voltage between the plasma 102 and each part of the outer casing 103 is set as the withstand voltage Vt of the inner wall of the processing chamber 101.

[0063] Furthermore, with the wafer 107 resting on the upper surface of the dielectric film 122 supporting the electrode 108, plasma 102 is formed inside the processing chamber 101, and a first high-frequency power is supplied to the substrate 109 from the first high-frequency power supply 112, forming a bias potential on the upper surface of the wafer 107. Furthermore, the dielectric film 122, along with inner electrostatic chuck electrodes 115 and outer electrostatic chuck electrodes 116 disposed therein, allows current to flow between these electrodes and the wafer 107 in response to the DC power supplied to the inner and outer electrostatic chuck electrodes 115 and 116. This current is required to generate the force that attracts the wafer 107, and flows between the inner and outer electrostatic chuck electrodes 115, the outer electrostatic chuck electrodes 116, and the wafer 107 through the resistance values ​​120 and 121 of the semiconducting film 119 constituting the dielectric film 122.

[0064] Furthermore, corresponding to the DC power supplied to the inner electrostatic chuck electrode 115 and the outer electrostatic chuck electrode 116, there is also electrostatic capacitance between these electrodes and the wafer 107, corresponding to the material and shape of the semiconductive film 119 and the dielectric film 122. The first high-frequency power supplied to the substrate 109 is coupled to the plasma 102 through the electrostatic capacitance of the dielectric film 122 containing the semiconductive film 119 and the electrostatic capacitance of the sheath (ion sheath) between the wafer 107 and the plasma 102 connected thereto.

[0065] A metal ground electrode 131, located on the inner side of the upper part of the housing 103 and surrounding the plasma 102 within the processing chamber 101, is connected to the plasma 102 via a thermally sprayed film 105 and a sheath formed on its upper surface. Static capacitance also exists within the sheath between the ground electrode 131 and the plasma 102. Figure 2 In this context, these electrostatic capacitances are shown as capacitors in an equivalent circuit having their capacitance values. Thus, with the plasma 102 formed, between the outer casing 103, which is set to ground potential, and the plasma 102, electrostatic capacitances and resistors corresponding to the material and shape of the sheath, thermal spray film 105, and ground electrode 131 disposed therebetween are also formed as elements of an equivalent circuit, coupling the ground potential location to the plasma 102.

[0066] Figure 3 It is a schematic representation in Figure 1 The figure shows a longitudinal cross-sectional view of an example of a method for detecting the resistance Rc and withstand voltage Vt of the inner wall of the treatment chamber in a plasma treatment apparatus according to the embodiment shown. The plasma treatment apparatus 100 shown in this figure has... Figure 1 The same structure is used, but structures not required for explanation are omitted. This figure is used to illustrate the method for testing the withstand voltage Vt and resistance Rc of the inner wall of the processing chamber 101.

[0067] First, a dielectric plate 201 is placed on the upper surface of the dielectric film 122 covering the upper surface of the electrode 108. Then, a temporary electrode 202 of conductive material is disposed near the inner wall of the space surrounding the processing chamber 101 where the plasma 102 is pre-formed. The temporary electrode 202 is connected to a covered cable 203, which is led out to the outside of the housing 103 via a feedthrough device (not shown) disposed in the housing 103, and connected to a variable DC power supply 206 via a low-pass filter 204 and a resistor 205 with a known resistance value (in this example, several MΩ).

[0068] Next, under the conditions of processing wafer 107 as a process for manufacturing semiconductor devices, plasma 102 is generated inside processing chamber 101. The voltage of the DC power output from variable DC power supply 206 is gradually increased, and a voltage is applied to the temporary electrode 202 connected to plasma 102. Ammeter 207 and potentiometer 208 are used to detect the value of the current flowing through the covered cable 203 and the potential of the temporary electrode 202. Since plasma 102 is a good conductor, the potential of the temporary electrode 202 disposed near the inner wall of processing chamber 101 is regarded as characterizing the potential of the surface of the inner wall where plasma 102 is connected to the inner wall of processing chamber 101. Using the potential difference and current of the circuit from the variable DC power supply 206 to the temporary electrode 202, the resistance value Rc of the circuit from the temporary electrode 202 through the DC resistance 132 of the entire inner wall of the processing chamber 101 connected to the plasma 102, to the conductive component constituting the outer shell 103 surrounding the processing chamber 101, to the ground electrode is obtained, and is taken as the value of the DC resistance 132.

[0069] exist Figure 4 The resulting voltage and resistance values ​​are shown. Figure 4 It means to use Figure 3 The graph shows the change in resistance value obtained by the detection method shown, relative to the change in voltage applied to the temporary electrode from a variable DC power supply.

[0070] As shown in this figure, the voltage value 302 at the location 301 where the resistance value changes discontinuously with the gradual increase of the DC voltage applied to the temporary electrode 202 is used as the withstand voltage Vt of the inner wall of the processing chamber 101. The resistance value 303 corresponding to a voltage value equal to but slightly smaller than that at the discontinuous location 301 is used as the resistance Rc of the inner wall of the processing chamber 101. In the example shown in this figure, the detected values ​​are withstand voltage Vt = 110V and resistance Rc = approximately 0.2MΩ. Furthermore, in this example, the withstand voltage Vt is defined as the location with the lowest voltage among the locations where the voltage changes discontinuously. The withstand voltage Vt is lower than that of the planar thermal spray film 105 and the normal anodic oxide film 106, and is considered to represent the withstand voltage of weaker areas such as boundaries and local corners.

[0071] The aforementioned withstand voltage value Vt and resistance value Rc vary depending on the usage history and condition of the components constituting the processing chamber 101 of the plasma processing apparatus 100, or the condition of the surface of the dielectric components disposed inside the processing chamber 101. Appropriate conditions must be selected for testing. Furthermore, the values ​​of withstand voltage Vt and resistance Rc may not be tested on multiple processing chambers 101 of the plasma processing apparatus 100 having identical structures. Instead, the range of variation in the test values ​​depending on the structure of the dielectric thermal spray film 105 on the inner wall of the processing chamber 101 having the same structure can be determined, and the results can be utilized.

[0072] The lower resistor Rps129 of the lifting pin is pre-adjusted to a value within the range of the following formula (1) before the etching process of the wafer 107 using the obtained withstand voltage Vt and the resistance Rc of the inner wall of the processing chamber.

[0073] 100MΩ>Rps>1 / {(Vt / ((δmax-Vt)Rc))-(1 / Resc)}···(1)

[0074] Here, the electrostatic chuck resistance Resc is the resistance value between the inner electrostatic chuck electrode 115 and the outer electrostatic chuck electrode 116, which are respectively given different polarities, and the wafer 107, and is half of the resistance value between one electrode and the wafer 107.

[0075] For example, if the resistance values ​​between the inner electrostatic chuck electrode 115 and the outer electrostatic chuck electrode 116 sandwiching the dielectric film 122 containing the semiconductive film 119 and the wafer 107 are set as Resc+, the positive and negative sides are respectively set as Resc+. Figure 2 The attached figures are labeled 120 and Resc- ( ). Figure 2(Referring to the attached figure 121), then Resc+ / 2≒Resc- / 2≒Resc. Furthermore, by setting the upper limit of the resistance of the lower resistor Rps129 of the lifting pin in equation (1) to 100MΩ, it is possible to prevent the lower part of the lifting pin 124 or the component with the front end of the lifting pin holding 126 from becoming energized.

[0076] In this embodiment, the value of the lower resistor Rps129 of the lifting pin is adjusted to a given range, and the average voltage Eesc of the electrostatic chuck electrode and the voltage Eps of the lower lifting pin via the variable DC power supply 130 connected to the lower resistor 129 are controlled. Both the electrostatic chuck average voltage Eesc and the lower lifting pin voltage Eps are controlled to follow the potential in conjunction with the estimated voltage Vdcs of the wafer self-bias.

[0077] δmax is called the maximum value of the potential difference. It is the largest difference between the actual self-bias voltage Vdc of the chip 107 and the control voltage of the follower control. In addition to the difference between the actual self-bias voltage Vdc and the estimated self-bias voltage Vdcs, it also includes the voltage deviation due to the time deviation of the follower control of the variable DC power supply and the error due to the voltage control accuracy.

[0078] Figure 5 This is a diagram illustrating a suitable range of resistance values ​​at the lower part of the lifting pin in this invention. That is, using... Figure 5 Let's explain equation (1) above.

[0079] In the plasma processing apparatus 100 of this embodiment, in Figure 5 (b) shows the equivalent circuit via the plasma 102 between the terminals on one end of the variable DC power supplies 117, 118, 130, which are electrically connected to the ground electrode, and the resistance value Rc of the inner wall of the processing chamber 101, when the plasma 102 is formed in the processing chamber 101 and the substrate 109 is etched by supplying a first high-frequency power from the high-frequency power supply 112 to the substrate 109. In particular, the circuit structure for the DC component of the current flowing between the wafer 107 and the surface of the lifting pin 124 connected to the lower part or the lower end of the lifting pin 124, where a discharge is induced inside the through hole 123 of the lifting pin 124, thereby creating a connection between the wafer 107 and the conductive part of the lifting pin 124 connected to the lower end of the lifting pin 124 with a conductive body 126, is shown.

[0080] The average potential Ec402 of the inner surface of the inner wall of the processing chamber 101 at a position on the left side of the resistance Rc401 characterized by the resistance value between the inner wall of the processing chamber 101 and the grounding electrode is the time-averaged potential of the surface of the inner wall of the processing chamber 101 facing the plasma 102. The difference between the average potential Ew403 of the wafer 107 and the average potential Ec402 of the inner surface of the inner wall of the processing chamber 101 corresponds to the actual self-bias voltage value Vdc of the wafer 107 (Ew - Vdc = Ec). Through the discharge in the through-hole 123, the wafer 107 is electrically connected to the variable DC power supplies 117, 118, and 130 via the resistance value of the electrostatic chuck portion including the dielectric film 122, i.e., the electrostatic chuck resistance Resc404, and the conductive member at the lower part of the lift pin 124 or the lift pin holder 126 and via the lower lift pin resistance Rps405, and their respective potentials are set to the electrostatic chuck average voltage Eesc406 as the voltage of the inner electrostatic chuck electrode 115 and the outer electrostatic chuck electrode 116 and the lower lift pin voltage Eps407 as the voltage value of the conductive member at the lower part of the lift pin 124 or the lift pin holder 126.

[0081] When adjusting the values of the electrostatic chuck average voltage Eesc406 and the lower lift pin voltage Eps407 to the estimated voltage value Vdcs of the self-bias, if it is the same as the actual self-bias voltage Vdc, the average potential Ec of the surface of the inner wall of the processing chamber 101 facing the plasma 102 becomes zero. In the case where Vdcs becomes a value different from Vdc, the potential difference δ408 between them is linearly distributed between the combined resistance 1 / (1 / Resc + 1 / Rps)409 of the electrostatic chuck resistance Resc and the lower lift pin resistance Rps and the resistance Rc401 of the inner wall of the processing chamber 101. The value of the average potential Ec402 of the inner surface of the inner wall of the processing chamber 101 at this time is determined as shown in Equation (2) in DC circuit calculations.

[0082] Ec = δ × Rc / ((1 / (1 / Resc + 1 / Rps)) + Rc) ··· Equation (2)

[0083] Figure 5 The (a) of is a graph showing the relationship of Equation (2) as a linear line. The condition for making the average potential Ec of the surface of the inner wall of the processing chamber 101 be below the withstand voltage Vt410 of the inner wall of the processing chamber 101 is 0 < Ec < Vt. This becomes the part for determining the lower limit of Equation (1) using this.

[0084] Next, the estimated voltage Vdcs of the self-bias of the wafer 107 will be described.

[0085] First, the plasma processing apparatus 100 of this embodiment is as Figure 1As shown, during the etching process, the voltage Vpp near the outlet of the matching box 111 is detected based on the output of the voltage detector 110. The matching box 111 is adjusted such that the impedance of the path from the high-frequency power supply 112 side of the matching box 111 matches the impedance Zc of the path leading to the plasma 102, which is closer to the processing chamber 101 than the matching box 111. Therefore, those skilled in the art can determine the impedance Zc based on the circuit structure from the power supply 112 to the matching box 111.

[0086] Furthermore, the impedance Zw at its frequency from the outlet of matching box 111 to wafer 107 of the first high-frequency power can also be obtained by measurement or careful calculation of the high-frequency electrical circuit. Therefore, the impedance Zp from wafer 107 to the plasma side is obtained by Zp=Zc-Zw, and thus the amplitude Vppw of the variation generated between one cycles of the potential based on the first high-frequency power becomes the following formula.

[0087] Next, Vppw = (|Zp| / |Zc|) × Vpp, and the variation amplitude Vppw is used to estimate the self-bias voltage Vdc.

[0088] use Figure 6 This will illustrate an example of the regulation of the output from the power supply of the plasma processing apparatus 100 in this embodiment. Figure 6 It means Figure 1 The illustrated embodiment shows a graph illustrating the changes in power supply output over time during wafer processing in the plasma processing apparatus. Specifically, this figure shows the changes over time in the self-bias voltage value and the high-frequency potential of the inner walls of wafer 107, plasma 102, and processing chamber 101 during wafer processing of 107.

[0089] exist Figure 6 (a) shows the amplitude of the potential variation (amplitude) Vppw501 between one cycle of the resistance value Rc of the inner wall of the processing chamber 101, the amplitude of the potential variation (amplitude) Vppp502 between one cycle of the first high-frequency power applied to the wafer 107 during processing, and the amplitude of the potential variation Vppc503 between one cycle of the plasma 102, when the average voltage Eesc of the bipolar electrostatic chuck electrode is set to 0. Furthermore, DC voltage values ​​Ew504, Ep505, and Ec506 are shown as average values ​​of each potential.

[0090] First, when the first high-frequency power is supplied to the substrate 109 and the wafer 107, the potential variation amplitude Vppc503 of the dielectric thermal spray film 105 on the inner wall of the processing chamber 101 facing the inner wall surface of the plasma 102 is "the electrostatic capacitance of the dielectric component between the entire inner wall surface of the processing chamber 101 and the outer casing 103 >> the electrostatic capacitance of the medium including the plasma 102 and the plasma sheath between the inner wall surface of the processing chamber 101 and the wafer 107". Therefore, the potential variation amplitude Vppc503 based on the high-frequency power of the inner wall surface of the processing chamber 101 is very small relative to the potential variation amplitude Vppw501 on the wafer 107, and can therefore be ignored.

[0091] Furthermore, the negatively charged electrons in plasma 102 have lower mass and therefore move faster than other positive and negative ions. Therefore, by rapidly dissipating from plasma 102 and incident on the wall, there is a physical constraint that the instantaneous potential 507 of plasma 102 is always higher than the instantaneous potential 508 of the inner wall of processing chamber 101 and the instantaneous potential 509 of wafer 107. Therefore, according to... Figure 6 The self-bias voltage Vdc510, which represents how much the average potential Ew504 on the upper surface of the wafer 107 is lower than the average potential Ec506 on the inner wall of the processing chamber 101, is approximately characterized by the following equation (3) using the potential variation amplitude Vppp502 of the plasma 102 and the high-frequency potential variation amplitude Vppw501 of the wafer.

[0092] Vdc=Vb-Vc=Vppw / 2-Vppp, Vppp=2Vc···(3)

[0093] Here, the sheath voltage Vb511 is the potential difference between the average potential Ep505 of the plasma 102 and the average potential Ew504 of the wafer 107, and the sheath voltage Vc512 is the potential difference between the average potential Ep505 of the plasma 102 and the average potential Ec506 of the inner wall of the processing chamber 101.

[0094] Generally, in the processing of a substrate that utilizes plasma formed by capacitive coupling (capacitively coupled plasma or capacitively coupled plasma), if the area of ​​the substrate to which high-frequency power is supplied is set as Ab, the value of the plasma sheath voltage (potential difference) formed on the upper surface of the substrate is set as Vb511, the area of ​​the ground electrode (grounding electrode) facing the plasma inside the processing chamber is set as Ac, and the value of the plasma sheath voltage (potential difference) formed on the ground electrode is set as Vc512, then there is generally a relationship characterized by the formula Vb / Vc=(Ac / Ab)^q, q=1~2.5. In plasma processing equipment, since there is usually an area ratio of Ac / Ab=1.5~3, if it is substituted into the previous formula, it becomes the following formula (4).

[0095] Vb / Vc=β=1.5~15···(4)

[0096] Vdc = -(Vppw / 2) × (1 - 2 / (β+1)) is characterized by the following equation (5) when β = 1.5 to 15, using equations (3) and (4).

[0097] Vdc=-(Vppw / 2)×(0.2~0.88)···(5)

[0098] Equation (5) can be characterized as Vdc = -0.27Vppw ± 0.17Vppw. In this embodiment, -0.27 × Vppw is regarded as the estimated voltage Vdcs of the self-bias, and 0.17 × Vppw is regarded as the estimation error. Since the estimation error increases or decreases proportionally with the value of Vppw, the maximum value of the estimation error becomes the value determined based on Vppwmax, which is the maximum value of Vppw. That is, the difference δmax between the control voltage of the average voltage Eesc406 of the electrostatic chuck and the voltage Eps407 at the bottom of the lifting pin and the potential difference of the actual self-bias voltage Vdc is characterized by the following equation (6).

[0099] 0.17×Vppwmax+“Error caused by control precision”···(6)

[0100] In this embodiment, Vppwmax = 1500V, and the error of ±50V for DC power supply control becomes δmax = 305V. Furthermore, considering the state of the back side of the wafer 107 and the temperature variation caused by the mounting electrode 108, the electrostatic chuck resistance Resc = 20MΩ is set. Equation (1) is calculated, and the result is 100MΩ > Rps > 0.36MΩ. Accordingly, in this embodiment, Rps = 1MΩ is set.

[0101] exist Figure 6 (b) shows the high-frequency potential variations Vppw, Vppp, Vppc and average potentials Ew, Ep, and Ec of the wafer 107, plasma 102, and inner wall of the processing chamber 101 when using such Rps settings. By adjusting the voltage Eps at the bottom of the lifting pin and the average voltage Eesc of the electrostatic chuck, the value of the self-bias voltage Vdc510b can be made to be approximately within a given allowable range that approximates the average potential Ew504b of the wafer 107. Furthermore, it can be seen that the average potential Ec506b of the inner wall of the processing chamber 101 is maintained below the wall's withstand voltage Vt513.

[0102] In the existing technology, the following problem arises: unexpected discharge occurs in the through hole 123 of the lifting pin 124, and a sudden discharge occurs. Figure 2As shown by the conduction 133, the average potential Ew of the wafer 107 increases. In this embodiment, the sudden increase in the average potential Ew of the wafer 107 is suppressed, thereby suppressing the insulation damage of the thermally sprayed film 105, which is made of dielectric material and forms the inner wall of the processing chamber 101 and faces the plasma 102. Therefore, the generation of foreign matter inside the processing chamber 101 is reduced, improving the yield, stability, and reproducibility of the processing.

[0103] Furthermore, by adjusting the average voltage Eesc of the electrostatic chuck electrodes to a value within a given permissible range of the self-bias estimation voltage Vdcs of the wafer 107, the average potential Ew of the wafer 107 and the average voltage Eesc of the electrostatic chuck electrodes become approximate values ​​within permissible ranges. The potential difference between the average potential Ew of the wafer 107 and the respective potentials of the inner electrostatic chuck electrode 115 and the outer electrostatic chuck electrode 116 becomes equal. Compared to the prior art, the difference in the force adsorbing the wafer 107 at the upper surface of the dielectric film 122 above these electrodes is reduced, allowing for precise temperature control of the wafer 107. This improves etching uniformity.

[0104] Alternatively, instead of estimating the self-bias voltage Vdc as described above, a conversion formula for estimating the self-bias voltage Vdc that varies during the etching process can be obtained based on pre-determined measured values. In this case, the value of the difference when the difference between the conversion formula and the actual self-bias voltage Vdc is maximized is used as the maximum value δmax of the potential difference, under the processing conditions used.

[0105] In the plasma treatment apparatus 100 of the above embodiment, the metal outer shell 103 constituting the inner wall of the treatment chamber 101, including the lower part of the treatment chamber 101, is substantially entirely covered with a thermally sprayed film. Furthermore, an anodized coating can be applied to the surface of areas facing low plasma density of the plasma 102 and made of aluminum or its alloy. According to the inventors' research, in this example, initially after the plasma treatment apparatus 100 is used, the resistance Rc between the inner wall surface of the treatment chamber 101 and the grounding electrode is 2 MΩ, but after a long period (100 hours in this example) of plasma treatment, it decreases to Rc = 60 kΩ. Furthermore, the withstand voltage Vt is 110 V.

[0106] Furthermore, the chip 107 in this example is made of silicon, and the electrostatic chuck resistance (Resc) between the bipolar electrostatic chuck electrode and the chip 107 is 2.5 MΩ. The maximum Vppw used is 1000 V.

[0107] Using the formula (1) of the above embodiment to obtain the appropriate lower resistance Rps of the lifting pin, in the case where the lower resistance Rps of the lifting pin is 100MΩ > Rps > 3.2MΩ and the wafer 107 has been processed in the processing chamber 101 for 100 hours, since it becomes 100MΩ > Rps > 42kΩ, the lower resistance Rps of the lifting pin is set to 5MΩ.

[0108] In this example, with the lower resistance Rps of the lifting pin being 5MΩ, the lower voltage Eps of the lifting pin and the average voltage Eesc of the electrostatic chuck being kept constant at 0V and the operation under the condition of Vppw 1000V, a self-bias voltage Vdc of approximately 270V is generated. In this case, according to equation (2), the average potential Ec of the inner wall surface of the processing chamber 101, which is expected to be relatively high at 147V during initial and long-term use, becomes higher than the withstand voltage Vt. There is a possibility that unexpected discharge or conduction may occur between the wafer 107 and the lower part of the lifting pin 124 or the component holding the lifting pin with the upper surface 126, which is a conductive structure, and thus unexpected discharge (abnormal discharge) may occur inside the processing chamber 101.

[0109] Therefore, it is necessary to appropriately adjust the voltage Eps at the bottom of the lifting pin and the average voltage Eesc of the electrostatic chuck. However, after long-term processing as described above, since the resistance Rc between the processing chamber 101 and the ground electrode decreases, the average potential Ec of the inner wall of the processing chamber 101 is expected to be around 9V, and the possibility of abnormal discharge becomes lower. However, if the resistance Rps at the bottom of the lifting pin is lower than the range determined in this example, when unexpected conduction occurs in the through hole 123, the average potential Ec of the inner wall of the processing chamber 101 increases by a corresponding amount equivalent to the self-bias voltage Vdc. Abnormal discharge may occur at the weak voltage withstand location on the inner wall of the processing chamber 101, potentially generating foreign matter on the wafer 107.

[0110] In the above embodiments, a Johnson-Rabec type electrostatic chuck is used, but it can also be replaced by a Coulomb type electrostatic chuck. In the case of the Coulomb type electrostatic chuck, since Resc >> Rc, equation (1) becomes equation (7) as follows.

[0111] 100MΩ>Rps>1 / {(Vt / ((δmax-Vt)Rc))}···(7)

[0112] Furthermore, if the same conditions as in Example 1 are applied, the resistance of the inner wall of the treatment room becomes Rc = 0.2 MΩ, the withstand voltage becomes Vt = 110 V, the maximum value of Vppw becomes Vppwmax = 1500 V, and the error of the DC power supply control becomes 50 V.

[0113] The appropriate value of the lower resistance Rps of the lifting pin is 100MΩ > Rps > 0.355MΩ according to equation (7), which is the same as in Example 1. Similarly to the above example, the case in this example can also be set to Rps = 1MΩ.

[0114] In addition, the voltage Eps at the bottom of the lifting pin and the average voltage Eesc of the electrostatic chuck are set to Vdcs = 0.27 × Vppw, so that they vary according to the magnitude of the first high-frequency power supplied to the chip 107.

[0115] In this example, the average voltage Eesc of the electrostatic chuck electrode does not affect the average potential Ew of the wafer 107 or the average potential Ep of the plasma 102. If the lower resistor Rps of the lifting pin is set as described above, and the lower voltage Eps of the lifting pin is controlled, then even if unexpected conduction occurs inside the through hole 123 housing the lifting pin 124, the rise in the average potential Ew of the wafer 107 can be suppressed. However, in order to eliminate adhesion deviation, it is preferable to adjust the average voltage Eesc of the electrostatic chuck to be consistent with the self-bias voltage Vdc. If the adhesion force has high uniformity in the in-plane direction of the wafer 107, the temperature deviation in the in-plane direction of the wafer 107 will be reduced, and the uniformity and stability of processes such as etching will be improved.

[0116] Furthermore, in the processing of wafer 107, when supplying high-frequency power to substrate 109 by periodically turning the supply of the first high-frequency power on and off at frequencies ranging from several hertz to tens of Hz or higher, the estimated self-bias voltage Vdcs during the period when the first high-frequency power is on is multiplied by the ratio of the on-time to the overall processing period. This value is used as the time-averaged Vdcs value, and the lower voltage Eps of the lifting pin and the average voltage Eesc of the electrostatic chuck electrode are adjusted based on this average Vdcs value. The reason for this is that since the orientation polarization and ion polarization of the dielectric film on the inner wall of processing chamber 101 have a time constant that is slower than the on / off frequency of the time-modulated wafer bias, the potential applied to the inner wall of the processing chamber is averaged through the polarized absorption current.

[0117] Furthermore, the present invention is not limited to the embodiments described above, and includes various modifications. The embodiments have been described in detail for ease of understanding of the invention, but are not necessarily limited to the same conditions of use as described. Moreover, a portion of the structure of one embodiment can be replaced with the structure of another embodiment. Furthermore, the control voltage, set resistance value, withstand voltage, and resistance of the treatment chamber wall are not limited to the examples given in the embodiments.

[0118] exist Figure 7The following chart is shown: under various conditions, such as the resistance Rc of the processing chamber wall being 50kΩ to 1.2MΩ, the control accuracy of the DC power supply being 10 to 50V, the resistance of the electrostatic chuck being 2.5MΩ to 3GΩ, and the withstand voltage of the processing chamber wall being 75V to 125V, in the case of a process using a wafer with a Vppw value up to 1000V, the lower limit value of the required lifting pin lower resistance Rps is obtained by formula (1) and formula (6).

[0119] Figure 7 Each point represents a combination of various parameters. The resistance Rc of the inner wall of the processing chamber is within the range assuming the inner wall is a thermally sprayed film. If the resistance Rc of the inner wall of the processing chamber is calculated to be 1.2 MΩ or higher, then depending on the combination of parameters, regardless of the setting of the resistance below the lifting pin, there is a possibility that the average potential Ec of the inner surface of the inner wall of the processing chamber will exceed the withstand voltage Vt during the etching process. Therefore, the resistance Rc of the inner wall of the processing chamber needs to be designed to be below 1.2 MΩ. It is constrained by the relative magnitude of the electrostatic chuck resistance Resc of the JR method.

[0120] The electrostatic chuck resistance Resc is a range envisioned from the JR method to the Coulomb method. The withstand voltage Vt of the treated interior wall is a range obtained from the results of measuring the withstand voltage Vt in several processes in an apparatus that primarily uses thermally sprayed films and partially uses anodized aluminum films.

[0121] The control accuracy of the DC power supply is generally achievable. For a device within the aforementioned range, setting the resistance value of the lower resistor Rps to 35MΩ or higher (601) will achieve the effect described in this example in processes where Vppw is below 1000V. More preferably, by setting it to 100MΩ > Rps > 35MΩ, the time constant for charge escape from the lower part of the lifting pin 124 can be shortened, and the charging of the lower part of the lifting pin 124 after conduction can be prevented.

[0122] Industrial availability

[0123] The plasma processing apparatus of the present invention can utilize the semiconductor wafer processing apparatus used in the process of manufacturing semiconductor devices.

[0124] Explanation of reference numerals in the attached figures

[0125] 100··· Plasma treatment device,

[0126] 101 Processing Room

[0127] 102··· Plasma,

[0128] 103···Outer shell,

[0129] 104···Top plate,

[0130] 105··· Thermal spray film,

[0131] 106···Anodized film,

[0132] 107··· chip,

[0133] 108···Electrode placement,

[0134] 109···Substrate,

[0135] 110 Voltage Detector

[0136] 111··· Matching Box

[0137] 112···High-frequency power supply,

[0138] 124··· Lifting pin,

[0139] 125··· Sleeve,

[0140] 126··· Lifting pin retainer,

[0141] 127··· Beam section

[0142] 128··· Drive mechanism,

[0143] 129··· Lower resistor of lifting pin,

[0144] 130... Variable DC power supply

[0145] 131···Ground electrode,

[0146] 132...resistance

[0147] 133···Conducting,

[0148] 136··· Corrugated pipe.

Claims

1. A plasma processing apparatus, comprising: The processing chamber, located inside the vacuum container, forms plasma on its inner side; A wafer stage, disposed inside the processing chamber, on which a wafer of the object to be processed is placed; An electrostatic chuck includes a film-shaped electrostatic adsorption electrode disposed within a dielectric film covering the upper surface of the wafer stage and for electrostatically adsorbing the wafer resting on the dielectric film. High-frequency electrodes, disposed within the wafer stage, are supplied with high-frequency power during wafer processing; and A lifting pin, disposed inside the wafer stage, moves vertically to move the wafer vertically, and its lower part is connected to a conductive component. The ratio of the area of ​​the ground electrode disposed inside the processing chamber and facing the plasma to the area of ​​the wafer is 1.5 or more and 3 or less. The plasma processing device is characterized in that... The resistance between the electrostatic adsorption electrode and the wafer is set as Resc; the resistance between the plasma and the grounding electrode separated by the inner wall of the processing chamber is set as Rc; the withstand voltage between the plasma and the vacuum container constituting the processing chamber is set as Vt; the expected maximum value of the difference between the actual self-bias voltage Vdc generated by the wafer during wafer processing and its expected value Vdcs is set as δmax; the amplitude of the potential formed on the wafer by the high-frequency power is set as Vppw; the expected value of the self-bias voltage Vdcs is set as the sum of a given coefficient multiple of Vppw and δmax; and the resistance Rps between the DC power supply and the lower part of the lifting pin electrically connected thereto is set in the range of 100MΩ > Rps > 1 / {(Vt / ((δmax-Vt)·Rc))-(1 / Resc)}. Furthermore, the average potential of the electrostatic adsorption electrode is set as Eesc. During the processing of the wafer, the voltage value Eps at the bottom of the lifting pin and the average potential Eesc of the electrostatic adsorption electrode are adjusted to match the expected value Vdcs of the wafer's self-bias voltage. The δmax is determined based on the maximum value of Vppw.

2. The plasma treatment apparatus according to claim 1, characterized in that, The expected value of the self-bias voltage of the wafer, Vdcs, is set to -0.27×Vppw±δmax, and δmax is set to the maximum value of Vppw, Vppmax×0.17±50.

3. The plasma treatment apparatus according to claim 1 or 2, characterized in that, The expected value of the self-bias voltage, Vdcs, is predetermined as a function of Vpp.

4. The plasma treatment apparatus according to claim 1 or 2, characterized in that, The electrostatic chuck is a bipolar electrostatic chuck.

5. The plasma treatment apparatus according to claim 1 or 2, characterized in that, The inner wall of the processing chamber is made of a dielectric component containing a film.

6. The plasma treatment apparatus according to claim 5, characterized in that, The dielectric component includes an anodized coating. The resistance Rc between the plasma and the grounding electrode separated by the inner wall of the processing chamber is less than 1.2 MΩ, the amplitude value Vppw of the high-frequency power potential is less than 1000 V, and the resistance value Rps is adjusted to 100 MΩ > Rps > 35 MΩ.

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