A Perturbation BGA Pin Arrangement Method for Suppressing Differential Via Crosstalk in Chips

Abstract

The present invention provides a perturbation BGA pin layout method for suppressing differential via crosstalk in a chip. Based on the traditional triangular layout model, this method conducts perturbation analysis on the angle between differential via pairs, the spacing between vias, and the position of ground vias, and establishes a perturbation BGA pin layout model for suppressing differential via crosstalk. Compared with the traditional triangular layout model, the insertion loss crosstalk ratio (ICR) increases by 5 dB in the frequency band range of 30 GHz, and the integrated crosstalk noise (ICN) decreases by 35.58% at a rate of 112 Gbps. The perturbation BGA pin layout model proposed by the present invention can suppress the differential crosstalk between differential pairs, improve the signal integrity, and provide a reference for the BGA pin layout design.

Description

Technical Field

[0001] The present invention relates to the field of system - in - package interconnection design, and more specifically, to a perturbed BGA pin arrangement method for suppressing chip differential via crosstalk. Background Art

[0002] In order to meet the development of emerging applications such as the Internet of Things and artificial intelligence, data communication is also constantly evolving. With the continuous development of data communication, the data rate of serial channels has reached 112 Gbps, and 224 Gbps is also under research. With the continuous improvement of communication rates, channel crosstalk has become one of the key problems that serial links must face. Crosstalk can cause signal timing and logic chaos, affecting the normal function of the circuit, and is one of the core problems of high - speed digital transmission channels. Differential transmission lines have the advantages of strong anti - interference ability, high signal - to - noise ratio, low radiation, and large bandwidth capacity. In order to be applicable to high - speed circuits and reduce the impact of noise, differential signals have become the preferred method for data transmission.

[0003] As the transmission rate reaches 56 / 112 Gbps or higher, the crosstalk between differential pairs also becomes non - negligible, restricting the maximum transmission rate of serial data transmission channels. To suppress the differential crosstalk between high - speed differential vias, the traditional method is to reduce differential crosstalk by adding a shielding ground or increasing the spacing between vias. However, with the continuous rapid development of electronic technology, the integration density of circuits is getting higher and higher. The method of adding a shielding ground is not very applicable to circuit designs with high signal density, such as the design of ball grid array (BGA). Scholar R. Enriquez et al. proposed that the symmetry principle can be used to reduce differential crosstalk. If symmetry is maintained between the differential victim line and the aggressor line, the differential crosstalk is minimized.

[0004] A prior art discloses an optimization method for high - speed differential vias. This invention patent uses the vertical symmetry principle to suppress the differential crosstalk between differential vias in the traditional triangular via arrangement process. Optimization of differential crosstalk has been carried out for differential signal routing, the ratio between signal vias and ground vias, and via stubs on wiring layers in the high - speed BGA package and PCB interconnection area. The optimization result has a very obvious inhibitory effect on differential crosstalk, providing a reference for multi - layer PCB and BGA package design. This patent does not involve proposing a new BGA pin arrangement diagram for reducing differential crosstalk. Summary of the Invention

[0005] The present invention provides a perturbed BGA pin arrangement method for suppressing chip differential via crosstalk, which can suppress the differential crosstalk between differential pairs and improve signal integrity.

[0006] To achieve the above - mentioned technical effects, the technical solution of the present invention is as follows:

[0007] A perturbation BGA pin layout method for suppressing differential via crosstalk in a chip, comprising the following steps:

[0008] S1: Design the via radius of the differential via, the spacing between two vias, and the size of the anti-pad radius;

[0009] S2: First, select a pair of vias in step S1 as the target differential via pair to be optimized. Rotate the differential via and the differential via pairs directly above and below it clockwise by α° around their respective centers, i.e., the center of the line connecting the two vias of the differential via pair. At the same time, rotate the differential via pairs in the upper left, lower left, upper right, and lower right of the target differential via pair counterclockwise by α° around their respective centers;

[0010] S3: Move the two vias in the target differential via pair and the six pairs of differential vias around it towards the center of the line connecting the two vias, so as to reduce the spacing between the two vias in the target differential via pair;

[0011] S4: Translate the ground vias directly above the target differential via pair and the six pairs of differential vias around it towards the direction close to the differential via pair;

[0012] S5: The seven pairs of differential vias and the ground vias around them form a basic unit. By expanding this basic unit up, down, left, and right, a complete perturbation BGA pin layout model for suppressing differential via crosstalk can be obtained.

[0013] Further, the process of step S1 is as follows:

[0014] Using Q2D simulation software, establish a pair of differential vias surrounded by 8 ground vias. Use a dielectric material Megtron7 with a dielectric constant of 3.3 and a tangent loss angle of 0.02. Through simulation, it can be known that when the via radius is 5 mil and the spacing between vias is 0.9 mm, the differential impedance is close to 100 ohms. Then, conduct simulation on the anti-pad radius. When the anti-pad radius is 15 mil, the differential impedance is approximately 100 ohms.

[0015] Further, the process of step S2 is as follows:

[0016] Based on the simulation parameters obtained in step S1, first construct a differential via pair unit and define it as the target differential via pair. Then, establish the unit structures of six pairs of differential via pairs around the target differential via pair. Then, rotate the target differential via pair and the differential via pairs directly above and below it clockwise by α° around their respective centers, denoted as +α, and rotate the differential via pairs in the upper left, lower left, upper right, and lower right counterclockwise by α° around their respective centers, denoted as -α.

[0017] Further, the process of step S3 is as follows:

[0018] In the BGA pin layout structure with the angle perturbation change obtained in step S2, move the two vias in all differential via pairs towards the center of the line connecting the two vias, so that the distance between the two vias in the differential via pair is reduced to d'; through the perturbation analysis of the distance between the two vias in the differential via pair, the smaller the distance between the two vias, the smaller the differential crosstalk effect on the differential via pair.

[0019] Further, the process of step S4 is as follows:

[0020] In the BGA pin layout structure with the angle and via pitch perturbation changes obtained in step S3, translate the ground via directly above all differential via pairs towards the direction close to the target differential via pair. The distance moved in the horizontal axis direction is denoted as a, and the distance moved in the vertical axis direction is denoted as b; through the perturbation analysis of a and b, when the moving distances in both directions are within a very small range, the closer to the corresponding differential via pair, the smaller the crosstalk between the differential via pairs.

[0021] Further, when the moving distances in both directions are within the range of ±5 mil, the closer to the corresponding differential via pair, the smaller the crosstalk between the differential via pairs; when a = b = 5 mil, the crosstalk between the differential via pairs is the smallest.

[0022] Further, the process of step S5 is as follows:

[0023] Regard the layout structure of the seven differential via pairs in step S4 as a basic unit, and expand this basic unit in the plane to form a periodic structure, obtaining a perturbed pin layout model.

[0024] Preferably, α is 20; d' is 0.8 mm.

[0025] Compared with the prior art, the beneficial effects of the technical solution of the present invention are as follows:

[0026] Based on the traditional triangular layout model, the present invention establishes a perturbed BGA pin layout model for suppressing differential via crosstalk through the perturbation analysis of the angle between differential via pairs, the distance between vias, and the position of ground vias. Compared with the traditional triangular layout model, the insertion loss crosstalk ratio (ICR) increases by 5 dB in the frequency band range of 30 GHz, and the integrated crosstalk noise (ICN) decreases by 35.58% at a rate of 112 Gbps. The perturbed BGA pin layout model proposed by the present invention can suppress the differential crosstalk between differential pairs, improve the signal integrity, and provide a reference for the BGA pin layout design. Description of the Drawings

[0027] Figure 1-1The unit structure arranged in a traditional triangular via array established for the present invention;

[0028] Figure 1-2 The top view of the traditional triangular arrangement model established for the present invention (S:G = 1:1.5);

[0029] Figure 2 The top view of the BGA pin arrangement structure after angular perturbation change established for the present invention;

[0030] Figure 3 The top view of the BGA pin arrangement structure after angular and via pitch perturbation changes established for the present invention;

[0031] Figure 4 The top view of the BGA pin arrangement structure after angular, via pitch, and ground via position perturbation changes established for the present invention;

[0032] Figure 5-1 The top view of the final perturbed BGA pin arrangement model established for the present invention;

[0033] Figure 5-2 For the traditional triangular arrangement model ( Figure 1-2 ), and the new perturbed BGA pin arrangement model proposed by the present invention for suppressing differential via crosstalk ( Figure 5-1 ), the curve comparison of insertion loss crosstalk ratio (ICR);

[0034] Figure 5-3 For the traditional triangular arrangement model ( Figure 1-2 ), and the new perturbed BGA pin arrangement model proposed by the present invention for suppressing differential via crosstalk ( Figure 5-1 ), the comparison of integrated crosstalk noise (ICN) (data rate is 112 Gbps). Specific implementation manner

[0035] The accompanying drawings are only for illustrative purposes and should not be construed as limitations on this patent;

[0036] In order to better illustrate this embodiment, some components in the accompanying drawings are omitted, enlarged, or reduced, and do not represent the dimensions of the actual product;

[0037] For those skilled in the art, it is understandable that some well-known structures and their descriptions in the accompanying drawings may be omitted.

[0038] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0039] Embodiment 1

[0040] A method for perturbing BGA pin arrangement to suppress differential via crosstalk in a chip, the specific steps are as follows:

[0041] S1: Design the via radius of the differential via, the spacing between two vias, and the size of the anti-pad radius to enable the differential via to achieve good electrical characteristics;

[0042] S2: Based on the traditional triangular arrangement array (S:G = 1:1.5), first select a pair of vias as the target differential via pair to be optimized. Rotate the differential via and the differential via pairs directly above and below it clockwise by 20° around their respective centers (i.e., the center of the line connecting the two vias of the differential via pair). At the same time, rotate the differential via pairs in the upper left, lower left, upper right, and lower right of the target differential via pair counterclockwise by 20° around their respective centers;

[0043] S3: Move the two vias in the target differential via pair and the two vias in the six pairs of differential vias around it towards the center of the line connecting the two vias to reduce the spacing between the two vias in the target differential via pair;

[0044] S4: Translate the ground vias directly above the target differential via pair and the six pairs of differential vias around it towards the direction close to the differential via pair;

[0045] S5: The seven pairs of differential vias and the ground vias around them form a basic unit. By expanding this basic unit up, down, left, and right, a complete micro-perturbation BGA pin arrangement model for suppressing differential via crosstalk can be obtained.

[0046] The specific process of step S1 is as follows:

[0047] Perform physical modeling on the differential via unit structure of the traditional triangular via arrangement array. The top view of its physical model is as shown in Figure 1-1 and 1-2As shown in the figure. The physical model is constructed in Q2D. 1 is the signal via, 2 is the anti-pad of the model, which consists of two circular anti-pads and one rectangular anti-pad. 3 is the ground via, d is the spacing between adjacent vias, and the spacing length between every two adjacent vias is d. To achieve good electrical performance, appropriate parameters need to be selected to make the impedance of the port close to 100 ohms. The via radius of the differential via, the spacing between two vias, and the size of the anti-pad radius jointly affect the characteristic impedance of the differential via. Among them, the size of the differential via radius and the spacing between two vias play a decisive role in the electrical performance of the differential via, and the influence of the anti-pad radius size is slightly smaller. In the Q2D simulation software, a unit structure model with a traditional triangular via arrangement is established, a pair of differential vias is established, surrounded by 8 ground vias, and the dielectric material Megtron7 with a dielectric constant of 3.3 and a tangent loss angle of 0.02 is used. It can be known from the simulation that when the via radius is 5 mil and the spacing between vias is 0.9 mm, the differential impedance is close to 100 ohms. Then, the simulation of the anti-pad radius is carried out. The simulation results show that when the radius of the anti-pad is 15 mil, the differential impedance is approximately 100 ohms. The parameter simulation of Q2D can make the impedance of the differential via close to 100 ohms and enable the differential via to achieve good electrical characteristics.

[0048] The specific process of step S2 is as follows:

[0049] Based on the various simulation parameters obtained in step S1, a traditional triangular via arrangement array is constructed. First, a differential via pair unit is constructed and designated as the target differential via pair. Then, unit structures of six pairs of differential via pairs are respectively established around the target differential via pair. Then, the target differential via pair and the differential via pairs directly above and below it are rotated clockwise by α° around their respective centers (denoted as +α), and the differential via pairs in the upper left, lower left, upper right, and lower right are rotated counterclockwise by α° around their respective centers (denoted as -α), as Figure 2 shown. The crosstalk of signals is usually caused by inductive coupling and capacitive coupling together, and inductive coupling is the main cause of crosstalk. According to the vertical symmetry principle, when two pairs of differential pairs are in a vertical structure, the differential crosstalk between the differential pairs is the smallest. However, due to process limitations, it is very difficult to make two pairs of differential pairs form a completely vertical structure. Based on the traditional triangular arrangement, the present invention conducts a perturbation analysis on the angle between differential via pairs and establishes a differential via arrangement structure as Figure 2 shown. The dotted line represents the via position before perturbation, and the solid line represents the via position after perturbation. The analysis shows that when the range of angle change is very small (not exceeding 20°), α = 20 can effectively reduce the differential crosstalk between differential pairs. The differential via pairs B - A - C and D - A - E both form a quasi-vertical structure, and this perturbation change can be achieved in the existing process.

[0050] The specific process of step S3 is as follows:

[0051] In the BGA pin layout structure with the angle perturbation change obtained in step S2, move the two vias in all differential via pairs towards the center of the line connecting the two vias, so that the distance between the two vias in the differential via pair is reduced to d'. Through the perturbation analysis of the distance between the two vias in the differential via pair, the smaller the distance between the two vias, the smaller the differential crosstalk effect on the differential via pair. In the traditional triangular via layout array, the distance between the two vias is d = 0.9 mm, and in the present invention, the distance between the vias is reduced to d' = 0.8 mm. As Figure 3 shown, the dotted line represents the via position before perturbation, and the solid line represents the via position after perturbation. This kind of perturbation change can be realized in the existing process and can effectively reduce the differential vias between the differential via pairs.

[0052] The specific process of step S4 is as follows:

[0053] In the BGA pin layout structure with the angle and via pitch perturbation changes obtained in step S3, translate the ground via directly above all differential via pairs towards the direction close to the target differential via pair. The specific moving method is as Figure 4 shown. The dotted line represents the via position before movement, the solid line represents the via position after movement, and the arrow is the direction of via movement. The distance moved in the horizontal axis direction is denoted as a, and the distance moved in the vertical axis direction is denoted as b. Through the perturbation analysis of a and b, when the moving distances in both directions are within a very small range (±5 mil), the closer to the corresponding differential via pair, the smaller the crosstalk between the differential via pairs. That is, when a = b = 5 mil, the crosstalk between the differential via pairs is the smallest. This kind of perturbation change can be realized in the existing process and can effectively reduce the differential vias between the differential via pairs.

[0054] The specific process of step S5 is as follows:

[0055] Expand the structure obtained in step S4 in space to obtain the final perturbed BGA pin layout model, as Figure 5-1 shown. As Figure 5-2 shown, compare the insertion loss crosstalk ratio (ICR) of the traditional triangular layout model ( Figure 1-2 ) and the perturbed BGA pin layout model proposed in the present invention ( Figure 5-1 ) in the frequency domain. The results in the figure show that in the frequency band range of 30 GHz, the value of the insertion loss crosstalk ratio (ICR) of the perturbed BGA pin layout model proposed in the present invention is larger. Further, according to the calculation standard of the integrated crosstalk noise (ICN), compare the perturbed BGA pin layout model proposed in the present invention with the traditional triangular layout model at a rate of 112 Gbps, as Figure 5-3In the 30 GHz frequency band, the integrated crosstalk noise ICN of the traditional triangular arrangement model is 3.8349 mV, while the integrated crosstalk noise ICN of the new differential via perturbation optimization arrangement model proposed by the present invention is 2.4705 mV, which is less than the integrated noise of the traditional triangular arrangement model, a reduction of 35.58%.

[0056] Based on the above description, compared with the traditional triangular arrangement model, the perturbation BGA pin arrangement model proposed by the present invention can effectively suppress differential crosstalk and has better signal integrity characteristics, providing technical guidance for BGA pin arrangement design.

[0057] Embodiment 2

[0058] As Figure 1-1 and 1-2 shown, a method for arranging perturbation BGA pins to suppress differential via crosstalk in a chip includes the following steps:

[0059] S1: Design the via radius of the differential via, the distance between two vias, and the size of the anti-pad radius;

[0060] S2: First, select a pair of vias in step S1 as the target differential via pair to be optimized, and rotate the differential via and the differential via pairs directly above and below it clockwise by α° around their respective centers, i.e., the center of the line connecting the two vias of the differential via pair; at the same time, rotate the differential via pairs in the upper left, lower left, upper right, and lower right of the target differential via pair counterclockwise by α° around their respective centers;

[0061] S3: Move the two vias in the target differential via pair and the six pairs of differential vias around it towards the center of the line connecting the two vias, reducing the distance between the two vias in the target differential via pair;

[0062] S4: Translate the ground via directly above the target differential via pair and the six pairs of differential vias around it towards the direction close to the differential via pair;

[0063] S5: The seven pairs of differential vias and the ground vias around them form a basic unit, and the complete perturbation BGA pin arrangement model for suppressing differential via crosstalk can be obtained by expanding this basic unit up, down, left, and right.

[0064] The process of step S1 is:

[0065] Using Q2D simulation software, a pair of differential vias are established, surrounded by 8 ground vias. The dielectric material Megtron7 with a dielectric constant of 3.3 and a tangent loss angle of 0.02 is used. Through simulation, it can be known that when the via radius is 5 mil and the distance between vias is 0.9 mm, the differential impedance is close to 100 ohms. Then, the simulation of the anti-pad radius is carried out. When the radius of the anti-pad is 15 mil, the differential impedance is approximately 100 ohms.

[0066] The process of step S2 is as follows:

[0067] Based on the various simulation parameters obtained in step S1, first construct a differential via pair unit and define it as the target differential via pair. Then, respectively establish the unit structures of six pairs of differential via pairs around the target differential via pair. Then, rotate the target differential via pair and the differential via pairs directly above and below it clockwise by α° around their respective centers, denoted as +α, and rotate the differential via pairs in the upper left, lower left, upper right, and lower right of the target differential via pair counterclockwise by α° around their respective centers, denoted as -α.

[0068] Embodiment 3

[0069] As Figure 1-1 and 1-2 shown, a micro-perturbation BGA pin layout method for suppressing differential via crosstalk in a chip includes the following steps:

[0070] S1: Design the via radius of the differential via, the distance between two vias, and the size of the anti-pad radius;

[0071] S2: First, select a pair of vias in step S1 as the optimized target differential via pair, and rotate the differential via and the differential via pairs directly above and below it clockwise by α° around their respective centers, i.e., the center of the line connecting the two vias of the differential via pair; at the same time, rotate the differential via pairs in the upper left, lower left, upper right, and lower right of the target differential via pair counterclockwise by α° around their respective centers;

[0072] S3: Move the two vias in the target differential via pair and the two vias in the six pairs of differential via pairs around it towards the center of the line connecting the two vias, so as to reduce the distance between the two vias in the target differential via pair;

[0073] S4: Translate the ground vias directly above the target differential via pair and the six pairs of differential via pairs around it towards the direction close to the differential via pair;

[0074] S5: The seven pairs of differential via pairs and the ground vias around them form a basic unit, and expanding this basic unit up, down, left, and right can obtain a complete micro-perturbation BGA pin layout model for suppressing differential via crosstalk.

[0075] The process of step S1 is as follows:

[0076] Using Q2D simulation software, a pair of differential vias is established, surrounded by 8 ground vias. The dielectric material Megtron7 with a dielectric constant of 3.3 and a tangent loss angle of 0.02 is used. It can be known from the simulation that when the via radius is 5 mil and the distance between vias is 0.9 mm, the differential impedance is close to 100 ohms. Then, the simulation of the anti-pad radius is carried out. When the radius of the anti-pad is 15 mil, the differential impedance is approximately 100 ohms.

[0077] The process of step S2 is as follows:

[0078] Based on the various simulation parameters obtained in step S1, first, a differential via pair unit is constructed and designated as the target differential via pair. Then, six pairs of differential via pair unit structures are established around the target differential via pair. Then, the target differential via pair and the differential via pairs directly above and below it are rotated clockwise by α° around their respective centers, denoted as +α, and the differential via pairs in the upper left, lower left, upper right, and lower right are rotated counterclockwise by α° around their respective centers, denoted as -α.

[0079] The process of step S3 is as follows:

[0080] In the BGA pin layout structure after the angular perturbation change obtained in step S2, the two vias in all differential via pairs are moved towards the center of the line connecting the two vias, so that the distance between the two vias in the differential via pair is reduced to d'. Through the perturbation analysis of the distance between the two vias in the differential via pair, the smaller the distance between the two vias, the smaller the differential crosstalk effect on the differential via pair.

[0081] The process of step S4 is as follows:

[0082] In the BGA pin layout structure after the angular and via pitch perturbation changes obtained in step S3, the ground vias directly above all differential via pairs are translated towards the direction close to the target differential via pair. The distance moved in the horizontal axis direction is denoted as a, and the distance moved in the vertical axis direction is denoted as b. Through the perturbation analysis of a and b, when the moving distances in the two directions are within a very small range, the closer to the corresponding differential via pair, the smaller the crosstalk between the differential via pairs.

[0083] When the moving distances in the two directions are within the range of ±5 mil, the closer to the corresponding differential via pair, the smaller the crosstalk between the differential via pairs. When a = b = 5 mil, the crosstalk between the differential via pairs is the smallest.

[0084] The process of step S5 is as follows:

[0085] Regarding the seven pairs of differential via arrangement structures in step S4 as a basic unit, expanding this basic unit in the plane to form a periodic structure, a perturbed pin arrangement model is obtained.

[0086] As Figure 5-1 and 5-2 shown, the insertion loss crosstalk ratio (ICR) of the traditional triangular arrangement model ( Figure 1-2 ) and the perturbed BGA pin arrangement model proposed by the present invention ( Figure 5-1 ) is compared in the frequency domain. The results in the figure show that in the frequency band range of 30 GHz, the value of the insertion loss crosstalk ratio (ICR) of the perturbed BGA pin arrangement model proposed by the present invention is larger. Further, according to the calculation standard of integrated crosstalk noise (ICN), at a rate of 112 Gbps, the perturbed BGA pin arrangement model proposed by the present invention is compared with the traditional triangular arrangement model. As Figure 5-3 shown, in the frequency band range of 30 GHz, the integrated crosstalk noise ICN of the traditional triangular arrangement model is 3.8349 mV, and the integrated crosstalk noise ICN of the new differential via perturbation optimization arrangement model proposed by the present invention is 2.4705 mV, which is less than the integrated noise of the traditional triangular arrangement model, reducing by 35.58%.

[0087] α is 20; the d' is 0.8 mm.

[0088] The same or similar reference numerals correspond to the same or similar components;

[0089] The positional relationships described in the drawings are for illustrative purposes only and should not be construed as limitations on this patent;

[0090] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A perturbation BGA pin layout method for suppressing differential via crosstalk in a chip, characterized in that, It includes the following steps: S1: Design the via radius of differential vias, the spacing between two vias, and the size of the anti-pad radius; S2: First, select a pair of vias in step S1 as the target differential via pair to be optimized. Rotate the differential via and the differential via pairs directly above and below it clockwise by α° around the center of the two vias in the differential via pair, that is, the center of the line connecting the two vias in the differential via pair; at the same time, rotate the differential via pairs in the upper left, lower left, upper right, and lower right of the target differential via pair counterclockwise by α° around their respective centers; S3: Move the two vias in the target differential via pair and the six pairs of differential vias around it towards the center of the line connecting the two vias to reduce the spacing between the two vias in the target differential via pair; S4: Translate the ground vias directly above the target differential via pair and the six pairs of differential vias around it towards the direction close to the differential via pair; S5: Seven pairs of differential vias and the ground vias around them form a basic unit. By expanding this basic unit up, down, left, and right, a complete micro-perturbation BGA pin layout model for suppressing differential via crosstalk can be obtained.

2. The perturbation BGA pin layout method for suppressing differential via crosstalk of a chip according to claim 1, wherein The process of step S1 is as follows: Using Q2D simulation software, establish a pair of differential vias surrounded by 8 ground vias. Use the dielectric material Megtron7 with a dielectric constant of 3.3 and a tangent loss angle of 0.02; through simulation, it can be known that when the via radius is 5 mil and the spacing between vias is 0.9 mm, the differential impedance is close to 100 ohms; then conduct the simulation of the anti-pad radius. When the radius of the anti-pad is 15 mil, the differential impedance is approximately 100 ohms.

3. The perturbation BGA pin layout method for suppressing differential via crosstalk of a chip according to claim 2, wherein The process of step S2 is as follows: Based on the various simulation parameters obtained in step S1, first construct a differential via pair unit and define it as the target differential via pair; then respectively establish the unit structures of six pairs of differential vias around the target differential via pair; then rotate the target differential via pair and the differential via pairs directly above and below it clockwise by α° around their respective centers, denoted as +α, and rotate the differential via pairs in the upper left, lower left, upper right, and lower right counterclockwise by α° around their respective centers, denoted as -α.

4. The perturbation BGA pin layout method for suppressing differential via crosstalk of a chip according to claim 3, wherein The α is 20.

5. The perturbation BGA pin layout method for suppressing differential via crosstalk of a chip according to claim 4, characterized in that The process of step S3 is as follows: In the BGA pin layout structure after the angular perturbation change obtained in step S2, move the two vias in all differential via pairs towards the center of the line connecting the two vias to reduce the spacing between the two vias in the differential via pair to d'; through the perturbation analysis of the spacing between the two vias in the differential via pair, the smaller the spacing between the two vias, the smaller the influence of differential crosstalk on the differential via pair.

6. The perturbation BGA pin layout method for suppressing differential via crosstalk of a chip, as described in claim 5, is characterized in that The d' is 0.8 mm.

7. The micro-perturbation BGA pin layout method for suppressing differential via crosstalk of a chip according to claim 6, wherein The process of step S4 is as follows: In the BGA pin layout structure after the angular and via spacing perturbation changes obtained in step S3, translate the ground vias directly above all differential via pairs towards the direction close to the target differential via pair. The moving distance in the horizontal axis direction is denoted as a, and the moving distance in the vertical axis direction is denoted as b; through the perturbation analysis of a and b, when the moving distances in both directions are within a very small range, the closer to the corresponding differential via pair, the smaller the crosstalk between differential via pairs.

8. The perturbation BGA pin layout method for suppressing differential via crosstalk of a chip according to claim 7, wherein When the moving distances in both directions are within the range of ±5 mil, the closer to the corresponding differential via pair, the smaller the crosstalk between the differential via pairs.

9. The perturbation BGA pin layout method for suppressing differential via crosstalk of a chip according to claim 8, wherein When a = b = 5 mil, the crosstalk between the differential via pairs is the smallest.

10. The method for perturbing BGA pin layout to suppress differential via crosstalk of a chip according to claim 8, wherein The process of step S5 is as follows: Regard the seven pairs of differential via layout structures in step S4 as a basic unit, expand this basic unit in the plane to form a periodic structure, and obtain a perturbed pin layout model.

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