Method for operating a memory, memory, and memory system

Abstract

Embodiments of the present disclosure provide an operation method, a memory, and a memory system for a memory. The memory includes a memory cell array composed of a plurality of memory blocks, and each of the memory blocks includes at least a plurality of memory strings and a plurality of word lines coupled to the memory strings; the operation method includes: applying an erase voltage to the memory block to be erased during a first period; turning on top select transistors and bottom select transistors of the respective memory strings in the memory block to be erased during a second period after the first period, so that charges in channels of the erased memory strings are released from both ends of the memory strings; and performing an erase verification operation on the memory block.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, an operation method of a memory, a memory, and a memory system. Background Art

[0002] A flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. The flash memory includes a NOR flash memory and a NAND flash memory. The gate of a flash memory cell has a structure including a tunnel insulating layer, a floating gate electrode, a dielectric layer, and a control gate. Since the non-volatile solid-state memory can still store data after the power supply is cut off, if data needs to be deleted, a special erasing operation is required to achieve this. The erasing operation is to apply a voltage between the gate and the substrate of the flash memory cell, so that the charges stored in the floating gate electrode are released, thereby changing the threshold voltage of the storage cell, and thus achieving the purpose of data erasing.

[0003] However, after performing an erasing operation on a storage cell, the charges remaining in the channel often interfere with the subsequent reading and writing of data. Therefore, how to clean up the remaining charges after erasing is an important operation for memory control. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide an operation method of a memory, a memory, and a memory system.

[0005] In a first aspect, embodiments of the present disclosure provide an operation method of a memory. The memory includes a storage cell array composed of a plurality of storage blocks, and each storage block includes at least a plurality of storage strings and a plurality of word lines coupled to the storage strings. The method includes:

[0006] Applying an erasing voltage to the storage block to be erased during a first time period;

[0007] During a second time period after the first time period, turning on the top selection transistor and the bottom selection transistor of each storage string in the storage block to be erased, so that the charges in the channels of the erased storage strings are released from both ends of the storage string;

[0008] Performing an erasing verification operation on the storage block.

[0009] In some embodiments, during the second time period after the first time period, turning on the top selection transistor and the bottom selection transistor of each storage string in the storage block to be erased includes:

[0010] Applying a first turn-on voltage to the top selection gate line in the storage block; wherein the top selection gate line is connected to the control electrode of the top selection transistor;

[0011] Apply a second turn-on voltage to the bottom select gate line in the memory block; wherein, the bottom select gate line is connected to the control electrode of the bottom select transistor

[0012] During the second period, simultaneously apply a first strobe voltage to the first strobe switch connected to the top select gate line and the second strobe switch connected to the bottom select gate line, so that the first turn-on voltage is applied to the top select transistor and the second turn-on voltage is applied to the bottom select transistor.

[0013] In some embodiments, the first turn-on voltage is equal to the second turn-on voltage.

[0014] In some embodiments, the method further includes:

[0015] During a first period, apply a second strobe voltage to the first strobe switch and the second strobe switch; the second strobe voltage is less than the first strobe voltage.

[0016] In some embodiments, the method further includes:

[0017] During the second period, turn on the discharge path in the page buffer coupled to the corresponding bit line of the memory string.

[0018] In some embodiments, turning on the discharge path in the page buffer coupled to the corresponding bit line of the memory string includes:

[0019] Apply a third turn-on voltage to the control switch in the discharge path of the page buffer coupled to the bit line.

[0020] In some embodiments, the method further includes:

[0021] During the second period, apply a cut-off voltage to the control switch between the bit line and the sense node in the page buffer to disconnect the pre-charge path and the path between the latches in the page buffer.

[0022] In some embodiments, applying an erase voltage to the memory block to be erased during the first period includes:

[0023] During the first period, apply a ground voltage to each word line of the memory block to be erased;

[0024] Simultaneously apply the erase voltage to each bit line or source line of the memory block to be erased.

[0025] In some embodiments, the method further includes:

[0026] During the second period, switch the erase voltage applied to each bit line or source line to a ground voltage.

[0027] In some embodiments, performing an erase verification operation on the memory block includes:

[0028] Applying an erase verification voltage to a selected word line on the memory block; wherein the selected word line is any word line on the memory block;

[0029] Applying an activation voltage to unselected word lines on the memory block; wherein the activation voltage is greater than or equal to the maximum threshold voltage of the memory cells; the erase verification voltage is less than the activation voltage;

[0030] Reading the memory cells corresponding to the selected word line to obtain a verification result of the erase verification operation.

[0031] In a second aspect, an embodiment of the present disclosure provides a memory, which includes:

[0032] A peripheral circuit and a memory cell array composed of a plurality of memory blocks;

[0033] Wherein, the peripheral circuit is at least configured to execute the operation method described in any of the above embodiments.

[0034] In a third aspect, an embodiment of the present disclosure provides a memory system, which includes:

[0035] A memory and a controller;

[0036] The memory at least includes a peripheral circuit and a memory cell array composed of a plurality of memory blocks; the peripheral circuit is at least configured to execute the operation method described in any of the above embodiments.

[0037] For the operation method of the memory provided by the embodiments of the present disclosure, in the process of erasing the memory block, the method of simultaneously turning on the top selection transistor and the bottom selection transistor is adopted for the problem of channel charge residue, so that the channel charge can be released from both ends of the channel, thereby reducing the channel charge residue after erasure, and further reducing the problem of subsequent read errors caused by the channel charge raising the channel potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic structural diagram of an exemplary system provided by an embodiment of the present disclosure;

[0039] Figure 2 It is a schematic structural diagram of a memory card provided by an embodiment of the present disclosure;

[0040] Figure 3 It is a schematic structural diagram of a solid state drive (SSD) provided by an embodiment of the present disclosure;

[0041] Figure 4Schematic diagram of a memory including a memory cell array and a peripheral circuit provided by an embodiment of the present disclosure;

[0042] Figure 5 Schematic diagram of a memory provided by an embodiment of the present disclosure;

[0043] Figure 6 Schematic diagram of a page buffer in a peripheral circuit of a memory provided by an embodiment of the present disclosure;

[0044] Figure 7 Schematic diagram of a memory string in a memory provided by an embodiment of the present disclosure;

[0045] Figure 8 Schematic diagram of a word line and a common word line in a memory provided by an embodiment of the present disclosure;

[0046] Figure 9 Schematic diagram of the principle of controlling the release of channel charge by a top selection transistor and a bottom selection transistor of a memory string in a memory provided by an embodiment of the present disclosure;

[0047] Figure 10 Schematic diagram of a waveform of an erase operation of a memory provided by an embodiment of the present disclosure;

[0048] Figure 11 Flowchart of an operation method of a memory provided by an embodiment of the present disclosure;

[0049] Figure 12 Schematic diagram of a waveform of an erase operation in an operation method of a memory provided by an embodiment of the present disclosure;

[0050] Figure 13 Schematic diagram of the control switch state of a page buffer in an operation method of a memory provided by an embodiment of the present disclosure;

[0051] Figure 14 Schematic diagram of the state distribution of memory cells in a memory provided by an embodiment of the present disclosure;

[0052] Figure 15 Schematic diagram of a memory provided by an embodiment of the present disclosure;

[0053] Figure 16 Schematic diagram of a memory system provided by an embodiment of the present disclosure. Detailed implementation manners

[0054] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this disclosure belongs. The terms used herein in the specification of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0056] As Figure 1 shown, an exemplary system 10 is shown in an embodiment of the present disclosure. The exemplary system 10 may include a host 20 and a storage system 30. Among them, the exemplary system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory 34; the host 20 may be a processor (e.g., a central processing unit (CPU)) of an electronic device or a system on a chip (SoC) (e.g., an application processor (AP)).

[0057] In an embodiment of the present disclosure, the host 20 may be configured to send data to or receive data from the storage system 30. Here, the storage system 30 may include a controller 32 and one or more memories 34. Among them, the memory 34 may include, but is not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc.

[0058] On the other hand, the controller 32 may be coupled to the memory 34 and the host 20 and is used to control the memory 34. Exemplarily, the controller may be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller may also be designed to operate in a high duty cycle environment, such as a Solid State Drive (SSD) or an embedded multimedia card (eMMC), where the SSD or eMMC is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays. Further, the controller may manage the data in the memory and communicate with the host. The controller may be configured to control operations such as memory read, erase, and program; may also be configured to manage various functions regarding the data stored in or to be stored in the memory, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc.; may also be configured to process the error correction code (ECC) regarding the data read from or written to the memory. In addition, the controller may also perform any other suitable functions, such as formatting the memory, or communicating with external devices according to a specific communication protocol (for example, Figure 1communicate with the host 20). Exemplarily, the controller can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0059] In the embodiments of the present disclosure, the controller and one or more memories can be integrated into various types of storage devices. For example, they can be included in the same package (such as Universal Flash Storage (UFS) package or eMMC package). That is to say, the storage system can be implemented and packaged into different types of terminal electronic products. As Figure 2 shown, the controller 32 and a single memory 34 can be integrated into the memory card 40. The memory card 40 can include PC Card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 40 can also include a memory card connector 42 that couples the memory card 40 to a host (such as, Figure 1 the host 20 in Figure 3 In another embodiment shown in Figure 1 the controller 32 and multiple memories 34 can be integrated into the SSD 50. The SSD 50 can also include an SSD connector 52 that couples the SSD 50 to a host (such as, Figure 1 the host 20 in

[0060] It should be noted that the memory involved in the embodiments of the present disclosure can be a semiconductor memory, which is a solid-state electronic device for storing data information made by semiconductor integrated circuit technology. Exemplarily, Figure 4 is a schematic diagram of an optional memory 60 in the embodiments of the present disclosure. Among them, the memory 60 can be Figures 1 to 3 the memory 34 in Figure 4As shown, the memory 60 may be composed of a memory cell array 62 and a peripheral circuit 64 coupled to the memory cell array 62, etc. Here, the memory cell array may be a NAND flash memory cell array, where the memory cells are provided in the form of an array of NAND memory strings 66, and each NAND memory string 66 extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 66 may include a plurality of memory cells coupled in series and vertically stacked. Among them, each memory cell holds a continuous analog value, for example, a voltage or a charge, which depends on the number of electrons captured within the memory cell region. Additionally, each memory cell in the above-mentioned memory cell array 62 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0061] In the embodiments of the present disclosure, the above-mentioned memory cell may be a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, the first storage state "0" may correspond to a first voltage range, and the second storage state "1" may correspond to a second voltage range. In some other embodiments, each memory cell is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to take a range of possible nominal storage values. Exemplarily, if each MLC stores two bits of data, the MLC may be programmed to take one of three possible programmed levels from an erased state by writing one of three possible nominal storage values into the memory cell. Among them, the fourth nominal storage value may be used for the erased state.

[0062] In the embodiments of the present disclosure, the above-mentioned peripheral circuit can be coupled to the memory cell array through bit lines (BL), word lines (WL), source lines, source select gates (SSG), and drain select gates (DSG). Here, the peripheral circuit can include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory cell array by applying voltage signals and / or current signals to each target memory cell and sensing voltage signals and / or current signals from each target memory cell via the bit lines, word lines, sources, SSGs, and DSGs. In addition. The peripheral circuit can also include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. Exemplarily, as Figure 5 shown. The peripheral circuit 70 includes a page buffer / sense amplifier 71, a column decoder / bit line driver 72, a row decoder / word line driver 73, a voltage generator 74, a control logic unit 75, a register 76, an interface 77, and a data bus 78. It should be understood that the above-mentioned peripheral circuit 70 can be the same as the Figure 4 peripheral circuit 64, and in some other embodiments, the peripheral circuit 70 can also include Figure 5 additional peripheral circuits not shown in

[0063] As Figure 6 shown, an embodiment of the present disclosure shows a page buffer 90. The page buffer 90 can be coupled to the memory cell array 80 via the bit line BL. Each page buffer includes a register bank 91 connected through a bit line bias switch VBL BIAS and a discharge path connected to the ground through a discharge switch VBL DISCH . In addition, at least one sense node can be included in the page buffer between the above-mentioned register bank and the word line. As Figure 6 shown, the page buffer 90 includes a sense node SO and a sense node SO2, and a selection transistor VSO BLK is also included between the two sense nodes. Additionally, the page buffer can also include a bit line switch V PASS between the bit lines for controlling whether the entire page buffer is connected to the bit lines.

[0064] In the embodiments of the present disclosure, the memory cell array can be composed of, such as Figure 7The storage string 700 shown is formed by connecting a plurality of memory cell stacks with a channel 720 perpendicular to the substrate 710. The word line 730 is perpendicular to the channel and can surround the channel for use as a gate electrode of the memory cell. The storage structure 740 between the gate electrode of the memory cell and the channel at least includes a tunneling layer 741, a storage layer 742 (charge trapping layer), and a blocking layer 743, etc. This storage structure generally can be a tunneling layer containing silicon oxide, a storage layer containing silicon nitride, and a blocking layer containing silicon oxide, that is, the so-called ONO structure.

[0065] Each memory cell can be in an erased state or a programmed state, and there can be multiple programmed states. The erased state is used to represent the original state where the memory cell has not been programmed, or the state where no data is stored, and can also be understood as the stored data being "0"; the programmed state is used to represent the state where different data is stored. For example, for the above-mentioned SLC memory cells, which can store 1 bit of data, only one erased state is needed to represent the data "0", and one programmed state to represent the data "1". For the above-mentioned MLC memory cells, which can store 2 bits of data, one erased state is needed to represent the data "00", and three programmed states to represent the data "01", "10", and "11".

[0066] The above-mentioned erased state and programmed state are essentially reflected by the threshold voltage of the memory cell. Since the memory cell with the ONO structure can achieve charge trapping, by applying a voltage between the gate electrode and the channel, the tunneling effect can be used to make the charge pass through the tunneling layer to reach the storage layer, that is, the charge trapping layer, so that the charge is trapped in the storage layer. The change in the amount of charge in the storage layer will cause a change in the threshold voltage of this memory cell. Therefore, if data is to be stored in the memory cell, corresponding charge can be injected into the storage layer to achieve it. Here, the process of injecting charge can be called "programming", that is, by programming, the state of the memory cell is adjusted from the erased state to different programmed states.

[0067] Correspondingly, if the data in the memory cell is to be erased, that is, to restore it from the programmed state to the erased state, a process opposite to programming needs to be adopted. Apply an opposite voltage between the gate electrode and the channel, and use the tunneling effect to make the charge trapped in the storage layer pass through the tunneling layer back to the channel, thereby releasing the charge in the storage layer and making the threshold voltage of the memory cell return to the range where the erased state is located.

[0068] In the embodiments of the present disclosure, the memory cell array of the above-mentioned memory may be composed of multiple memory blocks (blocks), each memory block having a source electrode. The bottom of the channel of each memory string in the memory block may be connected to the SL of the source electrode through a doped region in the substrate, and the top of the memory string is connected to the BL. A memory block is the smallest unit of an erase operation. When performing an erase, a high voltage may be applied to the SL or the BL, and at the same time, the channel of the memory string is maintained in a non-conducting state. For example, a voltage of 0V is applied to the word lines of each memory cell on the memory string. At this time, the high voltage of the BL or the SL will be coupled to the channel, raising the voltage of the channel, so that the charge stored in the storage layer tunnels into the channel, thereby achieving erasure.

[0069] In some embodiments, after applying the erase voltage, a verification process may be used to confirm whether the erase is successful. The principle of the verification process is similar to that of a read operation. For example, a verification voltage in the erased state is applied to the WL corresponding to the memory cell to be verified (which can be referred to as the selected word line, Sel Blk WL), and a pass voltage Vpass is applied to other WLs (unselected word lines), and then reading is performed through the BL. If a voltage is read, that is, the memory cell is conducting, it means that the threshold voltage of the memory cell is less than the verification voltage, that is, the memory cell has been successfully erased. If no voltage is read, that is, the memory cell is not conducting, it means that the threshold voltage of the memory cell is greater than the verification voltage, that is, the memory cell has not been successfully erased.

[0070] However, it can be understood that since the charge in the storage layer returns to the channel after erasure, and the channel is substantially non-conducting, therefore, these charges will affect subsequent reading or other operations. Therefore, after erasure, the charge in the channel also needs to be released to ensure that subsequent operations are not affected.

[0071] For the above verification process, since there is residual charge in the channel, the channel discharges at the beginning of the verification. At this time, the current generated by the discharge will have a coupling effect on the selected word line, causing the voltage of the selected word line to be pulled down, even reaching a negative voltage. And since each word line of the memory block is also coupled to a common word line (LWL, Local Word Line), as Figure 8 shown. The pulling down of the above-mentioned selected word line SEL_WL will cause the voltage of the unselected word line UNSEL_WL to leak, and then cause a threshold voltage shift after the verification is completed, and subsequent read operations will have errors.

[0072] In some embodiments, the method of turning on the bottom select gate (BSG) of the memory string may be adopted to make the channel partially conducting. As Figure 9As shown, by raising the voltage of SD Vg (String Driver Gate), the BSG voltage is raised after erasure. Here, SD Vg is a switch used to control whether a voltage is applied to the string selection lines of each memory string in the memory block. When SD Vg is turned on, the voltage signals applied to the BSG line and the TSG line are loaded onto the control gate of BSG and the control gate of TSG. As Figure 10 shown, SD Vg is maintained at 6V during the preparation stage and the erasure stage. During the erasure stage, an erasure voltage Vers is applied to the BL or SL, causing the voltages of BSG and TSG to be coupled from the low voltage vss to a relatively high voltage. When the application of the erasure voltage ends and enters the recovery stage, the voltages of BSG and TSG drop, such as to about 3V. At this time, if the voltage of SD Vg is raised to 15V, then TSG and BSG will be gated. Since Figure 9 shown, a 6V voltage is applied to BSG, while a 0V voltage is applied to TSG, so BSG is reopened for the purpose of discharging, while TSG remains in the off state.

[0073] Since BSG is located at the bottom of the memory string, by opening one end of BSG for channel discharge, charges can flow quickly to the substrate for subsequent erasure verification operations.

[0074] However, as the number of memory layers increases, it may be difficult to meet the discharge requirements after erasure only by opening BSG, requiring a longer discharge duration, and there is still likely to be charge residue, resulting in the above abnormalities after erasure verification.

[0075] Therefore, as Figure 11 shown, the embodiments of the present disclosure provide an operation method for a memory. The memory includes a memory cell array composed of a plurality of memory blocks, and each memory block includes at least a plurality of memory strings and a plurality of word lines coupled to the memory strings; including:

[0076] Step S101: Apply an erasure voltage to the memory block to be erased during a first time period;

[0077] Step S102: During a second time period after the first time period, turn on the top selection transistor and the bottom selection transistor of each memory string in the memory block to be erased, so that the charges in the channels of the erased memory strings are released from both ends of the memory strings;

[0078] Step S103: Perform an erasure verification operation on the memory block.

[0079] In the embodiments of the present disclosure, after applying the erasure voltage to the memory block, the top selection transistor and the bottom selection transistor can be turned on simultaneously, so that the charges in the channel are released from both ends of the channel, thereby accelerating the discharge speed and further reducing the residual charges, making the discharge more sufficient.

[0080] In some embodiments, in the above step S101, applying an erase voltage to the memory block to be erased includes:

[0081] Applying an erase voltage to the source of the memory block to be erased while floating the bit lines connected to the corresponding memory strings; or applying an erase voltage to each bit line of the memory block to be erased while floating the source; or alternatively, applying an erase voltage to both the source and each bit line of the memory block simultaneously.

[0082] During the erasing process, applying an erase voltage to the source means applying a high-level voltage to the above-mentioned SL. At this time, the BL can be floated. In this way, the channel of the entire memory string is not conducting, but it will be coupled to the high level under the action of the high-level voltage of the SL, thereby generating a voltage difference between the gate (word line) of each memory cell. Similarly, an erase voltage can also be applied to the bit line, that is, applying a high-level voltage to the BL while floating the source SL, so that the channel is coupled to the high level to achieve the erasure of the memory block. In addition, an erase voltage can also be applied to both the BL and the SL simultaneously to overall raise the potential of the channel to the high level, thereby achieving the erasure of the memory block.

[0083] It can be understood that applying an erase voltage to the memory block to be erased can be a high voltage applied to the BL or the SL. During this process, the floating channel is coupled to the high level, and at the same time, the TSG and the BSG may be coupled from the low-level state to the high-level state. Other WLs can be grounded or provided with a low voltage. The holes in the P+(P-type heavily doped) polysilicon enter the channel under the action of the electric field, and then enter the storage layer based on the electric field generated by the voltage difference between the WL and the channel, and neutralize the electrons in the storage layer, thereby achieving the erasing effect.

[0084] After this process ends, the application of the erase voltage is stopped, so that the holes stop entering the storage layer continuously. At this time, there will be a large number of residual holes in the channel.

[0085] Therefore, through the above step S102, the top selection transistor and the bottom selection transistor of the memory string are turned on, so that the residual charges can be released.

[0086] In some embodiments, in the above step S102, within a second time period after the first time period, turning on the top selection transistor and the bottom selection transistor of each memory string in the memory block includes:

[0087] Applying a first turn-on voltage to the top selection gate line in the memory block; wherein, the top selection gate line is connected to the control electrode of the top selection transistor;

[0088] Applying a second turn-on voltage to the bottom selection gate line in the memory block; wherein, the bottom selection gate line is connected to the control electrode of the bottom selection transistor;

[0089] During a second time period, a strobe voltage is simultaneously applied to a first strobe switch connected to the top selection gate line and a second strobe switch connected to the bottom selection gate line, so that the first turn-on voltage is applied to the top selection transistor, and the second turn-on voltage is applied to the bottom selection transistor.

[0090] The memory block is composed of a multi-layer stacked structure. Among them, the alternately stacked conductive layers and insulating layers are distributed in a plane perpendicular to the direction of the memory string channel. Each conductive layer can be used as a word line of the memory cell to control the memory cell of the ONO structure located on the sidewall of the channel. The conductive layer at the top of the stacked structure is the top selection gate line TSG, and the conductive layer at the bottom of the stacked structure is the bottom selection gate line BSG, as Figure 9 shown.

[0091] In some embodiments, during a second time period, a first turn-on voltage V1 and a second turn-on voltage V2 can be respectively applied to the top selection gate line TSG and the bottom selection gate line BSG, so that the selection transistors at both ends of the channel are turned on.

[0092] In addition, the above-mentioned TSG and BSG can be respectively connected to strobe switches. That is, the first strobe switch SD_Vg1 is connected to the TSG for strobbing the TSG. The second strobe switch SD_Vg2 is connected to the BSG for strobbing the BSG.

[0093] In this way, without changing the voltages applied to the TSG and BSG, the time when they are applied to the transistors at both ends of the channel can be controlled through the strobe switches, so as to achieve the purpose of controlling the on / off of the channel.

[0094] In some embodiments, the first turn-on voltage is equal to the second turn-on voltage. Providing equal turn-on voltages to the top selection gate line and the bottom selection gate line can make the top selection transistor and the bottom selection transistor have the same turn-on degree, which is convenient for the charge to be released from the channel. And the TSG and BSG can be connected to the same strobe switch SD. After the application of the above-mentioned erase voltage is completed, the strobe switch SD can be turned on, and at the same time, the first turn-on voltage is applied to the top selection gate line, and the second turn-on voltage is applied to the bottom selection gate line. Since the top selection gate line is connected to the control electrode of the TSG and the bottom selection gate line is connected to the control electrode of the BSG, the above-mentioned first turn-on voltage and second turn-on voltage can be synchronously applied to the TSG and BSG, and then the TSG and BSG are turned on to release the channel charge.

[0095] It should be noted that the above-mentioned first time period can be in the erase stage as Figure 12 shown, and the second stage can be in the recovery stage after the erase stage.

[0096] In some embodiments, the method further includes:

[0097] During a first time period, a second gating voltage is applied to the first gating switch and the second gating switch, and the second gating voltage is less than the first gating voltage.

[0098] Exemplarily, as Figure 12 shown, during the erasing stage, the gating switch SD connected to the TSG and the BSG can provide a lower second gating voltage, such as being grounded or a 6V voltage, etc. Since the channel potential is relatively high during the erasing stage, the TSG and the BSG are actually in an off state.

[0099] When switching to a second time period, such as Figure 12 the recovery stage in [reference], the gating voltage of the gating switch SD can be increased to the first gating voltage, for example, 15V. At this time, the BSG and the TSG are synchronously turned on, so that both ends of the channel are in a conducting state, thereby facilitating the release of channel charges from both ends.

[0100] In some embodiments, the method further includes:

[0101] During the second time period, turning on a discharge path in a page buffer coupled to a corresponding bit line of the memory string.

[0102] In some embodiments, turning on the discharge path in the page buffer coupled to the corresponding bit line of the memory string includes:

[0103] Applying a third turn-on voltage to a control switch in the discharge path in the page buffer coupled to the bit line.

[0104] In some embodiments, the method further includes:

[0105] During the second time period, applying a cut-off voltage to a control switch between the bit line and the sense node in the page buffer to disconnect a pre-charge path in the page buffer and a path between the latches.

[0106] It can be understood that the above-mentioned memory string is connected to the bit line BL, and the bit line is connected to other modules of the peripheral circuit through a page buffer as Figure 6 shown. Since the bit line is not directly grounded, when releasing channel charges by turning on the TSG, a path from the bit line BL to the ground Gnd needs to be provided.

[0107] Exemplarily, as Figure 13 shown, in the embodiments of the present disclosure, a control switch between the BL and the sense nodes SO and SO2 of the page buffer 90 can be turned off, and a discharge switch of the discharge path can be turned on. Specifically, a cut-off voltage is applied to the bit line bias switch VBL BIAS and the switch VSO BLK to disconnect this path, and at the same time, the bit line switch V PASS , and the discharge switch VBLDISCH and a bit line switch V PASS An opening voltage (i.e., the above-mentioned third opening voltage) is applied to conduct the discharge path. In this way, the residual charge in the above-mentioned channel can be released to the discharge path through the bit line, so as to achieve the purpose of quickly releasing the charge.

[0108] In addition, it should be noted that the above-mentioned erasing operation, that is, the step of applying an erasing voltage to the memory block to be erased within the first time period, may specifically include:

[0109] During the first time period, a ground voltage is applied to each word line of the memory block to be erased;

[0110] At the same time, the erasing voltage is applied to each bit line or source line of the memory block to be erased.

[0111] During the second time period, the erasing voltage applied to each bit line or source line is switched to a ground voltage.

[0112] In some embodiments, in the above step S103, performing an erasing verification operation on the memory block includes:

[0113] Applying an erasing verification voltage to the selected word line on the memory block; wherein, the selected word line is any word line on the memory block;

[0114] Applying an opening voltage to the unselected word lines on the memory block; wherein, the opening voltage is greater than or equal to the maximum threshold voltage of the memory cell; the erasing verification voltage is less than the opening voltage;

[0115] Reading the memory cell corresponding to the selected word line to obtain the verification result of the erasing verification operation.

[0116] The above verification process can be sequentially implemented for different word lines. Similar to the reading process, an erasing verification voltage is applied to the selected word line of the memory block, and an opening voltage is applied to other word lines. The process of reading the memory cell corresponding to the selected word line specifically includes: applying a voltage to the bit line, and through the sensing node connected to the bit line, it can be detected whether the channel is conducting. If the channel is conducting, it means that the above erasing verification voltage is greater than the threshold voltage of the memory cell coupled to the selected word line, that is, the erasing of the memory cell is successful. If the channel is not conducting, it means that the above erasing verification voltage is less than the threshold voltage of the memory cell, that is, the erasing of the memory cell fails.

[0117] It can be understood that, as Figure 14 shown, the above erasing verification voltage V vf0 is defined based on the target threshold voltage Vth after erasing. That is, the threshold voltage Vth of the memory cell with successful erasing should be less than the erasing verification voltage V vf0, so that during verification, as long as the memory cell remains in states such as the P1 state, P2 state, and P3 state where the erasure is not successful, its threshold voltage Vth is greater than the erasure verification voltage V vf0 , resulting in the memory cell being unable to conduct; only after successful erasure, the threshold voltage Vth of the memory cell is less than the erasure verification voltage V vf0 . That is to say, if successful erasure indicates that the memory cell has entered the erased state E0 and its maximum threshold voltage is V1, then the set erasure verification voltage V vf0 should be greater than or equal to V1.

[0118] As Figure 15 shown, an embodiment of the present disclosure further provides a memory 100, including:

[0119] a peripheral circuit 110 and a memory cell array 120 composed of a plurality of memory blocks;

[0120] wherein, the peripheral circuit 110 is at least configured to execute the operation method described in any one of the above embodiments. That is, the operation method provided in any one of the above embodiments can be applied to the memory 100.

[0121] As Figure 16 shown, an embodiment of the present disclosure further provides a memory system 200, including:

[0122] a memory 210 and a controller 220;

[0123] the memory 210 at least includes a peripheral circuit and a memory cell array composed of a plurality of memory blocks; the peripheral circuit is at least configured to execute the operation method described in any one of the above embodiments. The memory 210 can also be the memory 100 shown in the above embodiments Figure 12 .

[0124] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0125] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for operating a memory, characterized in that, The memory includes a memory cell array composed of a plurality of memory blocks, each of the memory blocks at least including a plurality of memory strings and a plurality of word lines coupled to the memory strings; the method includes: Applying an erase voltage to the memory block to be erased during a first period; During a second period after the first period, turning on the top select transistors and bottom select transistors of each memory string in the memory block to be erased, so that the charges in the channels of the erased memory strings are released from both ends of the memory strings; Performing an erase verification operation on the memory block.

2. The operating method according to claim 1, wherein During the second period after the first period, turning on the top select transistors and bottom select transistors of each memory string in the memory block to be erased includes: Applying a first turn-on voltage to the top select gate line in the memory block; wherein, the top select gate line is connected to the control electrode of the top select transistor; Applying a second turn-on voltage to the bottom select gate line in the memory block; wherein, the bottom select gate line is connected to the control electrode of the bottom select transistor; During the second period, synchronously applying a first strobe voltage to a first strobe switch connected to the top select gate line and a second strobe switch connected to the bottom select gate line, so that the first turn-on voltage is applied to the top select transistor and the second turn-on voltage is applied to the bottom select transistor.

3. The operating method according to claim 2, characterized in that, The first turn-on voltage is equal to the second turn-on voltage.

4. The operating method according to claim 2, characterized in that, The method further includes: Applying a second strobe voltage to the first strobe switch and the second strobe switch during the first period; the second strobe voltage is less than the first strobe voltage.

5. The operating method according to claim 1, characterized in that The method further includes: During the second period, turning on a discharge path in a page buffer coupled to a bit line corresponding to the memory string.

6. The operating method according to claim 5, characterized in that, Turning on the discharge path in the page buffer coupled to the bit line corresponding to the memory string includes: Applying a third turn-on voltage to a control switch in the discharge path in the page buffer coupled to the bit line.

7. The operating method according to claim 5, characterized in that The method further includes: During the second period, applying a cut-off voltage to a control switch between the bit line and a sense node in the page buffer to disconnect a pre-charge path and a path between latches in the page buffer.

8. The operating method according to claim 1, characterized in that Applying an erase voltage to the memory block to be erased during the first period includes: Applying a ground voltage to each word line of the memory block to be erased during the first period; Simultaneously applying the erase voltage to each bit line or source line of the memory block to be erased.

9. The operating method according to claim 8, characterized in that, The method further includes: During the second period, switching the erase voltage applied to each bit line or source line to a ground voltage.

10. The operating method according to any one of claims 1 to 9, characterized in that, Performing an erase verification operation on the memory block includes: Applying an erase verification voltage to a select word line on the memory block; wherein, the select word line is any word line on the memory block; Applying a turn-on voltage to an unselected word line on the memory block; wherein, the turn-on voltage is greater than or equal to the maximum threshold voltage of a memory cell; the erase verification voltage is less than the turn-on voltage; Reading a memory cell corresponding to the select word line to obtain a verification result of the erase verification operation.

11. A memory, characterized in that, The memory includes: An external circuit and a memory cell array composed of a plurality of memory blocks; Wherein, the external circuit is at least configured to perform the operation method according to any one of claims 1 to 10.

12. A memory system, characterized in that, The memory system includes: A memory and a controller; The memory at least includes an external circuit and a memory cell array composed of a plurality of memory blocks; the external circuit is at least configured to perform the operation method according to any one of claims 1 to 10.

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