Method of manufacturing a semiconductor structure

Abstract

The application discloses a preparation method of a semiconductor structure, comprising: providing a substrate, the substrate comprising a device region and an edge region surrounding the device region; forming a stack structure on the substrate, the stack structure comprising support layers and sacrificial layers arranged alternately; forming a plurality of conductive columns in the device region, the conductive columns penetrating the stack structure; forming a mask layer on the surface of the stack structure, and selectively etching the mask layer to expose a top sacrificial layer in the stack structure, so as to form a plurality of openings in a top support layer in the stack structure, wherein each opening in the device region overlaps at least one conductive column to form a top opening; removing part of the stack structure in the edge region to expose at least part of the sacrificial layer in the device region and form a lateral opening; and removing the sacrificial layer in the device region along the top opening and the lateral opening, and the remaining support layer supports the conductive column. The preparation method can remove the sacrificial layer in the device region completely.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for preparing a semiconductor structure. Background Technology

[0002] In semiconductor structures such as DRAM products, when forming capacitor structures, the oxide layer of the semiconductor structure is usually etched through the opening at the top of the semiconductor structure to provide space for subsequent material deposition. However, due to the high aspect ratio of the capacitor structure, when the actual opening area at the top is reduced, the oxide layer may not be completely removed, which will affect the subsequent processes and the performance of the semiconductor structure. It may even lead to chip probing (CP) failure and reduce the yield of the product. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a semiconductor structure, wherein the method can etch the sacrificial layer located in the device region along the top and sides to improve etching efficiency and remove the sacrificial layer cleanly.

[0004] A method for fabricating a semiconductor structure according to an embodiment of the present invention includes: providing a substrate, the substrate including a device region and an edge region surrounding the device region; forming a stacked structure on the substrate, the stacked structure including alternately disposed support layers and sacrificial layers; forming a plurality of conductive pillars penetrating the stacked structure in the device region; forming a mask layer on the surface of the stacked structure, and selectively etching the mask layer to expose a top sacrificial layer in the stacked structure to form a plurality of openings in a top support layer in the stacked structure, wherein each opening located in the device region overlaps with at least one of the conductive pillars to form a top opening;

[0005] The stacked structure located in the edge region is removed to expose at least a portion of the sacrificial layer in the device region, forming a lateral opening; the sacrificial layer in the device region is removed along the top opening and the lateral opening, and the remaining support layer supports the conductive pillar.

[0006] According to some embodiments of the present invention, the step of removing a portion of the stacked structure located in the edge region to at least expose a portion of the sacrificial layer of the device region to form a lateral opening includes: forming a photoresist layer on the device region and exposing the stacked structure of the edge region; etching the stacked structure of the edge region down to the bottom sacrificial layer in the stacked structure to form the lateral opening.

[0007] According to some embodiments of the present invention, in the step of forming a photoresist layer on the device region, the photoresist layer fills the top opening; prior to the step of removing the sacrificial layer in the device region along the top opening and the side opening, the photoresist layer is removed to expose the top opening.

[0008] According to some embodiments of the present invention, an ashing process is used to remove the photoresist layer located at the top opening in the step of removing the photoresist layer to expose the top opening.

[0009] According to some embodiments of the present invention, the step of removing the sacrificial layer in the device region along the top opening and the side opening includes: performing a first etching process along the top opening and the side opening to simultaneously etch the bottom sacrificial layer in the edge region and the top sacrificial layer in the device region; performing a second etching process along the top opening to etch a next support layer in the device region located below the top sacrificial layer and forming a via in the support layer, the via corresponding to and communicating with the top opening; repeating the first etching process and the second etching process until the bottom sacrificial layer of the device region is exposed; and etching away the bottom sacrificial layer along the top opening and the side opening.

[0010] According to some embodiments of the present invention, the first etching process is a wet etching process.

[0011] According to some embodiments of the present invention, the second etching process is a dry etching process.

[0012] According to some embodiments of the present invention, when the first etching process and the second etching process are repeated until the bottom sacrificial layer of the device region is exposed, the remaining portion of the bottom sacrificial layer in the edge region is the bottom sacrificial layer.

[0013] According to some embodiments of the present invention, in the stacked structure, the thickness of the bottom sacrificial layer is greater than the total thickness of all the sacrificial layers thereon.

[0014] According to some embodiments of the present invention, the mask layer is one or more combinations of a hard mask layer, a hard carbon layer, and an anti-reflective layer.

[0015] According to some embodiments of the present invention, the stacked structure includes, from top to bottom, a top support layer, a top sacrificial layer, an intermediate support layer, a bottom sacrificial layer, and a bottom support layer.

[0016] According to some embodiments of the present invention, the stacked structure further includes a stabilizing layer formed on the surface of the top support layer and the conductive pillar, the top opening penetrating the stabilizing layer.

[0017] According to some embodiments of the present invention, the conductive post is a lower electrode, and the method further includes: forming a dielectric layer on the surface of the conductive post; and forming an upper electrode on the surface of the dielectric layer.

[0018] According to the semiconductor structure fabrication method of the present invention, both the side opening and the top opening expose the sacrificial layer of the device region. This allows for etching of the sacrificial layer along the top and side openings, enabling simultaneous etching from both the top and side directions. This increases the contact area and time between the etchant and the sacrificial layer, improving the etching efficiency and ensuring thorough removal of the device region and its surrounding sacrificial layer. This guarantees the proper execution of subsequent CP testing and maintains the performance of the semiconductor structure. The embodiments of this disclosure avoid the problems of continuously changing wafer stress due to the stacking of multiple layers in a multilayer structure, and changes in overlay error in the device region and its surrounding area due to scribe line density, which can lead to incomplete cleaning of the bottom sacrificial layer. Attached Figure Description

[0019] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0020] Figures 2-11 This is a cross-sectional view of each step in a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0021] Figure label:

[0022] 1: Substrate, 11: Device area, 12: Edge area;

[0023] 2: Layered structure; 21: Bottom support layer; 22: Bottom sacrificial layer; 23: Middle support layer; 231: Through hole; 24: Top sacrificial layer; 25: Top support layer; 251: Top opening; 26: Stabilizing layer; 27: Lateral opening.

[0024] 3: Mask layer, 31: First mask layer, 32: Second mask layer;

[0025] 4: Photoresist pattern;

[0026] 5: Photoresist layer;

[0027] 6: Conductive pillar. Detailed Implementation

[0028] The following describes in further detail a method for preparing a semiconductor structure according to the present invention, with reference to the accompanying drawings and specific embodiments.

[0029] The following describes a method for fabricating a semiconductor structure according to an embodiment of the present invention with reference to the accompanying drawings.

[0030] like Figure 1 and Figure 2 As shown, a method for fabricating a semiconductor structure according to an embodiment of the present invention may include: providing a substrate 1, the substrate 1 including a device region 11 and an edge region 12 surrounding the device region 11; forming a stacked structure 2 on the substrate 1, the stacked structure 2 including alternately arranged support layers and sacrificial layers; forming a plurality of conductive pillars 6 through the stacked structure 2 in the device region 11; forming a mask layer 3 on the surface of the stacked structure 2, and selectively etching the mask layer 3 to expose a top sacrificial layer 24 in the stacked structure 2 to form a plurality of openings in a top support layer 25 in the stacked structure 2, wherein each opening in the device region 11 overlaps with at least one of the conductive pillars 6 to form a top opening 251; removing a portion of the stacked structure 2 located in the edge region 12 to expose at least a portion of the sacrificial layer in the device region 11 to form a lateral opening 27; removing the sacrificial layer in the device region 11 along the top opening 251 and the lateral opening 27, the remaining support layer supporting the conductive pillars 6.

[0031] like Figures 2-11 The diagram shows a cross-sectional view of the semiconductor structure at each step of the semiconductor structure fabrication method according to an embodiment of the present invention.

[0032] like Figure 2 As shown, a substrate 1 is provided. The substrate 1 may be, but is not limited to, a silicon substrate. In other examples, the substrate 1 may include semiconductor substrates such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 1 may include device structures formed therein, such as word lines, bit lines, capacitor contacts, pads, etc. The substrate 1 includes a device region 11 and an edge region 12 surrounding the device region 11; that is, the device region 11 forming the device structure and the edge region 12 surrounding the device region 11 are defined in the planar direction of the substrate 1.

[0033] like Figure 2 As shown, a laminated structure 2 is formed on the substrate 1. The laminated structure 2 may include support layers (e.g., ...) that are alternately arranged in the thickness direction. Figure 2 The bottom support layer 21, the middle support layer 23, and the top support layer 25 (as shown) and the sacrificial layer (e.g., as shown) Figure 2 The top sacrificial layer 24 and the bottom sacrificial layer 22 are shown. The specific number of support layers and sacrificial layers can be set according to actual needs, but the bottom and top layers in the stacked structure 2 are always support layers.

[0034] Multiple conductive pillars 6 are formed in the device region 11. The conductive pillars 6 penetrate the stacked structure 2 along the thickness direction and are formed within the stacked structure 2 located in the device region 11. The conductive pillars 6 can be used to form a capacitor structure. For example, the conductive pillars 6 can be used to form the lower electrode of the capacitor structure. Of course, it is not limited to this and can also be used in other suitable locations.

[0035] like Figure 3 and Figure 4 As shown, a mask layer 3 is formed on the surface of the stacked structure 2, and the mask layer 3 is selectively etched to expose the top sacrificial layer 24 in the stacked structure 2, so as to form a plurality of openings in the top support layer 25 in the stacked structure 2, wherein each opening located in the device region 11 overlaps with at least one of the conductive pillars 6 to form a top opening 251.

[0036] Specifically, such as Figure 3 As shown, a mask layer 3 is formed on the stacked structure 2, and a photoresist pattern 4 is formed on the mask layer 3 to define the position of the top opening 251. Photolithography is performed on the mask layer 3 to transfer the pattern to the mask layer 3. Then, the top support layer 25 of the stacked structure 2 is etched using the mask layer 3 as a mask to expose the top sacrificial layer 24. It should be noted that the top sacrificial layer 24 here refers to the sacrificial layer located at the topmost layer in the stacked structure 2, and the top support layer 25 is the support layer located at the topmost layer in the stacked structure 2 and located on the surface of the top sacrificial layer 24.

[0037] Optionally, the mask layer 3 can be a single-layer structure or a multi-layer composite film layer. For example, the mask layer 3 can be one or more combinations of a hard mask layer, a hard carbon layer, and an anti-reflective layer. Figure 3 In the example shown, the mask layer 3 may include a first mask layer 31 and a second mask layer 32 from bottom to top. The first mask layer 31 may be a hard carbon layer, and the second mask layer 32 may be a hard mask layer, for example, the second mask layer 32 may be a silicon oxynitride layer.

[0038] like Figure 4 As shown, the top support layer 25 is etched using the mask layer 3 as a mask to transfer the pattern of the mask layer 3 to the top support layer 25. An opening is formed in the top support layer 25 to expose the top sacrificial layer 24. The opening overlaps with at least one conductive post 6, thereby increasing the opening area, which is beneficial for subsequent etching of the sacrificial layers 24 and 22 through the opening. In this step, the top support layer 25 in the device region 11 is partially removed, and the opening can be formed as a top opening 251 to expose the top sacrificial layer 24 located in the device region 11. The top support layer 25 located in the edge region 12 is completely removed to expose the surface of the top sacrificial layer 24 located in the edge region 12.

[0039] like Figures 5-7As shown, a portion of the stacked structure 2 located in the edge region 12 is removed to expose at least a portion of the sacrificial layers 24 and 22 of the device region 11, forming a lateral opening 27. That is, the portion of the stacked structure 2 located in the edge region 12 is etched without etching the stacked structure 2 of the device region 11. After the portion of the stacked structure 2 located in the edge region 12 is removed, an opening can be formed in the edge region 12 to expose the sidewall of the stacked structure 2 of the corresponding device region 11, thereby forming a lateral opening 27 that exposes the sacrificial layers 24 and 22 located in the device region 11.

[0040] The side opening 27 and top opening 251 formed in this way expose the sacrificial layers 24 and 22 of the device region 11. Etching agent can be introduced through the top opening 251 and side opening 27 to etch the sacrificial layers 24 and 22 of the device region 11. This allows the sacrificial layers 24 and 22 of the device region 11 to be etched simultaneously from both the top and side directions. This increases the contact area and time between the etchant and the sacrificial layers 24 and 22 of the device region 11, improves the etching efficiency of the sacrificial layers 24 and 22 of the device region 11, and can thoroughly remove the sacrificial layer material in the device region 11 and its edge region 12. This prevents the presence of sacrificial layer material residue in the device region 11 from affecting the performance of the semiconductor structure. The remaining support layers 21, 23, and 25 can be used to support the conductive pillars 6.

[0041] In some embodiments of the present invention, the step of removing a portion of the stacked structure 2 located in the edge region 12 to at least expose a portion of the sacrificial layers 24, 22 of the device region 11 to form the lateral opening 27 may include:

[0042] like Figure 5 As shown, a photoresist layer 5 is formed on the device region 11, and the stacked structure 2 of the edge region 12 is exposed. The photoresist layer 5 is used to shield and protect the stacked structure 2 of the device region 11. When etching the stacked structure 2 of the edge region 12, the photoresist layer 5 can protect the stacked structure 2 located in the device region 11 from being etched, so that part of the stacked structure 2 located in the edge region 12 is etched to form a lateral opening 27.

[0043] like Figure 6 -like Figure 7As shown, the stacked structure 2 of the edge region 12 is etched down to the bottom sacrificial layer 22 in the stacked structure 2 to form the lateral opening 27. It should be noted that the bottom sacrificial layer 22 here refers to the sacrificial layer located at the bottommost layer in the stacked structure 2. Etching the stacked structure 2 located in the edge region 12 down to the bottom sacrificial layer 22 means removing all sacrificial layers 24 and support layers 23 above the bottom sacrificial layer 22 in the stacked structure 2 of the edge region 12 to form the lateral opening 27. In this way, the lateral opening 27 can expose the sides of all sacrificial layers 24 above the bottom sacrificial layer 22 in the device region 11. When etching all sacrificial layers 24 above the bottom sacrificial layer 22 in the device region 11, etchant can be introduced along the top opening 251 and the lateral opening 27 to etch from both the top and side directions, thereby further improving the etching efficiency and etching cleanliness of the sacrificial layers 24 and 22 in the device region 11.

[0044] In some examples of the present invention, such as Figures 5-6 As shown, in the step of forming the photoresist layer 5 on the device region 11, the photoresist layer 5 fills the top opening 251 to block the exposed top sacrificial layer 24. This prevents the etchant from etching the top sacrificial layer 24 of the device region 11 through the top opening 251 during etching of the stacked structure 2 located in the edge region 12. Figure 7 and Figure 8 As shown, after forming the lateral opening 27, and before removing the sacrificial layer in the device region 11 along the top opening 251 and the lateral opening 27, the photoresist layer 5 can be removed to expose the top opening 251, thereby exposing the top sacrificial layer 24 located in the device region 11. This allows for etching of the sacrificial layers 24 and 22 located in the device region 11 along the top opening 251 and the lateral opening 27. Optionally, an ashing process can be used to remove the photoresist layer 5 located in the top opening 251 in this step. This process is simple and can completely remove the photoresist layer 5 within the top opening 251, avoiding residue. Alternatively, other processes can be used, such as etching, to remove the photoresist layer 5, as long as the photoresist layer 5 can be removed and the top opening 251 exposed.

[0045] In some embodiments of the present invention, in the step of removing the sacrificial layers 24, 22 in the device region 11 along the top opening 251 and the side opening 27, the support layer 23 located in the middle portion of the stacked structure 2 is etched along the top opening 251. Specifically, in the stacked structure 2, support layers 25, 23, 21 and sacrificial layers 22, 24 are alternately arranged. The support layers 25, 23, 21 have a supporting function. A top opening 251 is formed in the top support layer 25. After the top sacrificial layer 24 located in the device region 11 is removed along the top opening 251 and the side opening 27, the next support layer 23 located below it is exposed. The support layer 23 blocks the next sacrificial layer 22. In order to etch the next sacrificial layer 22 of the device region 11 from the top and the side, a portion of the support layer 23 located in the device region 11 can be etched along the top opening 251 to form an opening in the support layer 23, thereby exposing the next sacrificial layer 22, and retaining the remaining support layer 23 to support the conductive pillar 6. Then, the next sacrificial layer 22 of the device region 11 is removed along the top opening 251 and the side opening 27, so that etching can be performed from the top and the side when removing each sacrificial layer 24, 22 located in the device region 11. It should be noted that the embodiments disclosed herein include a stacked structure consisting of 3 support layers and 2 sacrificial layers, but are not limited to this. When more alternately arranged support layers and sacrificial layers are included, such as 5 support layers or 4 sacrificial layers, the method provided in the embodiments disclosed herein can also be used.

[0046] In some specific examples, the step of removing the sacrificial layers 24, 22 in the device region 11 along the top opening 251 and the side opening 27 may include:

[0047] like Figures 7-8 As shown, a first etching process is performed along the top opening 251 and the side opening 27 to simultaneously etch the bottom sacrificial layer 22 of the edge region 12 and the top sacrificial layer 24 of the device region 11, down to the support layer 23 below them. Specifically, the stacked structure 2 may include multiple layers of sacrificial layers and support layers stacked together. A side opening 27 is formed in the edge region 12. The side opening 27 can expose the sides of all sacrificial layers 24 above the bottom sacrificial layer 22 and expose the bottom sacrificial layer 22 of the edge region 12. When etching the sacrificial layer 24 of the device region 11, an etchant is introduced along the top opening 251 and the side opening 27 to etch the sacrificial layer 24 of the device region 11 exposed by the top opening 251 and the side opening 27, and to etch the bottom sacrificial layer 22 of the edge region 12 along the side opening 27.

[0048] like Figure 9 and Figure 10As shown, during the etching operation on the device region 11, after etching the top sacrificial layer 24 to expose the next support layer 23 below, a second etching process is performed along the top opening 251 to etch the next support layer 23 located below the top sacrificial layer 24 in the device region, and a via 231 is formed in the support layer 23. The via 231 corresponds to and communicates with the top opening 251, so that etchant can be introduced through the top opening 251 and the side opening 27. The etchant introduced through the top opening 251 can etch the sacrificial layer 22 of the device region 11 located below the support layer 23 along the via 231. This allows the sacrificial layer 22 located in the device region 11 to be etched along the top opening 251 and the through hole 231, so that the sacrificial layer 22 located in the device region 11 can be etched simultaneously from the top and the side. This enables the sacrificial layers 24 and 22 located in the device region 11 to be etched from two directions, fully releasing the sacrificial layer material (e.g., oxide) in the device region 11 and its edges, especially the contact area and time between the bottom sacrificial layer 22 and the etchant (e.g., acidic reagent), thus improving the problem of the bottom sacrificial layer 22 residue in the device region 11 and its edges.

[0049] The stacked structure 2 may include multiple sacrificial layers and support layers stacked together. When etching multiple sacrificial layers and multiple support layers located in the middle part of the device region 11, the steps of the first etching process and the second etching process described above can be repeated until the bottom sacrificial layer 22 of the device region 11 is exposed, so that all sacrificial layers 24 of the device region 11 above the bottom sacrificial layer 22 can be etched in both the top and side directions.

[0050] like Figure 10 and Figure 11 As shown, the bottom sacrificial layer 22 can be etched again along the top opening 251 and the side opening 27. Specifically, a through hole corresponding to and communicating with the top opening 251 can be formed in the support layer 23 above the bottom sacrificial layer 22. Etching agent is introduced along the top opening 251 and the side opening 27 so that the bottom sacrificial layer 22 located in the device region 11 and the edge region 12 can be etched at the same time so that the bottom sacrificial layer 22 can be etched cleanly.

[0051] In some embodiments of the present invention, the first etching process can be a wet etching process, so that the sacrificial layer can be etched cleanly, and the second etching process can be a dry etching process. Thus, when etching the sacrificial layer 24 and the support layer 23, dry etching and wet etching can be alternated to etch the stacked structure 2, thereby improving the etching effect.

[0052] In some embodiments of the present invention, the bottom sacrificial layer 22 has a greater thickness. When the sacrificial layer 24 above the bottom sacrificial layer 22 is removed to expose the support layer 23, a portion of the bottom sacrificial layer 22 in the edge region 12 is retained. Thus, when the upper sacrificial layer material is completely removed, a small amount of sacrificial layer material remains in the edge region 11. When the support layer 23 above the bottom sacrificial layer 22 of the device region 11 is opened along the top opening 251, the remaining bottom sacrificial layer material in the edge region 12 can form a barrier layer for the bottom support layer 21 to prevent the bottom support layer 21 in the edge region 12 from being over-etched.

[0053] When etching the sacrificial layers 24 and 22 of the device region 11 from the top and sides, the bottom sacrificial layer 22 located in the edge region 12 is simultaneously etched. Optionally, in the stacked structure 2, the thickness of the bottom sacrificial layer 22 is greater than the total thickness of all the sacrificial layers 24 located thereon. Further, the thickness of the bottom sacrificial layer 22 can be 2 to 4 times the total thickness of the remaining sacrificial layers in the stacked structure 2, for example, 2 times or 3 times. Within this range, when etching to the support layer 23 on the bottom sacrificial layer 22, there is still a portion of the bottom sacrificial layer 22 remaining in the edge region 12 to protect the bottom support layer 21. Further, after removing the support layer 23 located on the bottom sacrificial layer 22, the bottom sacrificial layer 22 of the edge region 12 may still have at least a portion remaining, so that when removing the support layer 23 located on the bottom sacrificial layer 22, the remaining bottom sacrificial layer 22 in the edge region 12 can always form a barrier layer for the bottom support layer 21. Furthermore, the stacked structures within the aforementioned range are particularly suitable for applications with high integration, high conductor density, and small distances between adjacent conductors, ensuring the storage density of the semiconductor structure.

[0054] In some embodiments of the present invention, such as Figure 2 As shown, the stacked structure 2 includes, from top to bottom, the top support layer 25, the top sacrificial layer 24, the middle support layer 23, the bottom sacrificial layer 22, and the bottom support layer 21. The method for fabricating the semiconductor structure according to the present invention will be described below with reference to specific embodiments.

[0055] like Figure 3 As shown, a mask layer 3 is formed on the top support layer 25, and the mask layer 3 is selectively etched to expose the top sacrificial layer 24 to form an opening in the top support layer 25. This opening may partially overlap with the conductive pillar to form a top opening 251 exposing the top sacrificial layer in the top support layer 25 of the device region 11. Figure 4 As shown, the top support layer 25 located in the edge region 12 is removed to expose the top sacrificial layer 25 located in the edge region.

[0056] like Figure 5As shown, a photoresist layer 5 is formed on the stacked structure 2 of the device region 11. The photoresist layer 5 covers the surface of the stacked structure 2 of the device region 11, fills the top opening 251, and exposes the top sacrificial layer 24 of the edge region 12.

[0057] like Figure 6 and Figure 7 As shown, the top sacrificial layer 24 and the intermediate support layer 23 located in the edge region 12 are removed sequentially until the bottom sacrificial layer 22 is exposed, thereby forming a lateral opening 27 on the side of the top sacrificial layer 24 of the exposed device region 11. Wet etching can be used when removing the top sacrificial layer 24, and dry etching can be used when removing the intermediate support layer 23 located in the edge region 12.

[0058] like Figure 8 As shown, the photoresist layer 5 is removed to open the top opening 251 and expose the top sacrificial layer 24 located in the device region 11. In this step, an ashing process can be used to remove the photoresist layer 5, which can not only remove the photoresist layer 5 cleanly, but also avoid damaging the morphology of the semiconductor structure.

[0059] like Figure 9 As shown, etchant is introduced through the top opening 251 and the side opening 27 to etch the top sacrificial layer 24 located in the device region 11 from both the top and side directions. This increases the contact area and contact time between the etchant and the top sacrificial layer 24, thereby improving the etching efficiency of the top sacrificial layer 24 in the device region 11. This allows the top sacrificial layer 24 in the device region 11 to be completely removed, reducing the residue of the top sacrificial layer 24. When etching the top sacrificial layer 24 in the device region 11 along the side opening 27, the etchant simultaneously etches the bottom sacrificial layer 22 located in the edge region 12. The thickness of the bottom sacrificial layer 22 is greater than that of the top sacrificial layer 24. Thus, when removing the top sacrificial layer 24 located in the device region 11, part of the bottom sacrificial layer 22 located in the edge region 12 remains on the surface of the bottom support layer 21 located in the edge region 12.

[0060] like Figure 10 As shown, the intermediate support layer 23 is etched downward along the top opening 251 until the bottom sacrificial layer 22 located in the device region 11 is exposed, so as to form a through hole 231 corresponding to the top opening 251 in the intermediate support layer 23. The remaining intermediate support layer 23 can be used to support the conductive pillar 6. In this step, the remaining bottom sacrificial layer 22 located in the edge region 12 can form a barrier layer of the bottom support layer 21 of the edge region 12 to prevent the bottom support layer 21 located in the edge region 12 from being over-etched.

[0061] like Figure 11As shown, etchant is introduced through the top opening 251 and the side opening 27 to etch the bottom sacrificial layer 22 located in the device region 11 from the top and the side, and at the same time etch the bottom sacrificial layer 22 in the edge region 12 to clean the bottom sacrificial layer 22. The bottom support layer 21, as well as the remaining top support layer 25 and the middle support layer 23, support the conductive pillar 6.

[0062] In some embodiments of the present invention, the substrate 1 may further include a stabilizing layer 26, which is formed on the surface of the top support layer 25 and the conductive pillars 6. The top opening 251 penetrates the stabilizing layer 26. The upper surfaces of the multiple conductive pillars 6 can be connected to the top support layer 25 through the stabilizing layer 26, thereby further supporting and stabilizing the multiple conductive pillars 6 to enhance the stability of the semiconductor structure.

[0063] In some embodiments of the present invention, the substrate 1 may further include contact pads corresponding to and connected to the conductive pillars 6, the contact pads being electrically connected to the conductive pillars 6 so as to enable the electrical connection between the device structure within the substrate 1 and the conductive pillars 6.

[0064] In some embodiments of the present invention, the conductive pillar 6 can be used to form a capacitor structure, particularly a capacitor structure with a high aspect ratio, such as an aspect ratio greater than or equal to 25:1, and further greater than or equal to 35:1. The conductive pillar 6 can be formed as a lower electrode. After removing the bottom sacrificial layer 22, the method further includes the following steps: forming a dielectric layer on the surface of the conductive pillar 6; forming an upper electrode on the surface of the dielectric layer, wherein a dielectric layer is formed between the upper electrode and the lower electrode, wherein the dielectric layer can be a high-k dielectric material, and the upper electrode and the lower electrode can be metallic materials, such as metals or metal compounds, for example, gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), titanium nitride (TiN), platinum (Pt), palladium (Pd), tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), or molybdenum (Mo).

[0065] The semiconductor structure fabrication method of this invention exposes the sacrificial layer of the device region 11 through both the side opening 27 and the top opening 251. Etching agent can then be introduced along the top opening 251 and the side opening 27 to etch the sacrificial layer of the device region 11. This allows for simultaneous etching of the sacrificial layer of the device region 11 from both the top and side directions, increasing the contact area and time between the etchant and the sacrificial layer of the device region 11, improving the etching efficiency of the sacrificial layer, and thus thoroughly removing the sacrificial layer of the device region 11 and its surroundings. This ensures that subsequent CP testing can proceed normally and guarantees the performance of the semiconductor structure. This embodiment of the invention avoids the problem of continuously changing wafer stress due to the continuous stacking of multiple film layers in a multilayer structure, and the problem of changes in overlay error in the device region and its surrounding areas due to the scribing area and pattern density, which could lead to incomplete cleaning of the bottom sacrificial layer.

[0066] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a device region and an edge region surrounding the device region; A laminated structure is formed on the substrate, the laminated structure comprising alternating support layers and sacrificial layers; Multiple conductive pillars are formed in the device region, penetrating the stacked structure; A mask layer is formed on the surface of the stacked structure, and the mask layer is selectively etched to expose the top sacrificial layer in the stacked structure to form a plurality of openings in the top support layer in the stacked structure, wherein each opening located in the device region overlaps with at least one of the conductive pillars to form a top opening; Remove a portion of the stacked structure located in the edge region to expose at least a portion of the sacrificial layer in the device region, forming a lateral opening; The sacrificial layer in the device region is removed along the top opening and the side opening, and the remaining support layer supports the conductive pillar.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of removing a portion of the stacked structure located in the edge region to at least expose a portion of the sacrificial layer in the device region, forming a lateral opening, includes: A photoresist layer is formed on the device region, and the stacked structure of the edge region is exposed; The stacked structure of the edge region is etched down to the bottom sacrificial layer in the stacked structure to form the lateral opening.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, In the step of forming a photoresist layer on the device region, the photoresist layer fills the top opening; before the step of removing the sacrificial layer in the device region along the top opening and the side opening, the photoresist layer is removed to expose the top opening.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, In the step of removing the photoresist layer to expose the top opening, an ashing process is used to remove the photoresist layer located at the top opening.

5. The method for preparing a semiconductor structure according to any one of claims 2 to 4, characterized in that, The step of removing the sacrificial layer in the device region along the top opening and the side opening includes: A first etching process is performed along the top opening and the side opening to simultaneously etch the bottom sacrificial layer in the edge region and the top sacrificial layer in the device region; A second etching process is performed along the top opening to etch the next support layer located below the top sacrificial layer in the device region, and to form a via in the support layer, the via corresponding to and communicating with the top opening; Repeat the first etching process and the second etching process until the bottom sacrificial layer of the device region is exposed; The bottom sacrificial layer is etched away along the top opening and the side opening.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The first etching process is a wet etching process.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that, The second etching process is a dry etching process.

8. The method for preparing a semiconductor structure according to claim 5, characterized in that, When the first etching process and the second etching process are repeated until the bottom sacrificial layer of the device region is exposed, the remaining portion of the bottom sacrificial layer in the edge region is exposed.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, In the stacked structure, the thickness of the bottom sacrificial layer is greater than the total thickness of all the sacrificial layers above it.

10. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that, The mask layer is one or more combinations of a hard mask layer, a hard carbon layer, and an anti-reflective layer.

11. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that, The stacked structure, from top to bottom, includes a top support layer, a top sacrificial layer, a middle support layer, a bottom sacrificial layer, and a bottom support layer.

12. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that, The stacked structure further includes a stabilizing layer formed on the surface of the top support layer and the conductive pillar, with the top opening penetrating the stabilizing layer.

13. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that, The conductive post is the lower electrode, and the method further includes: A dielectric layer is formed on the surface of the conductive pillar; An upper electrode is formed on the surface of the dielectric layer.

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