Method for improving polysilicon cmp loading

Abstract

The application discloses a method for improving polysilicon CMP load, which comprises the following steps: providing a semiconductor substrate with a top layer of polysilicon growth and CMP, the CMP load effect is that the top surface of the top layer of polysilicon is uneven; forming a hard mask layer, the hard mask layer has a second step structure and a second groove transferred from the bottom; forming a second dielectric layer; coating a third material layer to completely fill the second groove; performing a first etching back of the third material layer with the second dielectric layer as a stop layer; performing a second etching back of the second dielectric layer with the hard mask layer as a stop layer; measuring a first height value of the second dielectric layer on the side of the second groove; performing a third etching of the hard mask layer with the second dielectric layer and the third material layer as masks, the etching amount is equal to the first height value; and removing the second dielectric layer and the third material layer. The application can accurately planarize the uneven surface of the hard mask layer formed by the polysilicon CMP load effect.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit, and more particularly, to a method for improving a polysilicon chemical mechanical polishing (CMP) loading. BACKGROUND

[0002] In a 28nm semi-floating-gate advanced process node, the presence of floating-gate makes the gate height twice as high as that of a normal 28nm semiconductor device. The pattern loading after polysilicon (Poly) CMP of the polysilicon control gate is about 10% to 20% of the gate height. This will have an impact on the development of subsequent processes, such as adversely affecting subsequent photolithography and etching processes.

[0003] The root cause of the pattern loading after Poly CMP is the floating-gate of the active area (AA) region, which causes the step height between the AA and the shallow trench isolation (STI) to be about 10% to 20% of the gate height. Secondly, the oxide dishing caused by the different polishing rates of the CMP slurry for different oxides, the pattern loading after Post Poly CMP will hinder the subsequent photolithography process.

[0004] The present application will be described in greater detail below with reference to the accompanying drawings, in which: FIG. 1A and FIG. 1B the prior art is described in more detail:

[0005] As shown in FIGS. 1A-1B , it is a device structure schematic diagram in each step of the prior art hard mask surface planarization method with polysilicon CMP loading effect; the prior art hard mask surface planarization method with polysilicon CMP loading effect includes the following steps:

[0006] Step one, as shown in FIG. 1A , a semiconductor substrate 101 is provided with completed top layer polysilicon 104 growth and CMP, the CMP loading effect refers to the top surface of the top layer polysilicon 104 is not flat and has a higher first surface in a first region and a lower second surface in a second region, a first step structure is formed between the first surface and the second surface, and the second surface and the first step structure on both sides form a first groove.

[0007] The semiconductor substrate 101 includes a silicon substrate.

[0008] In the semi-floating-gate process, the top polysilicon 104 is used to form the polysilicon control gate of the semi-floating gate device.

[0009] The first region is an active region 101a, and the second region is a shallow trench isolation 102 formation region. The active region 101a is composed of the semiconductor substrate 101 located between the shallow trench isolation 102.

[0010] In the first region, a bottom polysilicon 103 is also formed at the bottom of the top polysilicon 104, and the bottom polysilicon 103 is used to form a polysilicon semi-floating gate.

[0011] A control gate dielectric layer 105 is provided between the top polysilicon 104 and the bottom polysilicon 103, and a control gate dielectric layer 105 is also provided between the top polysilicon 104 and the shallow trench isolation 102.

[0012] A floating gate dielectric layer is provided to isolate the polysilicon semi-floating gate from the semiconductor substrate 101. An opening is formed in a portion of the floating gate dielectric layer, allowing the polysilicon semi-floating gate to directly contact the semiconductor substrate 101 to form a PN junction. During writing or programming, stored charges, such as electrons, pass through the PN junction into and out of the polysilicon semi-floating gate. A channel region, a source region, and lightly doped source / drain regions are formed on the semiconductor substrate 101.

[0013] Step Two, as follows FIG. 1A As shown, a hard mask layer 106 is formed on the surface of the top polysilicon layer 104, and a second step structure formed by the transfer of the first step structure and a second groove formed by the transfer of the first groove are formed on the top surface of the hard mask layer 106.

[0014] Typically, the hard mask layer 106 is formed by stacking a fourth silicon nitride layer 106a and a fifth oxide layer 106b.

[0015] The thickness of the fifth oxide layer 106b is greater than the thickness of the fourth silicon nitride layer 106a; the lower top surface of the fifth oxide layer 106b is higher than the higher top surface of the fourth silicon nitride layer 106a.

[0016] FIG. 1A In the diagram, the height of the second step structure is h101.

[0017] Step Two, as follows FIG. 1B As shown, CMP is performed on the hard mask layer 106. The CMP of the hard mask layer 106 is performed after the CMP of the top polysilicon layer 104, hence it is also called post poly CMP.

[0018] Due to the presence of the second groove, after post poly CMP, the disc-shaped defects in the dotted frame 107 are easily formed.

[0019] To solve the pattern loading problem of the following process due to the large step height of the front layer, there are two existing improvement methods, including:

[0020] The first existing improvement method is: before the CMP of the hard mask layer 106, a mask is added to protect the area of the shallow trench isolation 102, and then the height h101 of the second step structure is reduced by etch back, and finally the planarization is realized by the CMP of the hard mask layer 106. FIG. 1B

[0021] The second existing improvement method is: the height h101 of the second step structure is reduced by thickening the fifth oxide layer 106b of the hard mask layer 106, and then the planarization is realized by CMP multi-grinding.

[0022] The first existing improvement method has the following defects:

[0023] The mask needs to be added, which is expensive.

[0024] The etch back process has no characteristic position of the end point, and the etching amount can only be controlled by time, but this method cannot eliminate the difference between cover wafers.

[0025] The second existing improvement method has the following defects:

[0026] The increase amount of oxide thickness is difficult to determine.

[0027] Thickening the oxide does not necessarily achieve planarization by increasing the grinding amount of CMP. SUMMARY

[0028] The technical problem to be solved by the present application is to provide a polysilicon CMP load improvement method, which can planarize the top surface of the hard mask layer formed on the top surface of the top polysilicon layer with CMP load effect and accurately control the position of the top surface of the hard mask layer, and does not need to add a mask and increase the growth thickness of the hard mask layer.

[0029] To solve the above technical problems, the polysilicon CMP load improvement method provided by the present application comprises the following steps:

[0030] ​Step one, providing a semiconductor substrate with a top layer of polysilicon and CMP, the CMP load effect is that the top surface of the top layer of polysilicon is uneven and has a higher first surface in a first area and a lower second surface in a second area, a first step structure is formed between the first surface and the second surface, and the second surface and the first step structure on both sides form a first groove.

[0031] Step two, forming a hard mask layer on the surface of the top layer of polysilicon, and a second step structure formed by transferring the first step structure and a second groove formed by transferring the first groove are formed on the top surface of the hard mask layer.

[0032] Step three, forming a second dielectric layer on the top surface of the hard mask layer, the material of the second dielectric layer meets the requirement of being able to be selectively etched with the hard mask layer, and the second dielectric layer does not completely fill the second groove.

[0033] Step four, forming a third material layer on the surface of the second dielectric layer by coating process, and using the flowability of the third material layer in the coating process to completely fill the second groove and make the top surface of the third material layer a flat surface; the material of the third material layer meets the requirement of being able to be selectively etched with the second dielectric layer.

[0034] Step five, performing a first back etching of the third material layer with the second dielectric layer as a stop layer.

[0035] Step six, performing a second back etching of the second dielectric layer with the hard mask layer as a stop layer.

[0036] Step seven, measuring the height of the second dielectric layer located on the side of the second groove and obtaining a first height value.

[0037] Step eight, performing a third etching of the hard mask layer with the remaining second dielectric layer and the third material layer as a mask, and the etching amount of the third etching is equal to the first height value.

[0038] Step nine, removing the remaining second dielectric layer and the third material layer, so that the top surface of the hard mask layer is exposed and flat.

[0039] Further improvement is that in step one, the semiconductor substrate comprises a silicon substrate.

[0040] Further improvement is that in step two, the hard mask layer is composed of a fourth silicon nitride layer and a fifth oxide layer.

[0041] The fifth oxide layer has a thickness greater than the fourth silicon nitride layer; the lower top surface of the fifth oxide layer is higher than the higher top surface of the fourth silicon nitride layer, and in step eight, the third etching only etches the fifth oxide layer.

[0042] A further improvement is that in step three, the second dielectric layer is made of silicon nitride.

[0043] A further improvement is that in step four, the third material layer is made of a carbon coating (SOC).

[0044] A further improvement is that the first etching is dry etching.

[0045] A further improvement is that the second etching is dry etching.

[0046] A further improvement is that the third etching is dry etching.

[0047] A further improvement is that in step nine, the second dielectric layer and the third material layer are removed by wet etching.

[0048] A further improvement is that in step one, the top polysilicon layer is used to form a polysilicon control gate of a semi-floating gate device.

[0049] The first region is an active region, and the second region is a shallow trench isolation formation region, and the active region is composed of the semiconductor substrate between the shallow trench isolations.

[0050] In the first region, the bottom of the top polysilicon layer is also formed with a bottom polysilicon layer, which is used to form a polysilicon semi-floating gate.

[0051] The top polysilicon layer and the bottom polysilicon layer are separated by a control gate dielectric layer, and the top polysilicon layer and the shallow trench isolation are also separated by a control gate dielectric layer.

[0052] The polysilicon semi-floating gate and the semiconductor substrate are separated by a floating gate dielectric layer, and an opening is formed in a partial region of the floating gate dielectric layer to allow the polysilicon semi-floating gate to directly contact the semiconductor substrate to form a PN junction.

[0053] A further improvement is that the height of the first step structure is greater than or equal to

[0054] A further improvement is that the height of the second step structure is greater than the height of the first step structure.

[0055] A further improvement is that the thickness of the second dielectric layer is less than or equal to

[0056] Further improvement is that the thickness of the third material layer is greater than or equal to .

[0057] Further improvement is that the method further comprises:

[0058] The photoetching defines the forming area of the gate structure of the semi-floating gate device;

[0059] The top layer of polysilicon, the control gate dielectric layer, the bottom layer of polysilicon and the floating gate dielectric layer are etched in sequence to form the gate structure of the semi-floating gate device.

[0060] Further improvement is that the second dielectric layer is formed by PVD process in step three.

[0061] Further improvement is that the material of the control gate dielectric layer comprises a high dielectric constant layer.

[0062] After the hard mask layer is formed on the top surface of the top layer of polysilicon with the first step structure formed by CMP load effect, the hard mask layer is not directly planarized by CMP process, so that the dishing defect caused by CMP process can be avoided.

[0063] The present application is to increase the second dielectric layer and the third material layer with good trench filling performance, utilize the high selectivity between the third material layer and the second dielectric layer and between the second dielectric layer and the hard mask layer, and sequentially perform the second etching so that the second dielectric layer and the third material layer are only reserved in the second groove of the hard mask layer and the top surface of the second dielectric layer is flat with the top surface of the hard mask layer outside the second groove; then, the first height value of the second dielectric layer on the side of the second groove is measured, and the third etching of the hard mask layer is performed with the reserved second dielectric layer and the third material layer as the mask, and the etching amount of the third etching is the first height value, so that the top surface of the hard mask layer is flat, and since the etching amount of the third etching is accurately controlled, the position of the top surface of the hard mask layer can be accurately controlled, so that the present application can planarize the top surface of the hard mask layer formed on the top surface of the top layer of polysilicon with CMP load effect and accurately control the position of the top surface of the hard mask layer.

[0064] Since the first etching and the second etching of the present application are realized by utilizing the high etching selectivity between the film layers, the remaining second dielectric layer and the third material layer are self-aligned in the second groove after the first etching and the second etching are completed, and the third etching directly uses the remaining second dielectric layer and the third material layer as the mask, so that the photoetching process is not needed, and the present application does not need to increase the mask, so that the cost is low.

[0065] In addition, the present application does not need to reduce the height of the second step structure by increasing the growth thickness of the hard mask layer, and can reduce the production cost. BRIEF DESCRIPTION OF DRAWINGS

[0066] The present application will be further described below in conjunction with the drawings and specific embodiments:

[0067] FIGS. 1A-1B is a device structure schematic diagram in each step of the prior hard mask layer surface planarization method with polysilicon CMP load effect;

[0068] FIG. 2 is a flow chart of the polysilicon CMP load improvement method of the embodiment of the present application;

[0069] FIGS. 3A-3F is a device structure schematic diagram in each step of the polysilicon CMP load improvement method of the embodiment of the present application. DETAILED DESCRIPTION

[0070] As FIG. 2 shown, it is a flow chart of the polysilicon CMP load improvement method of the embodiment of the present application; as FIGS. 3A-3F shown, it is a device structure schematic diagram in each step of the polysilicon CMP load improvement method of the embodiment of the present application; the polysilicon CMP load improvement method of the embodiment of the present application comprises the following steps:

[0071] Step one, as FIG. 3A shown, a semiconductor substrate 201 with completed top layer polysilicon 204 growth and CMP is provided, the CMP load effect is that the top surface of the top layer polysilicon 204 is not flat and has a higher first surface in a first region and a lower second surface in a second region, a first step structure is formed between the first surface and the second surface, and the second surface and the first step structure on both sides form a first groove 301.

[0072] In the embodiment of the present application, the semiconductor substrate 201 comprises a silicon substrate.

[0073] The top layer polysilicon 204 is used to form a polysilicon control gate of a semi-floating gate device.

[0074] The first region is an active region 201a, and the second region is a shallow trench isolation 202 formation region, and the active region 201a is composed of the semiconductor substrate 201 between the shallow trench isolation 202.

[0075] In the first region, the bottom of the top layer polysilicon 204 further forms a bottom polysilicon 203, and the bottom polysilicon 203 is used to form a polysilicon semi-floating gate.

[0076] A control gate dielectric layer 205 is formed between the top polysilicon layer 204 and the bottom polysilicon layer 203, and also between the top polysilicon layer 204 and the shallow trench isolation 202.

[0077] A floating gate dielectric layer is formed between the polysilicon semi-floating gate and the semiconductor substrate 201, and an opening is formed in a partial area of the floating gate dielectric layer to allow the polysilicon semi-floating gate to directly contact the semiconductor substrate 201 to form a PN junction. When writing or programming, storage charges such as electrons pass through the PN junction to enter or exit the polysilicon semi-floating gate. A channel region, a source region, and a lightly doped source-drain region and a drain region of a device are formed on the semiconductor substrate 201.

[0078] In some preferred embodiments, the material of the control gate dielectric layer 205 includes a high dielectric constant layer.

[0079] Step two, as shown in the figure, a hard mask layer 206 is formed on the surface of the top polysilicon layer 204, and a second step structure is formed on the top surface of the hard mask layer 206 by transferring the first step structure, and a second recess 302 is formed by transferring the first recess 301. FIG. 3A

[0080] In the embodiments of the present application, the hard mask layer 206 is formed by stacking a fourth silicon nitride layer 206a and a fifth oxide layer 206b.

[0081] The thickness of the fifth oxide layer 206b is greater than the thickness of the fourth silicon nitride layer 206a, and the lower top surface of the fifth oxide layer 206b is higher than the higher top surface of the fourth silicon nitride layer 206a.

[0082] Step three, as shown in the figure, a second dielectric layer 207 is formed on the top surface of the hard mask layer 206, the material of the second dielectric layer 207 satisfies the condition of being able to be selectively etched with the hard mask layer 206, and the second dielectric layer 207 does not completely fill the second recess 302. FIG. 3B

[0083] In the embodiments of the present application, the material of the second dielectric layer 207 is silicon nitride. In some embodiments, the PVD process is used to form the second dielectric layer 207.

[0084] Step four, as shown in the figure, a third dielectric layer 208 is formed on the top surface of the second dielectric layer 207, the material of the third dielectric layer 208 satisfies the condition of being able to be selectively etched with the second dielectric layer 207, and the third dielectric layer 208 does not completely fill the second recess 302. FIG. 3B ​​As shown, a third material layer 208 is formed on the surface of the second dielectric layer 207 using a coating process. The flowability of the third material layer 208 in the coating process is used to completely fill the second groove 302 and make the top surface of the third material layer 208 a flat surface. The material of the third material layer 208 is such that it can be selectively etched with the second dielectric layer 207.

[0085] In this embodiment of the invention, the material of the third material layer 208 is a carbon coating.

[0086] Step 5, as follows FIG. 3C As shown, the third material layer 208 is etched back for the first time with the second dielectric layer 207 as the stop layer.

[0087] In this embodiment of the invention, the first etching back is performed using dry etching. FIG. 3C As shown, since the first etch is stopped by the second dielectric layer 207, after the first etch is completed, the third material layer 208 outside the second groove 302 is removed, and the top surface of the third material layer 208 in the second groove 302 is flush with the top surface of the second dielectric layer 207 outside the second groove 302.

[0088] Step Six, as FIG. 3D As shown, the second dielectric layer 207 is etched back a second time with the hard mask layer 206 as the stop layer.

[0089] In this embodiment of the invention, the second etching is performed using dry etching.

[0090] Depend on FIG. 3D As shown, since the second etch is stopped by the hard mask layer 206, after the second etch is completed, the second dielectric layer 207 outside the second groove 302 is removed, and the top surface of the second dielectric layer 207 in the second groove 302 is flush with the top surface of the hard mask layer 206 outside the second groove 302. The third material layer 208 and the second dielectric layer 207 are both located in the second groove 302, and the top surface of the third material layer 208 can be higher than or equal to the top surface of the second dielectric layer 207.

[0091] Step 7: Measure the height of the second medium layer 207 located on the side of the second groove 302 and obtain the first height value.

[0092] Step 8, as FIG. 3EAs shown, the hard mask layer 206 is etched for the third time with the remaining second medium layer 207 and the third material layer 208 as masks, and the etching amount of the third etching is equal to the first height value.

[0093] Since the etching amount of the third etching is controlled accurately, the top surface position of the hard mask layer 206 can be controlled accurately.

[0094] In the embodiment of the present application, the third etching is only performed on the fifth oxide layer 206b.

[0095] In the embodiment of the present application, the third etching is performed by dry etching.

[0096] Step nine, as shown, the remaining second medium layer 207 and the third material layer 208 are removed, so that the top surface of the hard mask layer 206 is exposed and flat. FIG. 3F

[0097] In the embodiment of the present application, the second medium layer 207 and the third material layer 208 are removed by wet etching.

[0098] Further comprising:

[0099] The photoetching defines the forming area of the gate structure of the semi-floating gate device. FIG. 3F In the embodiment of the present application, the hard mask layer 206 has been planarized, so that the precision of the photoetching process of the gate structure of the semi-floating gate device is improved.

[0100] The top layer polysilicon 204, the control gate medium layer 205, the bottom layer polysilicon and the floating gate medium layer are etched in sequence to form the gate structure of the semi-floating gate device.

[0101] The embodiment of the present application can be well applied to the manufacturing process of semi-floating gate with process nodes below 28nm, and the embodiment of the present application can adopt the following specific parameters:

[0102] The height of the first step structure is greater than or equal to

[0103] The height of the second step structure is greater than the height of the first step structure.

[0104] The thickness of the second medium layer 207 is less than or equal to

[0105] The thickness of the third material layer 208 is greater than or equal to

[0106] ​The embodiment of the present application forms the hard mask layer 206 on the top surface of the top polysilicon layer 204 with the first step structure formed by the CMP load effect, and then performs planarization on the hard mask layer 206 by the CMP process, so as to avoid the disc-shaped defects caused by the CMP process.

[0107] The embodiment of the present application forms the second dielectric layer 207 and the third material layer 208 with good trench filling performance, and uses the high selectivity between the third material layer 208 and the second dielectric layer 207 and between the second dielectric layer 207 and the hard mask layer 206 to perform etching in sequence, so as to reserve the second dielectric layer 207 and the third material layer 208 in the second groove 302 of the hard mask layer 206 and make the top surface of the second dielectric layer 207 and the top surface of the hard mask layer 206 outside the second groove 302 be flat; then, the first height value of the second dielectric layer 207 on the side of the second groove 302 is measured, and the third etching on the hard mask layer 206 with the etching amount of the first height value is performed by using the reserved second dielectric layer 207 and the third material layer 208 as a mask, so as to make the top surface of the hard mask layer 206 be flat, and the position of the top surface of the hard mask layer 206 is accurately controlled due to the accurate control of the etching amount of the third etching, so the present application can planarize the top surface of the hard mask layer 206 formed on the top surface of the top polysilicon layer 204 with the CMP load effect and accurately control the position of the top surface of the hard mask layer 206.

[0108] Since the first etching and the second etching are both realized by using the high etching selectivity between the film layers, the second dielectric layer 207 and the third material layer 208 remaining after the first etching and the second etching are self-aligned in the second groove 302, and the third etching directly uses the second dielectric layer 207 and the third material layer 208 as a mask, so the photolithography process is not needed to define, and the present application does not need to increase the mask, so it has the advantage of low cost.

[0109] In addition, the present application does not need to increase the growth thickness of the hard mask layer 206 to reduce the height of the second step structure, and can also reduce the production cost.

[0110] The present application is described in detail by the specific embodiments above, but these do not constitute the limitation of the present application. Those skilled in the art can also make many modifications and improvements without departing from the principle of the present application, and these should also be considered as the protection scope of the present application.

Claims

1. A method for improving the loading of a polysilicon CMP, characterized in that, The method comprises the following steps: Step one, providing a semiconductor substrate with completed top polysilicon growth and CMP, the CMP load effect is that the top surface of the top polysilicon is uneven, and has a higher first surface in a first area and a lower second surface in a second area, a first step structure is formed between the first surface and the second surface, and the second surface and the first step structure on both sides form a first groove; Step two, forming a hard mask layer on the surface of the top polysilicon, and a second step structure formed by transferring the first step structure and a second groove formed by transferring the first groove are formed on the top surface of the hard mask layer; Step three, forming a second dielectric layer on the top surface of the hard mask layer, the material of the second dielectric layer meets the requirement of selective etching with the hard mask layer, and the second dielectric layer does not completely fill the second groove; Step four, forming a third material layer on the surface of the second dielectric layer by coating process, and the second groove is completely filled by using the flowability of the third material layer in the coating process, and the top surface of the third material layer is a flat surface; The material of the third material layer meets the requirement of selective etching with the second dielectric layer; Step five, performing first back etching on the third material layer with the second dielectric layer as a stop layer; Step six, performing second back etching on the second dielectric layer with the hard mask layer as a stop layer; Step seven, measuring the height of the second dielectric layer located on the side of the second groove and obtaining a first height value; Step eight, performing third etching on the hard mask layer with the remaining second dielectric layer and the third material layer as a mask, and the etching amount of the third etching is equal to the first height value; Step nine, removing the remaining second dielectric layer and the third material layer, so that the top surface of the hard mask layer is exposed and flat.

2. The method of claim 1, wherein the method is performed in a CMP tool. In step one, the semiconductor substrate comprises a silicon substrate.

3. The method of claim 2, wherein the method is performed by: In step two, the hard mask layer is composed of a fourth silicon nitride layer and a fifth oxide layer; ​ The thickness of the fifth oxide layer is greater than that of the fourth silicon nitride layer; the lower top surface of the fifth oxide layer is higher than the higher top surface of the fourth silicon nitride layer, and in step eight, the third etching is only performed on the fifth oxide layer.

4. The method of claim 3, wherein the method is performed by: In step three, the material of the second dielectric layer is silicon nitride. ​ 5. The method of improving polysilicon CMP loading as claimed in claim 4, wherein: In step four, the material of the third material layer is a carbon coating layer.

6. The method of improving polysilicon CMP loading as claimed in claim 5, wherein: The first back etching adopts dry etching.

7. The method of improving polysilicon CMP loading as claimed in claim 4, wherein: The second back etching adopts dry etching.

8. The method of improving polysilicon CMP loading as claimed in claim 3, wherein: The third etching adopts dry etching.

9. The method for improving polycrystalline silicon CMP loading as described in claim 5, characterized in that: In step nine, the second dielectric layer and the third material layer are removed by wet etching.

10. The method for improving polycrystalline silicon CMP loading as described in claim 5, characterized in that: In step one, the top polysilicon is used to form a polysilicon control gate of a semi-floating gate device; The first area is an active area, and the second area is a shallow trench isolation formation area, and the active area is composed of the semiconductor substrate located between the shallow trench isolations; In the first area, the bottom of the top polysilicon also forms a bottom polysilicon, and the bottom polysilicon is used to form a polysilicon semi-floating gate. A control gate dielectric layer is isolated between the top polysilicon and the bottom polysilicon, and a control gate dielectric layer is also isolated between the top polysilicon and the shallow trench isolation; A floating gate dielectric layer is isolated between the polysilicon semi-floating gate and the semiconductor substrate, and an opening is formed in a partial area of the floating gate dielectric layer to allow the polysilicon semi-floating gate to directly contact the semiconductor substrate to form a PN junction.

11. The method of improving polysilicon CMP loading as claimed in claim 10, wherein: The height of the first step structure is greater than or equal to 300 Å.

12. The method of claim 11, wherein the improvement in polysilicon CMP loading is characterized by: The height of the second step structure is greater than the height of the first step structure.

13. The method of claim 12, wherein the improvement in polysilicon CMP loading is characterized by: The thickness of the second dielectric layer is less than or equal to 300 Å.

14. The method for improving polycrystalline silicon CMP loading as described in claim 13, characterized in that: The thickness of the third material layer is greater than or equal to 2000 Å.

15. The method of claim 10, wherein the improvement in polysilicon CMP loading is characterized by, Further comprising: Photolithography defines a formation area of a gate structure of the semi-floating gate device; The top polysilicon, the control gate dielectric layer, the bottom polysilicon, and the floating gate dielectric layer are etched in sequence to form the gate structure of the semi-floating gate device.

16. The method for improving polycrystalline silicon CMP loading as described in claim 4, characterized in that: The second dielectric layer is formed by a PVD process in step three.

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