Soi wafer and method for manufacturing tsv in soi wafer
The two-layer SOI wafer TSV fabrication method eliminates the notch effect of etched holes, solves the problem of abnormal morphology in traditional methods, improves the reliability and consistency of TSV, enhances high-frequency performance, and simplifies the process flow.
Patent Information
- Application Number
- CN202111008265.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2021-04-29
- Filing Date
- 2021-09-01
- Publication Date
- 2025-11-04
- Estimated Expiration
- 2041-09-01
AI Technical Summary
Traditional SOI wafer TSV processes suffer from morphological abnormalities caused by loading effects and gaps at different material interfaces during via etching, which affect device reliability and consistency, especially in high-frequency applications where parasitic inductance is increased, reducing device performance.
The SOI wafer TSV fabrication method employs a two-layer structure. By forming a first hole on the surface of the epitaxial layer and backfilling it with an insulating filler layer, the number of etching layers is reduced, the notch effect is eliminated, and an oxide layer and a diffusion barrier layer are formed in the third hole, which is then filled with conductive material to form a TSV via.
It improves the reliability and consistency of TSVs, reduces high-frequency parasitic inductance, enhances the high-frequency performance of devices, simplifies the process, is compatible with existing silicon manufacturing processes, and manufactures high-quality TSV vias.
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Figure CN115274548B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a TSV manufacturing method, in particular to a SOI wafer and a TSV manufacturing method in the SOI wafer, and belongs to the technical field of semiconductors. BACKGROUND
[0002] Figure 1a And Figure 1b is a schematic diagram of a TSV etching profile of a traditional SOI, wherein 1 is a silicon substrate, 2 is an insulating layer of silicon dioxide, 3 is an epitaxial silicon layer, 6 is a hole formed after etching the epitaxial silicon, the insulating layer of silicon dioxide and the substrate silicon, and 61 is a notching effect of the through hole caused by etching load effect in the etching process. The TSV process of the traditional SOI passes through the epitaxial silicon layer, the insulating layer and the silicon substrate when etching the through hole, and the load effect and different etching selection ratios will affect the morphology of the through hole, such as consistency and uniformity, thereby reducing the reliability and consistency of the device; and the alternative etching of the epitaxial silicon layer, the insulating layer and the silicon substrate will also cause notching at the interface of different materials, such as the notching 61 in Figure 1a For a three-layer structure, the serious notching will cause the insulating layer and the diffusion barrier layer on the sidewall to be deposited unevenly, thereby causing the sidewall leakage and electromigration problems of the TSV, and further reducing the reliability and consistency of the TSV through hole; in addition, for high-frequency applications, any abnormal morphology will cause high-frequency reflection, thereby increasing the parasitic inductance and reducing the high-frequency performance of the device. SUMMARY
[0003] The main purpose of the present application is to provide a SOI wafer and a TSV manufacturing method in the SOI wafer to overcome the deficiencies in the prior art.
[0004] To achieve the above-mentioned purposes, the technical solutions adopted by the present application include:
[0005] The present application provides a TSV manufacturing method in a SOI wafer, comprising:
[0006] 1) providing an epitaxial structure, the epitaxial structure comprising a substrate, an insulating layer and an epitaxial layer stacked in sequence, wherein the material of the substrate and the epitaxial layer is different from the material of the insulating layer;
[0007] 2) processing a first hole in a first region on the surface of the epitaxial layer, and exposing the insulating layer from the first hole;
[0008] 3) setting an insulating filling layer with the same material as the insulating layer in the first hole, the top surface of the insulating filling layer being located in the first hole, or the top surface of the insulating filling layer being flush with or higher than the surface of the epitaxial layer;
[0009] 4) processing a second region in the first region to form a third hole, and making the third hole penetrate the insulating filling layer, the insulating layer along the thickness direction and extend into the substrate, wherein the epitaxial layer and the third hole are left with the insulating filling layer;
[0010] 5) sequentially forming an oxidation layer and a diffusion barrier layer on the sidewall of the third hole;
[0011] 6) filling a conductive material in the third hole, and removing part of the substrate to expose the conductive material, thereby forming a TSV via.
[0012] The embodiment of the present application also provides an SOI wafer formed by the manufacturing method.
[0013] Compared with the prior art, the advantages of the present application include:
[0014] 1) The manufacturing method of the TSV in the SOI wafer provided by the embodiment of the present application reduces the number of etched different material layers from three layers to two layers, eliminates the notch effect of the etched hole, avoids the problem that the hole has a notch and it is difficult to deposit an oxidation layer and a diffusion barrier layer on the sidewall of the hole, improves the reliability and consistency of the TSV, reduces the high-frequency parasitic inductance caused by abnormal morphology, and thus improves the high-frequency performance of the device;
[0015] 2) The manufacturing method of the TSV in the SOI wafer provided by the embodiment of the present application can also relieve the stress mismatch of the TSV by backfilling amorphous silicon dioxide in the first hole after the first etching;
[0016] 3) The manufacturing method of the TSV in the SOI wafer provided by the embodiment of the present application is simple in process, compatible with the existing silicon manufacturing process, and can very conveniently manufacture a high-quality TSV via. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1a 、 Figure 1b is a cross-sectional structure schematic diagram of a TSV after etching in a traditional SOI wafer in the prior art;
[0018] Figures 2a-2h is a flow structure schematic diagram of a manufacturing method of a TSV in an SOI wafer provided by a typical embodiment case of the present application. DETAILED DESCRIPTION
[0019] In view of the deficiencies in the prior art, the present inventors have long-term research and a large number of practices, and thus propose the technical solution of the present application. The technical solution, the implementation process and principles thereof will be further explained and described as follows.
[0020] The embodiment of the present application provides a manufacturing method of a TSV in an SOI wafer, which comprises:
[0021] 1) providing an epitaxial structure, the epitaxial structure comprising a substrate, an insulating layer and an epitaxial layer stacked in sequence, wherein the material of the substrate and the epitaxial layer is different from the material of the insulating layer;
[0022] 2) processing a first hole in a first region on the surface of the epitaxial layer, and exposing the insulating layer from the first hole;
[0023] 3) disposing an insulating filling layer with the same material as the insulating layer in the first hole, the top surface of the insulating filling layer being located in the first hole, or the top surface of the insulating filling layer being flush with or higher than the surface of the epitaxial layer;
[0024] 4) processing a third hole in a second region within the first region, and extending the third hole through the insulating filling layer, the insulating layer and into the substrate in the thickness direction, wherein the epitaxial layer and the third hole are left with the insulating filling layer therebetween;
[0025] 5) sequentially forming an oxidation layer and a diffusion barrier layer on the sidewall of the third hole;
[0026] 6) filling a conductive material in the third hole, and removing part of the substrate to expose the conductive material, thereby forming a TSV via.
[0027] In an embodiment, the manufacturing method specifically comprises: disposing a first mask on the surface of the epitaxial layer, etching the first region not covered by the first mask, and stopping etching when reaching the insulating layer as the etching stop layer, thereby forming the first hole in the epitaxial layer.
[0028] In an embodiment, the manufacturing method specifically comprises: disposing a second mask on the surface of the epitaxial layer, etching the second region not covered by the second mask, and removing the insulating filling layer, the insulating layer and part of the substrate in the second region, thereby forming a third hole, wherein the second region is located in the first region, and the orthographic projection of the third hole is entirely located in the orthographic projection of the first hole.
[0029] In an embodiment, the manufacturing method specifically comprises:
[0030] In an embodiment, the manufacturing method specifically comprises: disposing a second mask on the surface of the epitaxial layer, etching the second region not covered by the second mask, and stopping etching when reaching the substrate as the etching stop layer, thereby forming a second hole, wherein the second region is located in the first region, the orthographic projection of the second hole is entirely located in the orthographic projection of the first hole, and the epitaxial layer and the second hole are left with the insulating filling layer therebetween.
[0031] Continuously etching the substrate at the bottom of the second hole to remove part of the substrate, so as to form a third hole.
[0032] In an embodiment, the interface between the insulating layer and the substrate in the three holes has defects, while the interface between the insulating layer and the epitaxial layer has no defects.
[0033] In an embodiment, the aperture or width of the second hole and the third hole is the same, and the aperture or width of the second hole and the third hole is smaller than that of the first hole.
[0034] In an embodiment, the aperture or width difference between the first hole and the second hole or the third hole is 0.5-8 μm.
[0035] In an embodiment, the width of the remaining insulating filling layer between the epitaxial layer and the second hole or the third hole in the radial direction of the second hole or the third hole is 0.25-4 μm.
[0036] In an embodiment, the thickness of the remaining substrate at the bottom of the third hole is 5-400 μm.
[0037] In an embodiment, the material of the oxide layer includes silicon oxide, and the thickness of the oxide layer is 20 nm-20 μm.
[0038] In an embodiment, the diffusion barrier layer includes a Ti layer and a TiN layer stacked in the radial direction of the third hole, the thickness of the Ti layer is 50-200 nm, and the thickness of the TiN layer is 100-600 nm.
[0039] In an embodiment, the manufacturing method specifically includes: thinning the substrate to expose the conductive material, preferably, the conductive material is a metal conductive material, and the metal conductive material includes tungsten.
[0040] In an embodiment, the materials of the substrate and the epitaxial layer are both silicon, and the material of the insulating layer is silicon dioxide.
[0041] The embodiment of the present application also provides an SOI wafer formed by the manufacturing method.
[0042] In an embodiment, the thickness of the substrate is 10-500 μm, the thickness of the insulating layer is 20 nm-20 μm, and the thickness of the epitaxial layer is 10 nm-20 μm.
[0043] The technical solutions, implementation processes and principles thereof will be further explained in combination with the accompanying drawings. Unless otherwise specified, the deposition, epitaxy, thinning, etching and other processes used in the embodiments of the present application can be known to those skilled in the art.
[0044] Embodiment 1
[0045] Please refer to Figures 2a-2h A method for manufacturing a TSV in an SOI wafer, comprising the following steps:
[0046] 1) manufacturing an epitaxial structure as shown in Figure 2a , the epitaxial structure comprising a substrate 1, an insulating layer 2 and an epitaxial layer 3 stacked in sequence, wherein the substrate 1 and the epitaxial layer 3 are both made of silicon, and the insulating layer 2 is made of silicon dioxide, the substrate 1 has a thickness of 100 um, the insulating layer 2 has a thickness of 600 nm, and the epitaxial layer 3 has a thickness of 400 nm;
[0047] 2) as shown in Figure 2b , a first mask is arranged on the surface of the epitaxial layer 3, the opening region of the first mask has a length and a width both of W1, for example, W1 = 8 um, a first region not covered by the first mask is subjected to etching treatment, and the insulating layer 2 is used as an etching stop layer, so that the etching is stopped when reaching the insulating layer 2, thereby forming a first hole 4 penetrating through the epitaxial layer 3 along the thickness in the epitaxial structure, and the insulating layer 2 is exposed from the first hole 4, and it can be understood that the aperture or width of the first hole 4 is W1;
[0048] 3) as shown in Figure 2c , an insulating filling layer 11 made of the same material as the insulating layer 2 is deposited in the first hole 4, the top surface of the insulating filling layer 11 is located in the first hole 4, or the top surface of the insulating filling layer 11 is flush with or higher than the surface of the epitaxial layer 3, and it can be understood that if the top surface of the insulating filling layer 11 is higher than the surface of the epitaxial layer 3, the CMP process is used to grind the insulating filling layer 11, so that the top surface of the insulating filling layer 11 is flush with the surface of the epitaxial layer;
[0049] 4) as shown in Figure 2dAs shown, a second mask is arranged on the surface of the epitaxial layer 3, the opening area of the second mask is smaller than that of the first mask, the length and width of the opening of the second mask are W2, for example, W2=5um, the second region not covered by the second mask is etched, the substrate 1 is used as the etching stop layer, so that the etching stops when reaching the substrate 1, thereby forming a second hole 5 in the epitaxial structure, which penetrates the insulating filling layer 11 and the insulating layer 2 along the thickness direction, wherein the substrate 1 is exposed from the second hole 5, the second region is completely within the first region, and the remaining insulating filling layer between the epitaxial layer and the second hole or the third hole has a width of 1.5um in the radial direction of the second hole or the third hole. It can be understood that the aperture or width of the second hole is W2, and the second hole is coaxially etched with the first hole, and the remaining insulating filling layer between the epitaxial layer and the second hole or the third hole has a width of (W1-W2) / 2 in the radial direction of the second hole or the third hole.
[0050] 5) as shown in Figure 2e , the substrate 1 at the bottom of the second hole 5 is continuously etched to remove part of the substrate 1 at the bottom of the second hole 5 to form a third hole 6, and finally the thickness of the substrate 1 remaining at the bottom of the third hole 6 is 80um;
[0051] 6) as shown in Figure 2f , a silicon oxide layer 7 and a Ti / TiN diffusion barrier layer 8 are sequentially deposited on the sidewall of the third hole 6, wherein the thickness of the silicon oxide layer 7 is 100nm, the thickness of the Ti layer 8 in the Ti / TiN diffusion barrier layer is 200nm, and the thickness of the TiN layer 9 is 500nm;
[0052] 6) as shown in Figure 2g , a conductive material 10 is deposited in the third hole 6, for example, it can be tungsten metal. It can be understood that the conductive material formed is in a columnar shape;
[0053] 7) as shown in Figure 2h , the substrate 1 is thinned to expose the conductive material 10 from the surface of the substrate 1 opposite to the insulating layer 2, thereby forming a TSV via hole.
[0054] Comparative Example 1
[0055] Please refer to Figure 1a and Figure 1b , a method for manufacturing a TSV in an SOI wafer, comprising the following steps:
[0056] 1) as shown in Figure 2aThe epitaxial structure shown in the figure comprises a substrate 1, an insulating layer 2 and an epitaxial layer 3 which are sequentially stacked, wherein the material of the substrate 1 and the epitaxial layer 3 is silicon, the material of the insulating layer 2 is silicon dioxide, the thickness of the substrate 1 is 100 um, the thickness of the insulating layer 2 is 600 nm, and the thickness of the epitaxial layer 3 is 400 nm;
[0057] 2) A mask is arranged on the surface of the epitaxial layer 3, and an etching treatment is performed on the region not covered by the mask to form a third hole 6 which penetrates the epitaxial layer 3, the insulating layer 2 and extends into the substrate 1 in the thickness direction, wherein a gap 61 is formed between the epitaxial layer 3 and the insulating layer 2;
[0058] 3) A conductive material 10 is arranged in the third hole 6, the conductive material is in the shape of a square column, and a thinning treatment is performed on the substrate 1 so that the conductive material 10 is exposed from the surface of the substrate 1 which is opposite to the insulating layer 2, thereby forming a TSV via hole.
[0059] The disadvantage of the TSV process of the SOI wafer in Comparative Example 1 is that continuous etching of multiple layers of different materials can cause abnormal morphology of the via hole, especially at the interface of different materials, which is caused by the etching ratio and anisotropy defects of different materials.
[0060] The TSV manufacturing method of the SOI wafer provided by the embodiment of the present application reduces the number of layers of different materials to be etched from three layers to two layers, eliminates the gap effect of the etching hole, avoids the problem that it is difficult to deposit an oxide layer and a diffusion barrier layer on the sidewall of the hole due to the gap of the hole, improves the reliability and consistency of the TSV via hole, reduces the high-frequency parasitic inductance caused by abnormal morphology, and thus improves the high-frequency performance of the device.
[0061] In addition, the amorphous silicon dioxide backfilled in the first hole after the first etching can also relieve the stress mismatch of the TSV.
[0062] In addition, the TSV manufacturing method of the SOI wafer provided by the embodiment of the present application is simple in process, compatible with the existing silicon manufacturing process, and can very conveniently manufacture a high-quality TSV via hole.
[0063] It should be understood that the above embodiments are only for illustrating the technical concept and characteristics of the present application, and the purpose is to enable those skilled in the art to understand the content of the present application and implement it, and cannot limit the protection scope of the present application. Any equivalent changes or modifications made according to the spirit and principle of the present application should be covered within the protection scope of the present application.
Claims
1. A method for fabricating a TSV in an SOI wafer, characterized in that... include: 1) Provide an epitaxial structure, the epitaxial structure comprising a substrate, an insulating layer and an epitaxial layer stacked sequentially, wherein the materials of the substrate and the epitaxial layer are different from the material of the insulating layer; 2) A first hole is formed in a first region on the surface of the epitaxial layer, and the insulating layer is exposed from the first hole; 3) An insulating filling layer of the same material as the insulating layer is provided in the first hole, and the top surface of the insulating filling layer is located in the first hole, or the top surface of the insulating filling layer is flush with or higher than the surface of the epitaxial layer. 4) A third hole is formed in a second region within the first region, and the third hole extends through the insulating filler layer and the insulating layer along the thickness direction and into the substrate, wherein the insulating filler layer remains between the epitaxial layer and the third hole; 5) An oxide layer and a diffusion barrier layer are sequentially formed on the sidewall of the third hole; 6) Fill the third hole with conductive material and remove part of the substrate to expose the conductive material, thereby forming a TSV via.
2. The manufacturing method according to claim 1, characterized in that... Specifically, it includes: A first mask is provided on the surface of the epitaxial layer, and the first area not covered by the first mask is etched. An insulating layer is used as an etching barrier layer to stop the etching when it reaches the insulating layer, thereby forming the first hole in the epitaxial layer.
3. The manufacturing method according to claim 1, characterized in that... Specifically, it includes: A second mask is provided on the surface of the epitaxial layer, and the second region not covered by the second mask is etched to remove the insulating filler layer, the insulating layer and part of the substrate located in the second region, thereby forming a third hole, wherein the second region is located in the first region, and the orthographic projection of the third hole is entirely located within the orthographic projection of the first hole.
4. The manufacturing method according to claim 1 or 3, characterized in that... Specifically, it includes: A second mask is provided on the surface of the epitaxial layer, and the second region not covered by the second mask is etched. An insulating layer is used as an etching barrier layer to stop the etching when it reaches the substrate, thereby forming a second hole. The second region is located within the first region, and the orthographic projection of the second hole is entirely within the orthographic projection of the first hole. The insulating filling layer remains between the epitaxial layer and the second hole. The substrate at the bottom of the second hole is etched to remove part of the substrate, thereby forming the third hole.
5. The manufacturing method according to claim 4, characterized in that: The second hole and the third hole have the same diameter or width, and the diameter or width of the second hole and the third hole is smaller than the diameter or width of the first hole.
6. The manufacturing method according to claim 5, characterized in that: The difference in diameter or width between the first hole and the second or third hole is 0.5-8 μm.
7. The manufacturing method according to claim 5, characterized in that: The width of the insulating filler layer remaining between the epitaxial layer and the second or third hole in the radial direction of the second or third hole is 0.25-4 μm.
8. The manufacturing method according to claim 4, characterized in that: The thickness of the substrate remaining at the bottom of the third hole is 5-400 μm.
9. The manufacturing method according to claim 1, characterized in that: The oxide layer is made of silicon oxide and has a thickness of 20 nm to 20 μm.
10. The manufacturing method according to claim 1, characterized in that: The diffusion barrier layer includes a Ti layer and a TiN layer stacked along the radial direction of the third hole, wherein the thickness of the Ti layer is 50-200 nm and the thickness of the TiN layer is 100-600 nm.
11. The manufacturing method according to claim 1, characterized in that... Specifically, it includes: The substrate is thinned to expose the conductive material.
12. The manufacturing method according to claim 11, characterized in that: The conductive material is a metallic conductive material, which includes tungsten metal.
13. The manufacturing method according to claim 1, characterized in that: The substrate and epitaxial layer are both made of silicon, and the insulating layer is made of silicon dioxide.
14. An SOI wafer formed by the fabrication method according to any one of claims 1-13.
15. The SOI wafer according to claim 14, characterized in that: The substrate has a thickness of 10-500 μm, the insulating layer has a thickness of 20 nm-20 μm, and the epitaxial layer has a thickness of 10 nm-20 μm.
Citation Information
Patent Citations
Semiconductor structure, preparation method thereof, wafer and chip manufacturing method
CN117637606A