Chip-on-film and packaging method thereof

Abstract

The present application discloses a chip-on-film and a packaging method thereof, wherein the chip-on-film comprises: a first tape; a second tape, which is partially stacked with the first tape, and a first conductive member is formed in the stacked portion of the first tape and the second tape, a first chip is welded to a first extension portion of the first tape protruding from the second tape, a second chip is welded to a second extension portion of the second tape protruding from the first tape, and the first chip and the second chip are electrically connected via the first conductive member. In the above manner, the present application can increase the number of chips in the chip-on-film.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a chip-on-chip film and a packaging method thereof. Background Art

[0002] In the field of semiconductor technology, Chip-on-Film (COF) packaging is a widely used IC packaging technology. COF is a technology that uses a tape as a carrier for packaging chips and connects the metal bumps on the chip to the inner pins on the tape through thermal compression.

[0003] At present, the tape in the Chip on Tape Film is a single-layer design, which limits the number of pins allowed, and therefore the number of chips packaged in the Chip on Tape Film is also limited accordingly. However, as the resolution of the display screen increases, the number of chips used is also increasing, so how to enable the Chip on Tape Film to package more chips is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The purpose of the present application is to provide a chip-on-film and a packaging method thereof, which can increase the number of chips in the chip-on-film.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a flip chip film, including: a first roll; a second roll, which is partially stacked with the first roll, and a first conductive member is formed in the stacked portion of the first roll and the second roll, a first chip is welded on a first extension portion of the first roll protruding from the second roll, and a second chip is welded on a second extension portion of the second roll protruding from the first roll, and the first chip and the second chip are electrically connected through the first conductive member.

[0006] In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a display device, comprising any of the above-mentioned chip-on-films.

[0007] To solve the above technical problems, another technical solution adopted in the present application is: to provide a packaging method for a chip-on-film, comprising: providing a first tape and a second tape; partially stacking the first tape and the second tape, and forming a first conductive member in the stacked portion of the first tape and the second tape, so that a first chip welded on a first extension portion of the first tape protruding from the second tape and a second chip welded on a second extension portion of the second tape protruding from the first tape are electrically connected through the first conductive member.

[0008] The beneficial effect of the present application is that, different from the prior art, the chip-on-film provided by the present application enables the first tape and the second tape to be partially stacked, and a first conductive member is formed in the stacked portion of the first tape and the second tape, and the first chip on the first tape and the second chip on the second tape are electrically interconnected through the first conductive member, so that the chip-on-film can encapsulate more chips and increase the number of chips in the chip-on-film. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] Figure 1 This is a schematic structural diagram of an implementation method of a flip chip film of the present application;

[0011] Figure 2 This is a schematic structural diagram of another embodiment of the flip chip film of the present application;

[0012] Figure 3 for Figure 1 A top view of the chip-on-film plus frame structure;

[0013] Figure 4 It is a structural schematic diagram of an embodiment of a display device of the present application;

[0014] Figure 5 It is a schematic flow chart of an implementation method of a chip-on-chip packaging method of the present application. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0016] See also Figure 1 , Figure 1 1 is a schematic structural diagram of a Chip-on-Flip Film (CFP) according to an embodiment of the present invention. The CFP 100 includes a first tape roll 1 , a second tape roll 2 , a first chip 4 and a second chip 5 .

[0017] The second tape 2 is partially stacked with the first tape 1, and a first conductive member 10 is formed in the stacked portion of the first tape 1 and the second tape 2, and the first conductive member 10 can transmit electrical signals. The first tape 1 and the second tape 2 are made of polyimide or polyester film as a substrate, and are highly reliable and excellently flexible printed circuit boards, which have the characteristics of high wiring density, light weight, thin thickness, and good bendability.

[0018] At the same time, the first tape 1 protrudes from the second tape 2 to form a first extension portion 11, the second tape 2 protrudes from the first tape 1 to form a second extension portion 12, the first chip 4 is welded on the first extension portion 11, and the second chip 5 is welded on the second extension portion 12. Among them, pins are formed on the first extension portion 11, and metal bumps are formed on the functional surface of the first chip 4. The solder is heated at high temperature by a reflow process so that the metal bumps and pins are welded in a fusion eutectic manner. Among them, the welding structure between the second chip 5 and the second extension portion 12 is similar to the welding structure between the first chip 4 and the first extension portion 11, and will not be described in detail here.

[0019] At the same time, the first chip 4 and the second chip 5 are electrically connected via the first conductive member 10 , that is, the first chip 4 and the second chip 5 can transmit electrical signals via the first conductive member 10 .

[0020] The number of the first chips 4 welded on the first extension portion 11 may be one or more, which is not limited here. Similarly, the number of the second chips 5 welded on the second extension portion 12 may be one or more.

[0021] At the same time, the number of first conductive members 10 formed in the stacked part can be one or more, and the first chip 4 can be electrically connected to the second chip 5 only through one first conductive member 10, or can be electrically connected to the second chip 5 through two, three or more first conductive members 10 at the same time, without limitation. It can be understood that the more the number of first conductive members 10, the stronger the welding strength between the first tape 1 and the second tape 2, and the more reliable the chip-on-chip film 100 can be. In the related art, the tape in the chip-on-chip film 100 is usually a single-layer design, and the allowable pins are limited. Therefore, the number of chips packaged in the chip-on-chip film 100 is also limited, and the mechanical strength of the single-layer tape is relatively small, and it is impossible to stack multiple layers of chips. However, in the present embodiment, the first tape 1 and the second tape 2 are stacked, and the first chip 4 on the first tape 1 and the second chip 5 on the second tape 2 are electrically interconnected through the first conductive member 10, so that the number of chips in the chip-on-chip film 100 can be increased.

[0022] Please continue reading Figure 1In this embodiment, the first chip 4 is welded on a side surface of the first extension portion 11 facing the second tape 2 , and the second chip 5 is welded on a side surface of the second extension portion 12 facing away from the first tape 1 .

[0023] Specifically, the above arrangement can facilitate operators to observe whether the first chip 4 and the second chip 5 are damaged from the same direction during the preparation process, thereby improving process efficiency.

[0024] Of course, the present application is not limited thereto. In other embodiments, Figure 2 As shown, the first chip 4 may also be welded on a side surface of the first extension portion 11 facing the second tape 2 , while the second chip 5 may be welded on a side surface of the second extension portion 12 facing the first tape 1 .

[0025] Please continue reading Figure 1 In this embodiment, the first conductive member 10 includes a first pin 7 and a second pin 8, wherein the first pin 7 is formed on a side surface of the first tape 1 facing the second tape 2, and the first pin 7 is electrically connected to the first chip 4; the second pin 8 is formed on a side surface of the second tape 2 facing the first tape 1, and the second pin 8 is electrically connected to the second chip 5, and the first pin 7 is electrically connected to the second pin 8.

[0026] Specifically, during the preparation process, the first tape 1 and the second tape 2 are partially stacked and placed, and then the first pins 7 and the second pins 8 are arranged opposite to each other and electrically connected together.

[0027] Among them, Figure 1 As shown, when the first pin 7 and the first chip 4 are arranged on the same side of the first tape 1, the first pin 7 is electrically connected to the first chip 4 through a circuit image (not shown) formed on the surface of the first tape 1, and when the second pin 8 and the second chip 5 are arranged on different sides of the second tape 2, the second pin 8 is connected to the third pin 9 through a through hole that penetrates the second tape 2 and is filled with a conductive material, wherein the third pin 9 and the second chip 5 are arranged on the same side of the second tape 2, and the third pin 9 is electrically connected to the second chip 5 through a circuit pattern (not shown) formed on the surface of the second tape 2.

[0028] It should be noted that, in other embodiments, the first conductive member 10 can also be other structures. For example, the first conductive member 10 includes a conductive column, which runs through the second tape 2, one end of which is electrically connected to the first chip 4 through the circuit pattern on the first tape 1, and the other end is electrically connected to the second chip 5 through the circuit pattern on the second tape 2, thereby realizing the electrical connection between the first chip 4 and the second chip 5 through the conductive column.

[0029] In this embodiment, the first pin 7 and the second pin 8 may be electrically interconnected by welding material or by conductive adhesive.

[0030] When electrical interconnection is achieved through welding material, welding material is formed on the surface of the first pin 7 and / or the second pin 8, and the first pin 7 and the second pin 8 are electrically connected through the welding material, that is, welding material is formed on the surface of at least one of the first pin 7 and the second pin 8. The welding material can be Au, Pb, Sn or a combination thereof. For example, in an application scenario, the material of the first pin 7 and the second pin 8 is copper (Cu), and the welding material tin (Sn) is formed on the surface of both.

[0031] When electrical interconnection is achieved through conductive glue, the conductive glue can be any glue that has an adhesive effect and can conduct electricity. In one application scenario, the conductive glue is set to be anisotropic conductive glue (ACF), which can only conduct electricity in the vertical direction but not in the parallel direction. When there are multiple first conductive members 10, during the preparation process, anisotropic conductive glue can be formed on the first pins 7 of the multiple first conductive members 10 by smearing or spraying. At this time, the anisotropic conductive glue on the multiple first pins 7 can be in contact with each other, and will not cause a short circuit between the first pins 7, thereby improving the preparation efficiency.

[0032] It is understandable that when the conductive glue is ordinary conductive glue, that is, it can conduct electricity in any direction, the conductive glue on different first pins 7 cannot contact, otherwise it will cause a short circuit between the first pins 7. At this time, it is necessary to use a glue dispensing method to apply conductive glue on each first pin 7 separately.

[0033] In summary, the present application does not impose any specific restrictions on the specific electrical connection structure between the first pin 7 and the second pin 8, as long as the electrical connection between the first pin 7 and the second pin 8 can be achieved.

[0034] Continue reading Figure 1 In this embodiment, the chip on film 100 further includes a third tape 3 and a third chip 6 .

[0035] The third tape 3 is partially stacked with the second extension portion 12, and a second conductive member 13 is formed in the stacked portion of the third tape 3 and the second extension portion 12. A third chip 6 is welded to a third extension portion 14 of the third tape 3 protruding from the second extension portion 12, and the third chip 6 is electrically connected to the second chip 5 through the second conductive member 13. The third tape 3 is arranged on the side of the second tape 2 away from the first tape 1.

[0036] The structure of the second conductive element 13 is similar to that of the first conductive element 10 , and will not be described in detail herein.

[0037] In this embodiment, the third tape roll 3 is arranged on the side of the second tape roll 2 away from the first tape roll 1. However, in other embodiments, the third tape roll 3 may also be arranged on the side of the second tape roll 2 facing the first tape roll 1.

[0038] It should be noted that in other embodiments, more tapes and more chips can be provided by analogy with the positional relationship among the first tape 1 , the second tape 2 , and the third tape 3 , so that the chip-on-film 100 can encapsulate more chips, which is not limited here.

[0039] See also Figure 3 , Figure 3 for Figure 1 Schematic top view of a COF frame structure. The COF 100 further includes a frame 110 .

[0040] The frame 110 is disposed on the periphery of the first roll 1 and the second roll 2, and is used to carry the first roll 1 and the second roll 2. The material of the frame 110 can be copper, aluminum, silver, alloy, or a combination of the above.

[0041] See also Figure 4 , Figure 4 The display device 200 includes a COF 210 , which has the same structure as the COF 100 in any of the above embodiments. For details, please refer to the above embodiments, which will not be described here.

[0042] The present application does not specifically limit the type of the display device 200 , which may be an LCD (Liquid Crystal Display) display device or an OLED (Organic Light-Emitting Diode) display device.

[0043] The above-mentioned chip-on-film 100 is further described below from the perspective of the preparation method. Figure 5 , Figure 5 This is a schematic diagram of a process for preparing a flip chip film according to an embodiment of the present invention, and is combined with Figures 1 to 3 , the preparation method comprises:

[0044] S10: Provide a first tape roll 1 and a second tape roll 2.

[0045] S20: The first tape 1 and the second tape 2 are partially stacked, and a first conductive member 10 is formed in the stacked portion of the first tape 1 and the second tape 2, so that the first chip 4 welded on the first extension portion 11 of the first tape 1 protruding from the second tape 2 and the second chip 5 welded on the second extension portion 12 of the second tape 2 protruding from the first tape 1 are electrically connected through the first conductive member 10.

[0046] In one application scenario, step S20 partially stacks the first tape 1 and the second tape 2, including:

[0047] S21 : Soldering material is formed on the surfaces of the first pins 7 arranged on the surface of the first tape 1 facing the second tape 2 and the second pins 8 arranged on the surface of the second tape 2 facing the first tape 1 .

[0048] S22: The first pin 7 and the second pin 8 are electrically connected.

[0049] Specifically, a soldering material is formed on the surface of the first pin 7 and / or the second pin 8, and the soldering material can be Au, Pb, Sn or a combination thereof, which is not limited here. For example, in an application scenario, the material of the first pin 7 and the second pin 8 is copper (Cu), and a soldering material tin (Sn) is formed on the surface of both, wherein tin (Sn) is highly valued due to its low melting point and good welding performance. At the same time, step S22 electrically connects the first pin 7 and / or the second pin 8 by adopting a reflow process, heating the solder at a high temperature, so that the first pin 7 and the second pin 8 are welded in a fusion eutectic manner.

[0050] In another application scenario, step S20 partially stacks the first tape 1 and the second tape 2 to provide another implementation method, including:

[0051] S23 : Apply conductive glue 111 on first pin 7 disposed on the surface of first tape 1 facing second tape 2 , and connect second pin 8 disposed on the surface of second tape 2 facing first tape 1 to first pin 7 through conductive glue 111 .

[0052] S24: The first pin 7 and the second pin 8 are electrically connected.

[0053] It should be noted that the number of the first pins 7 and the number of the second pins 8 are both plural, and the plurality of first pins 7 and the plurality of second pins 8 are electrically connected in a one-to-one correspondence.

[0054] Among them, the conductive glue 111 can be an anisotropic conductive glue (ACF), which can only conduct electricity in the vertical direction but not in the parallel direction. When forming the conductive glue 111 on the first pin 7, coating or spraying can be adopted, which can reduce the difficulty of preparation and improve the efficiency of preparation.

[0055] Of course, the conductive glue 111 can also be ordinary conductive glue, which can conduct electricity in any direction. However, the conductive glue 111 on different first pins 7 cannot touch each other, otherwise it will cause a short circuit between the first pins 7. At this time, it is necessary to use a glue dispensing method to apply the conductive glue 111 on each first pin 7.

[0056] It should be noted that, in other methods, a conductive glue may be formed on the second pin 8 and then the first pin 7 and the second pin 8 may be electrically connected. In short, as long as the first pin 7 and the second pin 8 can be electrically connected through the conductive glue 111, it will be sufficient.

[0057] It should be noted that the structure of the chip-on-film prepared by the packaging method in this embodiment is the same as the chip-on-film 100 in any of the above embodiments. For details, please refer to the above embodiments and will not be repeated here.

[0058] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A chip-on-film, characterized in that: The flip chip film comprises: First roll of tape; The second tape is partially stacked with the first tape, and a first conductive member is formed in the stacked portion of the first tape and the second tape, a first chip is welded to a first extension portion of the first tape protruding from the second tape, and a second chip is welded to a second extension portion of the second tape protruding from the first tape, and the first chip and the second chip are electrically connected via the first conductive member.

2. The chip-on-film according to claim 1, wherein: The first conductive member comprises: A first pin is formed on a surface of the first tape facing the second tape, and the first pin is electrically connected to the first chip; The second pin is formed on a surface of the second tape facing the first tape, the second pin is electrically connected to the second chip, and the first pin is electrically connected to the second pin.

3. The chip-on-film according to claim 2, wherein: A welding material is formed on the surface of the first pin and / or the second pin. A welding material is formed on the surface of at least one of the first pin and the second pin, and the first pin is electrically connected to the second pin through the welding material.

4. The chip-on-film according to claim 2, wherein: The first pin and the second pin are electrically connected via conductive glue.

5. The chip-on-film according to claim 4, characterized in that: The number of the first conductive members is plural, and the conductive glue is anisotropic electronic conductive glue.

6. The chip-on-film according to claim 1, wherein: The first chip is welded on a side surface of the first extension portion facing the second tape, and the second chip is welded on a side surface of the second extension portion facing away from the first tape.

7. The chip-on-film according to claim 1, wherein: The chip-on-film further comprises: The third tape is partially stacked with the second extension portion, and a second conductive member is formed in the stacked portion of the third tape and the second extension portion. A third chip is welded to the third extension portion of the third tape protruding from the second extension portion, and the third chip is electrically connected to the second chip through the second conductive member.

8. The chip-on-film according to claim 7, characterized in that: The third tape roll is arranged on a side of the second tape roll away from the first tape roll.

9. The chip-on-film according to claim 1, wherein: The chip-on-film further comprises: A frame is arranged on the periphery of the first roll tape and the second roll tape, and is used for carrying the first roll tape and the second roll tape.

10. A display device, characterized in that: The invention comprises a chip-on-film as claimed in any one of claims 1 to 9.

11. A packaging method of a chip-on-film, characterized in that: The method comprises: Providing a first tape roll and a second tape roll; The first tape and the second tape are partially stacked, and a first conductive member is formed in the stacked portion of the first tape and the second tape, so that a first chip welded on a first extension portion of the first tape protruding from the second tape and a second chip welded on a second extension portion of the second tape protruding from the first tape are electrically connected through the first conductive member.

12. The method according to claim 11, characterized in that The step of partially stacking the first tape roll and the second tape roll comprises: A first pin disposed on a surface of the first tape facing the second tape is electrically connected to a second pin disposed on a surface of the second tape facing the first tape.

13. The method according to claim 12, characterized in that A welding material is formed on the surface of the first pin and / or the second pin; The step of electrically connecting a first pin disposed on a surface of the first tape facing the second tape with a second pin disposed on a surface of the second tape facing the first tape comprises: The first pin and / or the second pin are heated so that the first pin is electrically connected to the second pin through the welding material.

14. The method according to claim 12, characterized in that The step of electrically connecting a first pin disposed on a surface of the first tape facing the second tape with a second pin disposed on a surface of the second tape facing the first tape comprises: Conductive glue is applied on the first pin, and the second pin is electrically connected to the first pin through the conductive glue.

15. The method according to claim 14, characterized in that The number of the first pins and the number of the second pins are both multiple, the multiple first pins are electrically connected with the multiple second pins in a one-to-one correspondence, and the conductive glue is anisotropic electronic conductive glue.

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