A multi-channel transceiving processing integrated high-density inner bump sip device

Abstract

The application provides a multi-channel transceiving processing integrated high-density inner bump SIP device, which internally integrates radio frequency, processing, storage and other functional devices, contains nearly 20 radio frequency transceiving channels and more than 8000 inner bumps. In the layout and wiring design, the isolation of radio frequency and high-speed digital signals is mainly considered, and an isolation degree index of more than 50 dB is realized; the heat dissipation cover adopts a special-shaped step and a sunken isolation cavity structure, so that heat dissipation is ensured and radio frequency isolation is improved; in the design of 1369 scale solder balls, the radio frequency solder balls are surrounded by floating ground, so that the wiring in the substrate is simplified and the isolation of the radio frequency key signals is ensured. The overall size of the SiP is 37.5 mm*37.5 mm*4.25 mm, which can provide support for the miniaturization and integration development of subsequent equipment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of basic electrical elements, and particularly relates to a multi-channel transceiving and processing integrated high-density inner bump sip device. BACKGROUND

[0002] With the continuous slowing down of Moore's law, domestic and foreign semiconductor companies have made a big push into the packaging field. SiP technology meets the performance requirements of various equipment with the characteristics of miniaturization, high performance and high reliability. In SiP packaging design, it is of great significance to realize high-density bump multi-channel RF transceiver and baseband processing integration with lower price, lighter weight and smaller size for the development of equipment.

[0003] In SiP design, meeting the overall size requirement and ensuring the isolation of high-density complex signals, chip layout and heat dissipation are key problems in design. The selection of SiP resistance and capacitance elements, substrate design, heat dissipation structure design and other factors will have a great impact on system reliability and yield.

[0004] In traditional equipment, in order to ensure the performance of RF high-speed signals, sensitive high-speed devices are generally distributed more dispersedly, and even isolated design is made alone, which is difficult to improve the size and weight indicators. Therefore, it is of great significance to study SiP with small size, high integration density, RF transceiver and processing integration, and good SI (Signal Integrity) and PI (Power Integrity) performance. SUMMARY

[0005] The present application is to solve the problem that the common RF and processing system architecture of existing devices and existing equipment cannot adapt to low cost, high interconnection density, small size, RF transceiver and baseband processing integration. A multi-channel transceiving and processing integrated high-density inner bump sip device is provided, which integrates RF, processing, storage and other functional devices internally, contains nearly 20 RF transceiver channels and more than 8000 internal bumps. In the layout and wiring design, the isolation of RF and high-speed digital signals is mainly considered, and an isolation degree index better than 50dB is realized. The heat dissipation cover adopts a special-shaped step and a sunken isolation cavity structure to ensure heat dissipation while improving RF isolation. In the design of 1369 scale solder balls, the RF solder balls are surrounded by floating ground, which simplifies the internal wiring of the substrate while ensuring the isolation of RF key signals. The overall size of the SiP is 37.5mm╳37.5mm╳4.25mm, which can provide support for the miniaturization and integration of subsequent equipment.

[0006] The application provides a multi-channel transceiving processing integrated high-density inner bump sip device, which comprises a substrate, a radio frequency transceiving module arranged on the upper portion of the substrate, a processing module, a storage module, a high-speed digital wiring area electrically connected with the processing module, and a special-shaped heat dissipation cover plate packaged on the upper portion of the substrate, the outside of the radio frequency transceiving module, the processing module and the storage module, and the processing module is electrically connected with the radio frequency transceiving module and the storage module.

[0007] The substrate is a multilayer substrate, at least two bumps are arranged on the substrate, the bumps comprise radio frequency bumps and high-speed bumps, and a solder ball array is arranged on the bottom of the substrate.

[0008] The radio frequency transceiving module is used for receiving and transmitting radio frequency signals and radio frequency state signals, the radio frequency transceiving module comprises at least two radio frequency transceiving channels, radio frequency chip pins and radio frequency lead pins of the radio frequency transceiving module are arranged on the corners of the substrate.

[0009] The processing module is used for receiving radio frequency state signals, processing radio frequency data, controlling and outputting radio frequency state signals, the processing module is used for inputting and outputting high-speed digital signals, and the processing module is arranged on the side away from the radio frequency transceiving module so as to reduce crosstalk between the radio frequency signals and the high-speed digital signals.

[0010] As a preferred mode, the number of the radio frequency transceiving modules is two, the radio frequency transceiving modules are arranged on the lower left corner and the lower right corner of the substrate respectively, and the processing module, the storage module and the high-speed digital wiring area are arranged on the upper portion of the substrate.

[0011] As a preferred mode, the pins of the high-speed digital wiring area are arranged on the upper left corner of the substrate, the pin wiring of the high-speed digital wiring area uses a ground coplanar waveguide differential form, and ground hole fences are densely arranged on the two sides of the pin wiring.

[0012] As a preferred mode, the radio frequency pins of the radio frequency transceiving module are arranged around the floating ground pins, and the floating ground pins form an independent network in the sip device.

[0013] The radio frequency transceiving module and the high-speed digital wiring area both adopt independent reference ground planes.

[0014] The decoupling resistance and the capacitance integrated in the sip device are distributed around the interconnection device.

[0015] As a preferred mode, the special-shaped heat dissipation cover plate comprises a heat dissipation cover plate body and first and second grooves arranged on the lower surface of the heat dissipation cover plate body, the first groove is arranged on the top of the radio frequency transceiving module, and the second groove is arranged on the top of the processing module and the storage module.

[0016] The multi-channel transceiving processing integrated high-density inner bump sip device, as a preferred mode, the depth of the first groove is less than the depth of the second groove, the distance between the upper part of the radio frequency transceiver module and the first groove is the same as the distance between the upper part of the processing module and the storage module and the second groove, the first groove and the radio frequency transceiver module form a shielding cavity, and the number of the first grooves is two.

[0017] The multi-channel transceiving processing integrated high-density inner bump sip device, as a preferred mode, the lower surface of the heat dissipation cover plate body is fixedly connected with the upper surface of the substrate by using glue, the top of the radio frequency transceiver module is filled with heat dissipation glue at the surface of the first groove, and the top of the processing module and the storage module is filled with heat dissipation glue at the surface of the second groove.

[0018] The multi-channel transceiving processing integrated high-density inner bump sip device, as a preferred mode, the bottom of the radio frequency transceiver module, the processing module and the storage module is filled with glue between the substrate.

[0019] The multi-channel transceiving processing integrated high-density inner bump sip device, as a preferred mode, the number of the bumps is greater than 8000, the radio frequency transceiver module includes at least 20 radio frequency transceiver channels, at least 10 active chips and at least 80 passive devices are arranged in the sip device, and a flip or SMT process is used.

[0020] The multi-channel transceiving processing integrated high-density inner bump sip device, as a preferred mode, the design method of the sip device is that the radio frequency transceiver module is arranged at the lower part of the two side edges of the substrate, so that the radio frequency wiring inside the substrate is shortened, the insertion loss and return loss of the radio frequency wiring in the whole working frequency band are reduced, and the isolation degree of different radio frequency transceiver modules is improved.

[0021] The radio frequency transceiver module and the high-speed digital wiring area respectively adopt independent reference ground planes, and the high-speed digital wiring area is limited to the upper part of the substrate, so that the isolation degree between the radio frequency signal and the digital signal is improved.

[0022] The digital signal pin layout of the high-speed digital wiring area is distributed at the upper left corner of the substrate, the length of the lead-out wiring inside the packaging substrate is reduced, the ground hole fence is densely arranged on both sides of the wiring in the form of a coplanar waveguide with ground, and the isolation between Serdes signals is enhanced.

[0023] The radio frequency pin is arranged around the floating ground pin and is set as an independent network, the internal wiring complexity is simplified, and in use, the floating ground pin is connected with the PCB ground plane, so that the key radio frequency signal is isolated and protected.

[0024] By setting the first groove and the second groove on the special-shaped heat dissipation cover plate to accommodate the thinned radio frequency chip, the consistency of the internal devices of the sip device and the special-shaped heat dissipation cover plate is maintained, the stability and heat dissipation effect of the chip are improved, and the special-shaped heat dissipation cover plate is sunken in the radio frequency chip area to form a shielding cavity, and the isolation degree of the radio frequency signal and the digital signal is improved.

[0025] By gluing the gap between the special-shaped heat dissipation cover plate and the substrate, and filling the gap between the special-shaped heat dissipation cover plate and the radio frequency transceiver module, the processing module and the storage module with heat dissipation glue, the radio frequency transceiver module, the processing module and the storage module are glued and fixed in the gap between the substrate, and the stability and heat dissipation effect of the sip device are improved.

[0026] A multi-channel transceiver processing integrated high-density inner bump sip device, comprising a top special-shaped heat dissipation cover, internal devices such as radio frequency, processing and storage are integrated, and a large-scale solder ball array at the bottom; the step height is adapted according to the height of the internal device, and the point glue is used to ensure the sufficient contact between the SIP internal device and the heat dissipation cover; the heat dissipation cover is sunken around the radio frequency chip to form a shielding; containing nearly 10 active devices and nearly 80 passive devices, a total of more than 8000 internal bumps, of which the radio frequency, high-speed bumps are nearly 1000;

[0027] Nearly 20 radio frequency transceiver channels, radio frequency data, control and status signals are directly connected to the internal processing unit;

[0028] The highest speed of the high-speed digital signal can reach 12.5Gbps, which is connected to the internal processing unit and led out to the solder ball;

[0029] The internal complex signal interweaves the substrate device layout and the wiring design;

[0030] The substrate is not more than 37.5mm in length and width, and 12 layers of wiring complete the interconnection and lead-out of more than 8000 internal bumps;

[0031] The radio frequency chip and the radio frequency lead pin are placed at the corner of the substrate, realizing that the radio frequency wiring insertion loss is better than 0.5dB and the return loss is better than 15dB in the whole working frequency band;

[0032] The radio frequency wiring and the high-speed digital wiring are placed at the farthest distance in the substrate, realizing that the isolation degree of the radio frequency signal and the high-speed digital signal is better than 54dB.

[0033] 1369 solder ball leads, and the floating ground pin is used around the key radio frequency pin;

[0034] The floating ground pin is an independent network, which is connected with the ground plane when used, simplifying the wiring in the substrate while ensuring the isolation of the key radio frequency signal.

[0035] A multi-channel radio frequency transceiver and baseband processing integrated high-density inner bump SiP structure, the substrate adopts a multilayer substrate, the size is 37.5mm*37.5mm, the thickness is 1.76mm, the wiring layer number is 12 layers, to meet the high-speed, high-density, flip-chip interconnection requirements of core chips; nearly 80 passive devices and near radio frequency, processing, storage and other functional devices are integrated inside, containing nearly 20 radio frequency transceiver channels, more than 8000 internal bumps, all devices adopt flip-chip or SMT process, wherein the DDR chip is converted to flip-chip process through RDL; the top heat dissipation cover adopts a stepped design to form an optimized heat dissipation scheme for different device heights, and a shielding grid is formed around the radio frequency chip to ensure isolation. The overall size of the heat dissipation cover is 37.3mm*37.3mm, the maximum height of the step is 1.835mm, the intermediate value is 0.45mm, and the minimum value is 0.385mm; the bottom is FCBGA pin, a total of 1369 pins, pin diameter 0.6mm, pin pitch 1mm; the SiP cavity is glued on the upper and lower chips, the heat dissipation cover and the substrate are glued and connected, the overall size is 37.5mm*37.5mm*4.25mm, and the weight is not more than 25g, which can support the miniaturization and integration development of subsequent equipment.

[0036] The present application has the following advantages:

[0037] (1) The present application integrates radio frequency, processing, storage and other functional devices and nearly 80 passive devices in a limited space of 37.5mm*37.5mm*4.25, and the SiP internal multi-channel radio frequency is interleaved with 12.5Gbps high-speed digital signals, and the design is more complex, and compared with the traditional discrete device use scheme, the volume is reduced by more than 40%.

[0038] (2) In the device layout aspect, the radio frequency chip and the radio frequency lead pin are placed at the corners of the substrate, which shortens the radio frequency wiring and increases the isolation of the radio frequency signal and other signals, realizes the technical index that the radio frequency wiring insertion loss is better than 0.5dB and the return loss is better than 15dB in the whole working frequency band. The memory devices are arranged around the processing devices according to the connection relationship, which effectively reduces the wiring loss.

[0039] (3) In the wiring design aspect, the wiring resources of the radio frequency wiring and the high-speed digital wiring are preferentially guaranteed, and the wiring areas of the two are placed at the farthest distance in the substrate to reduce the crosstalk between the two, and the isolation degree index of the key radio frequency signal and other signals is better than 54dB, which guarantees the signal quality.

[0040] (4) The heat dissipation cover of the application is designed in a special-shaped step design, the step height is adapted according to the height of the main heat generating device, the inside devices of the SIP and the heat dissipation cover are ensured to be in full contact through dispensing, the risk of chip heat dissipation failure is effectively reduced, and the heat dissipation capacity of the whole SiP is increased. At the same time, the heat dissipation cover is sunken around the radio frequency chip to form a shield, effectively improving the isolation degree of radio frequency and high-speed signals.

[0041] (5) In the pin arrangement aspect of the application, the floating ground is used to surround around the radio frequency pin, the floating ground pin is an independent network inside the SiP, and is connected with the ground plane during use, which simplifies the wiring in the substrate and ensures the isolation of the radio frequency key signal.

[0042] (6) The application adopts a 12-layer substrate, which meets the strict size requirements of the appearance, and a total of more than 8000 internal bumps inside, of which nearly 1000 are high-speed and radio frequency signals, and nearly 20 are radio frequency transceiver channels. Compared with the discrete device scheme, the convenience and reliability of application are greatly improved. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 It is a side view of a multi-channel transceiver processing integrated high-density internal bump SIP device SiP.

[0044] Figure 2 It is a three-dimensional structure schematic diagram of a heat dissipation cover of a multi-channel transceiver processing integrated high-density internal bump SIP device.

[0045] Figure 3 It is a device arrangement and key wiring area schematic diagram of a multi-channel transceiver processing integrated high-density internal bump SIP device.

[0046] Figure 4 It is a three-dimensional model diagram of a multi-channel transceiver processing integrated high-density internal bump SIP device agile chip package radio frequency interface simulation.

[0047] Figure 5 It is a multi-channel transceiver processing integrated high-density internal bump SIP device agile chip package radio frequency interface insertion loss and return loss simulation result diagram.

[0048] Figure 6 It is a multi-channel transceiver processing integrated high-density internal bump SIP device agile chip package radio frequency interface attention signal isolation degree simulation result diagram.

[0049] Figure 7 It is a three-dimensional model diagram of a multi-channel transceiver processing integrated high-density internal bump SIP device GTX109 MGTX RX simulation.

[0050] Figure 8The simulation results of differential mode insertion loss and return loss are shown for a multi-channel transceiver integrated high-density internal convex point SIP device GTX109 MGTX RX.

[0051] Figure 9 The simulation results of common mode return loss for a multi-channel transceiver integrated high-density internal convex SIP device, GTX109 MGTX RX.

[0052] Figure 10 The simulation results show the differential isolation of a multi-channel transceiver integrated high-density internal convex SIP device, GTX109 MGTX RX.

[0053] Figure label:

[0054] 1. Substrate; 2. RF transceiver module; 3. Processing module; 4. Storage module; 5. High-speed digital wiring area; 6. Irregularly shaped heat sink cover; 61. Heat sink cover body; 62. First groove; 63. Second groove. Detailed Implementation

[0055] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0056] Example 1

[0057] like Figures 1-2 As shown, a multi-channel transceiver integrated high-density internal bump SIP device includes a substrate 1, a radio frequency transceiver module 2, a processing module 3, and a storage module 4 disposed on the upper part of the substrate 1, a high-speed digital wiring area 5 electrically connected to the processing module 3, and an irregularly shaped heat dissipation cover plate 6 encapsulated on the upper part of the substrate 1 and outside the radio frequency transceiver module 2, the processing module 3, and the storage module 4. The processing module 3 is electrically connected to both the radio frequency transceiver module 2 and the storage module 4.

[0058] The substrate 1 is a multilayer substrate, and at least two bumps are provided on the substrate 1, including radio frequency bumps and high speed bumps. A solder ball array is provided on the bottom of the substrate 1.

[0059] The radio frequency transceiver module 2 is used to receive and transmit radio frequency signals and radio frequency status signals. The radio frequency transceiver module 2 includes at least two radio frequency transceiver channels. The radio frequency chip pins and radio frequency lead-out pins of the radio frequency transceiver module 2 are all located at the corners of the substrate 1.

[0060] Processing module 3 is used to receive radio frequency status signals and process radio frequency data, control the output of radio frequency status signals, and input and output high-speed digital signals. Processing module 3 is located on the side away from radio frequency transceiver module 2 to reduce crosstalk between radio frequency signals and high-speed digital signals.

[0061] The number of the radio frequency transceiver modules 2 is two, which are arranged at the lower left corner and the lower right corner of the substrate 1 respectively, the processing module 3, the storage module 4 and the high-speed digital wiring area 5 are arranged at the upper part of the substrate 1;

[0062] The pins of the high-speed digital wiring area 5 are arranged at the upper left corner of the substrate 1, and the pin lines of the high-speed digital wiring area 5 use the ground coplanar waveguide differential form and are densely arranged with ground hole fences on both sides of the lines;

[0063] The radio frequency pins of the radio frequency transceiver module 2 are arranged around the floating ground pins, and the floating ground pins are independent networks inside the sip device;

[0064] The radio frequency transceiver module 2 and the high-speed digital wiring area 5 both use independent reference ground planes;

[0065] The decoupling resistors and capacitors integrated in the sip device are distributed around the interconnection device;

[0066] The special-shaped heat dissipation cover plate 6 includes a heat dissipation cover plate body 61 and a first recess 62 and a second recess 63 arranged on the lower surface of the heat dissipation cover plate body 61, the first recess 62 is arranged at the top of the radio frequency transceiver module 2, and the second recess 63 is arranged at the top of the processing module 3 and the storage module 4;

[0067] The depth of the first recess 62 is less than the depth of the second recess 63, the distance between the first recess 62 and the upper part of the radio frequency transceiver module 2 is the same as the distance between the second recess 63 and the upper part of the processing module 3 and the storage module 4, the first recess 62 and the radio frequency transceiver module 2 form a shielding cavity, and the number of the first recess 62 is two;

[0068] The lower surface of the heat dissipation cover plate body 61 is fixedly connected with the upper surface of the substrate 1 by using adhesive, the top of the radio frequency transceiver module 2 is filled with heat dissipation glue at the surface of the first recess 62, and the top of the processing module 3 and the storage module 4 is filled with heat dissipation glue at the surface of the second recess 63;

[0069] The bottom of the radio frequency transceiver module 2, the processing module 3 and the storage module 4 is filled with glue between the substrate 1;

[0070] The number of the bumps is greater than 8000, the radio frequency transceiver module 2 includes at least 20 radio frequency transceiver channels, the inside of the sip device is provided with at least 10 active chips and at least 80 passive devices, and flip or SMT process is used;

[0071] The design method of the sip device is that the radio frequency transceiver module 2 is arranged at the lower part of the substrate 1 on both sides of the corner area to shorten the radio frequency line inside the substrate, reduce the insertion loss and return loss of the radio frequency line in the whole working frequency band, and improve the isolation of different radio frequency transceiver modules 2;

[0072] By making the radio frequency transceiver module 2 and the high-speed digital wiring area 5 adopt independent reference ground planes respectively, and limiting the high-speed digital wiring area 5 to the upper part of the substrate 1, the isolation degree between the radio frequency signal and the digital signal is improved;

[0073] By distributing the digital signal pin layout of the high-speed digital wiring area 5 to the upper left corner of the substrate 1, reducing the length of the internal lead-out wiring of the package substrate, and using the ground coplanar waveguide differential form, the ground hole fence is densely arranged on both sides of the wiring, and the isolation between the Serdes signals is enhanced.

[0074] By arranging the floating ground pins around the radio frequency pins and setting them as an independent network, the internal wiring complexity is simplified, and when in use, the floating ground pins are connected with the PCB ground plane, which plays a protective role in isolating the key radio frequency signals.

[0075] By setting the first recess 62 and the second recess 63 on the special-shaped heat dissipation cover plate 6 to accommodate the thinned radio frequency chip, the consistency of the distance between the internal devices of the sip device and the special-shaped heat dissipation cover plate 6 is maintained, the stability and heat dissipation effect of the chip are improved, and the special-shaped heat dissipation cover plate 6 is sunken in the radio frequency chip area to form a shielding cavity, which improves the isolation degree of the radio frequency signal and the digital signal.

[0076] By gluing the gap between the special-shaped heat dissipation cover plate 6 and the substrate 1, and filling the gap between the special-shaped heat dissipation cover plate 6 and the radio frequency transceiver module 2, the processing module 3 and the storage module 4 with heat dissipation glue, the radio frequency transceiver module 2, the processing module 3 and the storage module 4 are glued and fixed with the gap between the substrate 1, which improves the stability and heat dissipation effect of the sip device.

[0077] Embodiment 2

[0078] The present application provides a kind of multi-channel transceiver processing integrated high-density inner bump SiP device, substrate total 12 layers are stacked, nearly 10 active chips such as radio frequency, high speed, processing and nearly 80 passive devices, nearly 20 radio frequency transceiver channels, more than 8000 internal bumps are integrated, and structure miniaturization is realized.The whole structure of SiP in the present application can be divided into three parts: stepped special-shaped heat dissipation cover, high-speed digital and radio frequency limited space layout internal device, high-density bump integrated substrate. Figure 1 As shown in the figure, the whole adopts laminated structure, the overall size is 37.5mm╳37.5mm╳4.25mm, the pin form is 37╳37 diameter 0.6mm solder ball, the pin pitch is 1mm.The top heat dissipation cover and the bottom substrate are connected and fixed by gluing way.The middle cavity is the integrated device occupation space, the device bottom and the substrate are filled with glue, and the device top and the heat dissipation cover are filled with heat dissipation glue, which improves the stability of structure and improves the heat dissipation effect.

[0079] The structure of heat dissipation cover is as shown in the figure Figure 2As shown. The heatsink cover measures 37.30mm x 37.30mm x 1.835mm, with three corners rounded to a radius of 0.5mm, and one corner beveled for pin 1 marking. The internal cavity of the cover measures 31.30mm x 31.30mm, with a 1mm rounded corner design, to accommodate internal integrated components. The internal structure of the cavity is stepped, with the main cavity depth of 0.835mm accommodating most of the internal components. Two protrusions, each 7.833mm x 7.626mm in area and 0.385mm in height, are also present to accommodate thinned RF chips, maintaining consistent spacing between internal components and the heatsink cover, thus improving chip stability and heat dissipation. The heatsink cover recesses into the RF chip area to form a shielded cavity, enhancing the isolation between RF and digital signals.

[0080] The internal devices of this invention include multiple functions such as radio frequency, processing, and storage, and contain sensitive signals such as radio frequency signals and digital signals up to 12.5Gbps. In order to ensure the signal quality inside the SiP within the limited space of the substrate, the device layout and signal routing area inside the SiP need to be carefully designed.

[0081] like Figure 3 As shown, after reserving the cover plate width and a 1.7mm excess adhesive area, the RF devices and lead-out pins are placed in the lower corner area of ​​the overall layout, effectively shortening the RF traces inside the substrate. This achieves technical specifications of insertion loss better than 0.5dB and return loss better than 15dB across the entire operating frequency band of the RF traces. Simulation results are shown in [Figure number missing]. Figure 4 The processing chip carrying high-speed digital signals is placed at the top of the overall layout to maximize the distance between the radio frequency and high-speed digital signals and ensure isolation. Internally integrated decoupling resistors and capacitors are distributed around its interconnects to achieve optimal decoupling.

[0082] like Figure 3 As shown, the internal signal traces use independent reference ground planes for RF signals and digital signals. The high-speed digital trace area is confined to the upper part of the substrate, while the RF trace area is confined to the two lower corners of the substrate. This improves the isolation between RF and digital signals, as well as the isolation between different RF regions, achieving an isolation of better than 54dB between key RF signals and other signals. Simulation results are shown below. Figure 5 .

[0083] like Figure 3As shown, the high-speed SerDes digital signal pin layout is located in the upper left corner to reduce the length of the traces leading out from the package substrate. This portion of the traces uses a grounded coplanar waveguide (GCPW) differential configuration, and ground vias are densely distributed on both sides of the traces to enhance isolation between SerDes signals. Taking one set of received signals as an example, simulation results show that the SerDes traces achieve an insertion loss better than -2dB, a return loss better than -12dB, and isolation better than -33dB within the operating frequency band. Simulation results are shown below. Figure 5 and Figure 6 .

[0084] Regarding SiP pin layout, such as Figure 3 As shown, floating ground pins are arranged around the RF pins. These pins form an independent network within the SiP and are not connected to any device, simplifying internal wiring complexity compared to ordinary ground pins. In use, the floating ground pins are connected to the PCB ground plane, providing isolation and protection for critical RF signals.

[0085] Depend on Figure 6 It can be seen that the differential impedance of the RX channel is 100 ohms, and the differential impedance of the TX channel is 50 ohms. The common-mode return loss of the RX channel is relatively better than that of the TX channel.

[0086] Figures 7-10 The simulation results are for GTX109 MGTXRX.

[0087] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A multi-channel transceiving processing integrated high-density inner bump sip device, characterized by: The application relates to a SIP device, which comprises a substrate (1), a radio frequency transceiving module (2), a processing module (3), a storage module (4), a high-speed digital wiring area (5) electrically connected with the processing module (3), and a special-shaped heat dissipation cover plate (6) encapsulated on the upper part of the substrate (1) and outside the radio frequency transceiving module (2), the processing module (3) and the storage module (4); the processing module (3) is electrically connected with the radio frequency transceiving module (2) and the storage module (4). The substrate (1) is a multilayer substrate, at least two convex points are arranged on the substrate (1), the convex points comprise radio frequency convex points and high-speed convex points, and a solder ball array is arranged on the bottom of the substrate (1). The radio frequency transceiving module (2) is used for receiving and transmitting radio frequency signals and radio frequency state signals, the radio frequency transceiving module (2) comprises at least two radio frequency transceiving channels, radio frequency chip pins and radio frequency lead-out pins of the radio frequency transceiving module (2) are arranged at the corners of the substrate (1). The processing module (3) is used for receiving the radio frequency state signals, processing radio frequency data, and controlling the output of the radio frequency state signals, the processing module (3) is used for inputting and outputting high-speed digital signals, and the processing module (3) is arranged on the side far away from the radio frequency transceiving module (2) so as to reduce the crosstalk between the radio frequency signals and the high-speed digital signals. The special-shaped heat dissipation cover plate (6) comprises a heat dissipation cover plate body (61), a first groove (62) and a second groove (63) arranged on the lower surface of the heat dissipation cover plate body (61), the first groove (62) is arranged on the top of the radio frequency transceiving module (2), and the second groove (63) is arranged on the top of the processing module (3) and the storage module (4). The depth of the first groove (62) is smaller than that of the second groove (63), the distance between the first groove (62) and the upper part of the radio frequency transceiving module (2) is the same as the distance between the second groove (63) and the upper part of the processing module (3) and the storage module (4) so as to accommodate the thinned radio frequency chip, the consistency of the distance between the internal devices of the SIP device and the special-shaped heat dissipation cover plate (6) is maintained, the chip stability and the heat dissipation effect are improved, the special-shaped heat dissipation cover plate (6) is sunken in the radio frequency chip area to form a shielding cavity, and the isolation degree of the radio frequency signals and the digital signals is improved. The internal signal wiring radio frequency signals and digital signals adopt independent reference ground planes, the high-speed digital wiring area is limited on the upper part of the substrate (1), and the radio frequency wiring area is limited on the lower part of the substrate (1), so that the isolation degree between the radio frequency signals and the digital signals is improved, and the isolation degree between different radio frequency areas is also improved, and the key radio frequency signals are superior to other signals in the isolation degree index of 54 dB.

2. The multi-channel transceiving processing integrated high-density inner bump sip device according to claim 1, characterized in that: The number of the radio frequency transceiving modules (2) is two, the radio frequency transceiving modules (2) are arranged at the lower left corner and the lower right corner of the substrate (1) respectively, the processing module (3), the storage module (4) and the high-speed digital wiring area (5) are arranged on the upper part of the substrate (1).

3. The multi-channel transceiving processing integrated high-density inner bump sip device according to claim 2, characterized in that: The pin of the high-speed digital wiring area (5) is arranged at the upper left corner of the substrate (1), and the pin of the high-speed digital wiring area (5) is in the form of ground coplanar waveguide difference and is densely arranged with ground hole fences on both sides of the pin.

4. The multi-channel transceiving processing integrated high-density inner bump sip device according to claim 2, characterized in that: The radio frequency transceiver module (2) is surrounded by floating ground pins, which are independent networks in the sip device; The radio frequency transceiver module (2) and the high-speed digital wiring area (5) both adopt independent reference ground planes; The decoupling resistance and the capacitor integrated in the sip device are distributed around the interconnection device.

5. The multi-channel transceiving processing integrated high-density inner bump sip device according to claim 1, wherein The number of the first grooves (62) is two.

6. The multi-channel transceiving processing integrated high-density inner bump sip device according to claim 1, wherein: The lower surface of the heat dissipation cover plate body (61) is fixedly connected to the upper surface of the substrate (1) by using glue, the top of the radio frequency transceiver module (2) is filled with heat dissipation glue on the surface of the first groove (62), and the top of the processing module (3) and the storage module (4) is filled with heat dissipation glue on the surface of the second groove (63).

7. The multi-channel transceiving processing integrated high-density inner bump sip device according to claim 1, wherein: The bottom of the radio frequency transceiver module (2), the processing module (3) and the storage module (4) is filled with glue between the substrate (1).

8. The multi-channel transceiving processing integrated high-density inner bump sip device according to claim 1, wherein: The number of the convex points is greater than 8000, the radio frequency transceiver module (2) includes at least 20 radio frequency transceiver channels, the sip device is internally provided with at least 10 active chips and at least 80 passive devices, and a flip or SMT process is used.

9. The multi-channel transceiving processing integrated high-density inner bump sip device according to claim 1, characterized in that: The design method of the sip device is as follows: the radio frequency transceiver module (2) is arranged at the lower two side corner areas of the substrate (1) to shorten the radio frequency wiring inside the substrate, reduce the insertion loss and return loss of the radio frequency wiring in the whole working frequency band, and improve the isolation of different radio frequency transceiver modules (2); By making the radio frequency transceiver module (2) and the high-speed digital wiring area (5) adopt independent reference ground planes respectively, and limiting the high-speed digital wiring area (5) to the upper part of the substrate (1), the isolation between the radio frequency signal and the digital signal is improved. By arranging the digital signal pin layout of the high-speed digital wiring area (5) at the upper left corner of the substrate (1), the length of the lead-out wiring inside the packaging substrate is reduced, the ground coplanar waveguide difference form is used, and the ground hole fences are densely arranged on both sides of the wiring to enhance the isolation between Serdes signals. By arranging the floating ground pins around the radio frequency pins and setting them as independent networks, the internal wiring complexity is simplified, and when in use, the floating ground pins are connected to the PCB ground plane to isolate and protect the key radio frequency signals. By gluing the gap between the special-shaped heat dissipation cover plate (6) and the substrate (1), filling heat dissipation glue between the special-shaped heat dissipation cover plate (6) and the radio frequency transceiver module (2), the processing module (3) and the storage module (4), and gluing the gap between the radio frequency transceiver module (2), the processing module (3) and the storage module (4) and the substrate (1), the stability and heat dissipation effect of the sip device are improved.

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