Bidirectional scr device and method of manufacturing bidirectional scr device

Abstract

The application provides a bidirectional SCR device and a manufacturing method thereof, and is applied to the technical field of semiconductor protection devices, and comprises the following: an N+ substrate, a first P-type buried layer is arranged in the N+ substrate; an N-type epitaxial layer, a second P-type buried layer and a third P-type buried layer are arranged in the N-type epitaxial layer, and an N-type buried layer is arranged on the upper surface of the N-type epitaxial layer; a P-type epitaxial layer, four deep N regions and two P wells are arranged in the P-type epitaxial layer, one N-type heavily doped region is arranged in each deep N region, and one P-type heavily doped region is arranged in each P well; two P-type heavily doped regions and two N-type heavily doped regions are connected with a first input / output end and a second input / output end. The structure of the SCR device has very symmetrical protection characteristics, and the same PNPN structure is passed through from the first input / output end to the second input / output end or vice versa, the base region width of two directions is equal, the capacity is balanced, the conduction resistance is the same, and the flexibility in circuit application is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor protection device technology, specifically to a bidirectional SCR device and a method for manufacturing a bidirectional SCR device. Background Technology

[0002] A silicon controlled rectifier (SCR) is a device commonly used for electrostatic discharge (ESD) protection, possessing excellent static discharge capabilities. Compared to diodes, transistors, and field-effect transistors, it offers advantages such as strong current discharge capability, high discharge efficiency per unit area, low on-resistance, strong robustness, and high protection level due to its inherent positive feedback mechanism. It can achieve high ESD protection levels with a relatively small chip area on semiconductor planar processes.

[0003] SCR devices can be classified into lateral and vertical structures based on the current path direction. For chips of the same area, the vertical structure often has a larger PN junction area, thus exhibiting stronger current-carrying capacity. When a bidirectional SCR device is used in a circuit, one end is connected to the input / output (I / O) terminal, and the other end is grounded, i.e., connected in parallel to the front end of the integrated circuit (IC) being protected. When an ESD event occurs at the I / O terminal, it can trigger the SCR protection device to enter a low-impedance state, allowing the pulse current to pass through and be released to ground, thereby effectively protecting the downstream IC.

[0004] Existing vertically structured SCR devices suffer from structural asymmetry from top to bottom and bottom to top, and a significant difference in base region width between the two directions. This results in unbalanced capabilities and large differences in on-resistance between the two directions, severely impacting their flexibility in circuit applications.

[0005] Therefore, a new technical solution for the structure of SCR devices is needed. Summary of the Invention

[0006] In view of this, the embodiments of this specification provide a bidirectional SCR device and a method for manufacturing a bidirectional SCR device, which solves the technical problem that in the prior art, the vertical structure of the SCR device is asymmetrical from top to bottom and from bottom to top, and the base region widths from top to bottom and from bottom to top are significantly different, resulting in unbalanced capabilities and large differences in on-resistance in the two directions, which seriously affects the flexibility of circuit applications.

[0007] The embodiments in this specification provide the following technical solutions:

[0008] This specification provides an embodiment of a bidirectional SCR device, comprising:

[0009] An N+ substrate is provided with a first P-type buried layer within the N+ substrate;

[0010] An N-type epitaxial layer is provided, within which a second P-type buried layer and a third P-type buried layer are provided. An N-type buried layer is provided on the upper surface of the N-type epitaxial layer. The second P-type buried layer is located above the first P-type buried layer and does not contact the first P-type buried layer.

[0011] The P-type epitaxial layer has four deep N regions and two P wells. Each deep N region has one heavily doped N-type region, and each P well has one heavily doped P-type region. An N-type heavily doped region is set between the two heavily doped P-type regions. The two P wells are respectively set to correspond to the second P-type buried layer and the third P-type buried layer. The N+ substrate, N-type epitaxial layer, N-type buried layer and P-type epitaxial layer are connected from bottom to top in the vertical direction.

[0012] Three first isolation trenches are arranged in a direction perpendicular to the N+ substrate. One first isolation trench is arranged at each end of the first P-type buried layer, and one first isolation trench is arranged at the end of the third P-type buried layer away from the first P-type buried layer.

[0013] Two second isolation trenches are arranged in a direction perpendicular to the N+ substrate. A second isolation trench is provided at each end of the second P-type buried layer. Two first isolation trenches are arranged between the first isolation trenches at both ends of the first P-type buried layer.

[0014] Two P-type heavily doped regions are connected to the first input / output terminal and the second input / output terminal, respectively, and two N-type heavily doped regions are connected to the first input / output terminal and the second input / output terminal, respectively.

[0015] Preferably, the depth of the first isolation trench is greater than the sum of the thicknesses of the N-type epitaxial layer and the P-type epitaxial layer, and the bottom surface of the first isolation trench is at the same height as the bottom surface of the first P-type buried layer.

[0016] Preferably, the distance between the bottom of the second isolation trench and the top surface of the first P-type buried layer is less than the distance between the bottom surface of the second P-type buried layer and the top surface of the first P-type buried layer, and the second isolation trench is located inside the N-type epitaxial layer and does not contact the first P-type buried layer.

[0017] Preferably, a dielectric layer is provided on the P-type epitaxial layer, and a contact hole is provided on the dielectric layer. Metal is deposited in the contact hole to form a first input / output terminal and a second input / output terminal.

[0018] A passivation layer is provided at both ends of the first input / output terminal and the second input / output terminal on the metal.

[0019] Preferably, the second P-type buried layer and the third P-type buried layer are the same, and the second input / output terminal is reached by passing through the P-type heavily doped region, p-well, P-type epitaxial layer, N-type buried layer, third P-type buried layer and N-type epitaxial layer in sequence from the first input / output terminal.

[0020] From the second input / output terminal, the sequence passes through a P-type heavily doped region, a p-well, a P-type epitaxial layer, an N-type buried layer, a second P-type buried layer, and an N-type epitaxial layer to reach the first input / output terminal.

[0021] Preferably, the first P-type buried layer diffuses upward into the interior of the N-type epitaxial layer.

[0022] This specification also provides a method for manufacturing a bidirectional SCR device, comprising:

[0023] Step 1: Form a first P-type buried layer in the N+ substrate, and grow an N-type epitaxial layer on the N+ substrate;

[0024] Step 2: Form a second P-type buried layer and a third P-type buried layer within the N-type epitaxial layer, and form an N-type buried layer on the upper surface of the N-type epitaxial layer. The N-type buried layer is located above the second P-type buried layer and the third P-type buried layer. The second P-type buried layer is located above the first P-type buried layer and does not contact the first P-type buried layer.

[0025] Step 3: Generate a P-type epitaxial layer on the N-type buried layer to obtain the first structure;

[0026] Step 4: Three first isolation trenches and two second isolation trenches are formed on the first structure. One first isolation trench is formed at each end of the first P-type burial layer. One first isolation trench is formed at the end of the third P-type burial layer away from the first P-type burial layer. One second isolation trench is formed at each end of the second P-type burial layer. The two first isolation trenches are formed between the first isolation trenches at both ends of the first P-type burial layer.

[0027] Step 5: A deep N-region is formed within the P-type epitaxial layer, between the first and second isolation trenches, and on the outer sides of the first isolation trenches on both sides;

[0028] Step 6: Within the P-type epitaxial layer, the region between the two second isolation trenches on both sides of the second P-type buried layer and the region between the two first isolation trenches on both sides of the third P-type buried layer each form a P-trap;

[0029] Step 7: Form an N-type heavily doped region in each deep N-region and a P-type heavily doped region in each P-well to obtain the second structure;

[0030] Step 8: Form the first input / output terminal and the second input / output terminal on the second structure.

[0031] Preferably, the depth of the first isolation trench is greater than the sum of the thicknesses of the N-type epitaxial layer and the P-type epitaxial layer, and the bottom surface of the first isolation trench is at the same height as the bottom surface of the first P-type buried layer.

[0032] Preferably, the distance between the bottom of the second isolation trench and the top surface of the first P-type buried layer is less than the distance between the bottom surface of the second P-type buried layer and the top surface of the first P-type buried layer, and the second isolation trench is located inside the N-type epitaxial layer and does not contact the first P-type buried layer.

[0033] Preferably, step 8 includes:

[0034] Step 801: Deposit a dielectric layer on the second structure;

[0035] Step 802: Form multiple contact holes at the locations corresponding to the two heavily doped P-type regions and the two deep N-regions on the dielectric layer;

[0036] Step 803: Deposit metal on the surface of the dielectric layer so that the metal deposited in the contact hole contacts the corresponding P-type heavily doped region and N-type heavily doped region to form a metal end;

[0037] Step 804: Deposit a passivation layer on the surface of the dielectric layer and the metal end, and perform photolithography and etching on the passivation layer to form a first input / output terminal and a second input / output terminal on the metal end.

[0038] Preferably, the second P-type buried layer and the third P-type buried layer are the same, and the second input / output terminal is reached by passing through the P-type heavily doped region, p-well, P-type epitaxial layer, N-type buried layer, third P-type buried layer and N-type epitaxial layer in sequence from the first input / output terminal.

[0039] From the second input / output terminal, the sequence passes through a P-type heavily doped region, a p-well, a P-type epitaxial layer, an N-type buried layer, a second P-type buried layer, and an N-type epitaxial layer to reach the first input / output terminal.

[0040] Preferably, the first P-type buried layer diffuses upward into the interior of the N-type epitaxial layer.

[0041] Compared with the prior art, the beneficial effects that can be achieved by the above-mentioned at least one technical solution adopted in the embodiments of this specification include at least the following: the present invention has symmetrical protection characteristics, the PNPN structure traversed from the first input / output terminal to the second input / output terminal is the same, and the trigger protection voltage in both directions is consistent; and in both directions, the N+ substrate is used as the base region, the width is the same, and the turn-on voltage of the trigger protection device is consistent, resulting in balanced capability in both directions, the same on-resistance, and improved flexibility in circuit applications. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram illustrating the application of a bidirectional SCR device in a circuit according to an embodiment of this application;

[0044] Figure 2 This is a schematic diagram of a vertically structured SCR device provided in an embodiment of this application;

[0045] Figure 3 This is a schematic diagram of another vertically structured SCR device provided in an embodiment of this application;

[0046] Figure 4 This is a schematic diagram of an N+ substrate structure provided in an embodiment of this application;

[0047] Figure 5 This is a schematic diagram of the structure of an N-type epitaxial layer provided in an embodiment of this application;

[0048] Figure 6 This is a schematic diagram of another N-type epitaxial layer provided in an embodiment of this application;

[0049] Figure 7 This is a schematic diagram of a P-type epitaxial layer provided in an embodiment of this application;

[0050] Figure 8 This is a schematic diagram of the structure of an isolation groove provided in an embodiment of this application;

[0051] Figure 9 This is a schematic diagram of a deep N-region structure provided in an embodiment of this application;

[0052] Figure 10 This is a schematic diagram of a P-trap structure provided in an embodiment of this application;

[0053] Figure 11 This is a schematic diagram of the structure of an N-type heavily doped region and a P-type heavily doped region provided in an embodiment of this application;

[0054] Figure 12 This is a schematic diagram of the structure of a dielectric layer provided in an embodiment of this application;

[0055] Figure 13 This is a schematic diagram of a metal end structure provided in an embodiment of this application;

[0056] Figure 14This is an equivalent circuit diagram of an SCR device provided in an embodiment of this application;

[0057] Figure 15 This is a schematic diagram of a current path provided in an embodiment of this application;

[0058] Figure 16 This is another schematic diagram of the current path provided in the embodiments of this application. Detailed Implementation

[0059] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0060] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0061] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0062] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0063] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0064] SCR devices can be classified into lateral and vertical structures based on the current path direction. For chips of the same area, the vertical structure often has a larger PN junction area, and therefore a stronger current-carrying capacity. For example... Figure 1 As shown, when a bidirectional SCR device is used in a circuit, one end is connected to the I / O terminal, and the other end is grounded (Ground, Gnd), i.e., connected in parallel in front of the protected IC. When the I / O terminal encounters an ESD event, it can trigger the SCR protection device to enter a low-impedance state, allowing the pulse current to pass through and be released to ground, thereby effectively protecting the downstream IC.

[0065] like Figure 2 As shown, a traditional vertically structured SCR device includes: a P-type heavily doped region (P+), an N-type heavily doped region (N+), an N-well (N-Well, NW), a P-well (P-Well, PW), an N-substrate, a metal, a first input / output terminal (IO1), and a second input / output terminal (IO2). The top-down PNPN structure refers to the PNPN structure consisting of P+ / NW / PW / N-substrate / N+ that passes through from IO1 to IO2; the bottom-up PNPN structure refers to the PNPN structure consisting of P+ / N-substrate / PW / NW / N+ that passes through from IO2 to IO1. The resulting PNPN structure is not symmetrical because the paths "P+ / NW / PW / N" and "P+ / N substrate / PW / NW / N+" are different. This asymmetry can cause inconsistent trigger protection voltages in the two directions. Furthermore, since one direction uses NW as the base region and the other uses N substrate as the base region, their widths are different, resulting in inconsistent turn-on voltages for the trigger protection devices. This leads to an imbalance in the capabilities of the two directions, a large difference in on-resistance, and severely affects the flexibility of circuit applications.

[0066] Based on this, the embodiments of this specification propose a processing solution: improving the vertical structure of the SCR device to give it stronger flow capability and extremely symmetrical protection capability in both directions. It can be applied to various high-speed data I / O ports, as well as ESD protection between power rails and different power domains, with higher protection efficiency.

[0067] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0068] like Figure 3As shown in the embodiment of this specification, a bidirectional SCR device is provided, including: an N+ substrate, in which a first P-type buried layer (PBL1) is disposed; an N-type epitaxial layer (Nepi), in which a second P-type buried layer and a third P-type buried layer are disposed, and an N-type buried layer (NBL) is disposed on the upper surface of the N-type epitaxial layer. The second P-type buried layer is located above the first P-type buried layer and is not in contact with the first P-type buried layer; wherein, the second P-type buried layer and the third P-type buried layer are identical, therefore... Figure 3 The second and third P-type buried layers are both denoted by PBL2; the P-type epitaxial layer (Pepi) contains four deep N-regions and two P-wells. Each deep N-region contains one heavily doped N-type region (N+), and each P-well contains one heavily doped P-type region (P+). An N-type heavily doped region is positioned between two heavily doped P-type regions. The two P-wells correspond to the second and third P-type buried layers, respectively. The N+ substrate, N-type epitaxial layer, N-type buried layer, and P-type epitaxial layer are connected vertically from bottom to top; three first isolation trenches (isolation trench 1) are also present. The first P-type buried layer is arranged perpendicular to the N+ substrate, with a first isolation trench at each end and a third P-type buried layer at the end furthest from the first P-type buried layer. Two second isolation trenches (isolation trench 2) are arranged perpendicular to the N+ substrate, with a second isolation trench at each end of the second P-type buried layer and the two first isolation trenches located between the first isolation trenches at both ends of the first P-type buried layer. Two heavily doped P-type regions are connected to the first input / output terminal and the second input / output terminal, respectively, and two heavily doped N-type regions are connected to the first input / output terminal and the second input / output terminal, respectively.

[0069] The first P-type buried layer has a certain depth within the N+ substrate, which can achieve a relatively high reverse breakdown voltage of the N+ substrate / PBL1. Furthermore, the first P-type buried layer diffuses upward into the interior of the N-type epitaxial layer, increasing the thickness of the first P-type buried layer and further improving the reverse breakdown voltage of the N+ substrate / PBL1. The reverse voltage of the N-type epitaxial layer / PBL1 is also improved.

[0070] It is known that the second P-type buried layer (PBL2) and the third P-type buried layer (PBL2) in the N-type epitaxial layer use the same process. The second P-type buried layer is located above the first P-type buried layer in the N-type epitaxial layer and does not contact the first P-type buried layer. The third P-type buried layer is located in the N-type epitaxial layer away from the first P-type epitaxial layer and has the same thickness as the second P-type buried layer, and is at the same height.

[0071] In this structure, a P-type epitaxial layer is provided on the N-type buried layer. A first isolation trench and a second isolation trench are vertically arranged on the structure composed of the P-type epitaxial layer, the N-type mask layer, the N-type epitaxial layer and the N+ substrate. The first isolation trench penetrates the P-type epitaxial layer, the N-type mask layer and the N-type epitaxial layer, and extends into the N+ substrate. The second isolation layer penetrates the P-type epitaxial layer and the N-type mask layer, and extends into the N-type epitaxial layer.

[0072] Furthermore, the depth of the first isolation trench is greater than the sum of the thicknesses of the N-type epitaxial layer and the P-type epitaxial layer, and the bottom surface of the first isolation trench is at the same height as the bottom surface of the first P-type buried layer; the distance between the bottom of the second isolation trench and the top surface of the first P-type buried layer is less than the distance between the bottom surface of the second P-type buried layer and the top surface of the first P-type buried layer, and the second isolation trench is located inside the N-type epitaxial layer and does not contact the first P-type buried layer.

[0073] It is known that an SCR device unit requires 3 first isolation slots and 2 second isolation slots. In practical applications, multiple SCR devices in the embodiments of this application can be combined and multiple first isolation slots and multiple second isolation slots can be set. This application does not impose any restrictions.

[0074] The following description uses an SCR device as a unit to illustrate the situation of the first isolation slot and the second isolation slot.

[0075] Specifically, three first isolation trenches (isolation trenches 1) are arranged perpendicular to the N+ substrate, with one first isolation trench at each end of the first P-type buried layer and one first isolation trench at the end of the third P-type buried layer away from the first P-type buried layer; two second isolation trenches (isolation trenches 2) are arranged perpendicular to the N+ substrate, with one second isolation trench at each end of the second P-type buried layer, and the two first isolation trenches are positioned between the two first isolation trenches at each end of the first P-type buried layer. The three first isolation trenches and the two second isolation trenches do not overlap, thus creating six spaces in the horizontal direction, such as... Figure 3 As shown, from left to right, they can be identified as the first space, the second space, the third space, the fourth space, the fifth space, and the sixth space.

[0076] Furthermore, the P-type epitaxial layer is also divided into six spaces by the first and second isolation trenches. In this application, a deep N-region is provided between the first and second isolation trenches in the P-type epitaxial layer, and in the region outside the first isolation trenches on both sides. A P-well is provided in the region between the two first isolation trenches and the two second isolation trenches. For example, as shown... Figure 3As shown, deep N-regions are formed in the first, third, fifth, and sixth spaces of the P-type epitaxial layer, and P-wells are formed in the second and fourth spaces, totaling four deep N-regions and two P-wells. Each deep N-region contains one heavily doped N-type region (N+), and each P-well contains one heavily doped P-type region (P+). It can be seen that one heavily doped N-type region is positioned between two heavily doped P-type regions. The two P-wells correspond to the second and third P-type buried layers, respectively. In this application, the N+ substrate, N-type epitaxial layer, N-type buried layer, and P-type epitaxial layer are connected vertically from bottom to top.

[0077] Furthermore, such as Figure 3 As shown, a dielectric layer is provided on the P-type epitaxial layer, and a contact hole is provided on the dielectric layer. Metal is deposited in the contact hole to form a first input / output terminal (IO1) and a second input / output terminal (IO2). A passivation layer is provided at both ends of the first input / output terminal and the second input / output terminal on the metal.

[0078] Specifically, a dielectric layer, mainly composed of silicon dioxide, is deposited on the surface of the P-type epitaxial layer using a chemical vapor deposition process. Then, contact holes are formed through photolithography and etching. Subsequently, metal is deposited on the dielectric layer and the contact hole surfaces, and photolithography and etching are performed to form the IO (input / output) terminal metal. A passivation layer is deposited on it to protect the metal. The IO terminal metal is exposed through photolithography and etching of the passivation layer, forming the first input / output terminal and the second input / output terminal.

[0079] As can be seen, in this application, the second P-type buried layer and the third P-type buried layer are the same, passing sequentially from the first input / output terminal (IO1) through the P-type heavily doped region, p-well, P-type epitaxial layer, N-type buried layer, third P-type buried layer and N-type epitaxial layer to reach the second input / output terminal (IO2); and from the second input / output terminal (IO2) passing sequentially through the P-type heavily doped region, p-well, P-type epitaxial layer, N-type buried layer, second P-type buried layer and N-type epitaxial layer to reach the first input / output terminal (IO1).

[0080] In this embodiment, the path from IO1 to IO2 and from IO2 to IO1 both pass through a PNPN structure composed of P+ / PW / Pepi / NBL / PBL2 / Nepi. PBL2 has a thinner thickness, resulting in a lower breakdown voltage for the NPN transistor composed of NBL / PBL2 / Nepi. During an electrostatic discharge (ESD) event, it breaks down and conducts first, followed by the PNP transistor formed by Pepi / NBL / PBL2, creating positive feedback. The SCR device enters a negative resistance state to release the transient current, protecting the downstream circuit chips. When an ESD event occurs at IO1, the transient current flows from the IO1 metal... The current enters P+, passes through PW / Pepi / NBL / PBL2 / Nepi, reaches the N+ substrate, and is then discharged from Nepi / NBL / deep N region / N+, exiting from the IO2 metal terminal. When the IO2 terminal encounters an ESD event, the transient large current enters P+ from the IO2 metal, passes through PW / Pepi / NBL / PBL2 / Nepi, and is then discharged from NBL / deep N region / N+, exiting from the IO1 metal terminal. It has strong current carrying capacity and extremely symmetrical protection capabilities in both directions. It can be applied to various high-speed data IO ports, as well as ESD protection between power rails and different power domains, with higher protection efficiency.

[0081] This specification also includes an embodiment of a method for manufacturing a bidirectional SCR device, used to manufacture the aforementioned bidirectional SCR device, comprising:

[0082] Step 1: Form a first P-type buried layer (PBL1) in the N+ substrate and grow an N-type epitaxial layer (Nepi) on the N+ substrate.

[0083] Among them, the first P-type buried layer diffuses upward into the interior of the N-type epitaxial layer.

[0084] Specifically, an N+ substrate silicon wafer is selected, and the PBL1 pattern is defined on its surface by photolithography. Then, ion implantation is performed, and the wafer is placed in a high-temperature furnace tube for thermal propulsion to form PBL1.

[0085] The N+ substrate should be made of a low-resistivity material. In this embodiment, the resistivity of the material used is (0.001~0.005)Ω*cm.

[0086] In the embodiments described in this specification, ion implantation is performed according to the PBL1 pattern, and the implanted element is boron or boron difluoride, with an implantation dose of (1×10⁻⁶). 14 ~3×10 15 ) / cm 2 The injection energy is (100-120) keV. For example, it can be injected in two steps. The first step is to inject boron element at a dose of (5 × 10⁻⁶ keV). 13 ~5×10 14 ) / cm2 The second injection of boron difluoride was performed at a dose of (1×10⁻⁶). 15 ~5×10 15 ) / cm 2 Alternatively, only boron or only boron dioxide can be injected.

[0087] The thermal process conditions for the high-temperature furnace tube are: temperature (1100~1200)℃ and time (80~120) minutes. This allows PBL1 to have a certain depth within the N+ substrate, resulting in a relatively high N+ substrate / PBL1 reverse breakdown voltage.

[0088] like Figure 4 The structure obtained through step 1 is shown. PBL1 is located on the upper surface of the N+ substrate and has a certain depth within the N+ substrate.

[0089] In the embodiments of this specification, the depth of PBL1 in the N+ substrate is not limited. For example, when the depth of the N+ substrate is (100~200)um, the depth of PBL1 in the N+ substrate can be (2-4)um.

[0090] In this application, the PBL1 pattern is determined based on the current magnitude.

[0091] Furthermore, such as Figure 5 As shown, an N-type epitaxial layer is grown on an N+ substrate.

[0092] Specifically, the N+ substrate silicon wafer is cleaned to remove surface impurities and oxide layers, and then an N-type epitaxial layer (Nepi) is grown. For example, the Nepi thickness is (6–10) μm, the resistivity is (0.1–1) Ω*cm, and the doping element is phosphorus or arsenic. The N-type epitaxial layer is grown using a high-temperature process at (1150–1180) °C, which allows PBL1 to diffuse upwards into Nepi, increasing the thickness of PBL1. This is beneficial for further improving the reverse breakdown voltage of the N+ substrate / PBL1, and also enhances the reverse voltage of Nepi / PBL1, which is beneficial for achieving isolation in subsequent processes.

[0093] In the embodiments of this specification, there is no limitation on the thickness of PBL1 diffusing upward into Nepi. For example, when the thickness of Nepi is (6-10) μm, the thickness of PBL1 diffusing upward into Nepi is (1-2) μm.

[0094] Step 2: Form a second P-type buried layer (PBL2) and a third P-type buried layer (PBL2) within the N-type epitaxial layer, and form an N-type buried layer (NBL) on the upper surface of the N-type epitaxial layer. The N-type buried layer is located above the second P-type buried layer and the third P-type buried layer. The second P-type buried layer is located above the first P-type buried layer and is not in contact with the first P-type buried layer.

[0095] The second and third P-type buried layers were obtained using the same pattern and process, differing only in location. Figure 6 Both the second and third P-type burial layers are marked using PBL2.

[0096] like Figure 6 As shown, on the Nepi surface, the pattern is defined by PBL2 photolithography, then PBL2 ion implantation is performed, followed by NBL full-surface implantation, and then it enters the furnace tube for high-temperature propulsion, so that both PBL2 and NBL have a certain depth.

[0097] In the embodiments of this specification, the depth of PBL2 and the depth of NBL are not limited. For example, the depth of PBL2 is (1-2)um and the depth of NBL is (3-5)um.

[0098] In one optional embodiment, PBL2 ions are implanted with boron at an implantation dose of 1 × 10⁻⁶. 13 ~1×10 14 ) / cm 2 Injection energy (80-150) keV; NBL full-surface injection of phosphorus or arsenic, injection dose (2×10⁻⁶). 13 ~5×10 14 ) / cm 2 The injection energy is (50-80) keV; the high-temperature propulsion conditions are (1100-1150)℃ and the propulsion time is (30-60) minutes. Since boron itself is injected deeper and its diffusion rate is faster than that of phosphorus and arsenic, the PBL2 junction is formed deeper than that of NBL after propulsion. On the other hand, since the injection dose of NBL is greater than that of PBL2, the part near the Nepi surface is entirely NBL.

[0099] Step 3: Generate a P-type epitaxial layer (Pepi) on the N-type buried layer to obtain the first structure.

[0100] like Figure 7 As shown, the silicon wafer is cleaned to remove surface impurities, particles, and oxide layers, and then a P-type epitaxial layer (Pepi) is grown.

[0101] The production thickness of Pepi is not limited in the embodiments of this specification. For example, the growth thickness of Pepi is (3~6) μm and the resistivity is (1~10) Ω*cm.

[0102] Step 4: Three first isolation trenches and two second isolation trenches are formed on the first structure. One first isolation trench is formed at each end of the first P-type burial layer. One first isolation trench is formed at the end of the third P-type burial layer away from the first P-type burial layer. One second isolation trench is formed at each end of the second P-type burial layer. The two first isolation trenches are formed between the first isolation trenches at both ends of the first P-type burial layer.

[0103] The depth of the first isolation trench is greater than the sum of the thicknesses of the N-type epitaxial layer and the P-type epitaxial layer, and the bottom surface of the first isolation trench is at the same height as the bottom surface of the first P-type buried layer; the distance between the bottom of the second isolation trench and the top surface of the first P-type buried layer is less than the distance between the bottom surface of the second P-type buried layer and the top surface of the first P-type buried layer, and the second isolation trench is located inside the N-type epitaxial layer and does not contact the first P-type buried layer.

[0104] like Figure 8 As shown, an oxide layer is grown or deposited on the surface of the Pepi. Then, multiple deep trenches are formed by photolithography, etching of the oxide layer, and etching of silicon through isolation trench 1. The deep trenches are then filled with an insulating medium, such as silicon dioxide, to form multiple first isolation trenches (isolation trench 1). Then, multiple deep trenches are formed by photolithography, etching of the oxide layer, and etching of silicon through isolation trench 2. The deep trenches are then filled with an insulating medium, such as silicon dioxide, to form multiple second isolation trenches (isolation trench 2). Finally, the excess insulating medium on the surface is removed.

[0105] Specifically, an SCR device unit requires three isolation slots 1, the positions of which are determined by PBL2, and two isolation slots 2, the positions of which are determined by the boundaries of PBL2.

[0106] In one alternative implementation, the depth of isolation groove 1 is greater than the sum of the thicknesses of Nepi and Pepi, and its depth is level with the bottom of PBL1; the depth of isolation groove 2 is deeper than the bottom of PBL2, within the Nepi body, but with a certain distance from the top of PBL1.

[0107] Step 5: A deep N-region is formed within the P-type epitaxial layer, between the first and second isolation trenches, and on the outer sides of the first isolation trenches on both sides.

[0108] like Figure 9 As shown, multiple deep N regions are formed through deep N-region photolithography, ion implantation, and then thermal diffusion in the furnace tube.

[0109] In one optional implementation, the deep N-region implanted element is phosphorus, and the implantation dose is (5 × 10⁻⁶). 15 ~1×1016 ) / cm 2 The energy injected is (80~120) KeV; the thermal diffusion temperature of the furnace tube is (1050~1150)℃, and the time is (120~320) minutes.

[0110] One SCR device unit requires four deep N regions, located between isolation trench 1 and isolation trench 2, and also on the side of isolation trench 1.

[0111] Step 6: Within the P-type epitaxial layer, the region between the two second isolation trenches on both sides of the second P-type buried layer and the region between the two first isolation trenches on both sides of the third P-type buried layer each form a P-well (P-Well, PW).

[0112] like Figure 10 As shown, at least two PW regions are formed by PW lithography, ion implantation, and thermal diffusion in the furnace tube.

[0113] One SCR device unit requires two PWs, which need to be located between isolation slot 1 and between isolation slot 2, which is equivalent to PBL2.

[0114] In one optional implementation, the PW region is implanted with boron, and the implantation dose is (5 × 10⁻⁶). 14 ~1×10 15 ) / cm 2 The energy injected is (60-100) KeV; the thermal diffusion temperature of the furnace tube is (1000-1050)℃, and the time is 30-60 minutes.

[0115] Step 7: Form an N-type heavily doped region (N+) in each deep N-region and a P-type heavily doped region (P+) in each P-well to obtain the second structure.

[0116] like Figure 11 As shown, an N+ region is formed within a deep N region through N+ region photolithography and ion implantation. Then, a P+ region is formed within a PW region through P+ region photolithography and ion implantation, followed by a rapid thermal annealing process.

[0117] In one alternative embodiment, phosphorus or arsenic is implanted into the N+ region as ions, with an implantation dose (1 × 10⁻⁶). 15 ~1×10 16 ) / cm 2 The implantation energy is (60–100) keV; boron or boron difluoride is implanted into the P+ region, with an implantation dose of (1 × 10⁻⁶ keV). 15 ~1×10 16 ) / cm 2The injection energy is (40~80) keV; the rapid thermal annealing process temperature is (950~1050)℃, and the time is (20~40) seconds. Rapid thermal annealing can activate the injected impurities.

[0118] Step 8: Form the first input / output terminal (IO1) and the second input / output terminal (IO2) on the second structure.

[0119] Step 8 includes: Step 801: Depositing a dielectric layer on the second structure; Step 802: Forming multiple contact holes at the corresponding positions of two heavily doped P-type regions and two deep N-type regions on the dielectric layer; Step 803: Depositing metal on the surface of the dielectric layer, so that the metal deposited in the contact holes contacts the corresponding heavily doped P-type and heavily doped N-type regions to form metal terminals; Step 804: Depositing a passivation layer on the surface of the dielectric layer and the metal terminals, and performing photolithography and etching on the passivation layer to form a first input / output terminal and a second input / output terminal at the metal terminals.

[0120] like Figure 12 As shown, a dielectric layer, mainly composed of silicon dioxide, is deposited on the upper surface of a silicon wafer using a chemical vapor deposition process. Contact holes are then formed through photolithography and etching.

[0121] The contact holes are required to be located in the P+ and N+ regions, and there is no limit to the number of contact holes.

[0122] Furthermore, such as Figure 13 As shown, metal is deposited on the surface of the second structure, and photolithography and etching are performed to form a metal terminal. A passivation layer is deposited on it to protect the metal. The metal is exposed by photolithography and etching through the passivation layer to form the first input / output terminal (IO1) and the second input / output terminal (IO2).

[0123] In one optional embodiment, the metal thickness is (2-4) μm, which can withstand larger pulse currents and improve current protection capability. The passivation layer is a composite film containing silicon dioxide and silicon nitride.

[0124] Furthermore, the second P-type buried layer and the third P-type buried layer are the same, passing sequentially from the first input / output terminal through a heavily doped P-type region, a p-well, a P-type epitaxial layer, an N-type buried layer, a third P-type buried layer, and an N-type epitaxial layer to reach the second input / output terminal; and from the second input / output terminal passing sequentially through a heavily doped P-type region, a p-well, a P-type epitaxial layer, an N-type buried layer, a second P-type buried layer, and an N-type epitaxial layer to reach the first input / output terminal.

[0125] like Figure 14As shown in the embodiments of this specification, from IO1 to IO2 and from IO2 to IO1, both must pass through the PNPN structure composed of P+ / PW / Pepi / NBL / PBL2 / Nepi. Among them, PBL2 has a thinner thickness, so the NPN transistor composed of NBL / PBL2 / Nepi has a lower breakdown voltage. When an electrostatic event occurs, it breaks down and conducts first. Then, the PNP transistor formed by Pepi / NBL / PBL2 is also triggered to conduct, forming positive feedback. The SCR enters the negative resistance state to release the transient large current and protect the downstream circuit chip.

[0126] In the embodiments of this specification, PBL1 is disposed in the middle region formed by the first isolation trench 1 and the second isolation trench 1 from right to left. The two isolation trenches 1 restrict the current direction and prevent the current from flowing to the N+ substrate. PBL2 is disposed in the middle region formed by the two isolation trenches 2 and the two isolation trenches 1 respectively, forming the base region of NPN, which can serve as the emitter of PNP and the base region of NPN. In the embodiments of this specification, the left and right trench widths of PBL2 are symmetrical.

[0127] like Figure 15 As shown, the arrows indicate the direction of the current. When an ESD event occurs at the IO1 terminal, a transient large current enters P+ from the IO1 metal, passes through PW / Pepi / NBL / PBL2 / Nepi, reaches the N+ substrate, and is then discharged from Nepi / NBL / deep N region / N+, and released from the IO2 metal terminal.

[0128] like Figure 16 As shown, the arrows indicate the direction of the current. When an ESD event occurs at the IO2 terminal, a transient large current enters P+ from the IO2 metal, passes through PW / Pepi / NBL / PBL2 / Nepi, and is then discharged from NBL / deep N region / N+, and released from the IO1 metal terminal.

[0129] As can be seen, flexibility refers to the difference in practical applications. The protection voltage of the bidirectional symmetrical structure can switch directions arbitrarily in practical applications without causing the problem of the voltage being too small or too large to trigger the protection. The bidirectional SCR device in the embodiments of this specification can effectively improve the flexibility of SCR devices in circuit applications.

[0130] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the product embodiments described later are relatively simple since they correspond to the methods; relevant parts can be referred to the descriptions in the system embodiments.

[0131] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A bidirectional SCR device, characterized in that, include: An N+ substrate, wherein a first P-type buried layer is provided within the N+ substrate; An N-type epitaxial layer is provided, within which a second P-type buried layer and a third P-type buried layer are provided. An N-type buried layer is provided on the upper surface of the N-type epitaxial layer. The second P-type buried layer is located above the first P-type buried layer and does not contact the first P-type buried layer. The P-type epitaxial layer has four deep N-regions and two P-wells. Each deep N-region has one heavily doped N-type region, and each P-well has one heavily doped P-type region. An N-type heavily doped region is disposed between two heavily doped P-type regions. The two P-wells are respectively disposed corresponding to the second P-type buried layer and the third P-type buried layer. The N+ substrate, the N-type epitaxial layer, the N-type buried layer, and the P-type epitaxial layer are connected sequentially from bottom to top in the vertical direction. Three first isolation trenches are arranged in a direction perpendicular to the N+ substrate. One first isolation trench is arranged at each end of the first P-type buried layer, and one first isolation trench is arranged at the end of the third P-type buried layer away from the first P-type buried layer. Two second isolation trenches are arranged in a direction perpendicular to the N+ substrate. A second isolation trench is provided at each end of the second P-type buried layer. Two first isolation trenches are arranged between the first isolation trenches at both ends of the first P-type buried layer. The two P-type heavily doped regions are respectively connected to the first input / output terminal and the second input / output terminal, and the two N-type heavily doped regions are respectively connected to the first input / output terminal and the second input / output terminal.

2. The bidirectional SCR device according to claim 1, characterized in that, The depth of the first isolation trench is greater than the sum of the thicknesses of the N-type epitaxial layer and the P-type epitaxial layer, and the bottom surface of the first isolation trench is at the same height as the bottom surface of the first P-type buried layer.

3. The bidirectional SCR device according to claim 2, characterized in that, The distance between the bottom of the second isolation groove and the top surface of the first P-type buried layer is less than the distance between the bottom surface of the second P-type buried layer and the top surface of the first P-type buried layer, and the second isolation groove is located inside the N-type epitaxial layer and does not contact the first P-type buried layer.

4. The bidirectional SCR device according to claim 1, characterized in that, A dielectric layer is provided on the P-type epitaxial layer, and a contact hole is provided on the dielectric layer. Metal is deposited in the contact hole to form the first input / output terminal and the second input / output terminal. A passivation layer is provided at both ends of the first input / output terminal and the second input / output terminal on the metal.

5. The bidirectional SCR device according to claim 1, characterized in that, The second P-type buried layer is the same as the third P-type buried layer, and it passes sequentially from the first input / output terminal through the P-type heavily doped region, the p-well, the P-type epitaxial layer, the N-type buried layer, the third P-type buried layer, and the N-type epitaxial layer to reach the second input / output terminal; The signal travels sequentially from the second input / output terminal through the P-type heavily doped region, the p-well, the P-type epitaxial layer, the N-type buried layer, the second P-type buried layer, and the N-type epitaxial layer to reach the first input / output terminal.

6. The bidirectional SCR device according to claim 1, characterized in that, The first P-type buried layer diffuses upward into the interior of the N-type epitaxial layer.

7. A method for manufacturing a bidirectional SCR device, used to manufacture the bidirectional SCR device according to any one of claims 1-6, characterized in that, include: Step 1: Form a first P-type buried layer in the N+ substrate, and grow an N-type epitaxial layer on the N+ substrate; Step 2: Form a second P-type buried layer and a third P-type buried layer within the N-type epitaxial layer, and form an N-type buried layer on the upper surface of the N-type epitaxial layer. The N-type buried layer is located above the second P-type buried layer and the third P-type buried layer. The second P-type buried layer is located above the first P-type buried layer and is not in contact with the first P-type buried layer. Step 3: Generate a P-type epitaxial layer on the N-type buried layer to obtain the first structure; Step 4: Three first isolation grooves and two second isolation grooves are formed on the first structure. One first isolation groove is formed at each end of the first P-type burial layer. One first isolation groove is formed at the end of the third P-type burial layer away from the first P-type burial layer. One second isolation groove is formed at each end of the second P-type burial layer. Two first isolation grooves are formed between the first isolation grooves at both ends of the first P-type burial layer. Step 5: A deep N-region is formed within the P-type epitaxial layer between the first isolation trench and the second isolation trench, and on the outer side of the first isolation trench on both sides; Step 6: Within the P-type epitaxial layer, a P-well is formed in the region between the two second isolation trenches on both sides of the second P-type buried layer and in the region between the two first isolation trenches on both sides of the third P-type buried layer. Step 7: Form an N-type heavily doped region in each of the deep N regions and a P-type heavily doped region in each of the P wells to obtain the second structure; Step 8: Form a first input / output terminal and a second input / output terminal on the second structure.

8. The method for manufacturing a bidirectional SCR device according to claim 7, characterized in that, The depth of the first isolation trench is greater than the sum of the thicknesses of the N-type epitaxial layer and the P-type epitaxial layer, and the bottom surface of the first isolation trench is at the same height as the bottom surface of the first P-type buried layer.

9. The method for manufacturing a bidirectional SCR device according to claim 8, characterized in that, The distance between the bottom of the second isolation groove and the top surface of the first P-type buried layer is less than the distance between the bottom surface of the second P-type buried layer and the top surface of the first P-type buried layer, and the second isolation groove is located inside the N-type epitaxial layer and does not contact the first P-type buried layer.

10. The method for manufacturing a bidirectional SCR device according to claim 7, characterized in that, Step 8 includes: Step 801: Deposit a dielectric layer on the second structure; Step 802: Form a plurality of contact holes at the positions corresponding to the two P-type heavily doped regions and the two deep N-regions on the dielectric layer; Step 803: Deposit metal on the surface of the dielectric layer to deposit metal in the contact hole, so that the metal contacts the corresponding P-type heavily doped region and N-type heavily doped region to form a metal end; Step 804: Deposit a passivation layer on the surface of the dielectric layer and the metal end, and perform photolithography and etching on the passivation layer to form the first input / output terminal and the second input / output terminal on the metal end.

11. A method for manufacturing a bidirectional SCR device according to any one of claims 7-10, characterized in that, The second P-type buried layer is the same as the third P-type buried layer, and it passes sequentially from the first input / output terminal through the P-type heavily doped region, the p-well, the P-type epitaxial layer, the N-type buried layer, the third P-type buried layer, and the N-type epitaxial layer to reach the second input / output terminal; The signal travels sequentially from the second input / output terminal through the P-type heavily doped region, the p-well, the P-type epitaxial layer, the N-type buried layer, the second P-type buried layer, and the N-type epitaxial layer to reach the first input / output terminal.

12. The method for manufacturing a bidirectional SCR device according to claim 7, characterized in that, The first P-type buried layer diffuses upward into the interior of the N-type epitaxial layer.

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