Triggering device and method

Abstract

The application discloses a trigger device and method, the trigger device comprises a main stage latch, a clock signal generation circuit and a slave stage latch; the main stage latch is used for accessing a first clock signal, a second clock signal and input data, sampling the input data as a low level according to the first clock signal, sampling the input data as a high level according to the second clock signal, obtaining sampled data, and latching the sampled data when the first clock signal is a high level; the clock signal generation circuit is used for accessing the first clock signal, the input data and the sampled data, generating the second clock signal used for controlling the main stage latch and the slave stage latch to sample, and the second clock signal flips when the input data changes; the slave stage latch is used for accessing the first clock signal, the second clock signal and the sampled data, sampling the sampled data according to the first clock signal and the second clock signal, and obtaining output data. The application can effectively reduce the power consumption overhead of the trigger device in the working process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a trigger device and method. BACKGROUND

[0002] In the design of large-scale digital integrated circuits, clock power consumption is a very important part, accounting for 30%-60% of the total system power consumption. As the main component of digital circuits, the power consumption of flip-flops accounts for 80% of the entire clock power consumption. Current digital circuit design is based on standard cell library, and the flip-flop in the standard cell library usually adopts D flip-flop based on transmission gate structure. The D flip-flop based on transmission gate structure often includes a pair of clock inverters in its structure, which causes multiple transistors to charge and discharge continuously with the flipping of the clock signal, resulting in a large power consumption of the flip-flop circuit. SUMMARY

[0003] In view of this, the present application provides a trigger device and method to solve the technical problem of large power consumption of the traditional flip-flop circuit.

[0004] The present application provides a trigger device, comprising a main stage latch, a clock signal generating circuit and a slave stage latch;

[0005] The main stage latch is used to access a first clock signal, a second clock signal and input data, sample the input data as low level according to the first clock signal, sample the input data as high level according to the second clock signal, obtain sampled data, and latch the sampled data when the first clock signal is high level.

[0006] The clock signal generating circuit is used to access the first clock signal, the input data and the sampled data, generate a second clock signal for controlling the sampling of the main stage latch and the slave stage latch, and the second clock signal flips when the input data changes.

[0007] The slave stage latch is used to access a first clock signal, a second clock signal and sampled data, sample the sampled data according to the first clock signal and the second clock signal, and obtain output data.

[0008] Optionally, the main stage latch comprises a first sampling circuit and a first latch circuit; the first sampling circuit is used to sample the input data as low level when the first clock signal is low level, sample the input data as high level when the second clock signal is high level, obtain sampled data, and latch the sampled data when the first clock signal is high level; and the first latch circuit is used to latch the sampled data when the first clock signal is high level, for sampling by the slave stage latch.

[0009] Optionally, the first sampling circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor; a gate of the first MOS transistor is connected to the first clock signal, a source is connected to a high level signal, and a drain is connected to a source of the second MOS transistor; a gate of the second MOS transistor is connected to the input data, and a drain is connected to an input of the first latch circuit and a drain of the third MOS transistor; a gate of the third MOS transistor is connected to the input data, a source is connected to a drain of the fourth MOS transistor; a gate of the fourth MOS transistor is connected to the second clock signal, a source is grounded.

[0010] Optionally, the first latch circuit comprises a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and a first inverter; a gate of the fifth MOS transistor is connected to the second clock signal, a source is connected to a high level signal, and a drain is connected to an input of the first inverter; a gate of the sixth MOS transistor is connected to an output of the first inverter, a drain is connected to the input of the first inverter, and a source is connected to a drain of the seventh MOS transistor; a gate of the seventh MOS transistor is connected to the first clock signal, and a source is grounded.

[0011] Optionally, the clock signal generation circuit comprises a second inverter, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor and an eleventh MOS transistor; an input of the second inverter is connected to the input data, and an output is connected to a gate of the eighth MOS transistor; a source of the eighth MOS transistor is connected to a high level signal, and a drain is connected to a source of the ninth MOS transistor and a drain of the eleventh MOS transistor; a gate of the ninth MOS transistor is connected to the first clock signal, a drain is connected to a drain of the tenth MOS transistor, and is used for outputting the second clock signal; a gate of the tenth MOS transistor is connected to the first clock signal, and a source is connected to the sampling data; a gate of the eleventh MOS transistor is connected to the slave latch, and a source is connected to a high level signal.

[0012] Optionally, the slave latch comprises a second sampling circuit and a second latch circuit; the second sampling circuit is used for sampling a low level of the sampling data when the second clock signal is at a low level, and sampling a high level of the sampling data when the first clock signal is at a high level, to obtain output data; the second latch circuit is used for latching the output data when the first clock signal is at a low level.

[0013] Optionally, the second sampling circuit comprises a twelfth MOS transistor, a thirteenth MOS transistor and a fourteenth MOS transistor; a gate of the twelfth MOS transistor is connected to the second clock signal, a source of the twelfth MOS transistor is connected to a high-level signal, and a drain of the twelfth MOS transistor is connected to a drain of the thirteenth MOS transistor and the second latch circuit; a gate of the thirteenth MOS transistor is connected to the second clock signal, a source of the thirteenth MOS transistor is connected to a drain of the fourteenth MOS transistor and the second latch circuit; a gate of the fourteenth MOS transistor is connected to the first clock signal, and a source of the fourteenth MOS transistor is grounded.

[0014] Optionally, the second latch circuit comprises a fifteenth MOS transistor, a sixteenth MOS transistor and a third inverter; a gate of the fifteenth MOS transistor is connected to an output of the third inverter, a source of the fifteenth MOS transistor is connected to a drain of the first MOS transistor, and a drain of the fifteenth MOS transistor is connected to a drain of the twelfth MOS transistor and an input of the third inverter; a gate of the sixteenth MOS transistor is connected to the output of the third inverter, a drain of the sixteenth MOS transistor is connected to a source of the thirteenth MOS transistor, and a source of the sixteenth MOS transistor is grounded; and the output of the third inverter is used to output the output data.

[0015] Optionally, the trigger device further comprises an output stage circuit, which is used to buffer the output data.

[0016] Optionally, the output stage circuit comprises at least one inverter.

[0017] The application further provides a triggering method, which is applied to any one of the trigger devices and comprises the following steps:

[0018] The primary latch samples input data at a low level according to the first clock signal, samples input data at a high level according to the second clock signal, obtains sampling data, and latches the sampling data when the first clock signal is at a high level;

[0019] The clock signal generation circuit generates a clock signal used to control the primary latch and the secondary latch to sample and flip the second clock signal when the input data changes;

[0020] The secondary latch samples the sampling data according to the first clock signal and the second clock signal, and obtains output data.

[0021] In the trigger device and method provided by the present application, the main latch obtains sampled data based on the input data sampled as a low level according to the first clock signal and the input data sampled as a high level according to the second clock signal, and latches the sampled data when the first clock signal is at a high level to completely separate the latching and sampling paths, cut off the paths that may form competition, and enable the trigger device to operate stably at an ultra-low voltage. The clock signal generating circuit can generate a clock signal for controlling the sampling of the main latch and the slave latch, and flip the second clock signal when the input data changes, so that the second clock signal does not flip with the flip of the first clock signal, and only flips when the input data flips. The flip probability is low, each flip is necessary, there is no additional dynamic power consumption, and it can effectively reduce the power consumption overhead of the trigger device during operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 This is a schematic diagram of the structure of a trigger device according to an embodiment of the present application;

[0024] Figure 2 is a schematic structural diagram of a trigger device according to another embodiment of the present application;

[0025] Figure 3 is a schematic structural diagram of a trigger device according to another embodiment of the present application;

[0026] Figure 4 is a schematic structural diagram of a trigger device according to another embodiment of the present application;

[0027] Figure 5 This is a timing diagram of related signals of a trigger device in one embodiment of the present application. DETAILED DESCRIPTION

[0028] The following, in conjunction with the accompanying drawings, clearly and completely describes the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0029] The first aspect of the present application provides a trigger device, referring to Figure 1As shown in the figure, the trigger device comprises a main stage latch 110, a clock signal generating circuit 120 and a slave stage latch 130.

[0030] The main stage latch 110 is used to access a first clock signal, a second clock signal and input data, sample the input data as low level according to the first clock signal, sample the input data as high level according to the second clock signal, obtain sampled data, and latch the sampled data when the first clock signal is high level, so as to separate the latch and sample paths.

[0031] The clock signal generating circuit 120 is used to access the first clock signal, the input data and the sampled data, generate a second clock signal for controlling the main stage latch 110 and the slave stage latch 130 to sample, and the second clock signal flips when the input data changes.

[0032] The slave stage latch 130 is used to access a first clock signal, a second clock signal and sampled data, sample the sampled data according to the first clock signal and the second clock signal, and obtain output data.

[0033] The inventor finds that the main stage latch of most low-power triggers has a competition path, and the pull-up and pull-down of the related signals need a certain time. When the competition path exists, the pull-up and pull-down time of the signal will become longer and longer, thereby causing the function failure under low voltage. Therefore, the trigger device adopts a competition elimination method, and the latch and sample paths are completely separated in the main stage latch 110 to cut off the path that may form competition, so that the trigger device does not have a competition path and can work stably under ultra-low voltage.

[0034] In the trigger device, the main stage latch 110 samples the input data as low level according to the first clock signal, samples the input data as high level according to the second clock signal, obtains sampled data, and latches the sampled data when the first clock signal is high level, so as to completely separate the latch and sample paths, cut off the path that may form competition, and enable the trigger device to work stably under ultra-low voltage. The clock signal generating circuit 120 can generate a second clock signal for controlling the main stage latch and the slave stage latch to sample. The second clock signal does not flip with the first clock signal, but only flips when the input data flips, and the flipping probability is low. Each flipping is necessary, there is no additional dynamic power consumption, and the power consumption overhead of the trigger device in the working process can be effectively reduced.

[0035] In one embodiment, as Figure 2As shown, the master stage latch 110 comprises a first sampling circuit 111 and a first latch circuit 112; the first sampling circuit 111 is configured to sample input data as low level when the first clock signal is low level, sample input data as high level when the second clock signal is high level, obtain sampling data, and latch the sampling data when the first clock signal is high level; the first latch circuit 112 is configured to latch the sampling data for the slave stage latch to sample.

[0036] Optionally, the first sampling circuit 111 can comprise a plurality of transistors connected in series, and an input stage circuit is formed by the series connection of the transistors; the first latch circuit 112 can comprise three transistors connected in series and an inverter, to form a feedback latch loop; and the input stage circuit and the feedback latch loop are connected in sequence. Specifically, in the working process, the first sampling circuit 111 can sample master stage data (such as input data), and when the first clock signal is low level, the input data as 0 can be sampled, and when the first clock signal is high level, the sampling of the input data as 0 is prohibited. When the second clock signal is high level, the input data as 1 can be sampled, and when the second clock signal is low level, the sampling of the input data as 1 is prohibited. The first latch circuit 112 can latch the data for the slave stage latch 130 to sample when the first clock signal is high level. In this way, the first sampling circuit 111 and the first latch circuit 112 assist each other, and the master stage latch 110 can realize sampling of the input data when the first clock signal is low level and latching of the sampled data (sampling data) when the first clock signal is high level when the input data flips.

[0037] In one example, as shown in FIG. 2, the master stage latch 110 comprises a first sampling circuit 111 and a first latch circuit 112. Figure 3 As shown, the first sampling circuit 111 comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, and a fourth MOS transistor M4.

[0038] The gate of the first MOS transistor M1 is connected to the first clock signal CK, the source is connected to a high level signal, and the drain is connected to the source of the second MOS transistor M2; the gate of the second MOS transistor M2 is connected to the input data D, and the drain is connected to the input end (such as a first inverter I1 as shown) of the first latch circuit 112 and the drain of the third MOS transistor M3; the gate of the third MOS transistor M3 is connected to the input data D, and the source is connected to the drain of the fourth MOS transistor M4; the gate of the fourth MOS transistor M4 is connected to the second clock signal CK2, and the source is grounded. Figure 3

[0039] ​Optionally, the first MOS transistor M1 and the second MOS transistor M2 respectively comprise PMOS transistors, and the third MOS transistor M3 and the fourth MOS transistor M4 respectively comprise NMOS transistors, so that the first sampling circuit 111 can stably sample the input data D.

[0040] In one example, the first latch circuit 112 comprises a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7 and a first inverter I1; the gate of the fifth MOS transistor M5 is connected to the second clock signal CK2, the source is connected to a high-level signal, and the drain is connected to the input of the first inverter I1; the input of the first inverter I1 is the input of the first latch circuit 112, and the output is the output of the first latch circuit 112, used for outputting the sampling data DI; the gate of the sixth MOS transistor M6 is connected to the output of the first inverter I1, the drain is connected to the input of the first inverter I1, and the source is connected to the drain of the seventh MOS transistor M7; the gate of the seventh MOS transistor M7 is connected to the first clock signal CK, and the source is grounded. As shown in Figure 3 The drain of the second MOS transistor M2, the fifth MOS transistor M5, the third MOS transistor M3 and the sixth MOS transistor M6 are connected to sample the inverted signal of the input data D, and DN is the input of the first inverter I1; the output of the first inverter I1 can drive the clock signal generation circuit and the gate of the sixth MOS transistor M6.

[0041] Specifically, for the first sampling circuit 111 and the first latch circuit 112, when input data D undergoes a flip, sampling is performed when the first clock signal CK is at a low level, and latching is performed when the first clock signal CK is at a high level. That is, when the first clock signal CK is low, the inverted signal of input data D is sampled into DN; otherwise, DN remains unchanged. When the first clock signal CK is at a low level (signal logic value is 0), input data D = 0 can be transmitted to DN. When input data D = 1, sampling is controlled by the second clock signal CK2. When the second clock signal CK2 is 1, input data D = 1 can be transmitted to DN. When input data D undergoes a 0-to-1 flip, the second clock signal CK2 flips to 1 when the first clock signal CK is low, i.e., input data D undergoes a 0-to-1 flip. This is also sampling when the first clock signal CK is low. Sampling of input data D to 0 and 1 complies with the principle of sampling when the first clock signal CK is low. When the first clock signal CK is high, DN is maintained at a high level through the fifth MOS transistor M5. This is designed based on the characteristics of the second clock signal CK2. If the second clock signal CK2 is low, the first clock signal CK must be 1, and DN must be 1. Therefore, it is only necessary to determine whether the second clock signal CK2 is low to determine whether DN needs to be maintained at 1. When CK2 is high, it is also necessary to determine whether the first clock signal CK is high, and maintain the low level through the sixth MOS transistor M6 and the seventh MOS transistor M7.

[0042] In one embodiment, the clock signal generating circuit 120 may include an inverter and multiple transistors. The second clock signal generated by the clock signal generating circuit 120 directly controls the sampling and latching of the master latch 110 and the slave latch 130 to ensure that the master latch 110 and the slave latch 130 can sample or latch the correct data under the control of the second clock signal. The first clock signal CK and other related traditional clock signals will also continuously flip when the input data remains unchanged, causing the related transistors to continuously charge and discharge. The second clock signal designed in this embodiment only flips when the input data flips and the sampling channel needs to be opened or closed, greatly reducing power consumption. The second clock signal will only be pulled high when the first clock signal is low and the current input data flips from low to high, allowing the master latch 110 to sample. The low-to-high flip of the second clock signal is achieved through the inverter and related transistors. When the input data is likely to flip from low to high when the first clock signal is high, it is necessary to turn off the sampling of the main latch 110 to prevent the input data from being incorrectly sampled when the first clock signal CK is high, and pull the second clock signal CK2 low to prevent incorrect sampling of the input data.

[0043] During the operation of the clock signal generation circuit 120, when the sampling signal DI output by the first inverter I1 of the primary latch 110 is low and the first clock signal is high, the second clock signal CK2 is driven to a low level. In other operating scenarios, the second clock signal CK2 need not change. If the second clock signal CK2 was previously low, it can be stabilized at a low level. If the second clock signal CK2 was previously high, a high-level holding transistor can be used to prevent it from floating at a high level, causing long-term leakage and ultimately leading to functional errors. The second clock signal CK2 only flips when the input data D changes, and the flip probability is equivalent to the flip probability of the input data D. Its flip probability is significantly reduced compared to traditional related clock signals, that is, the inverse phase signal of the clock. Furthermore, the second clock signal CK2 has the largest fan-out besides the first clock signal, so reducing its flip probability can significantly reduce dynamic power consumption.

[0044] In one example, reference Figure 3 As shown, the clock signal generating circuit 120 includes a second inverter I2, an eighth MOS transistor M12, a ninth MOS transistor M13, a tenth MOS transistor M14, and an eleventh MOS transistor M15. The input end of the second inverter I2 is used to receive the input data D, and the output end is connected to the gate of the eighth MOS transistor M12. The source of the eighth MOS transistor M12 is connected to a high-level signal, and the drain is respectively connected to the source of the ninth MOS transistor M13 and the drain of the eleventh MOS transistor M15. The gate of the ninth MOS transistor M13 is connected to the first clock signal, and the drain is connected to the drain of the tenth MOS transistor M14, and is used to output the second clock signal CK2. The gate of the tenth MOS transistor M14 is connected to the first clock signal CK, and the source is connected to the sampled data DI. The gate of the eleventh MOS transistor M15 is connected to the slave latch (for example, connected to the drain of the twelfth MOS transistor M16), and the source is connected to the high-level signal.

[0045] In the clock signal generating circuit 120, the second inverter I2 receives the input data D, the eighth MOS transistor M12 receives the output signal of the second inverter I2, the ninth MOS transistor M13 and the tenth MOS transistor M14 receive the first clock signal CK. The eleventh MOS transistor M15 receives the signal from the slave stage latch 130, and mainly functions to maintain the high level of the second clock signal CK2. The drain of the ninth MOS transistor M13 and the tenth MOS transistor M14 are connected, and the output is the second clock signal CK2. The source of the tenth MOS transistor M14 is connected to the output of the first inverter II. The input source of the clock signal generating circuit 120 is from the output of the master stage latch 110, so the second clock signal CK2 generated thereby can serve as a transmission channel between the master stage latch 110 and the slave stage latch 120, and transmit the data output by the master stage latch 110 to the slave stage latch 130. Alternatively, the eighth MOS transistor M12, the ninth MOS transistor M13 and the eleventh MOS transistor M15 can comprise PMOS transistors, and the tenth MOS transistor M14 can comprise an NMOS transistor.

[0046] Specifically, the structure of the clock signal generating circuit 120 is designed based on the structural characteristics of the master latch 110 and the slave latch 130. The master latch 110 and the slave latch 130 are also optimized based on the characteristics of the second clock signal. The three designs can constrain and support each other. For the master latch 110, when the first clock signal CK is low and the input data D is high, the second clock signal CK2 is high. Only then can the third MOS transistor M3 and the fourth MOS transistor M4 in the master latch 110 correctly sample the input data D at a high level. Therefore, when the input data D is high and the first clock signal CK is low, the clock signal generating circuit 120 drives the second clock signal CK2 to a high level. If the current input data D changes while the first clock signal CK is high, the master latch 110 must prohibit sampling; otherwise, erroneous data will be sampled during the high level period of the first clock signal CK. When input data D flips from 1 to 0, the first MOS transistor M1 controlled by the first clock signal CK is already sampling disabled. When input data D flips from 0 to 1, the second clock signal CK2 is driven to 0 to disable sampling of input data D. Furthermore, the first clock signal CK controls the source of the tenth MOS transistor M14, which is connected to the sampling signal DI. The sampling signal DI is the inverted signal of the input data DN of the first inverter I1, i.e., the initial sampling signal for input data D by the main latch 110. If the sampling signal DI is 1 (high), it indicates that the previous input data D was 1 and a 0-to-1 flip is unlikely. Therefore, the second clock signal CK2 can remain high. If the sampling signal DI is 0 (low), it indicates that a 0-to-1 flip is possible. In this case, the second clock signal CK2 is driven to a low level. In other cases, the second clock signal CK2 maintains its level. The eleventh MOS transistor M15 is used to maintain the second clock signal CK2 at a high level to prevent the second clock signal CK2 from flipping to a low level due to long-term leakage. As can be seen from the above, the second clock signal CK2 does not flip along with the flip of the first clock signal CK, but only flips when the input data D flips. The flip probability is low, and each flip is necessary, without any additional dynamic power consumption.

[0047] In one embodiment, reference Figure 2 As shown, the slave latch 130 includes a second sampling circuit 131 and a second latch circuit 132; the second sampling circuit 131 is used to sample the low level of the sampled data when the second clock signal CK2 is at a low level, and to sample the high level of the sampled data when the first clock signal is at a high level to obtain output data; the second latch circuit 132 is used to latch the output data when the first clock signal CK is at a low level.

[0048] Optionally, the second sampling circuit 131 can include three transistors in series, and the second latch circuit 132 can include a plurality of transistors and an inverter, and the second sampling circuit 131 and the second latch circuit 132 can be connected in sequence.

[0049] In one example, the second sampling circuit 131 includes a twelfth MOS transistor M16, a thirteenth MOS transistor M17, and a fourteenth MOS transistor M18; a gate of the twelfth MOS transistor M16 is connected to the second clock signal window, a source is connected to a high-level signal, and a drain is connected to a drain of the thirteenth MOS transistor M17 and an input of the third inverter I3 of the second latch circuit 132, a gate of the thirteenth MOS transistor M17 is connected to the second clock signal reference, a source is connected to a drain of the fourteenth MOS transistor M18 and a drain of the sixteenth MOS transistor M20 of the second latch circuit 132, a gate of the fourteenth MOS transistor M18 is connected to the first clock signal CK, and a source is grounded.

[0050] Optionally, the twelfth MOS transistor M16 includes a PMOS transistor, the thirteenth MOS transistor M17 includes an NMOS transistor, inputs of the twelfth MOS transistor M16 and the thirteenth MOS transistor M17 are both the second clock signal CK2, the fourteenth MOS transistor M18 includes an NMOS transistor, and an input signal of the fourteenth MOS transistor M18 is the first clock signal CK. The second sampling circuit 131 realizes high-level sampling through a PMOS transistor and low-level sampling through an NMOS transistor.

[0051] In one example, the second latch circuit 132 includes a fifteenth MOS transistor M19, a sixteenth MOS transistor M20, and a third inverter I3; a gate of the fifteenth MOS transistor M19 is connected to an output of the third inverter I3, a source is connected to a drain of the first MOS transistor M1, and a drain is connected to a drain of the twelfth MOS transistor M16 and an input of the third inverter I3, a gate of the sixteenth MOS transistor M20 is connected to an output of the third inverter I3, a drain is connected to a source of the thirteenth MOS transistor M17, and a source is grounded, and the output of the third inverter I3 is used to output the output data.

[0052] In particular, the second latch circuit 132 can include four transistors in series and an inverter in operation, two of which are the fifteenth MOS transistor M19 and the sixteenth MOS transistor M20, both of which have an input of the output QI of the third inverter I3 in the second latch circuit 132; the other two transistors can reuse the first transistor M1 of the main stage latch 110 and the thirteenth MOS transistor M17 in the second sampling circuit 131. The drain of the twelfth MOS transistor M16, the thirteenth MOS transistor M17 and the fifteenth MOS transistor M19 in the second sampling circuit 131 are connected, and the output end is connected to the input end of the third inverter I3. The second latch circuit 132 can form a feedback latch loop, the first transistor in the feedback latch loop reuses the first transistor M1 of the main stage latch 110, so that the source of the fifteenth MOS transistor M19 in the feedback latch loop is connected to the drain of the first transistor M1 to form a latch pull-up path. The feedback latch loop also reuses the thirteenth MOS transistor M17 in the second sampling circuit 131, so that the drain of the sixteenth MOS transistor M20 in the feedback latch loop is connected to the source of the thirteenth MOS transistor M17 to form a latch pull-down path.

[0053] In this way, the slave stage latch 130 samples the sampling data output by the main stage latch 110 when the first clock signal CK is high to obtain initial output data, and latches the initial output data obtained when the first clock signal CK is low. In particular, the slave stage latch 130 samples the input DN of the first inverter to QN (the input of the third inverter) when the first clock signal CK is high, and maintains QN unchanged when the first clock signal CK is low. The specific implementation process can include: when the first clock signal CK=1, if the second clock signal CK2=0, at this time the first clock signal CK is necessarily high and the DN signal to be sampled from the main stage latch 110 is 1, so QN only needs to be synchronized to 1 through the twelfth MOS transistor M16 controlled by the second clock signal CK2; if the second clock signal CK2=1, at this time DN=0, the first clock signal CK can be at high or low, so QN needs to be pulled down through the thirteenth MOS transistor M17 and the fourteenth MOS transistor M18, and the fourteenth MOS transistor M18 needs to determine that the first clock signal CK is high to synchronize QN to 0. When the first clock signal CK=0, the fourteenth MOS transistor M18 is closed, and the high level of QN is maintained through the third inverter I3, the fifteenth MOS transistor M19 and the first MOS transistor M1, and the low level of QN is maintained through the third inverter I3, the thirteenth MOS transistor M17 and the sixteenth MOS transistor M20.

[0054] In one embodiment, with reference to Figure 4As shown, the trigger device further comprises an output stage circuit 140 for buffering the output data. Specifically, the output stage circuit 140 can receive the output data QI from the third inverter I3 in the slave latch 130, and buffer the output data QI to ensure the quality of the final output signal.

[0055] In one example, the output stage circuit 140 comprises at least one inverter. Optionally, the number and size of inverters can be increased according to the need of different driving capabilities to ensure the stability of the output stage circuit 140. Optionally, as shown in FIG. 2, the output stage circuit 140 comprises a fourth inverter I4, which drives QN as a Q signal in phase with the input data D to complete the sampling of the entire trigger device; at the same time, it can also buffer the initial output data to ensure the quality of the final output signal. Figure 4

[0056] In one example, to more clearly show the working process of the provided trigger device, the trigger device will be described in detail below. Figure 4 Figure 5 The waveform diagram of the key signals of the trigger device during operation is shown to illustrate the working process of the entire trigger device, which can be divided into two stages: the sampling of the master latch 110 and the sampling of the slave latch 130. Figure 5 The working process of the trigger device when the input data D signal flips from 1 to 0 is shown in the middle ①. At this time, the first clock signal CK is at a low level, DN is pulled up to 1 through the first MOS tube M1 and the second MOS tube M2, and the sampling of the master latch 110 is completed. When the first clock signal CK arrives at a high level, the sampling channel of the master latch 110 needs to be closed at this time, so the second clock signal CK2 signal is driven to a low level. Since the second clock signal CK2 = 0, DN can be kept unchanged through the fifth MOS tube M5 for the sampling of the slave latch 130, and QN is pulled up to a high level through the twelfth MOS tube M16 to complete the sampling of the slave latch 130. Figure 3 ​​The operation of each signal when the input data D signal turns from 0 to 1 is shown in Fig. 2. When the first clock signal CK = 0, because the input data D signal turns to 1, it needs to be sampled through the third MOS transistor M3 and the fourth MOS transistor M4, so the second clock signal CK2 signal needs to turn to 1 to allow the main stage latch to sample the input data D = 1 signal, which is realized by the second inverter I2, the eighth MOS transistor M12 and the ninth MOS transistor M13. When the second clock signal CK2 is driven to the logic high level, the inverted signal of the input data D is sampled to DN, completing the sampling of the main stage latch 110. When the first clock signal CK turns to the high level, the sixth MOS transistor M6 and the seventh MOS transistor M7 open to maintain DN low for the sampling of the slave stage latch 130. The fourteenth MOS transistor M18 in the slave stage latch 130 switches from the closed state to the open state, and DN is sampled to QN through the thirteenth MOS transistor M17 and the fourteenth MOS transistor M18, completing the sampling of the slave stage latch 130.

[0057] Because the main stage latch 110 samples at the low level and latches at the high level when the input data D turns, and the slave stage latch 130 samples at the high level and latches at the low level, the function of the corresponding trigger device is realized. The separate sampling and latching paths of the main stage latch 110 avoid the possible competition. The slave stage latch 130 uses transistor multiplexing, reducing the number of necessary transistors. Figure 5 The waveform diagram of the related clock signal CKB in the prior art is also given. Compared with the second clock signal CK2 provided by the embodiment, which is in the state of continuously turning with CK, the second clock signal CK2 of the embodiment follows the principle that when the input data signal does not turn, the circuit state only needs to be maintained. The turning probability of the second clock signal CK2 is the same as the turning probability of the input data D, which is much smaller than that of the clock signal. Moreover, the related clock signal CKB generally has a large load, and the elimination of the redundant turning reduces the number of charging and discharging of multiple transistors, greatly reducing the power consumption. It can be seen that the above trigger device is a single-phase clock low-power D trigger facing a wide voltage without internal competition path, which effectively overcomes the problem that many low-power triggers cannot work at ultra-low voltage due to competition, and can work normally at a wide voltage. The trigger device structure does not have a clock inverter inside, and the second clock signal eliminates all redundant turns, greatly reducing the turning probability and power consumption. It is a low-power trigger. The comparative analysis shows that, Figure 4The trigger device shown introduces a second clock signal CK2, the clock signal generation circuit 120 increases the number of partial transistors, but has the same number of transistors compared with the D flip-flop unit in the standard cell library, and the timing characteristics are similar, which has great advantages in the field of low-voltage and low-power circuit design, and the greater the proportion of trigger device power consumption, the lower the data flip probability, and the more obvious the benefit; the present example is applied to a circuit in which the power consumption of the trigger device accounts for 20%-30% of the total circuit power consumption, and about 10% of the power consumption can be reduced.

[0058] Optionally, each of the inverters (such as the first inverter I1 to the fourth inverter I4 and the like) can include two MOS tubes, such as the seventeenth MOS tube and the eighteenth MOS tube; the gate of the seventeenth MOS tube is the input end of the corresponding inverter, the source is connected to a high-level signal, and the drain is the output end of the inverter; the gate of the eighteenth MOS tube is the input end of the corresponding inverter, the drain is connected to the drain of the seventeenth MOS tube, and the source is grounded.

[0059] The above trigger device overcomes the problem that most low-power flip-flops cannot work normally at low voltage, does not have a competitive path inside, and can still work stably in the sub-threshold working interval, and is a low-power trigger device suitable for wide voltage. Unlike the first clock signal being in a state of constant flipping, the clock signal generation circuit 120 can generate a second clock signal for controlling the main-stage latch 110 and the slave-stage latch 130, the second clock signal only flips with the input data of the flip-flop, the flipping probability is low, there is no redundant flipping, and the dynamic power consumption of the entire trigger device is effectively reduced. The specific structure of the above trigger device further optimizes the timing and power consumption by means of port position redistribution and transistor multiplexing.

[0060] The first aspect of the present application provides a trigger method applied to the trigger device described in any of the above embodiments, including the following steps:

[0061] The main-stage latch samples the input data as low level according to the first clock signal, samples the input data as high level according to the second clock signal, obtains sampling data, and latches the sampling data when the first clock signal is high;

[0062] The clock signal generation circuit generates a second clock signal for controlling the sampling of the main-stage latch and the slave-stage latch, and flips the second clock signal when the input data changes;

[0063] The slave-stage latch samples the sampling data according to the first clock signal and the second clock signal to obtain output data.

[0064] The above trigger method is applied to the trigger device described in any of the above embodiments, and has all the beneficial effects of the trigger device, which will not be described here.

[0065] Although the present application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based on the foregoing description and accompanying drawings. The application includes all such modifications and alterations and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the above described components (assemblies), the terms (e.g., "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the exemplary implementation illustrated by the present application. In this manner, it will be understood that by virtue of the disclosure of the present application, those skilled in the art will be able to devise the equivalent structures and implementations which, although perhaps not explicitly set forth in the above description, embody the principles of the present application.

[0066] That is, the above description is merely illustrative of the application, and not limiting of the same, the scope of which is to be determined entirely by the following claims, which are to be interpreted in accordance with the principles of patent law. Any reference to claims in the following description is intended to refer to the claims as interpreted in accordance with the principles of patent law.

[0067] In addition, the terms "first", "second", etc. are used herein only to describe various steps in a method and are not intended to, nor should they be construed to, refer to a relative importance of the various steps used in the method. With this in mind, an element defined with "first", "second", etc. can include, explicitly or implicitly, one or more elements. In the description of the present application, the meaning of "a plurality of" is two or more, unless specifically defined otherwise.

[0068] The application is now described, by way of example only, with reference to the accompanying drawings in which: In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular architectures, techniques, etc. in order to provide a thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, processes, techniques, etc. are not presented in order to avoid obscuring the description of the present application. Accordingly, the present application is not intended to be limited by the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims

1. A trigger device, characterized in that: The trigger device includes a master latch, a clock signal generating circuit and a slave latch; The primary latch is configured to receive a first clock signal, a second clock signal, and input data, sample input data at a low level according to the first clock signal, and sample input data at a high level according to the second clock signal to obtain sampled data, and latch the sampled data when the first clock signal is at a high level; The clock signal generating circuit is used to receive the first clock signal, the input data and the sampled data, and generate a second clock signal for controlling the sampling of the master latch and the slave latch, wherein the second clock signal flips when the input data changes; The slave latch is used to access the first clock signal, the second clock signal and the sampled data, and to sample the sampled data according to the first clock signal and the second clock signal to obtain output data; The master-level latch includes a first sampling circuit and a first latch circuit; the first sampling circuit is used to sample low-level input data when the first clock signal is low, and to sample high-level input data when the second clock signal is high, to obtain sampled data, and to latch the sampled data when the first clock signal is high; the first latch circuit is used to latch the sampled data when the first clock signal is high, so as to provide the slave-level latch with sampling.

2. The trigger device according to claim 1, characterized in that: The first sampling circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor; The gate of the first MOS transistor is connected to the first clock signal, the source is connected to the high-level signal, the drain is connected to the source of the second MOS transistor, the gate of the second MOS transistor is connected to the input data, the drain is respectively connected to the input end of the first latch circuit and the drain of the third MOS transistor, the gate of the third MOS transistor is connected to the input data, the source is connected to the drain of the fourth MOS transistor, the gate of the fourth MOS transistor is connected to the second clock signal, and the source is grounded.

3. The trigger device according to claim 2, characterized in that: The first latch circuit includes a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and a first inverter; The gate of the fifth MOS transistor is connected to the second clock signal, the source is connected to the high-level signal, and the drain is connected to the input of the first inverter. The gate of the sixth MOS transistor is connected to the output of the first inverter, the drain is connected to the input of the first inverter, and the source is connected to the drain of the seventh MOS transistor. The gate of the seventh MOS transistor is connected to the first clock signal, and the source is grounded.

4. The trigger device according to claim 1, characterized in that: The clock signal generating circuit includes a second inverter, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, and an eleventh MOS transistor; The input end of the second inverter is used to receive the input data, and the output end is connected to the gate of the eighth MOS transistor. The source of the eighth MOS transistor is connected to a high-level signal, and the drain is respectively connected to the source of the ninth MOS transistor and the drain of the eleventh MOS transistor. The gate of the ninth MOS transistor is connected to the first clock signal, and the drain is connected to the drain of the tenth MOS transistor, and is used to output the second clock signal. The gate of the tenth MOS transistor is connected to the first clock signal, and the source is connected to the sampled data. The gate of the eleventh MOS transistor is connected to the slave latch, and the source is connected to the high-level signal.

5. The trigger device according to claim 1, characterized in that: The slave latch includes a second sampling circuit and a second latch circuit; The second sampling circuit is configured to sample a low level of the sampled data when the second clock signal is at a low level, and to sample a high level of the sampled data when the first clock signal is at a high level, to obtain output data; The second latch circuit is configured to latch the output data when the first clock signal is at a low level.

6. The trigger device according to claim 5, characterized in that: The second sampling circuit includes a twelfth MOS transistor, a thirteenth MOS transistor and a fourteenth MOS transistor; The gate of the twelfth MOS transistor is connected to the second clock signal, the source is connected to the high-level signal, the drain is respectively connected to the drain of the thirteenth MOS transistor and the second latch circuit, the gate of the thirteenth MOS transistor is connected to the second clock signal, the source is respectively connected to the drain of the fourteenth MOS transistor and the second latch circuit, the gate of the fourteenth MOS transistor is connected to the first clock signal, and the source is grounded.

7. The trigger device according to claim 6, characterized in that: The second latch circuit includes a fifteenth MOS transistor, a sixteenth MOS transistor and a third inverter; The gate of the fifteenth MOS transistor is connected to the output end of the third inverter, the source is connected to the drain of the first MOS transistor, and the drain is respectively connected to the drain of the twelfth MOS transistor and the input end of the third inverter. The gate of the sixteenth MOS transistor is connected to the output end of the third inverter, the drain is connected to the source of the thirteenth MOS transistor, and the source is grounded. The output end of the third inverter is used to output the output data.

8. The trigger device according to claim 1, characterized in that: The trigger device further includes an output stage circuit, and the output stage circuit is used for buffering the output data.

9. The trigger device according to claim 8, characterized in that: The output stage circuit includes at least one inverter.

10. A triggering method, characterized in that: The trigger device according to any one of claims 1 to 9 comprises the following steps: The primary latch samples input data at a low level according to the first clock signal and samples input data at a high level according to the second clock signal to obtain sampled data, and latches the sampled data when the first clock signal is at a high level; The clock signal generating circuit generates a second clock signal for controlling the sampling of the master latch and the slave latch, and flipping the second clock signal when the input data changes; The slave latch samples the sampled data according to the first clock signal and the second clock signal to obtain output data; The master-level latch includes a first sampling circuit and a first latch circuit; the first sampling circuit is used to sample low-level input data when the first clock signal is low, and to sample high-level input data when the second clock signal is high, to obtain sampled data, and to latch the sampled data when the first clock signal is high; the first latch circuit is used to latch the sampled data when the first clock signal is high, so as to provide the slave-level latch with sampling.

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