A 32-bit parallel self-synchronous codec, system and method thereof

Abstract

The present invention discloses a 32-bit parallel self-synchronous codec, system and method thereof. The codec and decoder each include 32 XOR gates and 51 D flip-flops. The XOR gates and D flip-flops are sequentially interleaved in series. The D flip-flops of the codec are connected in series. 50 …D 32 The output value and input signal X 31 …X 13 Performing modulo 2 addition operation obtains the output signal value of the high 19 bits of the coding sequence, which is also the 19-bit D flip-flop D 31 …D 13 Input value, input signal X 12 ...X0 and D 31 …D 19 The output value of the code sequence is obtained by modulo 2 addition to obtain the value of the lower 13-bit output signal of the code sequence. 12 ...the input value of D0; the D flip-flop of the decoder D 50 …D 19 The output value of the 32-bit input signal is subjected to a modulo-2 addition operation to obtain a 32-bit decoding sequence; the present invention uses a simple digital logic circuit to convert a serial code stream into parallel data, and can perform encoding and decoding processing on general data frames. It has strong universality, helps to enhance the security and reliability of data transmission quality, and improves the degree of integration of the system.

Description

Technical Field

[0001] The present invention relates to the technical field of data communication and transmission, and more particularly to a 32-bit parallel self-synchronizing codec, a system and a method thereof. Background Art

[0002] Currently, existing communication technology standards specify a self-synchronizing scrambler and descrambler capable of serially scrambling and descrambling data during transmission, and this technology is now being applied in practical engineering. Self-synchronization means that, under any initial state, as long as the descrambler correctly receives the scrambling and encoding sequences, the receiver can achieve synchronization within a certain timeframe and recover the correct original input data. Under these conditions, even if the receiver receives erroneous codeword information, it can still quickly recover synchronization.

[0003] To prevent all 1s or all 0s from appearing during data transmission and to ensure reliable transmission quality, a scrambler typically uses a scrambling code polynomial to scramble the data frame. After receiving the scrambling code sequence, the descrambler performs a descrambling operation to recover the original data. During scrambling and descrambling, the initial value is typically set to all 1s, the same as the input data bit width.

[0004] With the scrambling polynomial X 51 +1 as an example, the 51 D flip-flops used by the serial self-synchronous scrambler and descrambler are all used to shift the data, where the scrambler is to combine the input data with the last D flip-flop D 50 The output value of the modulo 2 addition operation is performed, and the serial data obtained is the output scrambling sequence of the scrambler. At the same time, the data is output to the input end of the first D flip-flop D0 as the input signal of the D0 flip-flop; the input data to be descrambled of the descrambler is connected to the last D flip-flop D 50 The output value of the D flip-flop is modulo 2 added, and the input data is also sent to the input end of the first D flip-flop D0 as the input signal of the D0 flip-flop.

[0005] Although the above-mentioned serial self-synchronizing scrambling and descrambling device has a simple circuit and is easy to process, it has significant limitations. It cannot perform scrambling and descrambling on various types of data, and is only applicable to situations where the data transmission rate requirement is not high. It is difficult to meet the actual high transmission rate requirements of current engineering projects.

[0006] Therefore, in order to achieve high transmission rate, wide applicability and high integration, how to provide a 32-bit parallel self-synchronizing codec, system and method thereof to meet the needs of data transmission in modern communication engineering is an urgent problem that technicians in this field need to solve. Summary of the Invention

[0007] In view of this, the present invention provides a 32-bit parallel self-synchronizing codec, system and method thereof, which converts serial data into parallel data and adopts a more universal scrambling polynomial X 51 +1 performs scrambling and descrambling processing, which greatly reduces the operating frequency of the system, improves the data transmission rate, and enhances the integration of the structure.

[0008] In order to achieve the above object, the present invention adopts the following technical solutions:

[0009] A 32-bit parallel self-synchronous encoder, wherein the input end of the parallel self-synchronous encoder is connected to the data signal output end, and the output end of the parallel self-synchronous encoder outputs a coding sequence, comprising: 32 XOR gates and 51 D flip-flops, the 32 XOR gates and the 51 D flip-flops are sequentially interleaved in series, the 32 XOR gates are represented as XOR0, XOR1, ..., XOR31, and the 51 D flip-flops are represented as D0, D1, ..., D 50 , the data signal output terminals are represented as X0, X1, ...X 31 , the output of the parallel self-synchronous encoder is represented by Y0, Y1, ..., Y 31 ;

[0010] D 18 ...D0 input terminal is connected to the encoder output terminal Y of the previous clock 18 ...Y0 is connected, D 18 ...the output terminals of D0 are connected to D 50 …D 32 The input terminals are connected in sequence, D 50 …D 32 The output terminal and data signal output terminal X 31 …X 13 They are respectively connected to the input terminals of the XOR gates XOR31…XOR13 in sequence;

[0011] D 31 …D 19 The input end is connected to the encoder output end Y of the previous clock 31 …Y 19 Connected, D 31 …D 19 The output terminal and data signal output terminal X 12 …X0 is connected to the input terminals of XOR gates XOR12…XOR0 in sequence respectively;

[0012] The output end of the exclusive OR gate XOR31…XOR0 is the output end of the parallel self-synchronous encoder.

[0013] Preferably, D 18 …D0 is used to temporarily store the output data of the encoder of the previous clock.

[0014] Preferably, the XOR gates XOR31...XOR13 are used to switch the D flip-flop D 50 ...D 32 The output value and data signal output terminal X 31 …X 13 The data to be encoded is modulo 2 added and the value of the high 19-bit output signal of the encoding sequence is output; the XOR gate XOR12...XOR0 is used to output the data signal to the output terminal X 12 ...X0's data to be encoded is connected to the D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the coding sequence.

[0015] A coding method for a 32-bit parallel self-synchronous encoder, comprising:

[0016] D 18 ...D0 temporarily stores the output data of the encoder of the previous clock and shifts it to D 50 …D 32 ;

[0017] XOR gates XOR31…XOR13 convert the D flip-flop D 50 ...D 32 The output value and data signal output terminal X 31 …X 13 Perform modulo 2 addition on the data to be encoded and output the value of the high 19-bit output signal of the encoding sequence;

[0018] At the same time, D 31 …D 19 Receive the output data of the encoder of the previous clock and transmit it to the exclusive OR gate XOR12...XOR0;

[0019] XOR gate XOR12…XOR0 outputs the data signal to the X 12 ...X0's data to be encoded is connected to the D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the coding sequence.

[0020] A 32-bit parallel self-synchronous decoder, wherein the input end of the parallel self-synchronous decoder is connected to the output end of the encoder, and the output end of the parallel self-synchronous decoder outputs a decoding sequence, comprising: 32 XOR gates and 51 D flip-flops, the 32 XOR gates and the 51 D flip-flops are sequentially interleaved in series, the 32 XOR gates are represented as XOR0, XOR1, ..., XOR31, and the 51 D flip-flops are represented as D0, D1, ..., D 50 , the encoder output is represented by Y0, Y1, ...Y 31 The output terminals of the parallel self-synchronous decoder are represented as X0, X1, ..., X 31;

[0021] D 18 ...D0 input terminal is connected to the encoder output terminal Y of the previous clock 18 ...Y0 is connected, D 18 ...the output terminals of D0 are connected to D 50 …D 32 The input terminals are connected in sequence, D 50 …D 32 The output terminal and encoder output terminal Y 31 …Y 13 They are respectively connected to the input terminals of the XOR gates XOR31…XOR13 in sequence;

[0022] D 31 …D 19 The input end is connected to the encoder output end Y of the previous clock 31 …Y 19 Connected, D 31 …D 19 The output terminal and encoder output terminal Y 12 …Y0 is connected to the input terminals of XOR gates XOR12…XOR0 in sequence respectively;

[0023] The output terminals of the XOR gates XOR31…XOR0 are the output terminals of the parallel self-synchronizing decoder.

[0024] Preferably, D 18 …D0 is used to temporarily store the output data of the encoder of the previous clock.

[0025] Preferably, the XOR gates XOR31...XOR13 are used to switch the D flip-flop D 50 ...D 32 The output value of the encoder output Y 31 …Y 13 The data to be decoded is modulo 2 added and the value of the high 19-bit output signal of the decoding sequence is output; the XOR gate XOR12…XOR0 is used to add the encoder output terminal Y 12 ...Y0's decoded data and D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the decoding sequence.

[0026] A decoding method for a 32-bit parallel self-synchronizing decoder, comprising:

[0027] D 18 ...D0 temporarily stores the output data of the encoder of the previous clock and shifts it to D 50 …D 32 ;

[0028] XOR gates XOR31…XOR13 convert the D flip-flop D 50 ...D 32 The output value of the encoder output Y 31 …Y 13 Perform modulo 2 addition on the data to be decoded and output the value of the high 19-bit output signal of the decoding sequence;

[0029] At the same time, D 31 …D 19 Receive the output data of the encoder of the previous clock and transmit it to D 31 …D 19 ;

[0030] XOR gate XOR12...XOR0 converts the encoder output Y 12 ...Y0's decoded data and D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the decoding sequence.

[0031] A 32-bit parallel self-synchronous encoding and decoding system, comprising: a parallel self-synchronous encoder and a parallel self-synchronous decoder; the parallel self-synchronous encoder input end is connected to the data signal output end, the parallel self-synchronous encoder output end outputs a coding sequence, the parallel self-synchronous decoder input end is connected to the encoder output end, and the parallel self-synchronous decoder output end outputs a decoding sequence;

[0032] The parallel self-synchronous encoder includes 32 XOR gates and 51 D flip-flops, wherein the 32 XOR gates and the 51 D flip-flops are sequentially interleaved in series, the 32 XOR gates are represented as XOR0, XOR1, ..., XOR31, and the 51 D flip-flops are represented as D0, D1, ..., D 50 , the data signal output terminals are represented as X0, X1, ...X 31 , the output of the parallel self-synchronous encoder is represented by Y0, Y1, ..., Y 31 ;

[0033] D 18 ...D0 input terminal is connected to the encoder output terminal Y of the previous clock 18 ...Y0 is connected, D 18 ...the output terminals of D0 are connected to D 50 …D 32 The input terminals are connected in sequence, D 50 …D 32 The output terminal and data signal output terminal X 31 …X 13 They are respectively connected to the input terminals of the XOR gates XOR31…XOR13 in sequence;

[0034] D 31 …D 19The input end is connected to the encoder output end Y of the previous clock 31 …Y 19 Connected, D 31 …D 19 The output terminal and data signal output terminal X 12 …X0 is connected to the input terminals of XOR gates XOR12…XOR0 in sequence respectively;

[0035] The output of the XOR gate XOR31…XOR0 is the output of the parallel self-synchronous encoder;

[0036] A parallel synchronous decoder includes 32 XOR gates and 51 D flip-flops, wherein the 32 XOR gates and the 51 D flip-flops are sequentially interleaved in series, the 32 XOR gates are represented as XOR0, XOR1, ..., XOR31, and the 51 D flip-flops are represented as D0, D1, ..., D 50 , the encoder output is represented by Y0, Y1, ...Y 31 The output terminals of the parallel self-synchronizing decoder are represented as X0, X1, ..., X 31 ;

[0037] D 18 ...D0 input terminal is connected to the encoder output terminal Y of the previous clock 18 ...Y0 is connected, D 18 ...the output terminals of D0 are connected to D 50 …D 32 The input terminals are connected in sequence, D 50 …D 32 The output terminal and encoder output terminal Y 31 …Y 13 They are respectively connected to the input terminals of the XOR gates XOR31…XOR13 in sequence;

[0038] D 31 …D 19 The input end is connected to the encoder output end Y of the previous clock 31 …Y 19 Connected, D 31 …D 19 The output terminal and encoder output terminal Y 12 …Y0 is connected to the input terminals of XOR gates XOR12…XOR0 in sequence respectively;

[0039] The output of the XOR gates XOR31…XOR0 is the output of the parallel self-synchronizing decoder;

[0040] D 18 ...D0, used for temporarily storing the output data of the encoder of the previous clock;

[0041] The XOR gates XOR31…XOR13 of the parallel self-synchronous encoder are used to convert the D flip-flop D 50 ...D 32 The output value and data signal output terminal X 31 …X 13 The data to be encoded is modulo 2 added and the value of the high 19-bit output signal of the encoding sequence is output; the XOR gate XOR12...XOR0 is used to output the data signal to the output terminal X 12 ...X0's data to be encoded is connected to the D flip-flop D 31 …D 19 Perform modulo 2 addition on the output value and output the value of the lower 13-bit output signal of the coding sequence;

[0042] The XOR gates XOR31…XOR13 of the parallel synchronous decoder are used to convert the D flip-flop D 50 ...D 32 The output value of the encoder output Y 31 …Y 13 The data to be decoded is modulo 2 added and the value of the high 19-bit output signal of the decoding sequence is output; the XOR gate XOR12…XOR0 is used to add the encoder output terminal Y 12 ...Y0's decoded data and D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the decoding sequence.

[0043] A 32-bit parallel self-synchronous encoding and decoding method, comprising:

[0044] Encoder D 18 ...D0 temporarily stores the output data of the encoder of the previous clock and transmits it to D 50 …D 32 ; XOR gates XOR31…XOR13 convert the D flip-flop D 50 ...D 32 The output value and data signal output terminal X 31 …X 13 The data to be encoded is modulo 2 added and the value of the high 19-bit output signal of the encoding sequence is output; at the same time, D 31 …D 19 Receive the output data of the encoder of the previous clock and transmit it to D 31 …D 19 ; XOR gate XOR12…XOR0 outputs the data signal to the X 12 ...X0's data to be encoded is connected to the D flip-flop D 31 …D 19 Perform modulo 2 addition on the output value and output the value of the lower 13-bit output signal of the coding sequence;

[0045] Decoder D18 ...D0 temporarily stores the output data of the encoder of the previous clock and transmits it to D 50 …D 32 ; XOR gates XOR31…XOR13 convert the D flip-flop D 50 ...D 32 The output value of the encoder output Y 31 …Y 13 The data to be decoded is modulo 2 added and the value of the high 19-bit output signal of the decoding sequence is output; at the same time, D 31 …D 19 Receive the output data of the encoder of the previous clock and transmit it to D 31 …D 19 ; XOR gate XOR12…XOR0 converts the encoder output terminal Y 12 ...Y0's decoded data and D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the decoding sequence.

[0046] Through the above technical solutions, it can be seen that compared with the prior art, the present invention discloses a 32-bit parallel self-synchronizing codec, system and method thereof, which uses a simple digital logic circuit to convert serial data into parallel data and adopts a more universal scrambling polynomial X 51 +1 performs scrambling and descrambling processing, and can encode and decode any type of data frame. It has strong universality, helps to reduce the operating frequency of the system, increase the data transmission rate, enhance the security and reliability of data transmission quality during transmission, and improve the degree of system integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0048] Figure 1 The accompanying drawing is a circuit diagram of a 32-bit parallel self-synchronous encoder provided by the present invention;

[0049] Figure 2 The accompanying drawing is a circuit diagram of a 32-bit parallel self-synchronizing decoder provided by the present invention;

[0050] Figure 3 The accompanying drawing is a circuit diagram of a serial self-synchronizing scrambler provided by the present invention;

[0051] Figure 4The accompanying drawing is a circuit diagram of a serial self-synchronizing descrambler provided by the present invention. DETAILED DESCRIPTION

[0052] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0053] The embodiment of the present invention discloses a 32-bit parallel self-synchronous encoder, wherein the input terminal of the parallel self-synchronous encoder is connected to the data signal output terminal, and the output terminal of the parallel self-synchronous encoder outputs a coding sequence, such as Figure 1 As shown, it includes: 32 XOR gates and 51 D flip-flops, the 32 XOR gates and the 51 D flip-flops are sequentially interleaved in series, the 32 XOR gates are represented as XOR0, XOR1, ..., XOR31, and the 51 D flip-flops are represented as D0, D1, ..., D 50 , the data signal output terminals are represented as X0, X1, ...X 31 , the output of the parallel self-synchronous encoder is represented by Y0, Y1, ..., Y 31 ;

[0054] D 18 ...D0 input terminal is connected to the encoder output terminal Y of the previous clock 18 ...Y0 is connected, D 18 ...the output terminals of D0 are connected to D 50 …D 32 The input terminals are connected in sequence, D 50 …D 32 The output terminal and data signal output terminal X 31 …X 13 They are respectively connected to the input terminals of the XOR gates XOR31…XOR13 in sequence;

[0055] D 31 …D 19 The input end is connected to the encoder output end Y of the previous clock 31 …Y 19 Connected, D 31 …D 19 The output terminal and data signal output terminal X 12 …X0 is connected to the input terminals of XOR gates XOR12…XOR0 in sequence respectively;

[0056] The output end of the exclusive OR gate XOR31…XOR0 is the output end of the parallel self-synchronous encoder.

[0057] In order to further implement the above technical solution, D18 …D0 is used to temporarily store the output data of the encoder of the previous clock.

[0058] In this embodiment, during the first encoding, the value stored in the D flip-flop is an initial value, and the initial value is set to all 1s that are the same as the input data bit width.

[0059] In order to further implement the above technical solution, the XOR gates XOR31...XOR13 are used to switch the D flip-flop D 50 ...D 32 The output value and data signal output terminal X 31 …X 13 The data to be encoded is modulo 2 added and the value of the high 19-bit output signal of the encoding sequence is output; the XOR gate XOR12...XOR0 is used to output the data signal to the output terminal X 12 ...X0's data to be encoded is connected to the D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the coding sequence.

[0060] A coding method for a 32-bit parallel self-synchronous encoder, comprising:

[0061] D 18 ...D0 temporarily stores the output data of the encoder of the previous clock and transmits it to D 50 …D 32 ;

[0062] XOR gates XOR31…XOR13 convert the D flip-flop D 50 ...D 32 The output value and data signal output terminal X 31 …X 13 Perform a modulo-2 addition operation on the data to be encoded, and output the value of the high 19-bit output signal of the encoding sequence;

[0063] At the same time, D 31 …D 19 Receive the output data of the encoder of the previous clock and transmit it to D 31 …D 19 ;

[0064] XOR gate XOR12…XOR0 outputs the data signal to the X 12 ...X0's data to be encoded is connected to the D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the coding sequence.

[0065] A 32-bit parallel self-synchronous decoder, wherein the parallel self-synchronous decoder input terminal is connected to the encoder output terminal, and the parallel self-synchronous decoder output terminal outputs a decoding sequence, such as Figure 2 As shown, it includes: 32 XOR gates and 51 D flip-flops, the 32 XOR gates and the 51 D flip-flops are sequentially interleaved in series, the 32 XOR gates are represented as XOR0, XOR1, ..., XOR31, and the 51 D flip-flops are represented as D0, D1, ..., D 50 , the encoder output is represented by Y0, Y1, ...Y 31 The output terminals of the parallel self-synchronous decoder are represented as X0, X1, ..., X 31 ;

[0066] D 18 ...D0 input terminal is connected to the encoder output terminal Y of the previous clock 18 ...Y0 is connected, D 18 ...the output terminals of D0 are connected to D 50 …D 32 The input terminals are connected in sequence, D 50 …D 32 The output terminal and encoder output terminal Y 31 …Y 13 They are respectively connected to the input terminals of the XOR gates XOR31…XOR13 in sequence;

[0067] D 31 …D 19 The input end is connected to the encoder output end Y of the previous clock 31 …Y 19 Connected, D 31 …D 19 The output terminal and encoder output terminal Y 12 …Y0 is connected to the input terminals of XOR gates XOR12…XOR0 in sequence respectively;

[0068] The output terminals of the XOR gates XOR31…XOR0 are the output terminals of the parallel self-synchronizing decoder.

[0069] In order to further implement the above technical solution, D 18 …D0 is used to temporarily store the output data of the encoder of the previous clock.

[0070] In order to further implement the above technical solution, the XOR gates XOR31...XOR13 are used to switch the D flip-flop D 50 ...D 32 The output value of the encoder output Y 31 …Y 13 The data to be decoded is modulo 2 added and the value of the high 19-bit output signal of the decoding sequence is output; the XOR gate XOR12…XOR0 is used to add the encoder output terminal Y 12 ...Y0's decoded data and D flip-flop D 31 …D 19The output value is added modulo 2 to output the value of the lower 13-bit output signal of the decoding sequence.

[0071] In this embodiment, the D flip-flop D 50 ...D 32 The output value and input signal X 31 ...X 13 The value obtained by performing the modulo 2 addition operation is the value of the high 19-bit output signal of the coding sequence, which is also the value of the 19-bit D flip-flop D 31 ...D 13 Input value at the input terminal; input signal X 12 ...X0 and D flip-flop D 31 ...D 19 The output value of the D flip-flop D is obtained by modulo 2 addition to obtain the value of the lower 13-bit output signal of the coding sequence. 12 ...the input value of D0.

[0072] A decoding method for a 32-bit parallel self-synchronizing decoder, comprising:

[0073] D 18 ...D0 temporarily stores the output data of the encoder of the previous clock and transmits it to D 50 …D 32 ;

[0074] XOR gates XOR31…XOR13 convert the D flip-flop D 50 ...D 32 The output value of the encoder output Y 31 …Y 13 Perform modulo 2 addition on the data to be decoded and output the value of the high 19-bit output signal of the decoding sequence;

[0075] At the same time, D 31 …D 19 Receive the output data of the encoder of the previous clock and transmit it to D 31 …D 19 ;

[0076] XOR gate XOR12...XOR0 converts the encoder output Y 12 ...Y0's decoded data and D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the decoding sequence.

[0077] A 32-bit parallel self-synchronous encoding and decoding system, comprising: a parallel self-synchronous encoder and a parallel self-synchronous decoder; the parallel self-synchronous encoder input end is connected to the data signal output end, the parallel self-synchronous encoder output end outputs a coding sequence, the parallel self-synchronous decoder input end is connected to the encoder output end, and the parallel self-synchronous decoder output end outputs a decoding sequence;

[0078] The parallel self-synchronous encoder includes 32 XOR gates and 51 D flip-flops, wherein the 32 XOR gates and the 51 D flip-flops are sequentially interleaved in series, the 32 XOR gates are represented as XOR0, XOR1, ..., XOR31, and the 51 D flip-flops are represented as D0, D1, ..., D 50 , the data signal output terminals are represented as X0, X1, ...X 31 , the output of the parallel self-synchronous encoder is represented by Y0, Y1, ..., Y 31 ;

[0079] D 18 ...D0 are connected to the encoder output terminals Y18...Y0 of the previous clock respectively. 18 ...the output terminals of D0 are connected to D 50 …D 32 The input terminals are connected in sequence, D 50 …D 32 The output terminal and data signal output terminal X 31 …X 13 They are respectively connected to the input terminals of the XOR gates XOR31…XOR13 in sequence;

[0080] D 31 …D 19 The input terminals of the D 31 …D 19 The output terminal and data signal output terminal X 12 …X0 is connected to the input terminals of XOR gates XOR12…XOR0 in sequence respectively;

[0081] The output of the XOR gate XOR31…XOR0 is the output of the parallel self-synchronous encoder;

[0082] A parallel synchronous decoder includes 32 XOR gates and 51 D flip-flops, wherein the 32 XOR gates and the 51 D flip-flops are sequentially interleaved in series, the 32 XOR gates are represented as XOR0, XOR1, ..., XOR31, and the 51 D flip-flops are represented as D0, D1, ..., D 50 , the encoder output is represented by Y0, Y1, ...Y 31 The output terminals of the parallel self-synchronizing decoder are represented as X0, X1, ..., X 31 ;

[0083] D 18 ...D0 input terminal is connected to the encoder output terminal Y of the previous clock 18 ...Y0 is connected, D 18 ...the output terminals of D0 are connected to D 50 …D 32The input terminals are connected in sequence, D 50 …D 32 The output terminal and encoder output terminal Y 31 …Y 13 They are respectively connected to the input terminals of the XOR gates XOR31…XOR13 in sequence;

[0084] D 31 …D 19 The input end is connected to the encoder output end Y of the previous clock 31 …Y 19 Connected, D 31 …D 19 The output terminal and encoder output terminal Y 12 …Y0 is connected to the input terminals of XOR gates XOR12…XOR0 in sequence respectively;

[0085] The output of the XOR gates XOR31…XOR0 is the output of the parallel self-synchronizing decoder;

[0086] D 18 ...D0, used for temporarily storing the output data of the encoder of the previous clock;

[0087] The XOR gates XOR31…XOR13 of the parallel self-synchronous encoder are used to convert the D flip-flop D 50 …D 32 The output value and data signal output terminal X 31 …X 13 The data to be encoded is modulo 2 added and the value of the high 19-bit output signal of the encoding sequence is output; the XOR gate XOR12...XOR0 is used to output the data signal to the output terminal X 12 ...X0's data to be encoded is connected to the D flip-flop D 31 …D 19 Perform modulo 2 addition on the output value and output the value of the lower 13-bit output signal of the coding sequence;

[0088] The XOR gates XOR31…XOR13 of the parallel synchronous decoder are used to convert the D flip-flop D 50 …D 32 The output value of the encoder output Y 31 …Y 13 The data to be decoded is modulo 2 added and the value of the high 19-bit output signal of the decoding sequence is output; the XOR gate XOR12…XOR0 is used to add the encoder output terminal Y 12 ...Y0's decoded data and D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the decoding sequence.

[0089] A 32-bit parallel self-synchronous encoding and decoding method, comprising:

[0090] Encoder D 18 ...D0 temporarily stores the output data of the encoder of the previous clock and transmits it to D 50 …D 32 ; XOR gates XOR31…XOR13 convert the D flip-flop D 50 …D 32 The output value and data signal output terminal X 31 …X 13 The data to be encoded is modulo 2 added and the value of the high 19-bit output signal of the encoding sequence is output; at the same time, D 31 …D 19 Receive the output data of the encoder of the previous clock and transmit it to D 31 …D 19 ; XOR gate XOR12…XOR0 outputs the data signal to the X 12 ...X0's data to be encoded is connected to the D flip-flop D 31 …D 19 Perform modulo 2 addition on the output value and output the value of the lower 13-bit output signal of the coding sequence;

[0091] Decoder D 18 ...D0 temporarily stores the output data of the encoder of the previous clock and transmits it to D 50 …D 32 ; XOR gates XOR31…XOR13 convert the D flip-flop D 50 …D 32 The output value of the encoder output Y 31 …Y 13 The data to be decoded is modulo 2 added and the value of the high 19-bit output signal of the decoding sequence is output; at the same time, D 31 …D 19 Receive the output data of the encoder of the previous clock and transmit it to D 31 …D 19 ; XOR gate XOR12…XOR0 converts the encoder output terminal Y 12 ...Y0's decoded data and D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the decoding sequence.

[0092] like Figure 3 and 4 In this embodiment, the serial self-synchronous scrambling and descrambling device is based on the scrambling polynomial X 51+1 scrambles and descrambles the transmitted data. Each value in the scrambling sequence is the result of a modulo-2 addition operation between the input data to be encoded and the output value of the D flip-flop 51 clocks ago. Each value in the descrambling sequence is the result of a modulo-2 addition operation between the input data to be descrambled and the output value of the D flip-flop 51 clocks ago.

[0093] In this embodiment, the input terminals of the D flip-flops are all connected to the line clock. The self-synchronous scrambler and descrambler generate a scrambling code value (or descrambling code value) under the drive of each line clock clk. Thus, 51 scrambling code values (or descrambling code values) are generated in 51 clock cycles.

[0094] In this embodiment, the output values of the D flip-flop in the serial self-synchronous scrambler and descrambler at different clock cycle times are expressed using a more intuitive mathematical relationship:

[0095] In the first clock cycle, the output value of each D flip-flop can be expressed as:

[0096] D i (t+1)=D i-1 (t), i = 1, 2, ..., 50;

[0097] D i (t+1)=X(t)⊕D 50 (t), i = 0;

[0098] At the 16th clock cycle, the output value of each D flip-flop can be expressed as:

[0099] D i (t+16)=D i-16 (t), i=16, 17,…,50;

[0100] D i (t+16)=X(t+15-i)⊕D i+35 (t), i = 0, 1, ..., 15;

[0101] At the 32nd clock cycle, the output value of each D flip-flop can be expressed as:

[0102] D i (t+32)=D i-32 (t), i=32, 33,...,50;

[0103] D i (t+32)=X(t+31-i)⊕D i+19 (t), i=0, 1,…, 31.

[0104] In this embodiment, the input of the D flip-flop at the current moment is derived from the output of the previous D flip-flop in the previous clock cycle, and the input data is temporarily stored by the D flip-flop.

[0105] In this example, the serial data in the scrambler is converted into parallel data, and 51 D flip-flops and 32 XOR gates are connected in series in descending order. The input data to be encoded is represented by X 31 , X 30 ,…,X0, after being coded by the scrambling code polynomial, the coded output data is expressed as Y 31 , Y 30 ,…,Y0 is used to represent it.

[0106] In this embodiment, 51 D flip-flops and 32 XOR gates in the 32-bit parallel self-synchronous encoder are connected in series in descending order. 50 …D 19 The output signal is the same as the 32-bit input data X 31 ...X0 modulo 2 addition results in a 32-bit parallel encoding sequence; the i-th input signal is combined with the D flip-flop D i+19 The output signal of the D flip-flop D is obtained by modulo 2 operation. i Input value of, where i = 0, 1, 2, …, 31.

[0107] In this example, the components of the decoder are the same as those of the encoder. The input data to be decoded is represented by Y31, Y 30 , ..., Y0, the data obtained after decoding is X 31 , X 30 ,…,X0; 32 D flip-flops D 50 …D 19 The output signal is the same as the 32-bit input data Y 31 ...Y0 modulo 2 addition results in a 32-bit parallel decoding sequence. The main difference between a 32-bit parallel self-synchronous encoder and a decoder is that the generated decoding sequence is different from the encoding sequence generation method. The decoding sequence generation process can be summarized as follows: the i-th input signal is combined with the D flip-flop D i+19 The value obtained by performing a modulo-2 addition operation on the output signal of is used as the output signal value of the i-th bit in the self-synchronous decoding sequence, where i = 0, 1, 2..., 31.

[0108] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0109] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A 32-bit parallel self-synchronous encoder, receiving a data signal to be encoded at a data signal output terminal, characterized in that: include: 32 XOR gates and 51 D flip-flops, 32 XOR gates and 51 D flip-flops are sequentially interleaved in series, 32 XOR gates are represented as XOR0, XOR1, ..., XOR31, 51 D flip-flops are represented as D0, D1, ..., D 50 , the data signal output terminals are represented as X0, X1, ...X 31 , the output of the parallel self-synchronous encoder is represented by Y0, Y1, ..., Y 31 ; D 18 ...The input of D0 is connected to the output of the encoder of the previous clock. 18 ...the output terminals of D0 are connected to D 50 …D 32 The input terminals are connected in sequence, D 50 …D 32 The output terminal and data signal output terminal X 31 …X 13 They are respectively connected to the input terminals of the XOR gates XOR31…XOR13 in sequence; D 31 …D 19 The input ends of the encoder are connected to the output end of the previous clock respectively, D 31 …D 19 The output terminal and data signal output terminal X 12 …X0 are connected to the input terminals of XOR gates XOR12…XOR0 in sequence respectively; The output of the XOR gate XOR31…XOR0 is the output of the parallel self-synchronous encoder; D 18 ...D0 temporarily stores the encoder output data of the previous clock and shifts it to D 50 …D 32 ; XOR gates XOR31…XOR13 convert the D flip-flop D 50 ...D 32 The output value and data signal output terminal X 31 …X 13 Perform a modulo-2 addition operation on the data to be encoded, and output the value of the high 19-bit output signal of the encoding sequence; At the same time, D 31 …D 19 Receive the output data of the encoder of the previous clock and shift it to the exclusive OR gate XOR12...XOR0; XOR gate XOR12…XOR0 outputs the data signal to the X 12 ...X0's data to be encoded is connected to the D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the coding sequence.

2. A coding method for a 32-bit parallel self-synchronous encoder, characterized in that: Using a 32-bit parallel self-synchronous encoder as claimed in claim 1, comprising: D 18 ...D0 temporarily stores the encoder output data of the previous clock and shifts it to D 50 …D 32 ; XOR gates XOR31…XOR13 convert the D flip-flop D 50 ...D 32 The output value and data signal output terminal X 31 …X 13 Perform a modulo-2 addition operation on the data to be encoded, and output the value of the high 19-bit output signal of the encoding sequence; At the same time, D 31 …D 19 Receive the output data of the encoder of the previous clock and shift it to the exclusive OR gate XOR12...XOR0; XOR gate XOR12…XOR0 outputs the data signal to the X 12 ...X0's data to be encoded is connected to the D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the coding sequence.

3. A 32-bit parallel self-synchronizing decoder, receiving a data signal to be decoded outputted from an encoder output terminal, characterized in that: include: 32 XOR gates and 51 D flip-flops, 32 XOR gates and 51 D flip-flops are sequentially interleaved in series, 32 XOR gates are represented as XOR0, XOR1, ..., XOR31, 51 D flip-flops are represented as D0, D1, ..., D 50 , the encoder output is represented by Y0, Y1, ...Y 31 The output terminals of the parallel self-synchronous decoder are represented as X0, X1, ..., X 31 ; D 18 ...The input of D0 is connected to the output of the encoder of the previous clock. 18 ...the output terminals of D0 are connected to D 50 …D 32 The input terminals are connected in sequence, D 50 …D 32 The output terminal and encoder output terminal Y 31 …Y 13 They are respectively connected to the input terminals of the XOR gates XOR31…XOR13 in sequence; D 31 …D 19 The input ends of the encoder are connected to the output end of the previous clock respectively, D 31 …D 19 The output terminal and encoder output terminal Y 12 …Y0 are connected to the input terminals of XOR gates XOR12…XOR0 in sequence respectively; The output of the XOR gate XOR31…XOR0 is the output of the parallel self-synchronizing decoder; D 18 ...D0 temporarily stores the decoded data output from the encoder output of the previous clock and shifts it to D 50 …D 32 ; XOR gates XOR31…XOR13 convert the D flip-flop D 50 ...D 32 The output value of the encoder output Y 31 …Y 13 Perform modulo 2 addition on the data to be decoded and output the value of the high 19-bit output signal of the decoding sequence; At the same time, D 31 …D 19 Receive the output data of the encoder output terminal of the previous clock and shift it to the exclusive OR gate XOR12...XOR0; XOR gate XOR12...XOR0 converts the encoder output Y 12 ...Y0's decoded data and D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the decoding sequence.

4. A decoding method for a 32-bit parallel self-synchronizing decoder, characterized in that: Using a 32-bit parallel self-synchronizing decoder as claimed in claim 3, comprising: D 18 ...D0 temporarily stores the decoded data output from the encoder output of the previous clock and shifts it to D 50 …D 32 ; XOR gates XOR31…XOR13 convert the D flip-flop D 50 ...D 32 The output value of the encoder output Y 31 …Y 13 Perform modulo 2 addition on the data to be decoded and output the value of the high 19-bit output signal of the decoding sequence; At the same time, D 31 …D 19 Receive the output data of the encoder output terminal of the previous clock and shift it to the exclusive OR gate XOR12...XOR0; XOR gate XOR12...XOR0 converts the encoder output Y 12 ...Y0's decoded data and D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the decoding sequence.

5. A 32-bit parallel self-synchronizing encoding and decoding system, characterized in that: include: The parallel self-synchronous encoder according to claim 1 and the parallel self-synchronous decoder according to claim 3; the parallel self-synchronous encoder input terminal is connected to the data signal output terminal, the parallel self-synchronous encoder output terminal outputs the encoding sequence, the parallel self-synchronous decoder input terminal is connected to the encoder output terminal, and the parallel self-synchronous decoder output terminal outputs the decoding sequence; The parallel self-synchronous encoder includes 32 XOR gates and 51 D flip-flops, wherein the 32 XOR gates and the 51 D flip-flops are sequentially interleaved in series, the 32 XOR gates are represented as XOR0, XOR1, ..., XOR31, and the 51 D flip-flops are represented as D0, D1, ..., D 50 , the data signal output terminals are represented as X0, X1, ...X 31 , the output of the parallel self-synchronous encoder is represented by Y0, Y1, ..., Y 31 ; D 18 ...The input of D0 is connected to the output of the encoder of the previous clock. 18 ...the output terminals of D0 are connected to D 50 …D 32 The input terminals are connected in sequence, D 50 …D 32 The output terminal and data signal output terminal X 31 …X 13 They are respectively connected to the input terminals of the XOR gates XOR31…XOR13 in sequence; D 31 …D 19 The input ends of the encoder are connected to the output end of the previous clock respectively, D 31 …D 19 The output terminal and data signal output terminal X 12 …X0 is connected to the input terminals of XOR gates XOR12…XOR0 in sequence respectively; The output of the XOR gate XOR31…XOR0 is the output of the parallel self-synchronous encoder; A parallel self-synchronous decoder includes 32 XOR gates and 51 D flip-flops, wherein the 32 XOR gates and the 51 D flip-flops are sequentially interleaved in series, the 32 XOR gates are represented as XOR0, XOR1, ..., XOR31, and the 51 D flip-flops are represented as D0, D1, ..., D 50 , the encoder output is represented by Y0, Y1, ...Y 31 The output terminals of the parallel self-synchronous decoder are represented as X0, X1, ..., X 31 ; D 18 ...The input of D0 is connected to the output of the encoder of the previous clock. 18 ...the output terminals of D0 are connected to D 50 …D 32 The input terminals are connected in sequence, D 50 …D 32 The output terminal and encoder output terminal Y 31 …Y 13 They are respectively connected to the input terminals of the XOR gates XOR31…XOR13 in sequence; D 31 …D 19 The input ends of the encoder are connected to the output end of the previous clock respectively, D 31 …D 19 The output terminal and encoder output terminal Y 12 …Y0 is connected to the input terminals of XOR gates XOR12…XOR0 in sequence respectively; The output of the XOR gates XOR31…XOR0 is the output of the parallel self-synchronizing decoder; D 18 ...D0, used for temporarily storing the output data of the encoder of the previous clock; The XOR gates XOR31…XOR13 of the parallel self-synchronous encoder are used to convert the D flip-flop D 50 ...D 32 The output value and data signal output terminal X 31 …X 13 The data to be encoded is modulo 2 added and the value of the high 19-bit output signal of the encoding sequence is output; the XOR gate XOR12...XOR0 is used to output the data signal to the output terminal X 12 ...X0's data to be encoded is connected to the D flip-flop D 31 …D 19 Perform modulo 2 addition on the output value and output the value of the lower 13-bit output signal of the coding sequence; The XOR gates XOR31…XOR13 of the parallel synchronous decoder are used to convert the D flip-flop D 50 ...D 32 The output value of the encoder output Y 31 …Y 13 The data to be decoded is modulo 2 added and the value of the high 19-bit output signal of the decoding sequence is output; the XOR gate XOR12…XOR0 is used to add the encoder output terminal Y 12 ...Y0's decoded data and D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the decoding sequence.

6. A 32-bit parallel self-synchronous encoding and decoding method, characterized in that: include: The parallel self-synchronous encoder according to claim 1 receives a data signal to be encoded and outputs an encoding sequence, and the parallel self-synchronous decoder according to claim 3 receives the data to be decoded output by the encoder and outputs a decoding sequence; Parallel self-synchronous encoder D 18 ...D0 temporarily stores the output data of the encoder of the previous clock and transmits it to D 50 …D 32 ; XOR gates XOR31…XOR13 convert the D flip-flop D 50 ...D 32 The output value and data signal output terminal X 31 …X 13 The data to be encoded is modulo 2 added and the value of the high 19-bit output signal of the encoding sequence is output; at the same time, D 31 …D 19 Receive the output data of the encoder of the previous clock and transmit it to D 31 …D 19 ; XOR gate XOR12…XOR0 outputs the data signal to the X 12 ...X0's data to be encoded is connected to the D flip-flop D 31 …D 19 Perform modulo 2 addition on the output value and output the value of the lower 13-bit output signal of the coding sequence; Parallel self-synchronizing decoder D 18 ...D0 temporarily stores the output data of the encoder of the previous clock and transmits it to D 50 …D 32 ; XOR gates XOR31…XOR13 convert the D flip-flop D 50 ...D 32 The output value of the encoder output Y 31 …Y 13 The data to be decoded is modulo 2 added and the value of the high 19-bit output signal of the decoding sequence is output; at the same time, D 31 …D 19 Receive the output data of the encoder of the previous clock and transmit it to the XOR gate XOR12...XOR0; the XOR gate XOR12...XOR0 converts the encoder output terminal Y 12 ...Y0's decoded data and D flip-flop D 31 …D 19 The output value is added modulo 2 to output the value of the lower 13-bit output signal of the decoding sequence.

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