Quantum dot devices

Abstract

A silicon-based quantum device for confining charge carriers is provided. The device comprises: a substrate having a first planar region (137); a silicon layer (32) forming a part of the substrate and comprising a step (33) having an edge (34) and a second planar region (135), wherein the second planar region (135) is substantially parallel to the first planar region (137) and offset from the first planar region (137); a first electrically insulating layer (42) disposed on the silicon layer (32) and covering the step (33); a first metal layer (51) disposed on the first electrically insulating layer (42), covering the step (33), and arranged to be electrically connected so that a first confinement region (10) can be induced, and a charge carrier or multiple charge carriers can be confined at the edge. (34); and a second metal layer (52) arranged to cover a second planar region (135) of the silicon layer, wherein the second metal layer: is electrically isolated from the first metal layer (51); and is arranged to be electrically connected so that a second confinement region (11) can be induced, a charge carrier or multiple charge carriers can be confined in the second confinement region, the second confinement region is only in a second planar region (135) of the silicon layer (32) below the second metal layer (52), and the first confinement region (10) can be coupled to the second confinement region (11); wherein the first confinement region (10) is displaced from the second confinement region (11) in a direction perpendicular to the edge (34). A method of assembling a silicon-based quantum device and a method of using a silicon-based quantum device are also provided.

Description

Technical Field

[0001] The present invention relates to a silicon-based quantum device for quantum computing. Background Art

[0002] The realization of quantum computers requires a large number of qubits. In the near-term intermediate-scale quantum computing or NISQ era, quantum computing processes can use 50-100 qubits.

[0003] A quantum bit or qubit is a quantum parallel to the classical "bit" used in classical computing. A qubit contains information, and quantum computing involves the manipulation and processing of qubits. In order to perform complex computational processes, a large number of qubits are used.

[0004] Qubits can be based on quantum dots, which are quantum confinement structures in which charge carriers such as electrons or holes can be electrostatically confined in three dimensions. The state of the electron (or hole) provides information. There are many ways to provide confinement in three dimensions. For example, a combination of geometry and gating can be used, as in the case of silicon nanowire (SiNW) quantum dots. A voltage can be applied to a narrow strip of conductive material (the "gate") located vertically on top of the insulating SiNW to induce a quantum dot in the corner of the SiNW. The corners of the SiNW provide two-dimensional confinement, and the gate provides the third dimension of confinement.

[0005] Multiple quantum dots can be positioned along a SiNW to create a one-dimensional array of quantum dots. However, this structure is very restrictive.

[0006] The hope is to create a scalable architecture for quantum computing. Summary of the invention

[0007] One aspect of the present invention provides a silicon-based quantum device for confining charge carriers. The device includes a substrate having a first planar region and a silicon layer forming a portion of the substrate. The silicon layer includes a step having an edge and a second planar region, wherein the second planar region is substantially parallel to the first planar region and offset from the first planar region. A first electrically insulating layer is disposed on the silicon layer, covering the step. A first metal layer is disposed on the first electrically insulating layer, covering the step and arranged to be electrically connected so that a first confinement region can be induced, and a charge carrier or multiple charge carriers can be confined in the first confinement region at the edge. A second metal layer covering the second planar region of the silicon layer is provided. The second metal layer is electrically isolated from the first metal layer; and the second metal layer is arranged to be electrically connected so that a second confinement region can be induced, and a charge carrier or multiple charge carriers can be confined in the second confinement region, the second confinement region is only in a second planar region of the silicon layer below the second metal layer, and the first confinement region can be coupled to the second confinement region. The first confinement region is displaced from the second confinement region in a direction perpendicular to the edge.

[0008] Using a silicon-based quantum device as described above, a first confinement region can be induced at the edge by applying a bias potential to the first metal layer. Optionally, the first confinement region can be a quantum dot, and the confined charge carrier or multiple charge carriers can represent quantum information in the form of a quantum bit, or can provide exchange of quantum information in the form of a mediator. The bias potential is usually a fixed voltage and can be used to change the charge carrier occupancy within the device. The charge carrier can be an electron or a hole. The corners of the step and the width of the first metal layer are usually used to confine the charge carriers, and the charging energy of the quantum dot (i.e., the energy required to add or remove a single charge carrier from the point) can be tuned by adjusting the width. A wider first metal layer generally has a lower charging energy. The width is measured along the edge of the step. The positioning of the first metal layer covering the step is advantageous because the corners of the step can provide effective spatial two-dimensional confinement. The induced quantum dots can confine a limited number of charge carriers. Optionally, the first metal layer extends laterally along the edge so that elongated quantum dots can be induced at the edge. Elongated quantum dots may be better suited as mediators of qubit interactions and may therefore be beneficially placed within a device architecture.

[0009] When a bias potential is applied to the second metal layer, the second confinement region can be supported in a second planar region of the silicon layer below the second metal layer. The charge carrier or multiple charge carriers can be confined only in the second planar region of the silicon layer. The second confinement region can be coupled to the first confinement region. Advantageously, this architecture provides good charge stability, and quantum computing processes involving confinement regions are generally more resilient to charge errors. In addition, the second confinement region can facilitate initialization of the first confinement region and allow the population of the first confinement region to be maintained.

[0010] The first confinement region is displaced from the second confinement region in a direction perpendicular to the edge. The first confinement region may be laterally spaced up to 100 nanometers from the second confinement region. The displacement is substantially perpendicular to the edge. However, it will be appreciated that there may be some angular variation in the displacement without loss of functionality. Typically, the displacement of the second confinement region relative to the first confinement region is achieved by providing a displacement between the second metal layer and the first metal layer in a direction perpendicular to the edge. The first metal layer and the second metal layer are arranged to be electrically connected to induce the first confinement region and the second confinement region, respectively, and therefore, the substantially perpendicular nature of the displacement between the first confinement region and the second confinement region also applies to the displacement between the first metal layer and the second metal layer.

[0011] The silicon layer includes a planar region, and the second confinement region is arranged in the planar region of the silicon layer. The first confinement region is preferably closely coupled to the second confinement region. This provides direct coupling between the first confinement region and the second confinement region. The second metal layer is arranged to cover the second planar region of the silicon layer. The second planar region is a substantially flat portion of the silicon layer, and the second metal layer can be arranged to cover only the substantially flat portion of the silicon layer. The substantially flat portion of the silicon layer may have a small deviation due to the natural roughness of the silicon substrate. In this device, the substantially flat portion is typically an unetched portion of the silicon layer. The substantially flat portion of the silicon layer is different from a step portion having an edge. The second confinement region can be, for example, in a two-dimensional planar channel, such as a planar quantum dot structure, an inversion channel, an injection region, or a metal oxide semiconductor field effect transistor (MOSFET).

[0012] The second metal layer can be disposed on the first electrically insulating layer. In one example, the first metal layer and the second metal layer are spatially spaced to provide electrical isolation. This arrangement advantageously reduces the number of steps required to be manufactured because the first metal layer and the second metal layer can be deposited simultaneously. In another example, the second metal layer can be arranged to be in ohmic contact with the silicon layer so that an ohmic region is induced in the silicon layer. The ohmic region provides a second confinement region that can be coupled to the first confinement region.

[0013] In another example, a barrier layer may be used to achieve electrical isolation between the first metal layer and the second metal layer. A second electrically insulating layer disposed on the first metal layer may optionally form an electrical barrier layer, and the second metal layer may be disposed on the electrical barrier layer. Advantageously, the second metal layer does not need to be precisely aligned using the device structure. The second metal layer may optionally overlie the first metal layer, and may also extend to overlie the step without affecting the electrical performance of the device. Preferably, the second metal layer is electrically connected to the silicon layer to support the charge carrier storage portion only in a flat and stable region of the silicon layer. The electric field generated by applying a bias to the second metal layer preferably provides doping only in a stable region of the silicon layer.

[0014] The first confinement region and the second confinement region are coupleable. Optionally, the first confinement region and the second confinement region can be coupled with a tunable coupling strength. The device may further include a first tuning metal layer positioned between the first metal layer and the second metal layer. Preferably, the first tuning metal layer is electrically insulated from the first metal layer and the second metal layer. This can be achieved by arranging a dielectric layer between the first metal layer and the second metal layer and the first tuning metal layer. Optionally, the first tuning metal layer is operable to tune the coupling strength between the first confinement region and the second confinement region. The coupling strength can be tuned by applying a bias potential to the first tuning metal layer. The first tuning metal layer can advantageously provide selective coupling and decoupling between the first metal layer and the second metal layer. The first tuning metal layer can provide dielectric coupling as an alternative to proximity coupling.

[0015] The first tuning metal layer is typically positioned between the first metal layer and the second metal layer. The first tuning metal layer preferably directly contacts the dielectric layer covering the edges of the first metal layer and the second metal layer, and optionally covers one or both of the first metal layer and the second metal layer. The first tuning metal layer is preferably arranged so that tunnel coupling between the first tuning metal layer and the first metal layer and tunnel coupling between the first tuning metal layer and the second metal layer can be adjusted so that the first tuning metal layer provides a tunable coupling between the first metal layer and the second metal layer. The first tuning metal layer can provide electrode-mediator coupling between charge confinement regions by using blocking electrodes.

[0016] The silicon-based quantum device optionally includes multiple first metal layers. For example, the first first metal layer can be arranged to be electrically connected to induce a first first confinement region; and the second first metal layer can be arranged to be electrically connected to induce a second first confinement region. Typically, the first first metal layer and the second first metal layer are electrically spaced from each other. Usually, electrical isolation is achieved by displacement along the edge. Optionally, the first first confinement region and the second second confinement region can be coupled with an adjustable coupling strength. Each of the first first confinement region and the second first confinement region can be a quantum dot for a quantum bit. Adjustment of the coupling strength can advantageously allow adjacent first confinement regions to couple or decouple. Coupled quantum dots can enable dual-qubit interactions between adjacent quantum bits in adjacent first confinement regions.

[0017] A second tuning metal layer may be provided between the first first metal layer and the second first metal layer. Preferably, the second tuning metal layer is electrically isolated from the first first metal layer and the second first metal layer. This may be achieved by providing a dielectric layer between the first first metal layer and the second first metal layer and the second tuning metal layer. The second tuning metal layer is preferably arranged so that the tunnel coupling between the second tuning metal layer and the first first metal layer and the second first metal layer, respectively, may be adjusted so that the second tuning metal layer provides a tunable coupling between the first first metal layer and the second first metal layer. This may be achieved by extending the second tuning metal layer so that it is in direct contact with an edge of a dielectric layer covering the first first metal layer and the second first metal layer. Alternatively, the second tuning metal layer may be positioned to cover one or both of the first first metal layer and the second first metal layer.

[0018] Optionally, the second tuning metal layer is operable to tune the coupling strength between a first first confinement region and a second first confinement region.Selective coupling and decoupling of adjacent first confinement regions advantageously provides flexibility in quantum computing processes that can be implemented using the quantum device.

[0019] Optionally, a plurality of first tuning metal layers and / or second tuning metal layers are arranged between adjacent metal layers. The coupling strength between corresponding adjacent confinement regions can be adjusted accordingly.

[0020] The silicon-based quantum device can be formed by a silicon substrate, or more preferably by a silicon-on-insulator (SOI) substrate. The SOI substrate is a layered silicon-insulator-silicon structure, in which the insulator is typically silicon dioxide or aluminum oxide. The steps in the silicon layer are preferably formed by selectively etching the substrate. Therefore, the silicon layer forms part of the substrate. Although silicon wafers are generally cheaper, the benefit of using an SOI substrate is that the depth of the etched portion is generally more reliable. For example, the etching process can etch silicon more easily than silicon dioxide. Preferably, the etching depth is the full depth of the topmost silicon layer in the SOI substrate. The device may further include a third electrically insulating layer below the silicon layer including the quantum confinement region. The third electrically insulating layer is preferably an insulating layer of the SOI substrate, and therefore the device typically also includes an additional silicon layer below the third electrically insulating layer.

[0021] Typically, the electrical insulating material of the SOI substrate is silicon dioxide or aluminum oxide, and therefore the third electrical insulating layer is preferably formed of silicon dioxide or aluminum oxide. The first electrical insulating layer disposed on the silicon layer and covering the step may be formed of any suitable dielectric material, such as silicon dioxide, aluminum oxide or hafnium oxide. Similarly, the second electrical insulating layer optionally disposed on the first metal layer may be formed of any suitable dielectric material, such as those listed above. The first electrical insulating layer and the second electrical insulating layer may be formed of the same material or different materials.

[0022] The first metal layer and the second metal layer preferably comprise a conductive material. Typically, the conductive material may be polysilicon or a metal such as gold or titanium or tungsten. However, any conductive material, or any combination of conductive materials, may be used. For example, a first portion of the first metal layer that contacts the first electrically insulating layer may be formed of polysilicon, and a second portion of the first metal layer that contacts the first portion may be formed of a metal.

[0023] Typically, the first metal layer and the second metal layer are in electrical contact with the first conductive via and the second conductive via, respectively. The first conductive via and the second conductive via may be formed of any conductive material. Typically, the first conductive via and the second conductive via may include metal, or may include polysilicon. Vias are vertical interconnect channels and typically extend vertically from the substrate. Silicon-based quantum devices suitable for confining charge carriers typically require that a bias voltage be applied to a small area within the device. Although electrical paths can extend parallel to the substrate, these structures are not scalable and do not allow dense two-dimensional arrangements of quantum dots and other quantum confinement regions. Vias provide vertical electrical connections, which advantageously allow the realization of dense two-dimensional architectures.

[0024] Embodiments of the present invention provide suitable building blocks for creating scalable dense two-dimensional architectures. A step in a silicon layer may include at least a first edge and a second edge, the first edge and the second edge generally being at a non-zero angle relative to each other. A first metal layer may overlie the first edge of the step and is preferably arranged to be electrically connected so that an elongated quantum dot may be induced in a first confinement region at the first edge. The device may further include a third metal layer, which may be disposed on the first electrically insulating layer overlapping the second edge of the step and is preferably arranged to be electrically connected so as to induce a quantum dot in the first confinement region at the second edge.

[0025] The first confinement region at the second edge may be adapted to confine qubits, and the first confinement region at the first edge may be adapted to provide an exchange region or mediator point. Optionally, the mediator point provides for the exchange of quantum information between qubits. Preferably, the width of the first metal layer measured along the edge is less than 1 micron, more preferably less than 500 nanometers. The mediator point optionally provides for the exchange of information between a plurality of qubits, and such that the width of the first metal layer is sufficiently small that the exchanged quantum information is retained.

[0026] Preferably, the two-dimensional architecture provides direct coupling between the charge carrier storage and the mediator dots and direct coupling between the mediator dots and the quantum dots. The quantum dots optionally support qubits that can carry quantum information for quantum computing. These qubits are preferably addressable and controllable using the charge carrier storage. Proximity coupling or electrode-mediator coupling can be provided between the storage, the mediator dots and the quantum dots so that each quantum dot can be separated from the storage by no more than one mediator dot. The architecture can be practically scaled up without loss of control over these qubits, particularly initialization or manipulation of the states of these qubits.

[0027] Alternatively, several first confinement regions may be induced in a row at the edge of the silicon layer to produce a one-dimensional array of first confinement regions. The first metal layer may include a plurality of electrodes, wherein each electrode covers a step and is spatially spaced from other electrodes within the first metal layer. A bias may be applied to each electrode so as to induce a first confinement region or quantum dot under a corresponding electrode at the edge of the silicon layer. The width of each electrode may determine the boundaries of the electrostatic confinement. However, a one-dimensional array of quantum dots is restrictive because a portion of the quantum dots will typically be spaced from the charge carrier storage portion, and therefore their state will be difficult to control.

[0028] Preferably, the silicon-based quantum device comprises a two-dimensional array of quantum dots confined in a first confinement region. It is particularly desirable to locate the charge carrier storage portion close to the quantum dots, because quantum dots far from the charge carrier storage portion are more difficult to control. Control may involve, for example, the preparation of an initial qubit state, or the manipulation of a qubit from one state to another. The advantages of the two-dimensional architecture in the present invention are the proximity of the storage portion or the second confinement region to the quantum dots or the first confinement region, and the dense arrangement of the quantum dots.

[0029] In order to provide a scalable two-dimensional architecture, the device preferably further includes a plurality of first metal layers and a plurality of third metal layers. The width of the first metal layer along the edge of the silicon layer is preferably suitable for inducing elongated dots. The width of the third metal layer along the edge of the silicon layer is preferably suitable for inducing quantum dots. Preferably, the plurality of first metal layers induce corresponding elongated quantum dots at the edge of the step of the silicon layer, and the plurality of third metal layers induce corresponding quantum dots at the edge of the step of the silicon layer. Optionally, each first metal layer can be adjacent to two separate third metal layers, so that each mediator dot can be coupled with two quantum dots.

[0030] This device structure can be advantageously used to provide a scalable two-dimensional architecture with good control of quantum bits. The expansion of this architecture can involve, for example, a polygonal step including multiple edges. The step can be formed, for example, by a mixture of long edges and short edges, the first metal layer can be arranged on the long edge, and the third metal layer can be arranged on the short edge. For example, the scalable structure can include multiple stable regions connected by nanowire regions. Optionally, the stable region can include multiple long edges, and the nanowire region can include two short edges separated by a narrow flat region. One or more second metal layers can be arranged to cover a substantially flat portion of the stable region so as to induce a corresponding second confinement region below the stable region. Typically, each of the one or more second metal layers only covers a substantially flat portion of the stable region. For example, each first metal layer can be coupled to a corresponding second confinement region. Optionally, an additional metal layer can be arranged on a substantially flat portion of the stable region to provide a further confinement region. This architecture can be practically expanded without losing control over these quantum bits.

[0031] Other aspects of the invention will now be described. With respect to the remaining features, any features discussed in conjunction with one aspect are equally applicable, and each aspect shares similar advantages. The preferred features of the device can advantageously be incorporated into the assembly method or the method of use, and the preferred features of the assembly method and the method of use can advantageously be incorporated into the device.

[0032] Another aspect of the present invention provides a method for assembling a silicon-based quantum device according to the first aspect. The method includes providing a substrate having a first planar region, and etching the substrate to form a silicon layer, the silicon layer including a step having an edge and a second planar region. The second planar region is substantially parallel to the first planar region and offset from the first planar region. Etching the step produces a portion of the silicon layer. After etching the silicon layer, a first electrically insulating layer is deposited on the silicon layer, covering the step. The method also includes depositing a first metal layer and a second metal layer. The first metal layer is deposited on the first electrically insulating layer, covering the step, and is configured to be electrically connected so that a charge carrier or multiple charge carriers can be confined in a first confinement region at the edge. The second metal layer is deposited on the second planar region of the silicon layer, and is deposited so that the second metal layer is electrically isolated from the first metal layer. The second metal layer is configured to be electrically connected so that a charge carrier or multiple charge carriers can be confined in a second confinement region, which is only in a second planar region below the second metal layer of the silicon layer. The second metal layer is configured to be electrically connected so that the first confinement region can be coupled to the second confinement region.

[0033] The etched silicon layer comprises an edge and a substantially planar area. The second metal layer is preferably deposited to cover the substantially planar area. More preferably, the second metal layer is deposited to cover only over the substantially planar area. Applying a bias to the second metal layer covering the planar area advantageously induces a second confined area in the silicon layer in the form of a planar charge carrier storage portion.

[0034] In one example, the first metal layer and the second metal layer are deposited simultaneously. This advantageously reduces the number of steps required to assemble the silicon-based quantum device. The first metal layer and the second metal layer can be deposited as two laterally spaced metal layers using a mask material. Alternatively, the first metal layer and the second metal layer can be deposited as a joined metal layer and then separated into two electrically isolated metal layers by removing a portion of the joined metal layer.

[0035] In another example, the method further comprises depositing a second electrically insulating layer on the first metal layer. The second metal layer is then preferably deposited on the second electrically insulating layer. The second electrically insulating layer may provide an electrostatic barrier between the first metal layer and the second metal layer to provide electrical isolation.

[0036] Silicon-based quantum devices are preferably assembled using silicon metal-oxide semiconductor or SiMOS fabrication processes.

[0037] Another aspect of the present invention provides a method of using a silicon-based quantum device according to the first aspect. The method includes: applying a first bias potential to a first metal layer to confine a charge carrier or multiple charge carriers in a first confinement region, and applying a second bias potential to a second metal layer to confine a charge carrier or multiple charge carriers in a second confinement region, wherein the second confinement region is only in a second planar region of the silicon layer below the second metal layer. The levels of the first bias potential and the second bias potential are configured so that the first confinement region and the second confinement region are coupled. The coupling can be close or can be tuned by a tuning electrode.

[0038] Typically, the second bias potential is greater than the first bias potential. The first bias potential and the second bias potential may be adjusted to change the charge carrier occupancy of the first confinement region and the second confinement region, respectively. Increasing the second bias potential preferably increases the strength of the coupling between the first confinement region and the second confinement region.

[0039] One aspect of the present invention provides a silicon-based quantum device for confining charge carriers. The device includes a silicon layer, the silicon layer including a step having an edge. A first electrically insulating layer is provided on the silicon layer, covering the step. A first metal layer is provided on the first electrically insulating layer, covering the step, and is arranged to be electrically connected so that a first confinement region can be induced, and a charge carrier or multiple charge carriers can be confined in the first confinement region at the edge. A second metal layer is provided covering a substantially flat portion of the silicon layer. The second metal layer is electrically isolated from the first metal layer, and is arranged to be electrically connected so that a second confinement region can be induced, and a charge carrier or multiple charge carriers can be confined in a second confinement region, the second confinement region is in the silicon layer below the second metal layer, and the first confinement region can be coupled to the second confinement region. The first confinement region is displaced from the second confinement region in a direction perpendicular to the edge.

[0040] When a bias potential is applied to the second metal layer, a second confinement region can be supported in the silicon layer below the second metal layer. The second confinement region can be coupled to the first confinement region. Advantageously, this architecture provides good charge stability, and quantum computing processes involving confinement regions are generally more resilient to charge errors. In addition, the second confinement region can facilitate initialization of the first confinement region and allow the population of the first confinement region to be maintained.

[0041] The silicon layer typically includes a planar region, and a second confinement region may be provided in the planar region. The first confinement region is preferably closely coupled to the second confinement region. This provides direct coupling between the first confinement region and the second confinement region. The second metal layer is provided to cover a substantially flat portion of the silicon layer. The substantially flat portion of the silicon layer may have a small deviation due to the natural roughness of the silicon substrate. In the device, the substantially flat portion is typically an unetched portion of the silicon layer. The substantially flat portion of the silicon layer is different from a step portion having an edge. The second confinement region can be, for example, in a two-dimensional planar channel, such as a planar quantum dot structure, an inversion channel, an implantation region, or a metal oxide semiconductor field effect transistor (MOSFET).

[0042] The silicon-based quantum device can be formed by a silicon substrate, or more preferably by a silicon-on-insulator (SOI) substrate. The SOI substrate is a layered silicon-insulator-silicon structure, in which the insulator is typically silicon dioxide or aluminum oxide. The steps in the silicon layer are preferably formed by selectively etching the substrate. Although silicon wafers are generally cheaper, the benefit of using an SOI substrate is that the depth of the etched portion is generally more reliable. For example, the etching process can etch silicon more easily than silicon dioxide. Preferably, the etching depth is the full depth of the topmost silicon layer in the SOI substrate. The device may further include a third electrically insulating layer below the silicon layer including the quantum confinement region. The third electrically insulating layer is preferably an insulating layer of the SOI substrate, and therefore the device typically also includes an additional silicon layer below the third electrically insulating layer.

[0043] Another aspect of the present invention provides a method for assembling a silicon-based quantum device according to the first aspect. The method includes etching a silicon layer to form a step having an edge. This produces a partial silicon layer. After etching the silicon layer, a first electrically insulating layer is deposited on the silicon layer, covering the step. The method also includes depositing a first metal layer and a second metal layer. The first metal layer is deposited on the first electrically insulating layer, covering the step, and is configured to be electrically connected so that a charge carrier or multiple charge carriers can be confined in a first confinement region at the edge. The second metal layer is deposited on a substantially flat portion of the silicon layer and is deposited so that it is electrically isolated from the first metal layer. The second metal layer is configured to be electrically connected so that a charge carrier or charge carriers can be confined in a second confinement region in the silicon layer below the second metal layer. The second metal layer is configured to be electrically connected so that the first confinement region can be coupled to the second confinement region.

[0044] The etched silicon layer includes an edge and generally includes a generally planar region. The second metal layer is preferably deposited to cover the generally planar region. Applying a bias to the second metal layer overlying the planar region advantageously induces a second confinement region in the silicon layer in the form of a planar charge carrier storage portion.

[0045] Another aspect of the invention provides a method of using a silicon-based quantum device according to the first aspect. The method includes applying a first bias potential to a first metal layer to confine a charge carrier or multiple charge carriers in a first confinement region, and applying a second bias potential to a second metal layer to confine a charge carrier or multiple charge carriers in a second confinement region. The levels of the first bias potential and the second bias potential are configured so that the first confinement region and the second confinement region are coupled. The coupling can be close or can be tuned by a tuning electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which:

[0047] Figure 1 is a top view of a silicon-based quantum device according to a first embodiment of the present invention;

[0048] Figure 2 is a cross-sectional side view of a silicon-based quantum device according to a first embodiment of the present invention;

[0049] Figure 3 is a cross-sectional side view of a silicon-based quantum device according to a second embodiment of the present invention;

[0050] Figure 4 is a cross-sectional side view of a silicon-based quantum device according to a third embodiment of the present invention;

[0051] Figure 5 is a top view of a silicon-based quantum device according to a fourth embodiment of the present invention;

[0052] Figure 6 is a cross-sectional side view of a silicon-based quantum device according to a fourth embodiment of the present invention;

[0053] Figure 7 is a top view of a silicon-based quantum device according to a fifth embodiment of the present invention; and

[0054] Figure 8 is a top view of a silicon-based quantum device according to a sixth embodiment of the present invention. DETAILED DESCRIPTION

[0055] Figure 1 and Figure 2 A silicon-based quantum device according to a first embodiment is schematically shown.The silicon-based quantum device is manufactured using a silicon metal-oxide semiconductor or SiMOS (Silicon Metal-Oxide Semiconductor) manufacturing process. Figure 1 shows a top view, Figure 2 Shown along Figure 1 A sectional side view in the direction A indicated in FIG. Figure 1 A first conductive via 61 and a second conductive via 62 are shown contacting the first metal layer 51 and the second metal layer 52, respectively. In this embodiment, the first conductive via 61 and the second conductive via 62 are formed of a metal such as gold, titanium, tungsten, copper, or aluminum, and the first metal layer 51 and the second metal layer 52 are formed of conductive polysilicon. In alternative embodiments, the first metal layer 51 and the second metal layer 52 and the first conductive via 61 and the second conductive via 62 may be formed of any conductive material.

[0056] The second metal layer 52 is disposed on the thin dielectric layer 42, and the thin dielectric layer 42 covers a portion of the silicon layer 32 ( Figure 23. As shown in FIG. 3 , the portion of silicon layer 32 is substantially flat. The second metal layer 52 does not extend beyond the portion of silicon layer 32. The first metal layer 51 covers the thin dielectric layer 42 and the thick dielectric layer 41. In this embodiment, the first metal layer 51 and the second metal layer 52 are laterally spaced about 10 nanometers apart. In other embodiments, the spacing can be as high as 100 nanometers. The spatial spacing provides electrical isolation between the first metal layer 51 and the second metal layer 52.

[0057] exist Figure 2 3, it can be seen that a first metal layer 51 covering both the thin dielectric layer 42 and the thick dielectric layer 41 is arranged on top of the step 33 formed in the portion of the silicon layer 32. The first metal layer 51 is schematically shown with a corresponding step 50. The first metal layer 51 can be deposited by evaporating a metal substance, which results in a metal layer having a substantially uniform thickness relative to the surface below. Therefore, a significant feature such as the step 33 in the portion of the silicon layer 32 can be reproduced in the layer covering the step 33.

[0058] The portion of the silicon layer 32 comprises a planar region 35 which may extend a few micrometers or even a few millimeters from the step 33. In another embodiment, the planar region ends in another step on which a further metal layer is provided.

[0059] The step 33 at the edge of the portion of the silicon layer 32 is formed by two orthogonal surfaces 35, 36 within the portion of the silicon layer 32. The planar region 35 and the vertical region 36 intersect at the edge 34. The planar region 35 and the vertical region 36 are substantially planar. The planar region 35 and the vertical region 36 are substantially orthogonal. The internal angle between the planar region 35 and the vertical region 36 is between 60 degrees and 135 degrees, preferably between 80 degrees and 100 degrees, and more preferably between 85 degrees and 95 degrees. The angle generally depends on the etching technique used. For example, a smaller internal angle can be achieved using a wet etching process, while a closer to vertical angle can be achieved using a dry etching process. A smaller internal angle advantageously provides greater charge confinement.

[0060] In this embodiment, a silicon-on-insulator (SOI) substrate including a lower silicon layer, an intermediate insulating layer, and an upper silicon layer is used. 2 The thick dielectric layer 41 is formed to be disposed on the lower silicon layer 31, and the thick dielectric layer 41 is the middle insulator layer of the SOI wafer. 2The thickness of the layer is 0.2-3 microns. In alternative embodiments, any suitable insulating material may be selected. A partial silicon layer 32 disposed on the thick dielectric layer 41 is formed by performing a selective etching process on the upper silicon layer of the SOI substrate. The etching process may be performed physically or chemically. The inner angle between the planar region 35 and the vertical region 36 of the partial silicon layer 32 may depend on the etching parameters. In this embodiment, a portion of the upper silicon layer of the SOI wafer is etched to form a step 33. The height of the step 33 is the same as the depth of the upper silicon layer of the SOI wafer, which may be between 20 nanometers and 200 nanometers. A thin dielectric layer 42 is disposed on the portion of the silicon layer 32 covering the step 33. The thin dielectric layer 42 is made of SiO 2 The thin dielectric layer 42 may be formed from any suitable dielectric material and may be deposited by atomic layer deposition.

[0061] The first and second conductive vias 61, 62 or vertical interconnect paths are electrically connected to the first and second metal layers 51, 52, respectively, and can be used to connect the first and second metal layers 51, 52 to source and / or measurement equipment. The source and / or measurement equipment can provide and / or measure electrical data, such as voltage, current, capacitance, resistance, or conductivity. The first and second metal layers 51, 52 are electrically different. In Figure 2 , the first conductive via 61 is shown as contacting the first metal layer 51 at one end of the first metal layer, and the second conductive via 61 is shown as contacting the second metal layer 52 at the center of the second metal layer. In alternative embodiments, the first conductive via 61 and the second conductive via 62 may be positioned at any point on the respective first metal layer 51 and the second metal layer 52. Applying a bias voltage to the conductive vias electrically connected to the metal layers results in a substantially uniform electric field beneath the metal layers.

[0062] The first confinement region 10 and the second confinement region 11 in a silicon-based quantum device are schematically shown. The step 33 at the edge of a portion of the silicon layer 32 has a corner 34, in which the first confinement region 10 can be induced when a bias (i.e., a DC voltage) is applied to the first metal layer 51 through the first conductive via 61. In this embodiment, the first confinement region is a quantum dot. The quantum dot 10 is a quantum confinement structure in which electrons or holes can be electrostatically confined in three dimensions. In this embodiment, two-dimensional confinement is achieved by the edge 34, and the width of the first metal layer 51 provides a third dimensional confinement. The width of the first metal layer 51 measured along the edge 34 is typically between 10 and 2000 nanometers, depending on the desired charging energy and architectural constraints. Figure 1 and 2, the length of the first metal layer 51 measured along the direction A is substantially greater than its width. However, its length does not affect the charge carrier confinement in the quantum dot 10 and can be selected according to the desired device architecture.

[0063] When a bias is applied to the second metal layer 52 through the second conductive via 62, the second confinement region 11 can be supported in the planar region of the partial silicon layer 32. The second confinement region 11 is only in the planar region of the partial silicon layer 32. The second confinement region can be a storage portion for charge carriers, such as an electron storage portion or a hole storage portion. The second metal layer 52 is substantially larger than the first metal layer 51. The size of the second metal layer 52 affects the size of the charge carrier storage portion. The size of the second metal layer 52 is typically selected so that a two-dimensional charge carrier storage portion can be supported below the second metal layer 52. Confinement in one dimension occurs at the interface between the partial silicon layer 32 and the thin dielectric layer 42. A reduction in the width or length of the second metal layer 52 can result in confinement in the second dimension, so that the charge carriers are confined in a quasi-one-dimensional structure in the partial silicon layer 32, and a reduction in the width and length of the second metal layer 52 can result in confinement in all three dimensions, so that the charge carriers are confined in a quasi-zero-dimensional structure, i.e., a quantum dot, in the partial silicon layer 32.

[0064] The storage unit 11 and the quantum dot 10 can be coupled. The tunneling rate can be adjusted by changing the spacing between the first metal layer 51 and the second metal layer 52 and by modifying the applied bias. In another embodiment, the second metal layer is in direct contact with a portion of the silicon layer without an intermediate dielectric layer. This results in an ohmic region below the second metal layer within the portion of the silicon layer. The ohmic region provides a charge carrier storage unit that can be coupled to the quantum dot. In another embodiment, the tuning electrode provides a tunable coupling between the quantum dot and the carrier storage unit. The coupling strength can be tuned by modifying the potential applied to the tuning electrode.

[0065] Figure 3A silicon-based quantum device according to a second embodiment is schematically shown. In this embodiment, a portion of a silicon layer 132 forms a portion of a silicon substrate 131. This is achieved by selectively etching a silicon wafer to form a step 133 having an edge 134. Similar to the first embodiment, a portion of the silicon layer 132 may extend beyond the portion of the device depicted in the figure. The stepped region provides a portion of the silicon layer 132. A first planar region 135 of the portion of the silicon layer 132 is substantially parallel to a second planar region 137 of the substrate 131. The first planar region 135 is in an unetched region of the substrate 131, and the second planar region 137 is in an etched region of the substrate 131. The second planar region 137 is therefore offset from the first planar region 135 and is below the first planar region 135. The step 133 includes a vertical region 136, which is substantially vertical and orthogonal to the first planar region 135 and the second planar region 137. A thin dielectric layer 142 is disposed on top of the portion of the silicon layer 132 and the substrate 131, providing an electrical insulating layer.

[0066] Similar to the first embodiment, the first metal layer 151 and the second metal layer 152 can be used to confine electrons or holes in a confinement region in a portion of the silicon layer 132. Applying a bias voltage to the first metal layer 151 and the second metal layer 152 through conductive vias 161 and 162 generates a coupled confinement region 110 and 111. The first metal layer 151 and the second metal layer 152 are electrically isolated. However, in contrast to the first embodiment in which electrical isolation is achieved by physical spacing, in the second embodiment, the first metal layer 151 and the second metal layer 152 are separated by a blocking dielectric layer 143 that forms an electrically insulating layer. The blocking dielectric layer 143 is made of silicon dioxide (SiO 2 In alternative embodiments, the blocking dielectric layer 143 may be formed of any suitable dielectric material, such as aluminum oxide, hafnium dioxide, or zirconium silicate. The blocking dielectric layer 143 may be formed of the same material as the thin dielectric layer 142 or a different material.

[0067] exist Figure 3 14, the second metal layer 152 is positioned to overlap with the first metal layer 151. The second metal layer 152 is deposited with an approximately uniform thickness, and thus the second metal layer 152 includes a step 153, wherein the second metal layer 152 covers the first metal layer 151. In another embodiment, there is no overlap between the first metal layer 151 and the second metal layer 152. However, due to the insulating properties of the blocking dielectric layer 143, no lateral spacing is required. The second metal layer 152 is arranged to cover a portion of the first planar region 135 of the portion of the silicon layer 132. In another embodiment, the second metal layer 152 may extend so that both the first metal layer and the second metal layer are positioned above the step 134.

[0068] Figure 4A silicon-based quantum device according to a third embodiment is schematically shown. The substrate in this embodiment is similar to the substrate of the second embodiment, including a partial silicon layer 232 that forms a part of a silicon substrate 231. A first metal layer 251 and a second metal layer 252 are disposed on top of a first thin dielectric layer 242, and a first conductive via 261 and a second conductive via 262 are electrically connected to the first metal layer 251 and the second metal layer 252, respectively. The first metal layer 251 covers a step 233 in a portion of the silicon layer 232. When a bias is applied to the first metal layer 251, charges can be confined in a first confinement region 210 at an edge 234. The second metal layer 252 is disposed on a portion of the silicon layer 232. When a bias is applied to the second metal layer 252, charges can be confined in a second confinement region 211.

[0069] The first metal layer 251 and the second metal layer 252 are spatially separated. A second thin dielectric layer 243 is provided so that it covers the first metal layer 251 and the second metal layer 252. In the present embodiment, the tuning metal layer 253 forms a blocking electrode. The tuning metal layer 253 is electrically connected to the via 263 and is arranged to cover both the first metal layer 251 and the second metal layer 252. The tuning metal layer 253 is arranged to be electrically connected to both the first metal layer 251 and the second metal layer 252 but electrically isolated. A bias potential can be applied to the tuning metal layer to control the strength of the coupling between the first confinement region 210 and the second confinement region 211.

[0070] Figure 5 and Figure 6 A silicon-based quantum device according to a fourth embodiment is schematically illustrated. Figure 5 A top view is shown and Figure 6 Shown along Figure 5334, so that the charge can be confined in the first first confinement area 312 and the second first confinement area 310, respectively. The second metal layer 352 is provided on the thin dielectric layer 342 and on a substantially flat portion of the portion of the silicon layer 332. In this embodiment, the second metal layer 352 has substantially the same size as each of the first metal layers 351 and 353. The second metal layer 352 is arranged to be electrically connected so that a charge carrier storage portion (not shown) can be induced in the silicon layer 332 below the second metal layer 352. The first first metal layer 351 and the second first metal layer 353 and the second metal layer 352 are electrically connected to corresponding conductive vias 361, 363, 362. The first first metal layer 351 and the second first metal layer 353 are arranged to be electrically connected so that the first quantum dot 312 and the second quantum dot 310 can be induced in the silicon layer 332 below the first first metal layer 351 and the second first metal layer 353, respectively.

[0071] In this embodiment, the blocking dielectric layer 343 covers the first first metal layer 351 and the second first metal layer 353. For clarity, Figure 5 The blocking dielectric layer is not shown in the figure. The tuning metal layer 354 is arranged on the blocking dielectric layer 343 and is positioned so that it covers both the first first metal layer 351 and the second first metal layer 353. The tuning metal layer is electrically connected to the corresponding conductive via 364. The tuning metal layer 354 is electrically isolated from the first first metal layer 351 and the second first metal layer 353. A bias voltage can be applied to the tuning metal layer 354 to control the strength of the coupling between the first quantum dot 312 and the second quantum dot 310. The first qubit and the second qubit can be supported by the first quantum dot 312 and the second quantum dot 310, respectively. The bias voltage applied to the tuning metal layer 354 can be used to couple the qubits so that a double qubit interaction can be achieved between the first qubit and the second qubit, or can be used to decouple the qubits so that the first qubit and the second qubit can each undergo a single qubit operation.

[0072] Figure 7A top view of a silicon-based quantum device according to a fifth embodiment is schematically shown. The silicon-based quantum device of the above embodiment can be implemented in the fifth embodiment. The fifth embodiment describes an exemplary portion of a possible two-dimensional architecture including a plurality of quantum dots and elongated quantum dots. The elongated quantum dots are referred to as mediator dots. In use, each mediator dot can be directly coupled to a charge carrier storage portion. When the device is in use, each mediator dot can be further coupled to two quantum dots. The architecture provides a dense arrangement of quantum dots while ensuring that each quantum dot is close to the charge carrier storage portion. Each quantum dot can be coupled to the charge carrier storage portion through a mediator dot. Quantum dots can be used to support quantum bits. The quantum bit can be a data quantum bit or an auxiliary quantum bit for carrying quantum information. The mediator dot is used to provide a mechanism for quantum information exchange between quantum bits.

[0073] The silicon layer is selectively etched to form a partial silicon layer (not shown in the top view) having a central body 420 and arms 421, 422, 423, 424 extending radially from the body 420, the arms forming a polygonal step 400 having a long edge 481 and a short edge 482 at the edge of the partial silicon layer. In this embodiment, the central body 420 is generally square and forms a plateau region, and each of the four arms 421 to 424 extends from a corner of the square to form a nanowire region. A thin dielectric layer 404 is disposed on top of the partial silicon layer. For clarity, the Figure 7Only the raised portion of the device is shown in FIG. However, the silicon-based quantum device further includes a substrate (not shown) below a portion of the silicon layer. Two quantum dot metal layers 429, 430, 431, 432, 433, 434, 435, 436 are disposed on each arm 421-424. The quantum dot metal layer 429-436 is a third metal layer that can be configured to induce a corresponding quantum dot. The quantum dot metal layer 429-436 is disposed on two short edges 482 of each arm 421-424. Four mediator dot metal layers 437, 438, 439, 440 are disposed on each edge 425, 426, 427, 428 of the central body 420. The mediator dot metal layer 437-440 is a first metal layer that can be configured to induce a corresponding elongated quantum dot. The mediator dot metal layer 437-440 is disposed on the long edge 481 of the central body 420. Five memory metal layers 441, 442, 443, 444, 445 are disposed on the central body 420. The first memory metal layer 441 is disposed in the center of the central body 420, and each of the second to fifth memory metal layers 442 to 445 is disposed on the central body between the first memory metal layer 441 and the corresponding interposer metal layer 437 to 440. Each metal layer 429-445 is in electrical contact with a corresponding conductive via 449, 450, 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, 461, 462, 463, 464, 465.

[0074] The device is configured so that a bias potential can be applied to each of the conductive vias 449-465. When a bias is applied to the conductive vias 449-465, electrons (or holes) can be trapped in a quantum confinement structure induced under the metal layer 429-445 for confining charge carriers. The size of the metal layer 429-445 and the applied bias are selected so that quantum dots 469, 470, 471, 472, 473, 474, 475, 476 can be induced in a portion of the silicon layer under each quantum dot metal layer 429-436; mediator dots 477, 478, 479, 480 can be induced in a portion of the silicon layer under each mediator dot metal layer 437-440; and a charge carrier storage portion can be induced in a portion of the silicon layer under each storage portion metal layer 441-445.

[0075] The sites of quantum dots 469-476 and the sites of mediator dots 477-480 are schematically shown. The mediator dot metal layer 437-440 is substantially wider than the quantum dot metal layer 429-436, where the width is measured along the edge of the portion of the silicon layer. Each mediator dot 477-480 is an elongated quantum dot that provides a tunable connection between two quantum dots 469-476. For example, the first mediator dot 477 can connect the second quantum dot 470 and the third quantum dot 471. Each mediator dot 477-480 is designed to provide a resonant transfer mechanism for the exchange of quantum information between qubits. To achieve this, the width of the mediator dot metal layer 437-440 is at least less than 1 micron so as to preserve the quantum information during the information exchange process. Although in principle the mediator dot 477-480 can be the same size as the quantum dot 469-476, the mediator dot 477-480 can have an elongated form to space the data qubits to provide a scalable architecture.

[0076] Figure 7 The structure shown provides a dense arrangement of quantum dots while ensuring that each quantum dot is close to the charge carrier storage portion. Each mediator dot is directly coupled to the charge carrier storage portion, and each mediator dot is directly coupled to two quantum dots. In this embodiment, the direct coupling is close. In an alternative embodiment, it can be as shown in FIG. Figure 4 , 5 A tuning metal layer is provided as shown in and 6 to provide coupling of the electrode mediator. This architecture provides several advantages over an architecture that may have a large number of quantum dots between the storage portions. Using the architecture of the fifth embodiment, the qubits are easy to initialize due to the proximity of the storage portions to the quantum dots. In addition, there is good charge stability and the architecture is more resilient to charge errors. In addition, the proximity of each quantum dot to the charge carrier storage portion ensures that the number of quantum dots can be maintained.

[0077] Each quantum dot site 469-476 can be occupied or unoccupied by a quantum bit (such as an electron spin quantum bit). Therefore, if both quantum dot sites are occupied, each arm 421 to 424 can support a dual-dot quantum bit, or if only one is occupied, each arm 421 to 424 can support a single-dot quantum bit.

[0078] Figure 8 Shows Figure 7 Extension of the exemplary two-dimensional architecture shown. Figure 7 The unit shown in can be repeated to enlarge the device so that a series of central bodies 501, 502, 503, 504 or plateau regions are connected by inner arms 521, 522, 523, 524 or nanowire regions. Figure 8, four central bodies 501-504 are depicted. However, the device architecture can be further expanded using additional central bodies attached to outer arms 531, 532, 533, 534, 535, 536, 537, 538. A plurality of edges defined in a portion of the silicon layer form a polygonal step 500.

[0079] It will be appreciated that a quantum dot device is provided that enables a scalable two-dimensional architecture in which quantum dots can be coupled to a charge carrier storage portion to improve resilience to charge errors and enable reliable quantum dot initialization. Due to the characteristics of the quantum device, further advantages arise, such as maintenance of the quantum dot population and good charge stability. In addition, methods for making such a device and methods of using the device are provided.

Claims

1. A silicon-based quantum device for confining charge carriers, the device comprising: a substrate having a first planar region; a silicon layer forming a portion of the substrate and comprising a step having an edge and a second planar region, wherein the second planar region is substantially parallel to and offset from the first planar region; a first electrical insulating layer, wherein the first electrical insulating layer is disposed on the silicon layer and covers the step; a first metal layer disposed on the first electrically insulating layer, covering the step, and arranged to be electrically connected so as to induce a first confinement region when a bias potential is applied to the first metal layer, confining a charge carrier or charge carriers in the first confinement region at the edge; as well as A second metal layer, the second metal layer is arranged to cover a second planar region of the silicon layer, wherein the second metal layer is: being electrically isolated from the first metal layer; as well as being arranged to be electrically connected so that when a bias potential is applied to the second metal layer a second confinement region is induced to confine a charge carrier or charge carriers in the second confinement region, the second confinement region being only in the second planar region of the silicon layer below the second metal layer, and the first confinement region being capable of coupling to the second confinement region; Wherein the first confinement area is displaced from the second confinement area in a direction perpendicular to the edge.

2. The silicon-based quantum device according to claim 1, wherein: The second metal layer is disposed on the first electrically insulating layer.

3. The silicon-based quantum device according to claim 1, wherein: The second metal layer is displaced from the first metal layer in a direction perpendicular to the edge.

4. The silicon-based quantum device according to claim 1, wherein: A second electrically insulating layer is disposed on the first metal layer, and the second metal layer is disposed on the second electrically insulating layer.

5. The silicon-based quantum device according to claim 1, wherein: The first confinement region is capable of coupling to the second confinement region with a tunable coupling strength, and the apparatus further comprises: a first tuning metal layer, the first tuning metal layer being located between the first metal layer and the second metal layer; wherein the first tuning metal layer is electrically insulated from the first metal layer and the second metal layer; and The first tuning metal layer is operable to tune the coupling strength between the first confinement region and the second confinement region.

6. The silicon-based quantum device according to claim 1, further comprising: a first first metal layer arranged to be electrically connected so as to induce a first first confinement region; a second first metal layer, the second first metal layer being electrically isolated from the first first metal layer and arranged to be electrically connected so as to induce a second first confinement region; as well as a second tuning metal layer, the second tuning metal layer being disposed between the first first metal layer and the second first metal layer and being electrically isolated from the first first metal layer and the second first metal layer; wherein the first first confinement region is capable of coupling to the second first confinement region with a tunable coupling strength; as well as The second tuning metal layer is operable to tune the coupling strength between the first first confinement region and the second first confinement region.

7. The silicon-based quantum device according to claim 1, wherein: A third electrically insulating layer is disposed below the silicon layer.

8. The silicon-based quantum device according to claim 1, wherein: The first metal layer and the second metal layer are in electrical contact with the first conductive via and the second conductive via, respectively.

9. The silicon-based quantum device according to claim 1, wherein: The first metal layer extends laterally along the edge so that elongated quantum dots can be induced at the edge in the first confinement region.

10. The silicon-based quantum device according to claim 9, in, The step comprises at least a first edge and a second edge, wherein the first edge and the second edge are at a non-zero angle relative to each other; wherein the first metal layer covers the first edge of the step, and the first metal layer is arranged to be electrically connected so as to be able to induce an elongated quantum dot in a first confinement region at the first edge; and Wherein, the device further comprises: A third metal layer is disposed on the first electrically insulating layer, covers the second edge of the step, and is arranged to be electrically connected so as to be able to induce quantum dots in the first confinement region at the second edge.

11. The silicon-based quantum device according to claim 10, further comprising: a plurality of first metal layers configured to support respective elongated quantum dots at respective edges of the steps in the silicon layer; as well as A plurality of third metal layers are configured to support respective quantum dots at respective edges of the steps in the silicon layer, and wherein each first metal layer is adjacent to two separate third metal layers such that each elongated quantum dot can couple to two quantum dots.

12. A method for assembling the silicon-based quantum device according to claim 1, comprising the following steps: providing a substrate having a first planar region; etching the substrate to form a silicon layer, the silicon layer comprising a step having an edge and a second planar region, wherein the second planar region is substantially parallel to and offset from the first planar region; depositing a first electrical insulating layer on the silicon layer to cover the step; depositing a first metal layer on the first electrically insulating layer, covering the step, wherein the first metal layer is configured to be electrically connected so as to confine a charge carrier or charge carriers in a first confinement region at the edge when a bias potential is applied to the first metal layer; as well as A second metal layer is deposited on the second planar region of the silicon layer, wherein the second metal layer is configured to be electrically isolated from and electrically connected to the first metal layer so that when a bias potential is applied to the second metal layer, a charge carrier or multiple charge carriers are confined in a second confinement region, the second confinement region is only in the second planar region of the silicon layer below the second metal layer, and the first confinement region is capable of coupling to the second confinement region.

13. The method for assembling a silicon-based quantum device according to claim 12, wherein: The steps of depositing the first metal layer and the second metal layer are performed simultaneously.

14. The method of assembling a silicon-based quantum device according to claim 12, further comprising the following steps: A second electrically insulating layer is deposited on the first metal layer; and wherein the second metal layer is disposed on the second electrically insulating layer.

15. A method of using a silicon-based quantum device according to claim 1, comprising the steps of: applying a first bias potential to the first metal layer to confine a charge carrier or charge carriers in a first confinement region; as well as applying a second bias potential to the second metal layer to confine the charge carrier or charge carriers in a second confinement region, wherein the second confinement region is only in a second planar region of the silicon layer below the second metal layer; The first bias potential and the second bias potential are configured to couple the first confinement region and the second confinement region.

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