Improved clocking scheme for receiving data

Abstract

Methods and apparatuses for improving a clock scheme to reduce power consumption are presented. An apparatus includes a host configured to communicate with a memory via a link. The host is further configured to receive a first clock from the memory, receive data from the memory based on the first clock in a first mode of a read operation, generate a second clock, the second clock being generated independent of the first clock, and receive data from the memory based on the second clock in a second mode of the read operation.

Description

[0001] Priority requirements

[0002] This application claims priority to U.S. Patent Application No. 16 / 832855, filed on March 27, 2020, entitled “IMPROVED CLOCKING SCHEME TORECEIVE DATA”, which is incorporated herein in its entirety. Technical Field

[0003] This disclosure generally relates to methods and apparatuses having an improved clock scheme for receiving data, and more specifically, to methods and apparatuses for receiving data from memory using an internal clock generated by a host computer. Background Technology

[0004] Computing devices (such as laptops, mobile phones, etc.) may include one or more processors to perform various functions, such as telephony, wireless data access, and camera / video capabilities. Memory is a crucial component of computing devices. A processor can be coupled to memory to perform these computational functions. For example, a processor can fetch instructions from memory to perform computational functions and / or store temporary data within memory for processing these computational functions. Improvements in memory performance also improve computing devices. Summary of the Invention

[0005] This invention discloses some exemplary features and is not an exclusive or exhaustive description of the subject matter. Additional features and aspects are described and will become clear to those skilled in the art upon reading the following detailed description and examining the accompanying drawings, which form a part thereof.

[0006] An apparatus according to at least one embodiment includes a host configured to communicate with a memory via a link. The host is further configured to: receive a first clock from the memory; receive data from the memory based on the first clock in a first mode of a read operation; generate a second clock, the second clock being generated independently of the first clock; and receive data from the memory based on the second clock in a second mode of a read operation.

[0007] Another apparatus according to at least one embodiment includes a host configured to communicate with a memory via a link. The host is further configured to: receive a clock from the memory at a frequency in a training mode; receive data from the memory based on the clock in a first mode of read operations; disable the memory from generating a clock; and receive data from the memory at the frequency in a second mode where the clock for read operations is disabled.

[0008] A method for reducing power in a system includes: receiving a first clock from a memory by a host; receiving data from the memory by the host and based on the first clock in a first mode of a read operation; generating a second clock by the host, the second clock being generated independently of the first clock; and receiving data from the memory by the host and based on the second clock. Attached Figure Description

[0009] Various aspects of the apparatus and method will now be presented in a detailed description by way of example rather than limitation, with reference to the accompanying drawings, in which:

[0010] Figure 1 The illustration shows an apparatus comprising a host, a memory, and a link coupling the host and the memory, according to certain aspects of this disclosure.

[0011] Figure 2 The illustrations depict certain aspects of this disclosure. Figure 1 The host I / O module is configured to generate and adjust the generation of the internal clock.

[0012] Figure 3 The diagram illustrates the relationship between the enable signal and the clock in the circuit according to this disclosure.

[0013] Figure 4 The illustrations depict certain aspects of this disclosure. Figure 1 Another example is a portion of the host I / O module that is configured to generate an internal clock and adjust the generation of the internal clock.

[0014] Figure 5 The diagram illustrates the communication between a host and a memory according to certain aspects of this disclosure. Figure 1 The operation of the improved clock scheme for the link. Detailed Implementation

[0015] The detailed description that follows, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. The detailed description includes specific details used to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0016] As used herein, the term "coupled to" in various tenses of the verb "couple" can indicate that element A is directly connected to element B or that other elements can be connected between element A and element B (i.e., element A is indirectly connected to element B) to perform certain intended functions. For example, the term "coupled" can mean that element A and element B communicate directly or via other elements or have information transmission.

[0017] In the context of electrical components, the term "coupled to" may also be used herein to refer to the electrical connection of component A and component B (and any components electrically connected between them) using wires, traces, or other conductive materials. In some examples, the term "coupled to" may refer to the transfer of electrical power between component A and component B to operate some intended function. In some examples, the terms "electrically connected" or "directly coupled" may refer to the presence or configuration of current flow between component A and component B. For example, in addition to wires, traces, or other conductive materials and components, component A and component B may also be connected via resistors, transistors, or inductors. Furthermore, for radio frequency functions, component A and component B may be "electrically connected" via capacitors.

[0018] The terms "first," "second," "third," etc., are used for ease of reference and may not have substantial meaning. Similarly, the names of components / modules may be used for ease of reference and may not be limiting. For example, such non-limiting names may include "enabling" circuitry. In some examples, the modules and components presented in this disclosure may be implemented by circuitry. Such circuitry may operate at least partially according to software / firmware instructions.

[0019] The terms “bus system” and / or “signal connection” can specify that the elements coupled thereto can exchange information directly or indirectly between them. In this way, the terms “bus system” and / or “signal connection” can encompass multiple physical connections as well as intermediate levels such as buffers, latches, registers, etc.

[0020] In this disclosure, the memory may be embedded on a semiconductor die together with the processor, or the memory may be a part of the semiconductor die that is separate from the processor. The memory can perform various functions. For example, the memory may be used as a cache, register file, or storage device. The memory can be of various types. For example, the memory may be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash memory, or NOR flash memory, etc.

[0021] As the demand for computing devices to perform more functions at increased speeds grows, so too does the demand for power efficiency. While energy saving may be of particular interest in mobile computing devices, non-mobile devices can also benefit from reduced power consumption to decrease waste heat generation. Therefore, various types of computing devices can benefit from memory systems with reduced power consumption. Thus, solutions for reducing power consumption are desired.

[0022] Methods and apparatus are proposed for receiving data when the data clock is disabled, utilizing an internal, host-generated clock. In some examples, in read mode and / or operation, the host (e.g., including a memory controller) can receive data from the memory via a source-synchronized clock. For example, the host can receive read data and a read clock (e.g., a read data strobe or RDQS) from the memory. The read data can be synchronized with the read clock, allowing the host to receive (e.g., latch, sample, or capture) the read data based on the read clock. However, for low-speed communication, the host may not require a synchronized data clock to receive read data. Therefore, disabling the read clock to further reduce power consumption in low-speed communication would be advantageous.

[0023] This disclosure presents methods and apparatus by way of non-limiting examples of low-power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM). For example, the LPDDR memory operates according to the LPDDR specification issued by the Joint Electronic Equipment Committee (JEDEC). This LPDDR specification may be LPDDR5. Furthermore, in this disclosure, reading data is used as an example of data. In some examples, the term "data" may refer to information provided by the memory to the host.

[0024] Figure 1 The illustration depicts an apparatus 100 comprising a host 110, a memory 150, and a link 190 coupling the host 110 and the memory 150, according to certain aspects of this disclosure. For example, the apparatus 100 may be one of a computing system (e.g., a server, data center, desktop computer), a mobile computing device (e.g., a laptop computer, cellular phone, vehicle, etc.), an Internet of Things (IoT) device, a virtual reality (VR) system, or an augmented reality (AR) system. The host 110 may be configured to communicate with the memory 150 via the link 190 (e.g., read, write, request information, interrupt, etc.). Figure 1 As illustrated, the host includes at least one processor 120 coupled to a memory controller 130 via a bus system 115, and the at least one processor 120 is coupled to a memory 150 via the memory controller 130 and a link 190. The memory may be LPDDR DRAM (e.g., LPDDR5). The host 110, memory 150, and / or link 190 may operate according to the LPDDR (e.g., LPDDR5) specification.

[0025] Host 110 may include at least one processor 120, which is coupled to memory 150 via link 190 to perform computing functions, such as data processing, data communication, graphics display, camera, AR or VR rendering, image processing, etc. For example, memory 150 may store instructions or data for at least one processor 120 to perform the aforementioned computing functions. At least one processor 120 may include a collection of processing logic or one or more central processing units. For example, at least one processor 120 may be a central processing unit (CPU) 122, a graphics processing unit (GPU) 123, or a digital signal processor (DSP) 124 configured to perform computing functions. Figure 1 At least one processor 120 is further illustrated, which is coupled to the memory controller 130 via a bus system 115.

[0026] The memory controller 130 may include a control module 132 and a host I / O module 134. The host I / O module 134 may be configured to output and / or receive signals on link 190. The host I / O module 134 may be referred to as a PHY layer and may be configured to control electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) or receive signals based on the electrical characteristics of signaling on link 190. The control module 132 may be configured to issue commands (e.g., read, write, or select operating mode) to the memory 150 via link 190.

[0027] In some examples, host 110 (e.g., control module 132) can issue read commands to memory 150 via host I / O module 134 and link 190 to implement read mode and / or operation. Furthermore, host 110 (e.g., host I / O module 134) can be configured to receive a data clock (e.g., RDQS) from memory 150 via link 190 for use in read mode and / or operation. For reference, the data clock RDQS may be referred to as a first clock. Host 110 (e.g., memory controller 130) can be further configured to receive read data (e.g., DQ) from memory 150 via link 190 based on the data clock RDQS in a first mode (e.g., a first setting) of read mode and / or operation. The first mode may be, for example, a high-speed mode, and the data clock RDQS can be enabled and utilized for read mode and / or operation. In some examples, high-speed and / or low-speed modes or settings are referenced based on relative rather than absolute operating speeds. In some examples, memory 150 may synchronously (e.g., phase-synchronized and / or frequency-synchronized) output and provide data clock RDQS and read data to allow host I / O module 134 to receive (e.g., latch, sample, or capture) read data based on data clock RDQS (e.g., a first clock).

[0028] The host 110 (e.g., host I / O module 134) can be further configured to adjust the generation of an internal clock (a second clock for reference) based on the data clock RDQS (e.g., a first clock) received by the host 110. For example, the control module 132 can be configured to issue a training command to the memory 150 via the host I / O module 134 and link 190 to implement a training mode and / or operation. In response, the host 110, memory 150, and link 190 can operate the training mode and / or operation. In the training mode and / or operation, the host 110 (e.g., host I / O module 134) can be configured to adjust the generation of the internal clock so that the internal clock is synchronized with the received data clock RDQS in phase and / or frequency. This training can be referred to as read-clock-window training.

[0029] The host 110 (e.g., control module 132) may be further configured to instruct the memory 150 to disable the output of the data clock RDQS to communicate in a read mode and / or a second mode of operation (e.g., a second setting). In some examples, the second mode may correspond to a read mode and / or operation that does not use the data clock RDQS. In some examples, the second mode may be a slow mode or a setting. In response, the memory 150 may output read data without outputting the data clock RDQS. The host 110 (e.g., host I / O module 134) may be further configured not to generate an internal clock based on the received data clock RDQS. For example, the host 110 may be configured to generate an internal clock independently of the received data clock RDQS, and / or the data clock RDQS may not be used as an input in the generation of the internal clock.

[0030] The host 110 (e.g., host I / O module 134) can be further configured to receive read data from the memory 150 based on an internal clock generated independently of the data clock RDQS in read mode and / or a second mode of operation. In some examples, since the internal clock is adjusted to synchronize with the data clock RDQS during training operations, the host (e.g., control module 132) can be configured to receive read data without using the data clock RDQS. For example, the host 110 (e.g., host I / O module 134) can use the internal clock instead of the data clock RDQS to latch, sample, or capture read data from link 190 (in which case the memory 150 can stop outputting the data clock RDQS). In this way, power consumed by outputting and switching the data clock RDQS in link 190 can be saved.

[0031] In some examples, link 190 may be a chip-to-chip or die-to-die link between host 110 and memory 150, where host 110 and memory 150 are on different dies. In some examples, link 190 may be an intra-die link, where host 110 and memory 150 are on the same die. For example, link 190 may include multiple signal lines, including signal lines for transmitting unidirectional signals (e.g., write data clock (WCK), command and address (CA), CA clock (CLK), etc.) from host 110 to memory 150, and signal lines for transmitting bidirectional directional signals (e.g., data or DQ), read data strobe clock (RDQS), etc. For example, CA may include CAS signaling / pin, chip select (CS) signaling / pin, and column address (CA) signaling. Link 190 and signaling between host 110 and memory 150 may be in accordance with JEDEC DRAM specifications (e.g., LPDDR5).

[0032] Figure 1 The diagram illustrates a memory 150, which includes a memory I / O module 160, a memory array 162, a mode register 170, and a command and control module 173, all coupled via a bus system 172. The memory 150 can be configured to communicate with a host 110 via a link 190. For example, the memory 150 can be configured to store write data in the memory array 162 in response to a write command (e.g., a write operation) from the host 110. The write data and write command can be received from the host 110 via link 190. The memory 150 can also be configured to output data stored in the memory array 162 as read data in response to a read command (e.g., a read mode and / or operation) from the host 110. Read data and read commands can be received from the host 110 via link 190. Other communications may include mode register reads and / or writes to adjust the operating mode or conditions of the memory 150 and to provide information about the operating mode or conditions of the host 110 and / or the memory 150.

[0033] To facilitate communication to / from host 110, memory array 162 can be configured to store write data from host 110 via link 190 and memory I / O module 160, and output the stored data to host 110 as read data. Mode register 170, which may include multiple registers, can be configured to store the operating mode and / or conditions of memory 150. Mode register 170 may include RDQS mode register 171. Host 110 (e.g., control module 132) can be configured to instruct memory 150 to disable the output data clock RDQS to communicate in read mode and / or a second operating mode. For example, host 110 can disable the data clock RDQS by accessing (reading or writing) mode register 170 (e.g., RDQS mode register 171) via link 190 and memory I / O module 160. Therefore, memory 150 can output read data without outputting the data clock RDQS (e.g., in read mode and / or the second operating mode) in response to the mode or setting of RDQS mode register 171.

[0034] Command and control module 173 can be configured to receive commands from host 110 via link 190 (e.g., CA) and memory I / O module 160. Commands may include read, write, mode register read / write, etc. Commands may include training mode commands that put memory 150 into training mode and / or operation. Command and control module 173 can be configured to decode various commands provided by host 110 (e.g., memory controller 130) via link 190 and arrange memory 150 to operate according to these commands. For example, command and control module 173 can be configured to decode training commands that put memory 150 into training mode and / or operation. In training mode and / or operation, memory 150 can be configured to output a data clock RDQS at a predetermined frequency (no data output).

[0035] Memory I / O module 160 can be configured to drive and receive signals on link 190. Memory I / O module 160 may be referred to as a PHY layer and can be configured to receive signals based on electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) or signal characteristics based on signaling on link 190. For example, memory I / O module 160 can be configured to capture (e.g., sample) write data (e.g., DQ) from host 110 via link 190 based on a data clock WCK. In some examples, memory I / O module 160 can be configured to output read data (e.g., DQ) to host 110 via link 190 based on a data clock RDQS in read mode and / or a first mode of operation (e.g., high-speed setting or mode). For example, host I / O module 134 can be configured to synchronize read data with data clock RDQS and output data clock RDQS along with the read data. In some examples, based on the setting or mode of the RDQS mode register 171, the memory I / O module 160 can be configured to output read data without outputting the data clock RDQS (e.g., read mode and / or a second mode of operation).

[0036] For a write operation, at least one processor 120 may issue a write request to the memory controller 130 via bus system 115. The memory controller 130 may issue a write (WRITE) command to the memory 150 via CA and CLK of link 190. The write data is provided by the memory controller 130 via DQ of link 190 and timed by the data clock WCK. In response, the memory 150 stores the write data in the memory array 162 addressed by the write (WRITE) command.

[0037] Figure 2 The illustrations depict certain aspects of this disclosure. Figure 1 The host I / O module 134 is configured to generate an internal clock and adjust the generation of the internal clock. Figure 2 The diagram illustrates components of host 110, including clock source 202, internal clock module 210, internal clock control 204, and input circuits 206_1 and 206_2. As illustrated, internal clock module 210 may include calibrated delay circuitry 212, phase detector 214, multiplexer 216, enable circuitry 218, and various signal connections. Input circuits 206_1 and 206_2 may be configured to receive signals from outside host 110 and may include, for example, input buffer / latch circuitry. Input circuitry 206_1 may be configured to receive a data clock RDQS from memory 150 and output an internal version of the received data clock RDQS to signal connection 211. Signal connection 211 may be provided to internal clock module 210.

[0038] In high-speed mode (e.g., read mode and / or the first setting or mode of operation), host 110 can be configured to receive (e.g., capture, sample, or latch) data (e.g., DQ) from memory 150 based on data clock RDQS, in read mode and / or high-speed mode of operation. For example, internal clock module 210 can be configured to provide a clock to input circuit 206_2 via multiplexer 216, signal connection 217, enable circuit 218, and signal connection 219 based on data clock received on signal connection 222, in read mode and / or high-speed mode of operation.

[0039] In read mode and / or low-speed mode of operation (e.g., second mode or setting), jitter on the received data can be relatively negligible or absorbed by timing margins. The internal clock module 210 can be further configured to generate an internal clock (e.g., a second clock) on signal connection 219 independently of the received data clock RDQS in read mode and / or low-speed mode of operation. For example, the data clock RDQS (e.g., a first clock) may not be an input in generating the internal clock (e.g., the second clock). The host 110 can be configured to receive data (e.g., via input circuitry 206_2) from the memory 150 based on the internal clock (e.g., the second clock) on signal connection 219 instead of the first clock. Therefore, in one aspect of this disclosure, the host 110 can be configured to instruct the memory 150 to disable the output of the data clock RDQS (e.g., the first clock) for communication in a low-speed mode (e.g., read mode and / or second setting or mode of operation). In this way, the power consumption used for timing the data clock RDQS on link 190 can be eliminated.

[0040] Clock source 202 can be configured to provide a reference clock to calibrated delay circuit 212 via signal connection 211. Calibrated delay circuit 212 can be configured to adjust the delay / phase / frequency of the reference clock based on control or settings on signal connection 208. Calibrated delay circuit 212 can be further configured to output the calibrated reference clock to signal connection 215 as an input to phase detector 214. Calibrated delay circuit 212 can also be further configured to output the calibrated reference clock to signal connection 215 as an input to multiplexer 216. Control signals on signal connection 208 can be output by internal clock control 204.

[0041] The host 110 can receive a data clock RDQS from the memory 150 via input circuit 206_1. Input circuit 206_1 can be configured to output the received data clock RDQS to signal connection 222 and serve as another input to multiplexer 216. Multiplexer 216 can be configured to select between a calibrated reference clock on signal connection 215 and the received data clock RDQS on signal connection 222 based on a selection signal on signal connection 207, and can be configured to output the selected signal to signal connection 217. Multiplexer 216 can be configured to output the selected signal to phase detector 214 and enable circuit 218 via signal connection 217. The selection signal on signal connection 207 can be output by internal clock control 204.

[0042] Enable circuit 218 can be configured to output a selected signal from signal connection 217 to signal connection 219 as an internal clock, based on an enable signal on signal connection 205. The enable signal on signal connection 205 can be controlled by the internal clock output 204. For example, enable circuit 218 can be configured to enable or disable the output of the internal clock to signal connection 219 based on the enable signal on signal connection 205. In some examples, enable circuit 218 can be configured to output an internal clock (e.g., a second clock) gated by an enable signal. For example, enable circuit 218 may include a gating circuit where the output is gated by the enable signal. In this way, the number of pulses of the internal clock can correspond to the on-duration of the enable signal (e.g., controlled by the on-duration of the enable signal).

[0043] In training mode and / or operation, memory 150 can be configured to allow host 110 to calibrate an internally set frequency when generating an internal clock to receive data (e.g., DQ) from memory 150, outputting a data clock RDQS. For example, host 110 can be configured to adjust the generation of the internal clock based on the data clock RDQS in training mode and / or operation. An example of such training mode and / or operation is presented herein. Internal clock control 204 can be configured to output a selection signal on signal connection 207, such that multiplexer 216 selects the received data clock RDQS on signal connection 222 and outputs it to phase detector 214 on signal connection 217. Phase detector 214 can be configured to detect the phase difference between the received data clock RDQS output by multiplexer 216 and the calibrated reference clock (from calibrated delay circuit 212) on signal connection 215. Phase detector 214 can also be configured to output the phase difference to internal clock control 204 via signal connection 213.

[0044] In response to a phase difference on signal connection 213, internal clock control 204 can be configured to adjust the settings of calibrated delay circuit 212 via signal connection 208. In subsequent loops of training mode and / or operation, calibrated delay circuit 212 can be configured to adjust the reference clock received on signal connection 211 based on the settings on signal connection 208, and output the calibrated reference clock to multiplexer 216 and phase detector 214 (via signal connection 215). In this way, the settings of calibrated delay circuit 212 can be adjusted such that the output calibrated reference clock is in phase and / or frequency synchronized with the received data clock RDQS. This setting can be stored (e.g., by internal clock control 204) to generate an internal clock (e.g., a second clock) via enable circuit 218 in readout mode and / or operation following training mode and / or operation. In this way, host 110 can be configured to synchronize the internal clock (e.g., the second clock) with the data clock RDQS (e.g., the first clock) to adjust the generation of the internal clock.

[0045] In read mode and / or operation, memory 150 can be configured to: in response to a read command from host 110, output the memory stored in memory array 162 (see link 190) via link 190. Figure 1 The host 110 can be configured to receive data from the memory 150 using different clock schemes in different settings or modes of read mode and / or operation. For example, in a high-speed mode (e.g., the first mode or setting), the host 110 can be configured to receive data on the DQ via input circuitry 206_2 based on the data clock RDQS. In a low-speed mode (e.g., the second mode or setting), the host 110 can be configured to receive data on the DQ via input circuitry 206_2 based on an internal clock on signal connection 219.

[0046] In low-speed mode, the internal clock can be generated independently of (e.g., not based on) the data clock RDQS. For example, in low-speed mode, internal clock control 204 can be configured to cause the calibrated delay circuit 212 to output a calibrated reference clock to signal connection 215 via signal connection 208. In low-speed mode, as a result of training mode, the calibrated reference clock can be synchronized with the expected data clock RDQS in phase and / or frequency. Therefore, the calibrated delay circuit 212 can output a version of the internal clock to signal connection 215. Multiplexer 216 can be configured to select the calibrated reference clock on signal connection 215 (and not the received data clock RDQS on signal connection 222) to output to enable circuit 218 when the internal clock is generated on signal connection 219. In some examples, the terms "high-speed" and "low-speed" refer to relative operating or I / O speeds, and are not necessarily defined by absolute speeds.

[0047] In some examples, multiplexer 216 can be configured to select between host 110 receiving data based on data clock RDQS and host 110 receiving data based on an internal clock generated independently of (e.g., not based on) data clock RDQS. For example, in high-speed mode, internal clock control 204 can be configured to place a selection signal on signal connection 207 so that multiplexer 216 selects the receive data clock on signal connection 222. Input circuitry 206_2 can be configured to receive data on DQ based on the selected receive data clock RDQS (e.g., timed by the received data clock RDQS), (via signal connection 219, enable circuitry 218, signal connection 217). In low-speed mode, internal clock control 204 can be configured to place a selection signal on signal connection 207 so that multiplexer 216 selects a calibrated reference clock on signal connection 215. The calibrated delay circuit 212 can be configured to output a calibrated reference clock to signal connection 215 based on the mode provided on signal connection 208.

[0048] The internal clock control 204 can be configured to store settings obtained from previous training modes and / or operations. This setting allows the calibrated reference clock on signal connection 215 (and therefore the internal clock on signal connection 219) to be synchronized with the data clock RDQS in phase and / or frequency. Furthermore, in low-speed mode, the enable circuit 218 can be configured to enable the internal clock to be transmitted to signal connection 219 based on the output of the multiplexer 216 on signal connection 217. In this way, in low-power mode, the internal clock is generated independently of the data clock RDQS (e.g., not based on the data clock RDQS). For example, when the internal clock is generated on signal connection 219 used to receive data on DQ, the data clock RDQS is not an input (e.g., not selected by multiplexer 216).

[0049] As described above, the enable circuit 218 can be configured to enable data reception from the memory 150 in both the read mode and / or the high-speed and low-speed modes of operation, based on an enable signal on the signal connection 205. The internal clock control 204 can be configured to generate an enable signal on the signal connection 205 based on the burst length of the read mode and / or operation (e.g., having an ON period corresponding to that burst length). For example, based on the clock cycle of the data clock RDQS and / or the internal clock, the internal clock control 204 can be configured to enable the enable signal for a period corresponding to the number of burst lengths multiplied by the clock cycle. In this way, burst length control and the enable circuit 218 are used in both the read mode and / or the high-speed and low-speed modes of operation, which reduces the overhead of receiving data using the improved clocking scheme in this disclosure.

[0050] Figure 3 The diagram illustrates an enable signal (e.g., in the circuit aspect according to this disclosure) Figure 2 The relationship between the signal connection 205 and the clock. In training mode and / or operation, the enable signal does not need to be turned on because no data is received. In burst operation of read mode and / or operation, the enable signal is turned on for a period of time corresponding to the burst length of data (e.g., DQ) from memory 150.

[0051] In some examples, reference Figure 1 and Figure 2The device 100 includes a host 110 configured to communicate with a memory 150 via a link 190. The host 110 may be further configured to receive a clock (e.g., a data clock RDQS) from the memory 150 at a frequency in a training mode. In training mode, the host 110 can train the generation of an internal clock in synchronization with the clock at that frequency. The host 110 may be further configured to receive data from the memory 150 based on a clock in a first mode of read operations. For example, in read mode and / or a high-speed mode of operation, the host 110 may receive data on the DQ based on the data clock RDQS.

[0052] The host 110 can be further configured to disable the memory 150 from generating a clock. For example, the host 110 can write to the RDQS mode register 171 (see...). Figure 1 The host 110 can be further configured to receive data from the memory 150 at this frequency in a second mode of read operations where the clock is disabled. For example, in a low-speed mode, the memory 150 can output data at DQ when the data clock RDQS is disabled. The data at DQ can be output at this frequency (e.g., at signal connection 219), and the host 110 trains its internal clock at this frequency. Therefore, in the low-speed mode of read operations where the data clock RDQS is disabled, the host 110 will use its internal clock to receive data at DQ at this frequency.

[0053] Figure 4 The illustrations depict certain aspects of this disclosure. Figure 1 Another example of a portion of the host I / O module 134, which is configured to generate an internal clock and adjust the generation of the internal clock. (See reference...) Figure 2 The reference numerals in the accompanying drawings are reserved for those that perform or have the same or similar functions / structures. Figure 4 In this configuration, clock source 202 can be configured to provide a reference clock to enable circuit 218 via signal connection 411. Enable circuit 218 can be configured to enable the generation of a second clock in low-speed mode or a second mode based on an enable signal on signal connection 205, and to disable the generation of a second clock in read mode and / or high-speed mode or a first mode of operation. For example, in low-speed mode, enable circuit 218 can be configured to provide a reference clock to signal connection 211 and to provide a reference clock to calibrated delay circuit 212.

[0054] The calibrated delay circuit 212 can be configured to output a calibrated reference clock to signal connection 215 based on settings provided on signal connection 208. Based on training mode, internal clock control 204 can be configured to provide settings on signal connection 208 such that the calibrated reference clock on signal connection 215 corresponds to a version of the internal clock. For example, this version of the calibrated reference clock, or the internal clock output by the calibrated delay circuit 212 to signal connection 215, can be synchronized with the phase and / or frequency of the data clock RDQS in low-speed mode. In some examples, the data clock RDQS in low-speed mode may not be output by memory 150 or received by host 110. In high-speed mode, enable circuit 218 can be configured to disable the generation of the internal clock at the input of multiplexer 216 (e.g., on signal connection 215). For example, enable circuit 218 can be configured not to provide a reference clock to signal connection 211 and calibrated delay circuit 212. In this way, the power used to generate the internal clock is saved because the internal clock is not used in read mode and / or high-speed mode of operation.

[0055] Figure 5 The diagram illustrates the communication between host 110 and memory 150 according to certain aspects of this disclosure. Figure 1 The operation of the improved clocking scheme for Link 190. These operations can be achieved, for example, by utilizing... Figure 1 and Figure 2 The structure is presented for execution. At 510, the host receives the first clock from memory. For example, refer to... Figure 1 The host 110 receives the data clock RDQS from the memory 150 via the host I / O module 134. (Reference) Figure 2 The host, including the input circuit 206_1, receives the data clock RDQS from the memory 150 and outputs the received data clock RDQS to the signal connection 222.

[0056] At 520, in read mode and / or the first mode of operation, data from the memory is received by the host based on a first clock. For example, refer to... Figure 2 In read mode and / or high-speed operation mode, the input circuit 206_2 receives data on DQ based on the received data clock RDQS.

[0057] At position 530, a second clock is generated by the host, and this second clock is generated independently of the first clock. For example, refer to... Figure 2In read mode and / or low-speed mode of operation, host 110 generates an internal clock on signal connection 219 without relying on the data clock RDQS. In low-speed mode, internal clock control 204 places a selection signal on signal connection 207 to allow multiplexer 216 to select the calibrated reference clock on signal connection 215. Based on the settings provided on signal connection 208, calibrated delay circuit 212 outputs the calibrated reference clock to signal connection 215.

[0058] Internal clock control 204 stores settings obtained from previous training modes and / or operations. These settings ensure that the calibrated reference clock on signal connection 215 (and therefore, the internal clock on signal connection 219) is synchronized with the data clock RDQS in phase and / or frequency. Furthermore, in low-speed mode, enable circuitry 218 enables the internal clock to reach signal connection 219 based on the output of multiplexer 216 on signal connection 217. In this way, in low-power mode, the internal clock is generated independently of the data clock RDQS. For example, when generating the internal clock on signal connection 219 for receiving data on DQ, the data clock RDQS is not an input (e.g., not selected by multiplexer 216).

[0059] At 540, in the second mode of the read operation, the host receives data from the memory based on a second clock. For example, refer to... Figure 1 The host 110 receives data from the memory 150 on the DQ. (See reference) Figure 2 In read mode and / or low-speed operation mode, the input circuit 206_2 receives data on DQ based on the clock on signal connection 219.

[0060] At 550, the host instructs the memory to disable the first clock output in order to communicate in the second mode of the read operation. For example, refer to... Figure 1 The host 110 instructs the memory 150 to turn off the data clock RDQS by accessing (reading or writing) the mode register 170 (e.g., RDQS mode register 171) via link 190 and memory I / O module 160. Therefore, in response to the mode or setting of the RDQS mode register 171, the memory 150 outputs read data without outputting the data clock RDQS (e.g., in read mode and / or a low-speed mode or a second mode of operation). In this way, power is saved by switching the data clock RDQS.

[0061] At point 560, in training mode, the host adjusts the generation of the second clock based on the first clock. At point 565, in the generation of the second clock, the second clock is synchronized with the first clock. For example, refer to... Figure 2In training mode and / or operation, memory 150 outputs a data clock RDQS to allow host 110 to calibrate internal settings when generating an internal clock to receive data (e.g., DQ) from memory 150. For example, in training mode and / or operation, host 110 adjusts the generation of its internal clock based on the data clock RDQS. Internal clock control 204 outputs a selection signal on signal connection 207, causing multiplexer 216 to select the received data clock RDQS on signal connection 222 and output it to phase detector 214 on signal connection 217. Phase detector 214 detects the phase difference between the received data clock RDQS output by multiplexer 216 and the calibrated reference clock (from calibrated delay circuit 212) on signal connection 215. Phase detector 214 outputs the phase difference to internal clock control 204 via signal connection 213.

[0062] In response to a phase difference on signal connection 213, internal clock control 204 adjusts the settings of calibrated delay circuit 212 via signal connection 208. In subsequent loops of training mode and / or operation, calibrated delay circuit 212 adjusts the reference clock received on signal connection 211 based on the settings on signal connection 208 and outputs the calibrated reference clock to multiplexer 216 and phase detector 214 (via signal connection 215). In this way, the settings of calibrated delay circuit 212 are adjusted such that the output calibrated reference clock is synchronized in phase and / or frequency with the received data clock RDQS. This setting is stored (e.g., by internal clock control 204) to generate an internal clock (e.g., a second clock) via enable circuit 218 in read mode and / or operation following training mode and / or operation. In this way, host 110 synchronizes the internal clock (e.g., the second clock) with the data clock RDQS (e.g., the first clock) to adjust the generation of the internal clock.

[0063] At position 570, the host's multiplexer selects between the host receiving data based on a first clock and the host receiving data based on a second clock generated independently of the first clock. For example, refer to... Figure 2Multiplexer 216 selects between the host 110 receiving data based on the data clock RDQS and the host receiving data based on an internal clock not generated according to the data clock RDQS. For example, in high-speed mode, internal clock control 204 arranges a selection signal on signal connection 207 so that multiplexer 216 selects the received data clock on signal connection 222. Input circuit 206_2 receives data on DQ (via signal connection 219, enable circuit 218, signal connection 217) based on the selected received data clock RDQS (e.g., timed by the received data clock RDQS). In low-speed mode, internal clock control 204 arranges a selection signal on signal connection 207 so that multiplexer 216 selects the calibrated reference clock on signal connection 215. Based on the settings provided on signal connection 208, calibration delay circuit 212 outputs the calibrated reference clock to signal connection 215.

[0064] Internal clock control 204 stores settings obtained from previous training modes and / or operations. These settings ensure that the calibrated reference clock on signal connection 215 (and therefore, the internal clock on signal connection 219) is synchronized with the data clock RDQS in phase and / or frequency. Furthermore, in low-speed mode, enable circuitry 218 enables the internal clock to reach signal connection 219 based on the output of multiplexer 216 on signal connection 217. In this way, in low-power mode, the internal clock is generated independently of the data clock RDQS. For example, when generating the internal clock on signal connection 219 for receiving data on DQ, the data clock RDQS is not an input (e.g., not selected by multiplexer 216).

[0065] At 580, based on the enable signal, the host's enable circuitry enables the generation of a second clock in the second mode and disables the generation of a second clock in the first mode of the read operation. For example, refer to... Figure 4 Clock source 202 provides a reference clock to enable circuit 218 via signal connection 411. Based on the enable signal on signal connection 205, enable circuit 218 enables the generation of a second clock in low-speed mode or second mode, and disables the generation of a second clock in read mode and / or high-speed mode or first mode of operation. For example, in low-speed mode, enable circuit 218 provides a reference clock to signal connection 211 and also provides a reference clock to calibrated delay circuit 212.

[0066] Based on the settings provided on signal connection 208, the calibration delay circuit 212 outputs a calibrated reference clock to signal connection 215. Based on the training mode, the internal clock control 204 provides settings on signal connection 208 such that the calibrated reference clock on signal connection 215 corresponds to a version of the internal clock. For example, this version of the calibrated reference clock or the internal clock output by the calibration delay circuit 212 to signal connection 215 is synchronized with the phase and / or frequency of the data clock RDQS in low-speed mode. In some examples, the data clock RDQS in low-speed mode may not be output by memory 150 or received by host 110. In high-speed mode, the enable circuit 218 disables the generation of the internal clock at the input of multiplexer 216 (e.g., on signal connection 215). For example, the enable circuit 218 provides a reference clock to signal connection 211 and the calibration delay circuit 212. In this way, since the internal clock is not used in read mode and / or high-speed mode of operation, the power used to generate the internal clock is saved.

[0067] The preceding description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but rather to conform to the full scope consistent with the language of the claims, wherein references to elements in the singular form, unless otherwise specifically stated, are not intended to mean “one and only one,” but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects. Unless otherwise specifically stated, the term “some” means one or more. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, and may include multiple A, multiple B, or multiple C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” can be A only, B only, C only, A and B, A and C, B and C, or A and B and C, wherein any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements of the aspects described in this disclosure that are known to or will be known hereafter by those skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be exclusive to the public, whether or not such disclosure is expressly referenced in the claims. Terms such as “module,” “mechanism,” “element,” and “device” may not replace the term “component.” Therefore, no claim element should be construed as a component plus a function unless the element is explicitly stated using the phrase “component for…”.

Claims

1. An apparatus comprising: a host configured to communicate with a memory via a link, the host further configured to: receive a first clock from the memory, synchronously receive data from the memory based on the first clock in a high speed mode of a read operation, generate a second clock, the second clock being generated independent of the first clock and being an internal clock of the host in a low speed mode of the read operation, wherein there is no read clock between the host and the memory in the low speed mode, and synchronously receive data from the memory based on the second clock in the low speed mode of the read operation.

2. The apparatus of claim 1, the host further configured to instruct the memory to disable output of the first clock in the low speed mode of the read operation.

3. The apparatus of claim 2, the host further configured to adjust generation of the second clock based on the first clock in a training operation.

4. The apparatus of claim 3, the host further configured to synchronize the second clock with the first clock to adjust generation of the second clock in the training operation.

5. The apparatus of claim 4, the host further comprising a multiplexer configured to select between receiving data by the host based on the first clock and receiving data by the host based on the second clock being generated independent of the first clock.

6. The apparatus of claim 5, the host further comprising an enable circuit configured to enable generation of the second clock in the low speed mode and disable generation of the second clock in the high speed mode of the read operation based on an enable signal.

7. The apparatus of claim 6, the enable circuit further configured to disable generation of the second clock at an input of the multiplexer in the high speed mode of the read operation.

8. The apparatus of claim 6, the enable signal having an on period corresponding to a burst length of data from the memory.

9. The apparatus of claim 6, further comprising a device selected from one of a computing system, a mobile computing system, an Internet of Things device, a virtual reality system, or an augmented reality system, the device including the memory, the host, and the link.

10. The apparatus of claim 9, the first clock comprising a read data strobe.

11. A method to reduce power in a system comprising: receiving, by a host, a first clock from a memory; synchronously receiving, by the host and based on the first clock, data from the memory in a high speed mode of a read operation; generating, by the host, a second clock, the second clock being generated independent of the first clock and being an internal clock of the host in a low speed mode of the read operation, wherein there is no read clock between the host and the memory in the low speed mode; and In the low speed mode of the read operation, data from the memory is received by the host and in synchronization based on the second clock.

12. The method of claim 11, further comprising: indicating, by the host, the memory to disable output of the first clock in the low speed mode of the read operation.

13. The method of claim 12, further comprising: in a training mode, adjusting, by the host, generation of the second clock based on the first clock.

14. The method of claim 13, the generating the second clock further comprising: in the training operation, synchronizing, by the host, the second clock to the first clock in the generation of the second clock.

15. The method of claim 14, further comprising: selecting, by a multiplexer of the host, between the host receiving data based on the first clock and the host receiving data based on the second clock not generated from the first clock.

16. The method of claim 15, further comprising: enabling, by an enable circuit of the host, generation of the second clock in the low speed mode, and disabling, by the enable circuit, generation of the second clock in the high speed mode of the read operation based on an enable signal.

17. The method of claim 16, the enable circuit disabling generation of the second clock at an input of the multiplexer in the high speed mode of the read operation.

18. The method of claim 16, the enable signal having an on period corresponding to a burst length of data from the memory.

19. The method of claim 16, the first clock comprising a read data strobe.

20. An apparatus comprising: a host configured to communicate with a memory via a link, the host further configured to: in a training mode, receive a clock from the memory at a frequency, in a high speed mode of a read operation, receive data from the memory in synchronization based on the clock, disable the memory from generating the clock, in a low speed mode of the read operation, receive data from the memory in synchronization at the frequency, the clock being disabled in the low speed mode and no read clock between the host and the memory.

21. The apparatus of claim 20, wherein: the host is further configured to: in the low speed mode of the read operation, receive data from the memory in synchronization based on a second clock, the second clock being generated by the memory in the low speed mode of the read operation.

22. The apparatus of claim 21, wherein: the host is further configured to: in the high speed mode of the read operation, receive data from the memory in synchronization based on the second clock, the second clock being generated by the memory in the high speed mode of the read operation.

23. The apparatus of claim 22, wherein: the host is further configured to: in the training mode, adjust generation of the second clock based on the first clock.

24. The apparatus of claim 23, wherein: the host is further configured to: in the training operation, synchronize the second clock to the first clock in the generation of the second clock.

25. The apparatus of claim 24, wherein: the host is further configured to: select, by a multiplexer of the host, between the host receiving data based on the first clock and the host receiving data based on the second clock not generated from the first clock.

26. The apparatus of claim 25, wherein: the host is further configured to: enable, by an enable circuit of the host, generation of the second clock in the low speed mode, and disable, by the enable circuit, generation of the second clock in the high speed mode of the read operation based on an enable signal.

27. The apparatus of claim 26, wherein: the enable circuit disables generation of the second clock at an input of the multiplexer in the high speed mode of the read operation.

28. The apparatus of claim 26, wherein: the enable signal has an on period corresponding to a burst length of data from the memory.

29. The apparatus of claim 26, wherein: the first clock comprises a read data strobe.

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