Superjunction Gated AlGaN GaN HEMT

Abstract

A transistor device includes a source (104) and a drain (105) located at a source and drain horizontal plane at a location along a vertical direction (V). A gate (111) is located at a gate horizontal plane that is higher than the source and drain horizontal plane along the vertical direction. A first region below the source and drain horizontal plane includes a first group III nitride (III-N) layer, a second III-N layer on the first III-N layer. A second region below the gate includes a first III-N layer, a second III-N layer on the first III-N layer, and a third III-N layer on the second III-N layer. The third III-N layer extends through the second III-N layer at a selective location along a width of the transistor and into a portion of the first III-N layer. The third III-N layer is P-type doped, and the first and second III-N layers are unintentionally doped.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more particularly to superjunction gating tri-gate devices that can provide an increased threshold voltage without loss of current. Background Technology

[0002] Given today's advanced technological systems, there is a need to improve power transistors to provide more robust energy delivery networks and efficient power generation and conversion methods. Traditional power transistor applications can include power supplies, electronic applications in many technology industries such as high-voltage direct current (HVDC) electronics, lamp ballasts, telecommunications circuits, and display drivers. These types of technological systems rely on efficient converters to step up or down voltages and use power transistors capable of blocking high voltages and / or carrying high currents.

[0003] Traditional power transistors used in such applications are made of silicon. However, silicon's finite critical electric field and relatively high resistance result in very large and heavy commercially available devices, circuits, and systems that operate at low frequencies. Therefore, such commercial devices are unsuitable for many different types of future applications.

[0004] For example, traditional power semiconductor devices require many characteristics, namely high breakdown voltage and low on-resistance. There is a trade-off between breakdown voltage and on-resistance in power semiconductor devices, determined by the device material. Low on-resistance, approaching the limits of the primary device material (such as silicon), can be achieved in power semiconductor devices. Some traditional power semiconductor devices using wide-gap semiconductors were not designed with the specific characteristics of power devices in mind, namely, electron avalanche withstand capability. This is because GaN-based devices are designed for radio frequency (RF) devices.

[0005] Therefore, given the aforementioned realities and difficulties, the need for devices and circuits to improve the performance of group III nitride semiconductor structures remains unresolved. Summary of the Invention

[0006] This disclosure relates generally to semiconductor devices, and more particularly to superjunction tri-gate devices capable of providing a threshold voltage of more than 3V without loss of on-current.

[0007] Some implementations generally relate to device structures and fabrication methods for constructing electronic devices including transistor devices such as field-effect transistors (FETs). A FET may include a source and a drain such that the source and drain are located at a horizontal plane at a position along a vertical direction. A gate is located along the vertical direction at a horizontal plane higher than the source and drain horizontal planes. A first region is located below the source and drain horizontal planes such that the first region includes a substrate layer, a buffer layer on the substrate layer, a first group III nitride (III-N) layer on the buffer layer, and a second III-N layer on the first III-N layer. The spontaneous polarization charge of the second III-N layer is higher than that of the first III-N layer. A second region is located below the gate such that the second region includes a substrate layer, a buffer layer on the substrate layer, a first III-N layer on the buffer layer, a second III-N layer on the first III-N layer, and a third III-N layer on the second III-N layer. The third III-N layer extends through the second III-N layer and into a portion of the first III-N layer at a selective location along the width of the field-effect transistor. The third III-N layer is P-type doped, and the first and second III-N layers are unintentionally doped.

[0008] During the experiments, high electron mobility transistors (HEMTs) based on AlGaN / GaN heterostructures were tested, revealing them as excellent candidates for high-power, high-voltage, and high-temperature applications. The tested depletion-mode (D-mode) HEMTs exhibited excellent performance, which is positive for digital IC applications and radio frequency integrated circuit (RFIC) or monolithic microwave integrated circuit (MMIC) designs. Meanwhile, the testing of enhancement-mode (E-mode) devices also showed potential for future development. For the tested digital IC applications, a circuit configuration characterized by the integration of D-mode and E-mode HEMTs was achieved using directly coupled FET logic (DCFL).

[0009] Meanwhile, for large-scale IC designs, E-mode devices that do not require a negative voltage power supply were tested, which are believed to significantly reduce circuit design complexity. Further testing was conducted on enhancement-mode devices based on AlGaN / GaN material systems. Thus, enhancement-mode devices and E-mode GaN HEMTs (including tri-gate (FinFET) devices) based on AlGaN / GaN material systems were also tested.

[0010] Some implementations of this disclosure obtained from experiments include testing with E-mode AlGaN GaN HEMTs (particularly in tri-gate (FinFETs)). Among these, the threshold voltage of the experimental tri-gate (FinFET) was found to be between 0.2V and 1.5V, depending on the fin width. It was understood that narrower fin widths provide more E-mode behavior, and vice versa. However, it was later recognized that narrower fin widths reduce the on-current of the transistor device, partly due to a lack of effective channel area.

[0011] Aspects of this disclosure include transistor devices that are superjunction trigate devices, which, as described above, can provide a threshold voltage exceeding 3V without sacrificing conduction current.

[0012] In the transistor device of this disclosure, the region below the gate has p-GaN that surrounds the fins of the AlGaN-GaN interface. Due to the p-GaN, the 2-DEG at the AlGaN-GaN interface is depleted, providing E-mode operation. Some features and characteristics of the transistor device of this disclosure, by way of non-limiting embodiments, include:

[0013] (a) Threshold voltage is higher than that of a tri-gate AlGaN GaN HEMT;

[0014] (b) Better gate control compared to gate-injected transistors;

[0015] (c) Due to the superjunction, the breakdown voltage is higher; and

[0016] (d) For the same active fin width, the proposed device provides higher on-current.

[0017] Practical Applications

[0018] The transistor devices disclosed herein can be used with a wide range of technologies, including, but not limited to, microwaves, millimeter-wave communications, imaging, radar, and radio astronomy. In fact, any application requiring high gain and low noise at high frequencies is possible. Other applications of the transistor devices disclosed herein include many types of devices, from mobile phones and DBS receivers to electronic systems such as radar, and applications in radio astronomy. Other applications of the transistor devices disclosed herein include their use as power switching transistors in voltage converter applications.

[0019] As described above, the transistors of this disclosure offer unique characteristics that are crucial for active components in almost all modern electronic products. The transistors of this disclosure can be fabricated in integrated circuits (ICs) and microchips, along with diodes, resistors, capacitors, and other electronic components to produce complete electronic circuits. The transistors of this disclosure can be manufactured at a lower cost (compared to conventional transistors) and are reliable, properties that highly contribute to their ubiquitous presence. Transistor electromechanical circuits have replaced electromechanical devices used to control electrical appliances and machinery. Using standard microcontrollers and writing computer programs to perform control functions is often easier and cheaper than designing equivalent mechanical systems to control the same functions.

[0020] According to one embodiment of this disclosure, a field-effect transistor includes: a source and a drain, such that the source and the drain are located at a horizontal plane at a position along a vertical direction; and a gate, such that the gate is located at a horizontal plane higher than the source and drain horizontal planes along the vertical direction. A first region is located below the source and drain horizontal planes, wherein the first region includes a first group III nitride (III-N) layer and a second III-N layer on the first III-N layer. A second region is located below the gate, such that the second region includes a first III-N layer, a second III-N layer on the first III-N layer, and a third III-N layer on the second III-N layer. The third III-N layer extends through the second III-N layer and into a portion of the first III-N layer at selective locations along the width of the field-effect transistor. The third III-N layer is P-type doped, and the first III-N layer and the second III-N layer are unintentionally doped.

[0021] According to another embodiment of this disclosure, a transistor includes: a source and a drain, such that the source and the drain are located at a horizontal plane at a position along a vertical direction; and a gate, such that the gate is located at a horizontal plane higher than the horizontal plane of the source and drain along the vertical direction. A first region is located below the horizontal plane of the source and drain, such that the first region includes a substrate layer, a buffer layer on the substrate layer, a first group III nitride (III-N) layer on the buffer layer, and a second III-N layer on the first III-N layer. The spontaneous polarization charge of the second III-N layer is higher than that of the first III-N layer. A second region is located below the gate, such that the second region includes a substrate layer, a buffer layer on the substrate layer, a first III-N layer on the buffer layer, a second III-N layer on the first III-N layer, and a third III-N layer on the second III-N layer. The third III-N layer extends through the second III-N layer and into a portion of the first III-N layer at a selective location along the width of the field-effect transistor. The third III-N layer is P-type doped, and the first III-N layer and the second III-N layer are unintentionally doped.

[0022] According to another embodiment of this disclosure, a transistor includes: a source and a drain, such that the source and the drain are located at a horizontal plane at a position along a vertical direction; a gate, such that the gate is located at a horizontal plane higher than the horizontal plane of the source and drain along the vertical direction, and wherein the gap distance between the gate and the drain is related to the breakdown voltage of the transistor; a first region located below the horizontal plane of the source and drain, such that the first region includes a first group III nitride (III-N) layer and a second III-N layer on the first III-N layer; a second region located below the gate, such that the second region includes a first III-N layer, a second III-N layer on the first III-N layer, and a third III-N layer on the second III-N layer; wherein the third III-N layer extends through the second III-N layer and into a portion of the first III-N layer at a selective location along the width of the field-effect transistor, wherein the third III-N layer is P-type doped, and the first III-N layer and the second III-N layer are unintentionally doped. Attached Figure Description

[0023] Embodiments of this disclosure will be further explained with reference to the accompanying drawings. The drawings shown are not necessarily drawn to scale, but generally focus on illustrating the principles of embodiments of this disclosure.

[0024] [ Figure 1A ]

[0025] Figure 1A A schematic three-dimensional (3D) view of a transistor device according to one embodiment of the present disclosure is shown.

[0026] [ Figure 1B ]

[0027] Figure 1B Schematic illustration Figure 1A The cross-sectional view shows the structure and thickness of the gate stack according to some embodiments of the present disclosure, as well as other structures and thicknesses of the transistor device.

[0028] [ Figure 1C ]

[0029] Figure 1C Schematic illustration Figure 1A The cross-sectional view shows the structure and thickness of the gate stack according to some embodiments of the present disclosure, as well as other structures and thicknesses of the transistor device.

[0030] [ Figure 1D ]

[0031] Figure 1D It shows Figure 1A The cross-sectional view shows the structure and thickness of the gate stack according to some embodiments of the present disclosure, as well as other structures and thicknesses of the transistor device.

[0032] [ Figure 2A ]

[0033] Figure 2A Schematic illustration Figure 1A A cross-sectional view of the gate of a transistor device, showing a second region and a Mg-implanted region below the gate region according to some embodiments of the present disclosure.

[0034] [ Figure 2B ]

[0035] Figure 2B Schematic illustration Figure 1A Another cross-sectional view of the gate of the transistor device shows a second region and a Mg implantation region below the gate region according to some embodiments of the present disclosure, wherein different intervals may be present between selected locations, and along the width direction from location A to location B (see...). Figure 1A ) have different widths.

[0036] [ Figure 2C ]

[0037] Figure 2C Schematic illustration Figure 1AAnother cross-sectional view of the gate of a transistor device, showing selected Mg implantation locations according to some embodiments of the present disclosure below the gate region, which may include locations along the path from location C to location D (see...). Figure 1A The different vertical lengths in the vertical direction of ).

[0038] [ Figure 2D ]

[0039] Figure 2D Schematic illustration Figure 1A Another cross-sectional view of the gate of a transistor device, showing selected Mg implantation locations according to some embodiments of the present disclosure below the gate region, which may be along a path from location A to location B (see...). Figure 1A The width direction of the ) is at different angles ranging from 100 degrees to about 80 degrees.

[0040] [ Figure 3 ]

[0041] Figure 3 This is a block diagram illustrating the fabrication process of a transistor device according to some embodiments of the present disclosure.

[0042] While the foregoing figures illustrate embodiments of the present disclosure, other embodiments are also contemplated, as noted in the discussion. This disclosure presents illustrative embodiments by way of explanation and not limitation. Many other variations and embodiments can be devised by those skilled in the art, which fall within the scope and spirit of the principles of the embodiments of this disclosure. Detailed Implementation

[0043] This disclosure relates generally to semiconductor devices, and more particularly to transistors incorporating an etch-free process.

[0044] Figure 1A This is a schematic illustration of a three-dimensional (3D) view of a transistor device according to one embodiment of the present disclosure. For example, Figure 1A A field-effect transistor 100A is shown, including a source 104 and a drain 105, such that the source 104 and the drain 105 are positioned at a location on a horizontal plane HP along the vertical direction V. S&D The gate 111 is positioned vertically V at the same level as the source and drain horizontally at HP. S&D Higher level HP G At this location, the gate horizontal plane HP G The position of V along the vertical direction is at HP G-S&D (Gate horizontal plane HP) G Subtract source and drain horizontal planes HP S&D The first region is at the source and drain horizontal plane HP. S&DBelow, the first region includes a first group III nitride (III-N) layer and a second III-N layer on the first III-N layer. The field-effect transistor in the first region may also include a substrate layer and a buffer layer on the substrate layer, wherein the first III-N layer is on the buffer layer.

[0045] The second region is located below the gate 111, and includes a first III-N layer, a second III-N layer on the first III-N layer, and a third III-N layer on the second III-N layer. The third III-N layer extends through the second III-N layer and into a portion of the first III-N layer at selective locations along the width of the field-effect transistor. The third III-N layer is P-type doped, and the first and second III-N layers are unintentionally doped. The second region below the gate may include a substrate layer and a buffer layer on the substrate layer, with the first III-N layer located on the buffer layer. The second III-N layer may be Al. x In y Ga 1-x-y N is a matrix such that the values ​​of x and y are between 0 and 1 (0≦x≦1), (0≦y≦1), where the first and third III-N layers are gallium nitride (GaN). Furthermore, the spontaneous polarization charge of the second III-N layer can be higher than that of the first III-N layer. In terms of dimensions, the vertical thickness of the first III-N layer is greater than that of the second III-N layer. Alternatively, the vertical thickness of the first III-N layer can be 10 times greater than that of the second III-N layer, or the vertical thickness of the first III-N layer can be 1000% greater than that of the second III-N layer.

[0046] Still referencing Figure 1A The device extends from its first width end A to its other width end B, representing the width direction W. Further, the distance from the other width end B to position C represents the direction of electron flow. Additionally, the distance from position C to position D represents the vertical direction V of the device. The source 104 includes a ground line 103, and the drain 105 has an applied voltage between the source 104 and drain 105 of the device 100A to read the state of the device 100A connected to the ground line 108. DS 106 is the read voltage, and 108 can be positive or negative relative to ground. DS 107 represents the source-to-drain current from device 100A. DS 107 represents the resistance state of the device at 100A. It can be either a high-resistance state or a low-resistance state, depending on the polarity of the applied voltage.

[0047] Figure 1B , Figure 1C and Figure 1DSchematic illustration Figure 1A The cross-sectional view shows the structure and thickness of the gate stack according to some embodiments of the present disclosure, as well as other structures and thicknesses of the transistor device. Figure 1B The source 104 is shown disposed on a portion of the III-N layer (or AlGaN layer), and Figure 1D The drain 105 is shown on a portion of the III-N layer (or AlGaN layer). Figure 1C The diagram shows that the gate 111 is positioned over the entire III-N layer (or AlGaN layer), such that selective Mg implantation sites 113 convert AlGaN to p-AlGaN and GaN to p-GaN, respectively, and generate holes in the implantation region.

[0048] Figure 2A Schematic illustration Figure 1A A cross-sectional view of the gate of a transistor device, showing a second region and a Mg-implanted region below the gate region according to some embodiments of the present disclosure. For example, Figure 2A The bottom edge B of the GaN layer is shown. GaN and the top edge T of the GaN layer GaN The second region R below gate 211 second Mg is implanted at selected sites 213, followed by annealing. This selective Mg implantation at sites 213 converts AlGaN to p-AlGaN and GaN to p-GaN, respectively, creating holes in the implanted regions. These implanted regions deplete the 2-DEG and provide E-mode operation for the device. The depth of each selected Mg implantation site can extend across the top edge T of the GaN. GaN This extends into the GaN layer. The idea is that each selected Mg implantation site can extend approximately 10% into the GaN layer.

[0049] Figure 2B Schematic illustration Figure 1A Another cross-sectional view of the gate of the transistor device shows a second region and a Mg implantation region below the gate region according to some embodiments of the present disclosure, wherein different intervals may be present between selected locations, and along the width direction from location A to location B (see...). Figure 1A They have different widths. For example, Figure 2B The top edge T of the III-N layer (the second layer on top of the GaN layer) is shown. second and bottom edge B second The second layer (III-N layer) can be aluminum gallium nitride (AlGaN). Furthermore, each selected site in the second region doped with Mg ions can have a certain depth, extending from the top edge T of the III-N layer. second B spanning the bottom edge of layer III-Nsecond The interface extends to the top edge T of the GaN layer. GaN The concept is that the spacing between the selected Mg injection sites can be symmetrical or asymmetrical. The width of the selected Mg injection sites can also be symmetrical or asymmetrical.

[0050] Figure 2C Schematic illustration Figure 1A Another cross-sectional view of the gate of a transistor device, showing selected Mg implantation locations according to some embodiments of the present disclosure below the gate region, which may include locations along the path from location C to location D (see...). Figure 1A Different vertical lengths in the vertical direction. Figure 2A subregion R sub Mg-doped Figure 2A Each selected position 213 has a profile, such that the profile includes Figure 2B The vertical profile lengths L1 and L2 and the profile widths W1 and W2.

[0051] One aspect could be that each contour at the selected location includes Figure 2B The constant profile width (W1 = W2) Figure 2B The variable profile width (W1≠W2), constant vertical profile length (L1=L2), or variable vertical profile length (L1≠L2), or a combination thereof. One aspect can be: the profile forms a pattern, such that the profile... Figure 2B The profile widths W1 and W2 are along the field-effect transistor. Figure 1A First width end A to Figure 1A The direction of the second width end B increases, resulting in higher linearity than a profile with a constant profile width in the direction from the first width end to the second width end of the field-effect transistor. One possible aspect is that each profile is equally spaced along the width of the field-effect transistor, or that each profile is not equally spaced and varies along the width of the field-effect transistor.

[0052] Figure 2D Schematic illustration Figure 1A Another cross-sectional view of the gate of a transistor device, showing selected Mg implantation locations according to some embodiments of the present disclosure below the gate region, which may be along a path from location A to location B (see...). Figure 1A The width direction of the Mg injection can be at different angles ranging from 100 degrees to approximately 80 degrees. The different angles for the selected Mg injection location can be changed based on specific user parameters and the intended application.

[0053] Figure 3 This is a block diagram illustrating the fabrication process of a transistor device according to some embodiments of the present disclosure.

[0054] Step 305 illustrates the fabrication of a transistor starting with the growth of an epitaxial structure. This process begins with a Si / sapphire / SiC / GaN wafer. The wafer size can be 2 / 4 / 6 / 12 inches.

[0055] Step 310 shows that if the wafer is not a GaN wafer, a buffer layer is grown to address the lattice mismatch between the wafer material and the III-N semiconductor.

[0056] Then, step 315 shows the growth of a GaN semiconductor on the buffer layer. The thickness of this layer can range from 450 nm to several micrometers. Ideally, this layer is a thicker GaN layer because a thicker layer helps reduce the defect density in the III-N layer, which in turn helps to achieve optimal device performance. This is the first III-N layer according to some embodiments of the invention.

[0057] Then, step 320 shows the growth of a second III-N layer on top of the first III-N layer. However, the band gap of the III-N layer needs to be higher than that of the GaN layer. Typically, the thickness of the second III-N layer can be from 5 nm to 30 nm. The buffer layer, the first III-N layer, and the second III-N layer can be grown by any growth method using one or a combination of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or remote plasma chemical vapor deposition (RPCVD), pulsed laser deposition (PLD), sputtering, etc. According to some embodiments, the second III-nitride layer can be AlGaN.

[0058] Step 325 illustrates the electron beam lithography technique required to form the Ni hard mask.

[0059] Step 330 illustrates the Ni hard mask formation process. Following electron beam lithography, a 50 nm thick layer of nickel metal is deposited using electron beam evaporation. This is then followed by lift-off to create a fin pattern.

[0060] Step 335 illustrates the etching process. Etching is performed using an ICP-RIE process with BCl3 and Cl2 plasma. The plasma power is adjusted to obtain a vertically anisotropic profile.

[0061] Step 340 illustrates the selective regrowth of the p-GaN layer in the gate region.

[0062] Step 345 illustrates the formation of the source and drain terminals. Photolithography is performed, and a metal layer of 20 nm Ti / 100 nm Al / 25 nm Ni / 50 nm is deposited and then stripped to form metal contacts in the source and drain regions. The contacts are then annealed at a high temperature of N2 to form ohmic contacts.

[0063] Step 350 illustrates the formation of the gate terminal. Photolithography is performed, and a Ni 20nm / Au 80nm metal is deposited and stripped to form a metal contact at the gate region.

[0064] feature

[0065] One embodiment of this disclosure includes a field-effect transistor (FET) comprising: a source and a drain such that the source and drain are located at a horizontal plane at a position along a vertical direction; and a gate such that the gate is located at a horizontal plane higher than the source and drain horizontal planes along the vertical direction. A first region is located below the source and drain horizontal planes, wherein the first region includes a first group III nitride (III-N) layer and a second III-N layer on the first III-N layer. A second region is located below the gate such that the second region includes a first III-N layer, a second III-N layer on the first III-N layer, and a third III-N layer on the second III-N layer. The third III-N layer extends through the second III-N layer and into a portion of the first III-N layer at selective locations along the width of the FET. The third III-N layer is P-type doped, and the first III-N layer and the second III-N layer are unintentionally doped. The following aspects are considered to constitute variations of the above embodiment.

[0066] One aspect may include: the first region comprising: a substrate layer; and a buffer layer on the substrate layer such that the first group III nitride (III-N) layer is located on the buffer layer. The second region below the gate comprises: a substrate layer; and a buffer layer on the substrate layer such that the first group III nitride (III-N) layer is located on the buffer layer.

[0067] On the other hand, it can include: the second III-N layer is Al x In y Ga 1-x-y N is a number such that the values ​​of x and y are between 0 and 1 (0 ≦ x ≦ 1), (0 ≦ y ≦ 1), where the first III-N layer and the third III-N layer are gallium nitride (GaN). Furthermore, in one aspect, the spontaneous polarization charge of the second III-N layer is higher than that of the first III-N layer. Moreover, in another aspect, the vertical thickness of the first III-N layer may be greater than the vertical thickness of the second III-N layer.

[0068] Alternatively, the vertical thickness of the first III-N layer may be 10 times greater than that of the second III-N layer, or the vertical thickness of the first III-N layer may be 1000% greater than that of the second III-N layer.

[0069] One aspect may include: the gap distance between the source and the gate, and the gap distance between the gate and the drain, being either symmetrical or asymmetrical. Another aspect may include: the gap distance between the gate and the drain being related to the breakdown voltage of the field-effect transistor.

[0070] Another aspect is that the third III-N layer, extending at selective locations through the second III-N layer and into a portion of the first III-N layer, has a profile such that the profile has a vertical profile length and a profile width. One aspect may include each profile at the selected location comprising one or a combination of a constant profile width, a variable profile width, a constant vertical profile length, or a variable vertical profile length. Another aspect is that the profiles are patterned such that the profile width increases along a direction from a first width end to a second width end of the field-effect transistor, thereby producing a higher linearity than a profile of the field-effect transistor with a constant profile width. Yet another aspect may be that each profile is equidistant along the width of the field-effect transistor. One envisioned aspect is that each profile is not equidistant and varies along the width of the field-effect transistor. Yet another aspect is that the profiles at the selected locations have a profile width and a vertical profile length such that the profiles are arranged at an angle to the vertical direction in the range of 100 degrees to 80 degrees.

[0071] Another aspect is the accumulation of a two-dimensional electron gas (2-DEG) at the interface between the first III-N layer and the second III-N layer. One aspect of this is that the accumulation of the 2-DEG is depleted by the third III-N layer, thereby generating enhancement-mode (E-mode) operation of the field-effect transistor. Furthermore, another aspect is that both the first III-N layer and the second III-N layer have band gaps, such that the band gap of the second III-N layer is larger than that of the first III-N layer.

[0072] Another aspect could be that the first III-N layer, the second III-N layer, and the third III-N layer are grown using one or a combination of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or remote plasma chemical vapor deposition (RPCVD), and wherein selected sites in the sub-region are doped with Mg ions by Mg ion planting.

[0073] definition

[0074] Based on various aspects of this disclosure and on experimental basis, the following definitions are established, which are not, of course, complete definitions of every phrase or term. The definitions provided are based on knowledge learned from experiments and are offered only as embodiments, and other interpretations, definitions, and other aspects may exist. However, such definitions are provided for at least a basic preview of the proposed phrases or terms, but should "in no way" be applied as prior art, as this is merely knowledge gained from experiments.

[0075] Two layers in direct contact The two layers in direct contact can be understood as an arrangement where there are no other intermediate layers. That is, there is direct physical contact between the two layers.

[0076] Two-dimensional (2D) semiconductor layer A two-dimensional (2D) semiconductor layer refers to a semiconductor layer comprising a two-dimensional material layer. Such materials possess desirable properties in terms of anisotropic mobility, thus allowing for future expansion of transistor performance. For example, in some embodiments, the dimension of the two-dimensional material layer in one direction may be smaller than its dimensions in other orthogonal directions, such that at least one physical property in one direction may differ from that in other orthogonal directions. For example, orientation-related physical properties include band gap, electrical and / or thermal conductivity, density of states, carrier mobility, etc. For example, when the two-dimensional material layer is formed as a sheet in a plane formed by the x and y directions, and its dimension in the orthogonal z direction is sufficiently small compared to its dimensions in the x and y directions, the two-dimensional material layer may have a band gap different from, for example, larger than, the band gap in the x and / or y directions. Furthermore, in some embodiments, the two-dimensional material layer may be a material with a layered structure, wherein the atoms of the two-dimensional material layer may have one type of bonding in the x and y directions and a different type of bonding in the z direction. For example, the atoms of the two-dimensional material layer may be covalently bonded in the x and y directions and weakly bonded in the z direction, for example, by van der Waals forces.

[0077] Gallium nitride (GaN)Gallium nitride (GaN) is a binary III / V direct bandgap semiconductor used in light-emitting diodes (LEDs). This compound is a very hard material with a Wooltz crystal structure. Its wide bandgap of 3.4 eV makes it suitable for optoelectronic, high-power, and high-frequency devices. For example, GaN is a substrate that enables violet (405 nm) laser diodes without the need for nonlinear optical frequency doubling. GaN's low sensitivity to ionizing radiation (like other group III nitrides) makes it a suitable material for satellite solar cell arrays. Space applications can also benefit from its stability in radiative environments. Because GaN transistors can operate at much higher temperatures and voltages than gallium arsenide (GaAs) transistors, they are ideal power amplifiers at microwave frequencies. Furthermore, GaN offers excellent characteristics for terahertz devices.

[0078] GaN's very high breakdown voltage, high electron mobility, and saturation velocity also make it an ideal candidate for high-power and high-temperature microwave applications, as evidenced by its high Johnson quality factor. Potential markets for GaN-based high-power / high-frequency devices include microwave RF power amplifiers (such as those used for high-speed wireless data transmission) and high-voltage switching devices for power grids. A potential mass-market application for GaN-based RF transistors is as microwave sources in microwave ovens, replacing currently used magnetrons. The large band gap means that GaN transistors can maintain performance at temperatures higher than silicon transistors (around 150°C) (around 400°C) because it reduces the heating effect of charge carriers inherent in any semiconductor. An enhancement-mode GaN transistor with only n-channel transistors is designed to replace power MOSFETs in applications where switching speed or power conversion efficiency is critical. These transistors, also known as eGaN FETs, can be constructed by growing a thin layer of GaN on top of a standard silicon wafer. This allows eGaN FETs to maintain a similar cost to silicon power MOSFETs but with the superior electrical performance of GaN. Gallium nitride transistors can be depletion-mode devices, meaning they are on / off when the gate-source voltage is zero.

[0079] Gallium nitride aluminum(AlGaN): AlGaN is a semiconductor material and any alloy of aluminum nitride and gallium nitride. The band gap of AlxGa1-xN can be tuned from 3.4 eV (xAl = 0) to 6.2 eV (xAl = 1). Furthermore, AlGaN can be used to fabricate light-emitting diodes operating in the blue to ultraviolet region, where wavelengths down to 250 nanometers (far ultraviolet) can be achieved. AlGaN can be used in blue semiconductor lasers, detectors for ultraviolet radiation, and AlGaN / GaN high electron mobility transistors. AlGaN can be used with gallium nitride or aluminum nitride to form heterojunctions. AlGaN layers can be grown on gallium nitride, sapphire, or silicon, and sometimes together with additional GaN layers.

[0080] Digital IC Applications The simplest circuit configuration can be achieved by using directly coupled FET logic (DCFL), which features the integration of D-mode and E-mode HEMT.

[0081] RFIC Design RFIC is an abbreviation for Radio Frequency Integrated Circuit. Applications of RFICs include radar and communications, but the term RFIC can be applied to any electronic integrated circuit operating within a frequency range suitable for wireless transmission. RFICs offer the potential cost advantage of transferring as many wireless transceivers as possible to a single technology, which in turn allows for system-on-chip solutions rather than the more common system-in-package (SoC).

[0082] MMIC Design A monolithic microwave integrated circuit, or MMIC, is an integrated circuit (IC) device that operates at microwave frequencies (300 MHz to 300 GHz). These devices perform functions such as microwave mixing, power amplification, low-noise amplification, and high-frequency switching. The inputs and outputs of MMIC devices are often matched to a characteristic impedance of 50 ohms. This makes them easier to use because cascading MMICs does not require an external matching network. Furthermore, most microwave test devices are designed to operate in a 50-ohm environment. MMICs are small in size (from approximately 1 mm). 2 Up to 10mm 2MMICs (Multi-Instrument Microcontrollers) can be mass-produced, making high-frequency devices such as mobile phones possible. Compared to silicon (Si), a traditional IC implementation material, MMICs have two fundamental advantages: device (transistor) speed and a semi-insulating substrate. Both factors contribute to the design of high-frequency circuit functions. However, as transistor feature sizes shrink, the speed of Si-based technologies also increases, making MMICs possible to fabricate using Si technology. The main advantage of Si technology compared to GaAs is its lower manufacturing cost. Silicon wafers have larger diameters (typically 8 to 15 inches, compared to 4 to 8 inches for GaAs) and lower wafer costs, helping to reduce IC costs. Gallium nitride (GaN) is another option for MMICs. Because GaN transistors can operate at much higher temperatures and voltages than GaAs transistors, they are ideal power amplifiers at microwave frequencies.

[0083] High electron mobility transistor (HEMT) Also known as a heterojunction FET (HFET) or modulation-doped FET (MODFET), it is a field-effect transistor that uses a junction between two materials with different band gaps (i.e., a heterojunction) as the channel instead of the doped region (as is typically in MOSFETs). The material combination can be GaAs or AlGaAs, but varies greatly depending on the application. Devices containing more indium generally exhibit better high-frequency performance, while gallium nitride (GaN) HEMTs offer high power performance. Like other FETs, HEMTs are used as digital on / off switches in integrated circuits. FETs can also be used as high-current amplifiers using small voltages as control signals. The unique current-voltage characteristics of field-effect transistors enable both applications. HEMT transistors can operate at higher frequencies than ordinary transistors (up to millimeter-wave frequencies) and are used in high-frequency products such as mobile phones, satellite TV receivers, voltage converters, and radar equipment. They are used in satellite receivers, low-power amplifiers, and the defense industry. Some advantages of HEMTs include: high gain, which allows them to be used as amplifiers; high switching speed, achieved because the majority carriers in MODFETs are dominant, while minority carriers are not significantly involved; and extremely low noise levels, due to the lower current variation in these devices compared to other FETs. HEMTs are heterojunctions. This means that the semiconductors used have different band gaps. For example, silicon has a band gap of 1.1 electron volts (eV), while germanium has a band gap of 0.67 eV. When forming a heterojunction, the conduction band and valence band of the entire material must be bent to form continuous energy levels.

[0084] The unique carrier mobility and switching speed of HEMTs arise from the following conditions: the broadband element is doped with donor atoms; therefore, it has excess electrons in its conduction band. Due to the availability of lower-energy states, these electrons diffuse into the conduction band of the adjacent narrow-bandgap material. The movement of electrons causes a change in potential, thus creating an electric field between the materials. The electric field pushes the electrons back into the conduction band of the broadband element. The diffusion process continues until electron diffusion and electron drift balance each other, creating an equilibrium junction similar to a pn junction. Note that the undoped narrow-bandgap material now has excess majority charge carriers. The fact that charge carriers are majority carriers results in high switching speeds, while the fact that the low-bandgap semiconductor is undoped means there are no donor atoms causing scattering, resulting in high mobility.

[0085] A key aspect of HEMTs is the ability to modify the band discontinuities across the conduction and valence bands independently. This allows control over the types of charge carriers entering and leaving the device. Since HEMTs require electrons as the primary charge carriers, hierarchical doping can be applied to one of the materials, reducing the conduction band discontinuity while keeping the valence band discontinuity unchanged. This carrier diffusion leads to the accumulation of electrons at the boundary between two regions within the narrow bandgap material. This accumulation results in very large currents in these devices. The accumulated electrons are also known as a 2DEG or two-dimensional electron gas. The term "modulation doping" refers to the dopant being spatially located in a region different from the charge carriers.

[0086] To allow conduction, semiconductors are doped with impurities that provide mobile electrons or holes. However, these electrons are slowed down by collisions with the impurities (dopants) initially used to generate them. HEMT avoids this by utilizing the high-mobility electrons generated by a heterojunction of a highly doped, wide-bandgap n-type donor-supply layer (AlGaAs in this embodiment) and an undoped, narrow-bandgap channel layer without dopant impurities (GaAs in this example). Electrons generated in the thin n-type AlGaAs layer fall entirely into the GaAs layer, forming a depleted AlGaAs layer, because the heterojunction created by the different bandgap materials forms quantum wells (steep valleys) in the conduction band on the GaAs side. Since the GaAs layer is undoped, electrons can move rapidly on the GaAs side without colliding with any impurities and cannot escape from it. The effect is the creation of a very thin layer of highly mobile conductive electrons (with a very high concentration), resulting in a channel with very low resistivity (or, in other words, "high electron mobility"). Furthermore, HEMTs based on AlGaN / GaN heterostructures provide an excellent candidate for high-power, high-voltage, and high-temperature applications.

[0087] D-mode HEMTIn field-effect transistors (FETs), depletion mode and enhancement mode are two main transistor types, corresponding to the transistor being in a conducting or off state when the gate-source voltage is zero. Enhancement-mode MOSFETs (metal-oxide-semiconductor field-effect transistors) are common switching elements in most integrated circuits. These devices are off when the gate-source voltage is zero. NMOS can be turned on by pulling the gate voltage above the source voltage, and PMOS can be turned on by pulling the gate voltage below the source voltage. In most circuits, this means that pulling the gate voltage of an enhancement-mode MOSFET towards its drain voltage will turn it on. In depletion-mode MOSFETs, the device is typically turned on when the gate-source voltage is zero. This device is used as a load "resistor" in logic circuits (e.g., in depletion-load NMOS logic). For N-type depletion-load devices, the threshold voltage may be around -3V, so it can be turned off by pulling the gate to -3V (in contrast, the drain is more positive than the source in NMOS). In PMOS, the polarity is reversed. The mode can be determined by the sign of the threshold voltage (the gate voltage relative to the source voltage at the point in the channel where the inversion layer has just formed): for N-type FETs, enhancement-mode devices have a positive threshold, and depletion-mode devices have a negative threshold; for P-type FETs, enhancement-mode is negative and depletion-mode is positive.

[0088] Large-scale integrated circuit design Virtually Large Scale Integration (VLSI) is the process of creating integrated circuits (ICs) by combining millions of MOS transistors onto a single chip. Structured VLSI design is a modular approach used to save microchip area by minimizing interconnect structure area. This is achieved by repeatedly arranging rectangular macroblocks that are interconnected using wiring in an adjacency manner. One embodiment is to divide the layout of adders into a row of equal bit slice cells. In complex designs, this structuring can be achieved through hierarchical nesting.

[0089] Two-dimensional electron gas (2-DEG) Two-dimensional electron gas (2DHG) is a scientific model in solid-state physics. It is a gas of electrons that can move freely in two dimensions but are strictly confined in the third. This strict confinement results in quantized energy levels for upward movement in the third dimension, which can be neglected in most problems. Thus, electrons appear as two-dimensional sheets embedded in a three-dimensional world. A similar structure to holes is called two-dimensional hole gas (2DHG), and this system has many useful and interesting properties.

[0090] Most 2DEGs exist in transistor-like structures made of semiconductors. The most common 2DEG is the electron layer present in MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). When the transistor is in inverted mode, electrons below the gate oxide are confined to the semiconductor-oxide interface, thus occupying well-defined energy levels. For sufficiently thin potential wells and at relatively low temperatures, only the lowest energy level is occupied (see figure caption), so electron movement perpendicular to the interface can be neglected. However, electrons move freely parallel to the interface, thus it is quasi-two-dimensional.

[0091] In engineering terms, 2DEG stands for High Electron Mobility Transistor (HEMT) and Rectangular Quantum Well. HEMT is a field-effect transistor that uses a heterojunction between two semiconductor materials to confine electrons within a triangular quantum well. Electrons confined to the HEMT heterojunction exhibit higher mobility than electrons in a MOSFET because the former utilizes intentionally undoped channels, mitigating the detrimental effects of ionized impurity scattering. Two closely spaced heterojunction interfaces can be used to confine electrons within a rectangular quantum well. Careful selection of materials and alloy compositions allows control over the carrier density within the 2DEG.

[0092] Electrons can also be confined to the surface of a material. For example, free electrons can float on the surface of liquid helium and move freely along the surface, but are adhered to the helium; some of the earliest work in 2DEG was accomplished using this system. In addition to liquid helium, there are solid insulators (such as topological insulators) that support conductive surface electronic states.

[0093] Floating key In chemistry, a dangling bond is an unsaturated valence state on a fixed atom. Atoms with dangling bonds are also called immobilized free radicals or stationary radicals, referring to their structural and chemical similarity to free radicals. To gain enough electrons to fill their valence shell (see also the octagonal rule), many atoms form covalent bonds with other atoms. In the simplest case, a single bond, each atom contributes one unpaired electron, and the resulting pair of electrons is shared between them. Atoms with too few bonding partners to satisfy their valence and possessing unpaired electrons are called "free radicals"; therefore, molecules containing these atoms are often also free radicals. When a free radical exists in a stationary environment (such as a solid), it is called an "immobilized free radical" or "dangling bond."

[0094] Both free radicals and immobilized radicals exhibit chemical properties very different from atoms and molecules containing only complete bonds. Generally, they are extremely reactive. Immobilized free radicals, like their mobile counterparts, are highly unstable, but they acquire some kinetic stability due to limited mobility and steric hindrance. While free radicals typically have short lifetimes, immobilized free radicals tend to exhibit longer lifetimes due to reduced reactivity.

[0095] Ferroelectricity Ferroelectricity is a property of certain materials that exhibit spontaneous polarization, which can be reversed by applying an external electric field. All ferroelectrics are thermoelectrics, and their additional property is that their spontaneous polarization is reversible. The term is used as an analogy to ferromagnetism, in which materials exhibit a permanent magnetic moment.

[0096] polarization When most materials are polarized, the resulting polarization P is almost exactly proportional to the applied external electric field E; therefore, polarization is a linear function. This is called dielectric polarization. Some materials, known as paraelectric materials, exhibit more nonlinear polarization. The capacitance corresponding to the slope of the polarization curve is not constant like that of dielectrics, but is a function of the external electric field. In addition to nonlinearity, ferroelectric materials exhibit spontaneous nonzero polarization even when the applied field E is zero. A prominent feature of ferroelectrics is that spontaneous polarization can be reversed by applying a reasonably strong electric field in the opposite direction; therefore, polarization depends not only on the current electric field but also on its history, resulting in a hysteresis loop. They are called ferroelectric, similar to ferromagnetic materials, which have spontaneous magnetization and exhibit similar hysteresis loops. Typically, materials exhibit ferroelectricity only below a certain phase transition temperature (called the Curie temperature (TC)) and paraelectricity above that temperature: spontaneous polarization disappears, and the ferroelectric crystal transitions to a paraelectric state. Many ferroelectrics completely lose their piezoelectric properties above TC because their paraelectric phases have a centrosymmetric crystal structure. The nonlinear properties of ferroelectric materials can be used to manufacture capacitors with adjustable capacitance. Typically, a ferroelectric capacitor consists of only a pair of electrodes sandwiched with a layer of ferroelectric material. The dielectric constant of ferroelectrics is not only adjustable but also typically very high in absolute value, especially near the phase transition temperature. Because of this, ferroelectric capacitors have a very small physical size compared to dielectric (non-tunable) capacitors with similar capacitance.

[0097] Spontaneous polarization The spontaneous polarization of ferroelectric materials implies a hysteresis effect, which can serve as a memory function. Ferroelectric capacitors are indeed used to fabricate ferroelectric RAMs for computers and RFID cards [6]. In these applications, thin films of ferroelectric materials are typically used because the field required to switch polarization can be achieved with a moderate voltage. However, when using thin films, great attention must be paid to the interface, electrodes, and sample quality to ensure that the device can operate reliably.

[0098] Implementation

[0099] The following description provides only exemplary embodiments and is not intended to limit the scope, applicability, or construction of this disclosure. Rather, the following description of exemplary embodiments will provide those skilled in the art with an enabling description for implementing one or more exemplary embodiments. Various changes that may be made to the function and arrangement of the elements are contemplated without departing from the spirit and scope of the subject matter disclosed in the appended claims.

[0100] Specific details are set forth in the following description to provide a thorough understanding of the embodiments. However, those skilled in the art will understand that embodiments can be practiced without these specific details. For example, systems, processes, and other elements in the disclosed subject matter may be shown as components in block diagram form so as not to obscure the embodiments with unnecessary details. In other cases, well-known processes, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments. Furthermore, the same reference numerals and designations denote the same elements in the various figures.

[0101] Furthermore, various implementations can be described as processes depicted as program block diagrams, flowcharts, data flow diagrams, structural diagrams, or block diagrams. Although program block diagrams can describe operations as sequential processes, many operations can be performed in parallel or simultaneously. Additionally, the order of operations can be rearranged. When an operation of a process completes, it may terminate, but there may be other steps not discussed or included in the diagram. Moreover, not all operations in any specifically described process will occur in all implementations. A process can correspond to a method, function, procedure, subroutine, subroutine, etc. When a process corresponds to a function, the termination of the function can correspond to the function returning to the calling function or the main function.

[0102] Furthermore, implementations of the disclosed subject matter can be carried out, at least partially, manually or automatically. Manual or automatic implementation can be performed or at least assisted by using machines, hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, program code or code segments performing the necessary tasks can be stored in a machine-readable medium. The processor can perform the necessary tasks.

[0103] Furthermore, the embodiments of this disclosure and the functional operations described in this specification can be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, in computer hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of these. Additionally, some embodiments of this disclosure can be implemented as one or more computer programs, i.e., one or more computer program instruction modules encoded on a tangible, non-transitory program carrier for execution by or control of the operation of a data processing device. Furthermore, program instructions can be encoded on artificially generated propagation signals, such as machine-generated electrical, optical, or electromagnetic signals, which encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, or a combination of one or more of these.

[0104] According to embodiments of this disclosure, the term "data processing apparatus" can include all kinds of devices, apparatuses, and machines for processing data, including, for example, a programmable processor, a computer, or a plurality of processors or computers.

[0105] Computer programs (also referred to or described as programs, software, software applications, modules, software modules, scripts, or code) can be written in any form of programming language (including compiled or interpreted languages) or declarative or procedural languages, and can be deployed in any form (including as standalone programs or as modules, components, subroutines, or other units suitable for use in a computing environment). Computer programs may, but do not need to, correspond to files in a file system. Programs can be stored as a part of a file that contains other programs or data, for example, in one or more scripts in a markup language document, in a single file dedicated to the program, or in multiple coordinating files (e.g., files storing one or more modules, subroutines, or portions of code). Computer programs can be deployed to execute on one or more computers located in one place or distributed across multiple locations and interconnected by a communication network. Computers suitable for executing computer programs include, for example, microprocessors that may be based on general-purpose or special-purpose microprocessors or both, or any other type of central processing unit. Generally, the central processing unit receives instructions and data from read-only memory or random access memory or both. The basic elements of a computer are the central processing unit for making or executing instructions and one or more storage devices for storing instructions and data. Generally, a computer also includes, or is operatively coupled to, receiving data from or transferring data to one or more mass storage devices (e.g., magnetic, magneto-optical disks, or optical disks) for storing data, or both. However, a computer does not necessarily need to have such a device. Furthermore, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive), to name just a few.

[0106] Although this disclosure has been described with reference to certain preferred embodiments, it should be understood that various other changes and modifications can be made within the spirit and scope of this disclosure. Therefore, the appended claims cover all such changes and modifications within the true spirit and scope of this disclosure.

Claims

1. A field-effect transistor, the field-effect transistor comprising: The source and drain are positioned at a horizontal plane at a location along the vertical direction; A gate is positioned along the vertical direction at a horizontal plane higher than the source and drain planes. A first region, located below the source and drain planes, comprising a first group III nitride III-N layer and a second III-N layer on the first III-N layer; and A second region, located below the gate, includes a first III-N layer, a second III-N layer on the first III-N layer, and a third III-N layer on the second III-N layer. The third III-N layer extends through the second III-N layer and into a portion of the first III-N layer at selective locations along the width of the field-effect transistor. The third III-N layer is P-type doped, and both the first and second III-N layers are unintentionally doped. The vertical length of the first III-N layer is longer than the vertical length of the second III-N layer. In a cross-section along the width of the field-effect transistor, The vertical length from the upper surface of the third III-N layer connected to the gate to the upper surface of the second III-N layer is longer than the vertical length from the lower surface of the second III-N layer to the lower surface of the third III-N layer extending into a portion of the first III-N layer. The vertical length of the second III-N layer is longer than the spacing between the second III-N layers in the width direction of the field-effect transistor.

2. The field-effect transistor according to claim 1, wherein, The first region includes: basal layer; The buffer layer on the substrate layer, wherein the first group III nitride III-N layer is located on the buffer layer, and The second region below the gate includes: basal layer; The buffer layer on the base layer, wherein the first group III nitride III-N layer is located on the buffer layer.

3. The field-effect transistor according to claim 1, wherein, The second III-N layer is Al x In y Ga 1-x-y N, such that the values ​​of x and y are between 0 and 1 (0≦x≦1), (0≦y≦1), where the first III-N layer and the third III-N layer are gallium nitride (GaN).

4. The field-effect transistor according to claim 1, wherein, The spontaneous polarization charge of the second III-N layer is higher than that of the first III-N layer.

5. The field-effect transistor according to claim 1, wherein, The vertical thickness of the first III-N layer is greater than the vertical thickness of the second III-N layer.

6. The field-effect transistor according to claim 1, wherein, The vertical thickness of the first III-N layer is 10 times greater than the vertical thickness of the second III-N layer, or the vertical thickness of the first III-N layer is 1000% greater than the vertical thickness of the second III-N layer.

7. The field-effect transistor according to claim 1, wherein, The gap distance between the source and the gate, and the gap distance between the gate and the drain, are either symmetrical or asymmetrical.

8. The field-effect transistor according to claim 1, wherein, The gap distance between the gate and the drain is related to the breakdown voltage of the field-effect transistor.

9. The field-effect transistor according to claim 1, wherein, The third III-N layer, which extends at a selective location through the second III-N layer and into the portion of the first III-N layer, has a profile such that the profile has a vertical profile length and a profile width.

10. The field-effect transistor according to claim 9, wherein, Each profile at the selected location includes one or a combination of a constant profile width, a variable profile width, a constant vertical profile length, or a variable vertical profile length.

11. The field-effect transistor according to claim 9, wherein, The contour forming pattern causes the contour width to increase along the direction from the first width end to the second width end of the field-effect transistor, thereby producing a higher linearity than the contour of the field-effect transistor with a constant contour width.

12. The field-effect transistor according to claim 9, wherein, Each profile is equidistant from the width of the field-effect transistor.

13. The field-effect transistor according to claim 9, wherein, Each contour is not equidistant and varies along the width of the field-effect transistor.

14. The field-effect transistor according to claim 9, wherein, The profile at the selected location has a profile width and a vertical profile length, such that the profile is arranged at an angle to the horizontal direction within the range of 100 degrees to 80 degrees.

15. The field-effect transistor according to claim 1, wherein, At the interface between the first III-N layer and the second III-N layer, there is an accumulation of two-dimensional electron gas 2-DEG.

16. The field-effect transistor according to claim 15, wherein, The accumulation of the 2-DEG is depleted by the third III-N layer, thereby generating the enhancement mode E-mode operation of the field-effect transistor.

17. The field-effect transistor according to claim 1, wherein, The first III-N layer has a band gap, and the second III-N layer has a band gap, such that the band gap of the second III-N layer is larger than the band gap of the first III-N layer.

18. A transistor comprising: The source and drain are positioned at a horizontal plane at a location along the vertical direction; A gate, wherein the gate is located at a horizontal plane higher than the source and drain horizontal planes along the vertical direction; A first region, located below the source and drain horizontal planes, includes a substrate layer, a buffer layer on the substrate layer, a first group III nitride III-N layer on the buffer layer, and a second III-N layer on the first III-N layer, wherein the spontaneous polarization charge of the second III-N layer is higher than that of the first III-N layer. A second region, located below the gate, includes a substrate layer, a buffer layer on the substrate layer, a first III-N layer on the buffer layer, a second III-N layer on the first III-N layer, and a third III-N layer on the second III-N layer. The third III-N layer extends through the second III-N layer and into a portion of the first III-N layer at selective locations along the width of the field-effect transistor. The third III-N layer is P-type doped, and the first and second III-N layers are unintentionally doped. The vertical length of the first III-N layer is longer than the vertical length of the second III-N layer. In a cross-section along the width of the transistor, The vertical length from the upper surface of the third III-N layer connected to the gate to the upper surface of the second III-N layer is longer than the vertical length from the lower surface of the second III-N layer to the lower surface of the third III-N layer extending into a portion of the first III-N layer. The vertical length of the second III-N layer is longer than the spacing between the second III-N layers in the width direction of the transistor.

19. The transistor of claim 18, wherein, The first III-N layer, the second III-N layer, and the third III-N layer are grown using one or a combination of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or remote plasma chemical vapor deposition (RPCVD), and wherein selected sites in the sub-region are doped with Mg ions by Mg ion implantation.

20. A transistor comprising: The source and drain are positioned at a horizontal plane at a location along the vertical direction; A gate is positioned at a horizontal plane higher than the source and drain planes along the vertical direction, and wherein the gap distance between the gate and the drain is related to the breakdown voltage of the transistor. A first region, located below the source and drain horizontal planes, such that the first region includes a first group III nitride III-N layer and a second III-N layer on the first III-N layer; A second region, located below the gate, includes a first III-N layer, a second III-N layer on the first III-N layer, and a third III-N layer on the second III-N layer. The third III-N layer extends through the second III-N layer and into a portion of the first III-N layer at selective locations along the width of the field-effect transistor. The third III-N layer is P-type doped, and both the first and second III-N layers are unintentionally doped. The vertical length of the first III-N layer is longer than the vertical length of the second III-N layer. In a cross-section along the width of the transistor, The vertical length from the upper surface of the third III-N layer connected to the gate to the upper surface of the second III-N layer is longer than the vertical length from the lower surface of the second III-N layer to the lower surface of the third III-N layer extending into a portion of the first III-N layer. The vertical length of the second III-N layer is longer than the spacing between the second III-N layers in the width direction of the transistor.

Images