LED precursor

Abstract

Provided are a method for manufacturing an LED precursor and an LED precursor. The LED precursor is manufactured by forming a monolithic growth stack having a growth surface and forming a monolithic LED stack on the growth surface. The monolithic growth stack includes a first semiconductor layer comprising a Group III nitride, a second semiconductor layer, and a third semiconductor layer. The second semiconductor layer includes a first Group III nitride containing a donor dopant, such that the second semiconductor layer has a donor density of at least 5×1018 cm-3. The second semiconductor layer has an area porosity of at least 15% and a first in-plane lattice constant. The third semiconductor layer includes a second Group III nitride different from the first Group III nitride. The monolithic growth stack includes a terrace structure including the third semiconductor layer, such that the growth surface includes a terrace surface of the third semiconductor layer and sidewall surfaces of the third semiconductor layer surrounding the terrace surface. The sidewall surfaces of the third semiconductor layer are inclined relative to the terrace surface. The terrace surface of the third semiconductor layer has a second in-plane lattice constant that is greater than the first in-plane lattice constant.

Description

Technical Field

[0001] The present disclosure relates to a light emitting diode (LED), and in particular to an LED comprising a group III nitride. Background Art

[0002] Micro-LED arrays are generally defined as LEDs with dimensions of 100 × 100 μm² or less. Micro-LEDs can be assembled to form two-dimensional micro-LED arrays. Micro-LED arrays can form self-luminous displays or projectors suitable for various devices, such as smart watches, head-mounted displays, head-up displays, cameras, viewfinders, multi-point excitation sources, and micro-projectors.

[0003] In many applications, it is desirable to provide a microdisplay / projector that can output light having a certain wavelength range. For example, in many color displays, it is common to provide each pixel with the ability to output a combination of red, green, and blue light.

[0004] One known form of micro-LED array includes a plurality of LEDs formed from group III nitrides. Group III nitride LEDs are inorganic semiconductor LEDs that contain GaN and its alloys with InN and AlN in the active light-emitting region. Group III nitride LEDs can be driven at significantly higher current densities and emit higher light power densities than conventional large-area LEDs (e.g., organic light emitting diodes (OLEDs) in which the light-emitting layer is an organic compound). Therefore, the higher luminance (brightness, which is defined as the amount of light emitted per unit area by a light source in a given direction) makes micro-LEDs suitable for applications that require or benefit from high brightness. For example, applications that benefit from high brightness can include displays in high-brightness environments, or projectors. In addition, group III nitride micro-LEDs are known to have relatively high luminous efficiency (expressed in lumens per watt (lm / W)) compared to other conventional light sources. The relatively high luminous efficiency of group III nitride micro-LED arrays reduces power consumption compared to other light sources, making micro-LEDs particularly suitable for portable devices.

[0005] One known type of III-nitride LED utilizes an In-Ga-N alloy system to define multiple quantum wells in the active region of the LED. Typically, GaN and In x Ga 1-x Alternating layers of N define quantum wells. For blue LEDs, the indium mole fraction X is typically <0.2. Increasing the incorporation into In x Ga 1-xThe amount of indium in the N layer increases the depth of the potential well, thereby increasing the wavelength of the light emitted by the LED.

[0006] It is well known that increasing the indium mole fraction X above 0.2 to provide natural green and red LEDs, for example, significantly reduces the efficiency of the LED. One of the fundamental problems is the low incorporation efficiency of indium if deposited on relaxed or compressively strained GaN. x Ga 1-x N layers (i.e., X>0.2) are typically formed using low growth temperatures and are prone to phase separation that has a detrimental effect on IQE (e.g., Journal of Applied Physics 123, 160901 (2018)).

[0007] In particular, to form a natural red LED (ie, an LED with a peak emission wavelength in the range of 600 nm to 680 nm), the active region of the LED typically includes In x Ga 1-x N layer, where X≥0.3. x Ga 1-x The strain induced in the N layer may lead to the formation of defects, which in turn reduces the efficiency of the LED.

[0008] "InGaN lattice constant engineering via growth on (In, Ga) N / GaN nanostripe arrays", Keller S et al., Semicond. Sci. Technol., vol. 30, (2015) discloses a planar (In, Ga) N layer grown on a nanostrip array composed of InGaN / GaN multiple quantum wells. After patterning, the nanostrip array exhibits elastic relaxation in the direction perpendicular to the stripe, resulting in a ┴ The lattice constant is greater than that of the GaN-based layer.

[0009] It is an object of the present invention to provide an improved method for forming LED precursors, and improved LED precursors, which solve at least one of the problems associated with prior art methods and arrays, or at least provide a commercially useful alternative thereto. Summary of the Invention

[0010] The present inventors have recognized that to improve the efficiency of LEDs comprising Group III nitrides, the formation of defects caused by strain between the active layer and the LED precursor layer on which the active layer is deposited should be reduced. The present inventors have recognized that by providing a strain-relaxed growth surface for the active layer (having an in-plane lattice constant that more closely matches the (unstrained) in-plane lattice constant of the active layer), the strain at the interface can be reduced. This, in turn, can reduce the formation of defects at the interface, thereby improving the efficiency of the LED precursor.

[0011] According to a first aspect of the present disclosure, an LED precursor is provided. The method comprises: a) forming a monolithic growth stack having a growth surface, and b) forming a monolithic LED stack on the growth surface of the monolithic growth stack.

[0012] The forming of the monolithic growth stack includes forming a first semiconductor layer including a Group III nitride, forming a second semiconductor layer, and forming the second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer includes the first Group III nitride containing a donor dopant, such that the second semiconductor layer has a density of at least 5×10 18 cm -3 The method provides a method for forming a monolithic growth stack by selectively removing a portion of the third semiconductor layer from the growth surface. The method selectively removes the third semiconductor layer through the thickness of the third semiconductor layer so that the growth surface of the monolithic growth stack includes a terrace surface of the third semiconductor layer and a sidewall surface of the third semiconductor layer surrounding the terrace surface. The third semiconductor layer provides a growth surface of the monolithic growth stack, and the third semiconductor layer includes a second Group III nitride different from the first Group III nitride, so that the third semiconductor layer is formed on the second semiconductor layer under compressive strain. After forming the third semiconductor layer, the second semiconductor layer is subjected to a porosity treatment to increase the area porosity of the second semiconductor layer to at least 15%, and the third semiconductor layer is heated to a strain relaxation temperature so that the third semiconductor layer relaxes so that the in-plane lattice constant of the terrace surface increases.

[0013] Forming a monolithic LED stack includes: forming a fourth semiconductor layer including a group III nitride on a growth surface of the monolithic growth stack so that the fourth semiconductor layer covers a platform surface of the third semiconductor layer; forming an active layer on the fourth semiconductor layer, the active layer including a plurality of quantum well layers, each quantum well layer including a group III nitride; and forming a p-type semiconductor layer including a group III nitride on the active layer.

[0014] An LED precursor according to the presently claimed invention provides a monolithic growth stack having a growth surface. The growth stack includes a plurality of Group III nitride layers. The growth surface is suitable for forming a monolithic LED stack including a plurality of Group III nitride layers thereon. In particular, the growth surface is suitable for forming a monolithic LED stack for a native red or green LED. The growth stack includes three semiconductor layers, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The third semiconductor layer has a different composition than the second semiconductor layer (on which the third semiconductor layer is formed). As a result, the third semiconductor layer is formed on the second semiconductor layer under compressive stress. That is, the lattice structure of the third semiconductor layer is subjected to compressive strain from the lattice structure of the second semiconductor layer.

[0015] The selective removal of the third semiconductor layer provides a growth surface comprising a terrace surface. Thus, the monolithic growth stack is patterned into a terrace structure, upon which the monolithic LED stack can be overgrown. By overgrowing the monolithic LED stack on the terrace structure of the monolithic growth stack, an LED precursor can be formed using a method that does not require etching the LED junction. This method of forming the LED precursor without etching the sidewall surfaces of the LED junction can reduce or eliminate defects formed on the sidewall surfaces of the LED junction, thereby improving the EQE of the LED.

[0016] The heat treatment process allows the third semiconductor layer to release its compressive strain through plastic deformation in the porous semiconductor layer, so that the in-plane lattice constant of the third semiconductor layer increases (relative to the in-plane lattice constant of the third semiconductor layer in the deposited state). Plastic deformation in the porous semiconductor layer (formation and movement of misfit dislocations) occurs near the interface between the porous semiconductor layer and the semiconductor layer. The presence of voids and a large number of dangling bonds reduces the mechanical toughness of the porous semiconductor layer, which contributes to the formation and movement of misfit dislocations. Therefore, the third semiconductor layer can be more easily strain-relaxed on the third semiconductor layer. By providing a growth surface of a monolithic growth stack with an increased in-plane lattice constant, the in-plane lattice constant of the growth surface can reduce and / or eliminate the strain at the interface between the monolithic growth stack and the monolithic LED stack. Therefore, the formation of defects at the interface can be reduced and / or eliminated, thereby improving the efficiency of the LED precursor.

[0017] A heat treatment step is provided to induce strain relaxation in the third semiconductor layer formed under compressive strain. However, due to the difference in lattice constants between the unstrained planes of the second and third semiconductor layers, excessive strain relaxation of the compressively strained layer may result in bowing and / or delamination of the compressively strained layer. Thus, the method according to the first aspect provides increased strain relaxation while reducing or eliminating the occurrence of bowing and / or delamination at the interface between the second and third semiconductor layers.

[0018] An important feature is that the second semiconductor layer is subjected to an etching process so as to provide the second semiconductor layer with an areal porosity of at least 15%. Thus, the second semiconductor layer is a relatively porous layer. The porosity of the second semiconductor layer provides a local region at the interface between the second semiconductor layer and the third semiconductor layer where the strain in the third semiconductor layer can be reduced. Importantly, the provision of the porous semiconductor layer 14' allows misfit dislocations to propagate as half-loop dislocations in the porous semiconductor layer 14'. Thus, the porous semiconductor layer 14' can undergo plastic deformation during the heat treatment step, which results in the preferential propagation of half-loop dislocations in the porous semiconductor layer 14' rather than the propagation of screw dislocations in the third semiconductor layer 16. The formation of half-loop dislocations in the porous semiconductor layer 14' allows strain relaxation of the third semiconductor layer 16, thereby providing an improved growth surface for the monolithic LED stack.

[0019] The inventors also realized that since the second and third semiconductor layers can be formed as substantially continuous layers, such as a layer extending over an area of at least 30 μm × 30 μm, it is important that there is sufficient space for the third semiconductor layer to relax into. Such a layer may be prone to bending: it attempts to strain relax without sufficient (lateral) volume for the layer to relax (expand) into. By selectively removing portions of the third semiconductor layer, the remaining portion of the third semiconductor layer can relax into the free space created by the selective removal process. That is, the sidewall surface of the third semiconductor layer has space for (lateral) strain relaxation to occur.

[0020] In some embodiments, the second semiconductor layer comprises GaN. For example, in some embodiments, the second semiconductor layer may comprise substantially undoped GaN (i.e., GaN that is not intentionally doped). In some embodiments, the third semiconductor layer comprises In x Ga 1-X N, where 0 < X ≤ 1. Thus, in some embodiments, a second semiconductor layer and a third semiconductor layer can be provided such that the third semiconductor layer is formed on the second semiconductor layer under compressive strain. By forming the third semiconductor layer under compressive strain, the monolithic growth stack can then be subsequently processed for strain relaxation, thereby providing a strain-relaxed growth surface for the formation of the monolithic LED stack. The strain-relaxed growth surface can have an in-plane lattice constant that more closely matches the unstrained lattice constant of the active layer, particularly an active layer configured to emit light having a wavelength of at least 525 nm (i.e., green or red visible light).

[0021] For example, in some embodiments, each quantum well layer of the active layer comprises In Z Ga 1-ZN, wherein 0.2≤Z≤0.5. Thus, the active layer can be configured to emit light having a peak emission wavelength of at least 525 nm. In some embodiments, each quantum well layer of the active layer includes In Z Ga 1-Z N, wherein 0.3≤Z≤0.5. In this way, the active layer can be configured to emit light having a peak emission wavelength of at least 600 nm.

[0022] In some embodiments, the third semiconductor layer has a thickness in a direction perpendicular to the growth surface of the monolithically grown stack of at least 200 nm.

[0023] In some embodiments, the second semiconductor layer is subjected to a porosity treatment prior to selectively removing a portion of the third semiconductor layer from the growth surface. Thus, the porosity treatment process can be performed prior to any patterning of the layers forming the monolithic growth stack.

[0024] In some embodiments, the third semiconductor layer is selectively removed such that the growth surface of the monolithically grown stack includes a surface of the second semiconductor layer. For example, in some embodiments, the monolithically grown stack can include a surface of the second semiconductor layer that is substantially parallel to a terrace surface of the third semiconductor layer. In some embodiments, selectively removing the third semiconductor layer can allow for the formation of a terrace structure, wherein the third semiconductor layer includes a terrace surface surrounded by sidewall surfaces. The sidewall surfaces of the terrace structure can be surrounded by a bulk semiconductor surface of the second semiconductor layer. Thus, the terrace surface and sidewall surfaces of the third semiconductor layer and the bulk semiconductor surface of the second semiconductor layer provide growth surfaces on which the monolithic LED stack can be formed.

[0025] In some embodiments, forming the monolithic growth stack further includes selectively removing a portion of the second semiconductor layer aligned with the removed portion of the third semiconductor layer, such that a growth surface of the monolithic growth stack includes a sidewall surface of the second semiconductor layer. In this manner, a terrace structure can be formed that extends from a surface of the first semiconductor layer in a direction substantially perpendicular to the surface of the first semiconductor layer.

[0026] In some embodiments, the second semiconductor layer is selectively removed such that the sidewall surface of the second semiconductor layer is aligned with the sidewall surface of the third semiconductor layer. Thus, the sidewall surface of the third semiconductor layer and the sidewall surface of the second semiconductor layer extend in a substantially coplanar direction. For example, in some embodiments, the sidewall surface of the second semiconductor layer and the sidewall surface of the third semiconductor layer may extend in a direction substantially perpendicular to the terrace surface of the third semiconductor layer.

[0027] In some embodiments, the second semiconductor layer is selectively removed such that the growth surface includes a portion of the surface of the first semiconductor layer.

[0028] In some embodiments, the fourth semiconductor layer includes GaN. In some embodiments, the fourth semiconductor layer may also include an n-type dopant, such that the fourth semiconductor layer is an n-type semiconductor. In other embodiments, the fourth semiconductor layer may be an undoped semiconductor layer (i.e., not intentionally doped).

[0029] In some embodiments, the fourth semiconductor layer is formed on the growth surface to provide an inclined sidewall portion extending from a first portion of the fourth semiconductor layer on the terrace surface of the third semiconductor layer toward the second semiconductor layer. In this way, the fourth semiconductor layer can have a substantially trapezoidal cross-section.

[0030] In some embodiments, forming the monolithic growth stack further comprises selectively forming a mask layer on the growth surface of the monolithic growth stack. The mask layer may include openings aligned with the terrace surfaces of the monolithic growth stack. Thus, providing the mask layer on a portion of the growth surface can prevent or reduce growth of the monolithic LED stack on areas outside the terrace surfaces of the growth surface. Thus, providing the mask layer can provide a method for forming the monolithic LED stack while avoiding the use of etching of the monolithic LED stack to pattern the LED junctions.

[0031] In some embodiments, the monolithic LED stack is selectively formed on the mesa surface of the monolithic growth stack rather than on the growth surface covered by the mask layer.

[0032] According to a second aspect of the present disclosure, an LED precursor is provided. The LED precursor includes a monolithic growth stack having a growth surface and a monolithic LED stack disposed on the growth surface of the monolithic growth stack. The monolithic growth stack includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer includes a Group III nitride. The second semiconductor layer is disposed on the first semiconductor layer. The second semiconductor layer includes a first Group III nitride containing a donor dopant, such that the second semiconductor layer has a density of at least 5×10 18 cm -3The donor density. The second semiconductor layer has an air porosity of at least 15% and a first in-plane lattice constant. The third semiconductor layer is disposed on the side of the second semiconductor layer opposite to the first semiconductor layer. The third semiconductor layer includes a second group-III nitride different from the first group-III nitride. The monolithic growth stack includes a mesa structure that includes the third semiconductor layer such that the growth surface includes the mesa surface of the third semiconductor layer and the sidewall surfaces of the third semiconductor layer surrounding the mesa surface, and the sidewall surfaces of the third semiconductor layer are inclined with respect to the mesa surface. The mesa surface of the third semiconductor layer has a second in-plane lattice constant greater than the first in-plane lattice constant. The monolithic LED stack includes a fourth semiconductor layer, an active layer, and a p-type semiconductor layer. The fourth semiconductor layer is disposed on the growth surface of the monolithic growth stack such that the fourth semiconductor layer covers the mesa surface of the third semiconductor layer and the sidewall surfaces of the third semiconductor layer. The active layer includes a plurality of quantum well layers. Each quantum well layer includes a group-III nitride. The p-type semiconductor layer includes a group-III nitride disposed on the active layer.

[0033] Thus, the LED precursor according to the second aspect of the present disclosure can be formed using the method of the first aspect. Therefore, the LED precursor according to the second aspect of the present disclosure can include all the advantages and optional features of the first aspect described above.

[0034] Specifically, the monolithic LED stack can be formed by overgrowing the monolithic LED stack on the mesa structure of the monolithic growth stack. Therefore, a method that does not require etching the sidewall surfaces of the LED junction can be used to form the LED precursor. A method of forming the LED precursor that avoids etching the sidewall surfaces of the LED junction can result in reducing or eliminating defects formed on the sidewall surfaces of the LED junction, thereby improving the EQE of the LED.

[0035] In some embodiments, the second semiconductor layer includes GaN. In some embodiments, the third semiconductor layer includes In X Ga 1-X N, where 0 < X ≤ 1. Thus, in some embodiments, the In content (X) of the third semiconductor layer can be controlled to provide the desired in-plane lattice constant for the third semiconductor layer after the heat treatment process. Specifically, in some embodiments, the third semiconductor layer includes In X Ga 1-X N, where 0.2 ≤ X ≤ 0.5, such that the third semiconductor layer provides a growth surface particularly suitable for forming the active layer thereon, and the peak emission wavelength of the active layer is in the green or red visible spectrum (e.g., a peak emission wavelength of at least 525 nm).

[0036] For example, in some embodiments, each quantum well layer of the active layer includes In Z Ga 1-ZN, wherein 0.2≤Z≤0.5. Thus, the active layer can be configured to emit light having a peak emission wavelength of at least 525 nm. In some embodiments, each quantum well layer of the active layer includes In Z Ga 1-Z N, wherein 0.3≤Z≤0.5. In this way, the active layer can be configured to emit light having a peak emission wavelength of at least 600 nm.

[0037] In some embodiments, the sidewall surface of the third semiconductor layer is inclined in a direction transverse to the terrace surface, so that the sidewall surface of the third semiconductor layer can extend in a direction substantially perpendicular to the first semiconductor layer.

[0038] In some embodiments, the terrace structure extends from the porous semiconductor layer such that the growth surface comprises the porous semiconductor layer.

[0039] In some embodiments, the growth surface of the monolithic growth stack includes a sidewall surface of the porous semiconductor layer aligned with a sidewall surface of the third semiconductor layer.

[0040] In some embodiments, the mesa structure extends from the first semiconductor layer such that the growth surface includes a portion of a surface of the first semiconductor layer.

[0041] In some embodiments, the fourth semiconductor layer includes GaN.

[0042] In some embodiments, the fourth semiconductor layer is provided on the growth surface to provide an inclined sidewall portion extending from a mesa portion of the fourth semiconductor layer on the mesa surface of the third semiconductor layer toward the second semiconductor layer.

[0043] In some embodiments, the monolithic growth stack further includes a mask layer disposed on a growth surface of the monolithic growth stack, the mask layer including openings aligned with a terrace surface of the monolithic growth stack.

[0044] In some embodiments, the monolithic LED stack is only selectively disposed on the platform surface of the monolithic growth stack.

[0045] In some embodiments, the LED precursor and the method of forming the LED precursor according to the first and second aspects of the present disclosure can provide an LED array precursor including a plurality of LED precursors and a method of forming the same. The plurality of LED precursors can be arranged in a two-dimensional array, wherein each LED precursor is spaced apart from the other LED precursors.

[0046] In some embodiments, the LED precursors, LED array precursors, and methods of forming the LED precursors and LED array precursors according to the first and second aspects of the present disclosure may provide micro-LED precursors and micro-LED array precursors. A micro-LED array precursor is an array of micro-LED precursors. A micro-LED precursor may include a monolithic LED stack having a surface area dimension in a plane aligned with the first semiconductor layer of less than 100 μm × 100 μm. For example, in some embodiments, a micro-LED precursor may have a surface area dimension of less than 10 μm × 100 μm. -8 m 2 surface area. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The present disclosure will now be described in conjunction with the following non-limiting drawings. Further advantages of the present disclosure will become apparent by reference to the detailed description when considered in conjunction with the accompanying drawings, in which:

[0048] Figure 1 shows a schematic diagram of an intermediate stage of forming a monolithic growth stack according to a first embodiment of the present disclosure;

[0049] Figure 2 shows a schematic diagram of an intermediate stage of forming a monolithic growth stack according to a first embodiment of the present disclosure;

[0050] Figure 3 shows a schematic diagram of an intermediate stage of forming a monolithic growth stack according to a first embodiment of the present disclosure;

[0051] Figure 4 shows a schematic diagram of a plurality of monolithic growth stacks according to an embodiment of the present disclosure;

[0052] Figure 5 shows a schematic diagram of a plurality of LED precursors according to a first embodiment of the present disclosure;

[0053] Figure 6 shows a schematic diagram of a plurality of monolithic growth stacks according to a second embodiment of the present disclosure;

[0054] Figure 7 shows a schematic diagram of a plurality of LED precursors according to a second embodiment of the present disclosure;

[0055] Figure 8 shows a schematic diagram of a plurality of monolithic growth stacks according to a third embodiment of the present disclosure;

[0056] Figure 9 A schematic diagram showing a plurality of LED precursors according to a third embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0057] According to a first embodiment, a method of forming an LED precursor 1 is provided.

[0058] Regarding the term "precursor" in LED precursor, it is noted that the described LED precursor does not necessarily include electrical contacts for the LED, for example, to allow light emission, nor does it necessarily include associated circuitry. Of course, the method of forming the LED precursor of the first embodiment does not preclude the addition of additional electrical contacts and associated circuitry. Therefore, the use of the term "precursor" in this disclosure is intended to include the final product (i.e., LED, LED array, etc.).

[0059] Figures 1 to 5 A schematic diagram of an LED precursor formed according to the method of the first embodiment is shown. The method according to the first embodiment includes forming a monolithic growth stack 10 and a monolithic LED stack 20. Monolithic LED stack 20 is formed on growth surface 11 of monolithic growth stack 10. According to the method of the first embodiment, monolithic growth stack 10 includes a first semiconductor layer 12, a second semiconductor layer 14, and a third semiconductor layer 16.

[0060] A monolithically grown stack refers to a stack of layers providing the growth surface forming the LED, the layers being formed as a single piece. That is, the monolithically grown stack 10 is formed as a single piece.

[0061] A monolithic LED stack refers to providing a stack of layers forming an LED, these stacks being formed as a single piece. That is, the monolithic LED stack is formed as a single piece on the growth surface 11 of the monolithic growth stack 10.

[0062] In the method of the first embodiment, a plurality of LED precursors 1 are formed in a single forming process. The plurality of LED precursors 1 are formed into an LED precursor array. Thus, the method according to the first embodiment provides a method for forming an LED array precursor including a plurality of LED precursors.

[0063] like Figure 1 As shown, forming the monolithic growth stack 10 includes forming a first semiconductor layer 12. Figure 1 In some embodiments, the first semiconductor layer 12 includes a Group III nitride. For example, the first semiconductor layer may include GaN. In some embodiments, the first semiconductor layer may be an undoped semiconductor layer (i.e., not intentionally doped). In other embodiments, the first semiconductor layer 12 may be a doped semiconductor layer (e.g., including an n-type dopant such as Si).

[0064] The first semiconductor layer 12 may be formed on the substrate ( Figure 1). The substrate can provide a growth surface for the first semiconductor layer 12. The substrate can be a substantially flat substrate. The substrate can have an in-plane lattice constant that is configured to correspond to the in-plane lattice constant of the first semiconductor layer 12 to reduce lattice mismatch. Various substrates suitable for growing the first semiconductor layer 12 comprising a Group III nitride are known to those skilled in the art. For example, the substrate can be a sapphire substrate or a silicon substrate. The substrate can include one or more buffer layers configured to provide a substrate surface suitable for forming a Group III nitride layer. The substrate can be provided so that the first semiconductor layer 12 is grown on the substrate so that the (0001) crystal plane of the first semiconductor layer 12 is aligned with the substrate surface. In this way, the first semiconductor layer 12 can have a (0001) crystal plane orientation.

[0065] The first semiconductor layer 12 may be formed using any suitable process for manufacturing a Group III nitride semiconductor layer, for example, using a Metal Organic Chemical Vapor Deposition (MOCVD) process or a Molecular Beam Epitaxy (MBE) process.

[0066] like Figure 1 As shown, the second semiconductor layer 14 is formed on the first semiconductor layer 12. The second semiconductor layer 14 is formed on the first surface 13 of the first semiconductor layer 12. The first semiconductor surface 13 is a surface of the first semiconductor layer 12 that is provided on the side of the first semiconductor layer 12 opposite to the substrate. In this way, the first semiconductor layer 12 is provided between the second semiconductor layer 14 and the substrate.

[0067] The second semiconductor layer 14 includes a group III nitride. The second semiconductor layer 14 has a first composition including a donor dopant, so that the second semiconductor layer has a density of at least 5×10 18 cm -3 In some embodiments, the donor density of the second semiconductor layer may be at least: 1×10 19 cm -3 , 3×10 19 cm -3 , 5×10 19 cm -3 , 7×10 19 cm -3 or 1×10 20 cm -3. Thus, the second semiconductor layer 14 is an n-type semiconductor layer. In particular, the second semiconductor layer 14 has a higher donor dopant density than the first semiconductor layer 12. The second semiconductor layer 14 may include any suitable donor dopant. For example, the second semiconductor layer 14 may include a donor dopant that includes at least one of Si and Ge. The second semiconductor layer 14 is provided with a relatively high donor density to allow for targeted formation of pores in the porosity treatment step described below. By providing the second semiconductor layer 14 with a relatively high donor dopant density, the porosity treatment selectively targets the second semiconductor layer 14.

[0068] The second semiconductor layer 14 can be formed as a substantially continuous layer across the major surface of the first semiconductor layer 12. In this way, the first semiconductor layer 12 and the second semiconductor layer 14 can be provided substantially continuously across the substrate. The second semiconductor layer 14 has a second surface 15 on a side of the second semiconductor layer 14 opposite to the first semiconductor layer 12.

[0069] The second surface 15 of the second semiconductor layer 14 has a first in-plane lattice constant. The second semiconductor layer 14 may have a wurtzite crystal structure. In some embodiments, the second semiconductor layer 14 may be formed on the first semiconductor layer 12, the first semiconductor layer 12 having a (0001) crystal plane arranged parallel to the first surface 13. Therefore, for the second semiconductor layer 14 having a second surface aligned with the (0001) crystal plane, the in-plane lattice constant may be a constant reflecting the a (or b) lattice constant.

[0070] In some embodiments, the second semiconductor layer 14 may have a thickness of at least 50 nm in a direction perpendicular to the substrate. In some embodiments, the second semiconductor layer 14 may have a thickness of no greater than 2000 nm.

[0071] In some embodiments, the first semiconductor layer 12 may have a thickness of at least 100 nm. In some embodiments, the first semiconductor layer 12 may have a thickness of no greater than 2000 nm.

[0072] The second semiconductor layer 14 can be formed using any suitable process for manufacturing a Group III nitride semiconductor layer, such as an MOCVD process or an MBE process. Thus, the second semiconductor layer 14 can be formed in a manner similar to the first semiconductor layer 12 and using similar equipment.

[0073] like Figure 2As shown, after forming the second semiconductor layer 14, a third semiconductor layer 16 is formed on the main surface of the second semiconductor layer 14. Thus, the third semiconductor layer 16 is formed on the side of the second semiconductor layer 14 opposite to the first semiconductor layer 12. The third semiconductor layer 16 provides the growth surface 11 of the monolithic growth stack 10.

[0074] The third semiconductor layer 16 comprises a group III nitride. The third semiconductor layer 16 has a second composition different from the first composition of the second semiconductor layer 14. The compositional difference between the second semiconductor layer 14 and the third semiconductor layer 16 results in the formation of the third semiconductor layer 16 under compressive strain. That is, the difference in the in-plane lattice constants of the second semiconductor layer and the third semiconductor layer causes the thus formed third semiconductor layer 16 to be under compressive strain. Thus, the in-plane lattice constant of the unstrained film having the (third semiconductor layer 16's) second composition will be greater than the in-plane lattice constant of the unstrained film having the (second semiconductor layer 14's) first composition.

[0075] The third semiconductor layer 16 is formed of a crystal structure that can be coherent with the second semiconductor layer 14. Thus, the interface between the third semiconductor layer 16 and the second semiconductor layer 14 can be a coherent interface. After a heat treatment process (discussed in more detail below), the third semiconductor layer 16 relaxes to form a strain-relaxed third semiconductor layer 16. The strain-relaxed third semiconductor layer 16 has a strain-relaxed surface, which forms part of the growth surface 11 of the monolithic growth stack 10 having a second in-plane lattice constant. The second in-plane lattice constant is greater than the first in-plane lattice constant of the second semiconductor layer 14. In some embodiments, the strain-relaxed third semiconductor layer 16 can have a wurtzite crystal structure, similar to the first semiconductor layer 12 and the second semiconductor layer 14. In some embodiments, the third semiconductor layer 16 can be formed on the first semiconductor layer 12 and the second semiconductor layer 14 with its (0001) crystal plane set parallel to the first surface 13 and the second surface 15.

[0076] For example, in Figure 2 embodiments, the third semiconductor layer 16 can comprise In X Ga 1-X N, where 0 < X ≤ 1. In particular, in some embodiments, the third semiconductor layer 16 can comprise In X Ga 1-X N, where 0.03 < X ≤ 0.2. Thus, the In content of the third semiconductor layer 16 can be selected to provide a platform surface having a desired in-plane lattice constant.

[0077] In Figure 2 embodiments, the first composition of the second semiconductor layer 14 comprises GaN. The second composition of the third semiconductor layer 16 can comprise In X Ga1-X N, where 0 < X ≤ 1. Thus, the formation of the third semiconductor layer 16 having the second composition and the second semiconductor layer 14 having the first composition will result in the formation of the third semiconductor layer 16 on the second semiconductor layer 12 under compressive strain.

[0078] In some embodiments, the third semiconductor layer 16 may be a substantially undoped layer. That is, the third semiconductor layer 16 may be formed without any intentional doping. For example, in the method of forming the first embodiment, the third semiconductor layer 16 is a substantially undoped layer. In some embodiments, the third semiconductor layer 16 may include a dopant, such as a donor dopant. In embodiments where the third semiconductor layer includes a dopant, the third semiconductor layer may be doped with a donor density not greater than the donor density of the second semiconductor layer 14. For example, in some embodiments, the donor density of the third semiconductor layer 15 may not be greater than 50%, 25%, 10%, 5%, 1%, or 0.1% of the donor density of the second semiconductor layer 14.

[0079] In some embodiments, the third semiconductor layer 16 may have a thickness of at least 200 nm. In some embodiments, the third semiconductor layer 16 may have a thickness not greater than 10 μm. For example, Figure 2 the third semiconductor layer 16 in [[ ]] may have a thickness of at least 1 μm and not greater than 10 μm.

[0080] As Figure 2 shown, the third semiconductor layer 16 is a bulk semiconductor layer formed of a substantially continuous group III nitride semiconductor layer. It should be understood that the third semiconductor layer 16 is provided to form a strain-relaxed surface (growth surface 11) for forming the monolithic LED stack 20. In other embodiments, the third semiconductor layer 16 may include a plurality of group III nitride layers forming a superlattice structure. For example, the third semiconductor layer 16 may include a plurality of first group III nitride layers and second group III nitride layers arranged in an alternating stack, where the first group III nitride layer and the second group III nitride layer have different lattice constants. For example, an example of the superlattice structure is an alternating stack of In Y Ga 1-Y N layers and GaN layers, where 0 < Y ≤ 1.

[0081] After forming the third semiconductor layer 16, the second semiconductor layer 14 is subjected to a porosity treatment to increase the area porosity of the second semiconductor layer 14 to at least 15%. Methods for increasing the porosity of Group III nitride layers are known to those skilled in the art. For example, "In-plane bandgap control in porous GaN through electroless wet chemical etching", Xiuling Li, Young Woon-Kim et al., Applied Physics Letters, Vol. 8, No. 6, February 11, 2002, describes several methods for increasing the porosity of n-type doped Group III nitride layers.

[0082] In the method according to the present disclosure, it is possible to selectively treat a donor density of at least 5×10 18 cm -3 The second semiconductor layer 14 is subjected to a porosity treatment to increase the area porosity of the second semiconductor layer. The donor density of the second semiconductor layer allows the porosity treatment process to selectively increase the porosity of the second semiconductor layer 14.

[0083] For example, the porosity treatment may include subjecting the layers of the monolithic growth stack to an electrochemical treatment process. The electrochemical treatment process may include immersing the monolithic growth stack in an oxalic acid bath. An electrical connection is formed between the oxalic acid bath and the monolithic growth stack 10. In order to electrochemically form pores in the second semiconductor layer 14, an electric current is passed between the oxalic acid bath and the electrical contacts of the monolithic growth stack. In some embodiments, the oxalic acid bath includes an oxalic acid solution with a concentration between 0.03M and 0.3M. In other embodiments, the oxalic acid bath can be replaced with other electrolytes, such as KOH or HCl. The level of electrical bias applied to the electrochemical process will depend on the electrochemical solution used and the relative sizes of the bath and the monolithic growth stack 10. Further examples of porosity treatment are described in ACS Applied NanoMaterials, 2020, 3, 399-402 and US2017 / 0237234.

[0084] The porosity treatment process results in the formation of pores present in the second semiconductor layer 14, or an increase in the size of the pores. The porosity of the second semiconductor layer 14 can be characterized by area porosity. Area porosity is the area fraction of pores present in a cross section through the material (i.e., through the second semiconductor layer 14). In some embodiments, the porous semiconductor layer 14' has an area porosity of at least 15%. In some embodiments, the porous semiconductor layer 14' has an area porosity of at least 30%. By providing a porous semiconductor layer 14' having such an area porosity, the third semiconductor can be strain-relaxed to a greater extent in a subsequent heat treatment process. Importantly, the provision of the porous semiconductor layer 14' allows misfit dislocations in the porous semiconductor layer 14' to propagate as half-ring dislocations. In this way, the strain relaxation of the third semiconductor layer 16 results in preferential propagation of half-ring dislocations in the porous semiconductor layer 14', rather than propagation of screw dislocations in the third semiconductor layer 16. Therefore, by providing the porous semiconductor layer 14', the defect density in the third semiconductor layer 16 can be reduced.

[0085] In some embodiments, the porous semiconductor layer 14' has an area porosity of no greater than 80%. In some embodiments, the area porosity of the porous semiconductor layer 14' is no greater than 50%. Thus, the structural integrity of the porous semiconductor layer 14' can be maintained after the porous treatment process.

[0086] like Figure 3 As shown, after the pore treatment step, the second semiconductor layer 14 is a porous semiconductor layer 14 ′. Thus, the monolithically grown stack 10 is formed of the first semiconductor layer 12 and the third semiconductor layer 16 , with the porous semiconductor layer 14 ′ provided therebetween.

[0087] In the method according to the first embodiment, the third semiconductor layer 16 is further processed to define a terrace structure for each LED precursor 1 of the LED array precursor. In the method of forming the first embodiment, the terrace structure is formed after the porosity treatment process. Of course, in other embodiments, the porosity treatment process can be performed after the terrace structure is formed. Figure 4 As shown, a plurality of monolithically grown stacks 10 are thus provided; one monolithically grown stack 10 for each LED precursor 1 of the LED array precursor.

[0088] like Figure 4 As shown, a plurality of monolithic growth stacks 10 (composed of Figure 4). The plurality of monolithic growth stacks 10 are spaced apart from one another to form an array of monolithic growth stacks 10. The array of monolithic growth stacks 10 can be spaced apart in a two-dimensional array across the first semiconductor layer 12. The plurality of monolithic growth stacks 10 can be spaced apart in a two-dimensional array, for example, in a square stacking arrangement or a hexagonal stacking arrangement. The array of monolithic growth stacks 10 defines the arrangement of LED precursors in the LED array precursor. Therefore, it should be understood that the method according to the first embodiment can be used to manufacture a plurality of LED precursors arranged in an array across the first semiconductor layer 12.

[0089] like Figure 4 As shown, the monolithic growth stack 10 of the first embodiment is formed by selectively removing a portion of the third semiconductor layer 16 from the growth surface 11 through the thickness of the third semiconductor layer 16. Therefore, the growth surface 11 of each monolithic growth stack 10 includes a terrace surface 30 of the third semiconductor layer 16 and a sidewall surface 32 of the third semiconductor layer 16 surrounding the terrace surface 30. Figure 4 In the embodiment of the present invention, the third semiconductor layer 16 is selectively removed throughout its entire thickness (in the thickness direction perpendicular to the growth surface 11) so that the growth surface 11 of the monolithic growth stack 10 includes the surface of the porous semiconductor layer 14'. In this way, the growth surface 11 of the monolithic growth stack 10 is shaped to define a terrace structure including the third semiconductor layer 16.

[0090] According to the method of the first embodiment, a selective removal process is performed before the heat treatment process. By performing the selective removal process before the heat treatment process, additional spatial volume is provided between each platform structure, and during the heat treatment process, the third semiconductor layer 16 can be strain-relaxed into this spatial volume. By providing a third semiconductor layer 16 with additional volume (which can be strain-relaxed into this additional volume), the increase in the in-plane lattice constant of the platform surface can be further improved. This in turn can reduce the strain formed when forming the active layer of the device, thereby improving the efficiency of the LED.

[0091] The terrace structure of the third semiconductor layer 16 can be formed using a selective removal process. In this way, portions of the third semiconductor layer 16 can be selectively removed to form Figure 4 For example, in Figure 4In the embodiment of the present invention, the growth surface 11 can be shaped using an etching process. In the etching process, a platform-defining mask layer (not shown) can be deposited on the surface of the third semiconductor layer 16. The platform-defining mask layer can be configured to mask a portion of the third semiconductor layer 16 that is intended to form a platform surface 30 of the monolithic growth stack 10. An etchant can then be used to selectively remove the unmasked portion of the third semiconductor layer 16. The etchant can etch away a portion of the third semiconductor layer 16 to expose the surface of the porous semiconductor layer 14'. Of course, in other embodiments, the etchant may not completely etch through the thickness of the third semiconductor layer to expose the porous semiconductor layer 14' below. The platform-defining mask layer can then be removed from the third semiconductor layer 16. By following the above process, the third semiconductor layer 16 can be shaped to provide a growth surface 11, which includes a platform surface 30 and sidewall surfaces 32 formed by the third semiconductor layer 16.

[0092] The platform surface 30 of each monolithic growth stack can have any desired shape. The shape of each platform surface 30 can be determined by the shape of the platform-defining mask layer. For example, the platform surface 30 can have an elliptical, triangular, rectangular, or hexagonal shape, or indeed any regular or irregular polygonal shape. In some embodiments, each platform surface 30 of the LED array precursor can have the same shape, thereby providing a relatively uniform array of monolithic growth stacks. Of course, in other embodiments, the platform surfaces 30 can have different shapes.

[0093] The shape of the terrace surface 30 (i.e., the edge of the terrace surface 30) affects the shape of the sidewall surface 32 of the third semiconductor layer 16. For example, in the case where the terrace surface 30 has an elliptical shape, the sidewall surface 32 can be provided as a single continuous surface. In other embodiments, such as in the case where the terrace surface 30 has a regular or irregular polygonal shape, there can be multiple sidewall surfaces 32, one of which corresponds to each side of the regular or irregular polygonal shape of the terrace surface 30.

[0094] exist Figure 4 , a monolithically grown stack 10 is shown having sidewall surfaces 32 that extend substantially perpendicular to the terrace surface 30 of the third semiconductor layer 16. In other embodiments, the sidewall surfaces of the terrace structure can be formed to have different angles of inclination relative to the terrace surface 30. That is, the sidewall surface 30 can be inclined. In this way, the terrace structure formed by the third semiconductor layer 16 can have a trapezoidal cross-section in a plane perpendicular to the terrace surface 30.

[0095] exist Figure 4In the figure, the terrace structure may extend from the porous semiconductor layer 14' by a distance of no more than 100 μm. Thus, in some embodiments, the thickness of the third semiconductor layer 16 in a direction perpendicular to the terrace surface may be no more than 10 μm. In particular, in some embodiments, the terrace structure may extend from the porous semiconductor layer 14' by a distance of between 1 μm and 5 μm. Thus, in some embodiments, the third semiconductor layer 16 may have a thickness in a direction perpendicular to the terrace surface of approximately 1 μm to 5 μm.

[0096] In some embodiments of the present disclosure, the terrace surfaces 30 may each have a surface area dimension of at least 1 μm x 1 μm. Therefore, to fully relax the terrace surface, an elastic deformation mechanism would be insufficient. That is, the propagation of misfit dislocations may provide a mechanism by which the terrace surface may be strain-relaxed to a desired lattice constant. Importantly, the presence of the porous semiconductor layer 14' provides a region in which misfit dislocations preferentially propagate as half-loop dislocations, thereby providing a terrace structure with a reduced defect density. Further information on misfit dislocations at III-nitride heterointerfaces may be found at least in "Basal-plane SlipinInGaN / GaN Hetero Structures in the Presence of Threading Dislocations, Applied Physics Letters, vol. 90, 2007".

[0097] In some embodiments, platform surfaces 30 may each have a surface area dimension of no greater than 100 μm x 100 μm.

[0098] After forming the terrace structure in the third semiconductor layer 16 , the layers of the monolithically grown stack are subjected to a heat treatment process to increase the in-plane lattice constant of the growth surface of the monolithically grown stack 10 .

[0099] The heat treatment process includes heating the third semiconductor layer 16 of the monolithic growth stack 10 to a strain relaxation temperature. The strain relaxation temperature causes the third semiconductor layer 16 to relax strain on the porous semiconductor layer 14'. Therefore, after the heat treatment process, the in-plane lattice constant of the growth surface 11 of the third semiconductor layer 16 will increase.

[0100] The heat treatment process allows the third semiconductor layer 16 to relax strain, such that the in-plane lattice constant of the third semiconductor layer 16 increases relative to the in-plane lattice constant of the as-deposited third semiconductor layer 16 .

[0101] In some embodiments, the heat treatment process includes heating the third semiconductor layer 16 from room temperature to a strain relaxation temperature. The strain relaxation temperature is a temperature sufficient to cause deformation of the compressively strained third semiconductor layer 16. For example, in some embodiments, the strain relaxation temperature can be a temperature of at least 500°C. Thus, the third semiconductor layer can be heated to a temperature at which the third semiconductor layer releases the mechanical potential energy generated by its compression. The strain relaxation of the third semiconductor layer 16 may result in the formation of (misfit) dislocations toward the interface between the third semiconductor layer 16 and the second semiconductor layer 14. As a result of the heat treatment process, strain relaxation can occur by propagating misfit dislocations substantially throughout the c-plane of the porous semiconductor layer 14' toward or at the interface between the porous semiconductor layer 14' and the third semiconductor layer 16, rather than in a direction transverse to the c-plane (i.e., misfit dislocation slip in the c-plane). The propagation of the dislocations releases at least some of the strain in the newly formed third semiconductor layer 16, causing the third semiconductor layer 16 to relax. Thus, the third semiconductor layer 16 is strain-relaxed by the propagation of misfit dislocations rather than by the propagation of screw dislocations. Thus, the heat treatment process can reduce the strain in the region of the third semiconductor layer 16 above the narrow band of propagating dislocations. The presence of pores and dangling bonds in the porous semiconductor layer 14' improves the propagation of misfit dislocations in the porous semiconductor layer 14'. In this way, the third semiconductor layer 16 effectively strain relaxes (i.e., slides) on top of the porous semiconductor layer 14'. Further discussion of the propagation of misfit dislocations can be found in at least Mei et al., Basal-plane Slip in InGaN / GaN Hetero Structures in the Presence of Threading Dislocations, Applied Physics Letters, vol. 90, 2007, and Floro JA et al., Misfit Dislocation Formation in the AlGaN / GaN Heterointerface, Journal of Applied Physics, vol. 96, 2004.

[0102] It should be understood that in embodiments where the third semiconductor layer 16 forms a coherent interface with the second semiconductor layer 14 , the thermal treatment process causes the interface between the second semiconductor layer 14 and the third semiconductor layer 16 to no longer be a coherent interface.

[0103] The heat treatment process can be provided by any suitable method of annealing the material. For example, the heat treatment step can be provided by heating the third semiconductor layer 16 from room temperature to a first strain relaxation temperature. The third semiconductor layer 16 can be maintained at the first strain relaxation temperature for a first time period. The third semiconductor layer 16 can then be cooled back to room temperature. The heat treatment step can be performed in air, for example on a hot plate or in an oven. The heat treatment process can also be performed in a controlled atmosphere. In a controlled atmosphere, atmospheric compounds such as oxygen and water can be significantly reduced or completely eliminated. For example, the controlled atmosphere can be an NH3, Ar, or N2 atmosphere. In some embodiments, the heat treatment process can be formed under a controlled atmosphere including N2 and NH3. Performing the heat treatment process under a controlled atmosphere can reduce or eliminate any undesirable chemical reactions that occur on the surface of the third semiconductor layer 16 during the heat treatment process. For example, in some embodiments, the heat treatment process can be performed immediately before the process of forming the monolithic LED stack (i.e., in situ in the MOCVD reactor).

[0104] In some embodiments, the heat treatment process may heat the third semiconductor layer 16 to a first strain relaxation temperature of at least 500°C. In some embodiments, the first strain relaxation temperature may be at least 800°C, 950°C, 1000°C, or 1050°C. The first time period may be at least 5 minutes. In some embodiments, the first time period may be at least: 10 minutes, 20 minutes, 30 minutes, or 1 hour. For example, in some embodiments, the heat treatment step may include heating the third semiconductor layer 16 to 800°C, maintaining the third semiconductor layer at this temperature for 1 hour, and then cooling to room temperature. At a higher first strain relaxation temperature, the first time period may be shortened.

[0105] By performing the heat treatment step after the porosity treatment process, misfit dislocations propagating at the interface between the third semiconductor layer 16 and the second semiconductor layer 14 can more easily propagate due to the presence of the voids in the second semiconductor layer 14 .

[0106] Next, a monolithic LED stack 20 may be formed on the growth surface 11 of each monolithically grown stack 10 .

[0107] For each LED precursor 1, a monolithic LED stack 20 is formed on the growth surface 11. Figure 5 As shown, the monolithic LED stack 20 covers the terrace surface 30 and the sidewall surface 32. The monolithic LED stack 20 includes a plurality of layers, wherein each layer includes a group III nitride. In some embodiments, the group III nitride layer includes one or more of AlInGaN, AlGaN, InGaN, and GaN. Figure 5In the illustrated first embodiment, the monolithic LED stack 20 includes a fourth semiconductor layer 40 , an active layer 22 , and a p-type semiconductor layer 24 .

[0108] like Figure 5 As shown, a fourth semiconductor layer 40 is formed on the growth surface 11 of the monolithic growth stack 10. Thus, the fourth semiconductor layer 40 covers the terrace surface 30 of the third semiconductor layer 16 and the sidewall surface 32 of the third semiconductor layer 16. In this way, the fourth semiconductor layer 40 is formed on the third semiconductor layer 16 on the side of the third semiconductor layer 16 opposite to the porous semiconductor layer 14'.

[0109] The fourth semiconductor layer 40 may be formed on the growth surface 11 by any suitable method for growing Group III nitrides. Figure 5 In the embodiment of FIG. 1 , the fourth semiconductor layer 40 is monolithically formed on the growth surface 11 (ie, an overgrowth method). Figure 5 As shown, the fourth semiconductor layer 40 may be formed as a substantially continuous layer that substantially covers the entire growth surface 11 .

[0110] like Figure 5 As shown, the fourth semiconductor layer 40 is formed on the growth surface 11 so that it forms a generally inclined sidewall portion 42 extending from a terrace portion 44 of the fourth semiconductor layer 40 on the terrace surface 30 of the third semiconductor layer 16 toward the porous semiconductor layer 14'. The fourth semiconductor layer 40 also includes a body portion 46 that extends over the surface of the porous semiconductor layer 14' between the inclined sidewall portions 42 of each monolithic LED precursor 1.

[0111] Thus, the fourth semiconductor layer 40 can be overgrown on the terrace structure of the third semiconductor layer 16 to provide a III-nitride semiconductor layer including a fourth semiconductor layer terrace surface 44 surrounded by an inclined sidewall surface 42. In this way, the fourth semiconductor layer 40 can be overgrown on the terrace structure of the third semiconductor layer 16 to form a column having a regular trapezoidal cross-section in a plane perpendicular to the terrace surface 30, wherein the fourth semiconductor layer terrace surface 44 forms a substantially flat upper surface of the trapezoidal cross-section. A regular trapezoidal cross-section means that the top of the column is narrower than the bottom and has a substantially flat upper surface with a slope on the side. This may result in a frustroconical shape, or a frustropyramidal shape having three or more sides, typically six sides.

[0112] In some embodiments, for example, Figure 5As shown, the sidewall portion 42 of the fourth semiconductor layer 40 has a substantially consistent angle (α) with a plane parallel to the terrace surface 30 of the growth surface 11. That is, the angle α between the sidewall surface 42 of the fourth semiconductor layer and the plane parallel to the terrace surface 30 does not vary significantly. For example, in some embodiments, the angle α may be at least 50 degrees to no greater than 70 degrees, and in some embodiments, the angle α may be between 58 degrees and 64 degrees.

[0113] Thus, in some embodiments, the sidewall portion 42 of the fourth semiconductor layer can be tilted relative to the (0001) plane of the crystal structure of the third semiconductor layer 16. The tilted sidewall can be oriented generally along the {110 1} or {110 2} planes of the wurtzite crystal and exhibit a reduced polarization field compared to a C-plane surface (semi-polar surface).

[0114] Alternatively, as discussed with respect to the second embodiment, for example, the fourth semiconductor layer 40 may be formed as a substantially discontinuous layer that covers the terrace surfaces 30 and sidewall surfaces 32 of each monolithically grown stack 10 and extends over the region of the porous semiconductor layer 14′ surrounding the terrace structure of the third semiconductor layer 16. The fourth semiconductor layer 40 may be deposited using any suitable process for fabricating Group III nitride films, such as MOCVD or MBE.

[0115] The fourth semiconductor layer 40 includes a group III nitride. Figure 5 In some embodiments, the fourth semiconductor layer 40 includes GaN. In some embodiments, the fourth semiconductor layer 40 may be n-type doped. The fourth semiconductor layer 40 may be n-type doped using a suitable dopant such as Si or Ge. Figure 5 In certain embodiments, the fourth semiconductor layer 40 is not intentionally doped. Thus, the fourth semiconductor layer 40 can be a (substantially) undoped layer. By "substantially undoped," it is understood that the Group III nitride does not include any significant amount of doping elements, while recognizing that some impurities may be present due to the manufacturing process. By forming the fourth semiconductor layer 40 from an undoped semiconductor, the flow of charge carriers through the LED precursor can be more effectively confined within the terrace structure.

[0116] By growing a fourth semiconductor layer 40 on the growth surface provided by the third semiconductor layer 16, the fourth semiconductor layer 40 can have a crystal structure consistent with that of the third semiconductor layer 16. For example, when the terrace surface 30 of the third semiconductor layer 16 is aligned with the (0001) plane of the group-III nitride, the fourth semiconductor layer 40 formed on the terrace surface 30 can form a coherent interface and have a similar (0001) crystal orientation. Thus, the in-plane lattice constant of the fourth semiconductor layer 40 on the terrace surface 30 can correspond to the in-plane lattice constant of the third semiconductor layer 16 at the terrace surface 30.

[0117] As Figure 5 shown, an active layer 22 can then be formed on the fourth semiconductor layer 40. The active layer 22 is configured to generate light of a first wavelength and is part of a monolithic LED stack 20.

[0118] The active layer 22 is configured to generate light of a first wavelength and is part of a monolithic LED stack 20. In Figure 5 an embodiment, the active layer 22 can include one or more quantum well layers (not shown). Thus, the active layer 22 can be a multi-quantum well layer. The quantum well layers within the active layer 22 can each include a group-III nitride semiconductor, such as a group-III nitride alloy including In. In Figure 5 an embodiment, the active layer 22 includes alternating layers of GaN and In<> Z Ga<> 1-Z Z, where 0 < Z ≤ 1. In particular, in some embodiments, the active layer can include In<> Z Ga<> 1-Z N layers, where 0.2 ≤ Z ≤ 0.5. Thus, the active layer 22 of the monolithic LED stack can be configured to output light having a wavelength of at least 525 nm. The thickness and In content of the quantum well layers can be controlled to control the wavelength of the light generated by the active layer 22. The active layer 22 can be formed as a continuous layer covering most of the exposed growth surface. The active layer 22 can be deposited using any suitable process for fabricating group-III nitride thin films, such as MOCVD or MBE.

[0119] In some embodiments, the active layer 22 can include a strain interface layer (not shown). As is known in the art, a strain interface layer can be formed between the growth surface 11 and the multi-quantum well structure.

[0120] The deposition of the active layer 22 on the fourth semiconductor layer 40 can occur at a relatively high deposition rate on the terrace portion 44 of the fourth semiconductor layer, and at a significantly lower deposition rate on the inclined sidewall portion 42 of the fourth semiconductor layer. This effect is due to the different crystal plane alignments of the different surfaces, resulting in the active layer 22 being thicker above the terrace surface 30 than on the inclined sidewall portion 42. This effect is described in more detail in GB1811190.6.

[0121] Thus, the active layer 22 may include an active layer terrace portion 23 extending over the terrace portion 44 of the fourth semiconductor layer 40. The active layer 22 may also include an active layer sidewall portion 28 extending over the sidewall portion 42 of the fourth semiconductor layer 40. The active layer sidewall portion 28 surrounds the active layer terrace portion 23 and extends from the active layer terrace portion 23 toward the porous semiconductor layer 14'. In this way, the active layer sidewall portion 28 is generally aligned with the sloped sidewall portion 42 of the fourth semiconductor layer. The active layer 22 may also include an active layer bulk portion 29 extending over the bulk portion 46 of the fourth semiconductor layer 40 between the active layer sidewall portions 28 of each monolithic LED precursor 1.

[0122] It will be appreciated that various methods for forming a monolithic LED stack 20 including an active layer 22 are known to those skilled in the art. Figures 1 to 5 The method described is only one example of possible methods of forming a monolithic LED stack 20. For example, in Figure 5 In some embodiments, the active layer 22 may have a thickness of at least 30 nm and no more than 150 nm in a direction substantially perpendicular to the growth surface. In some embodiments, the active layer 22 may have a thickness of at least 40 nm and no more than 60 nm in a thickness direction.

[0123] The other layers of the monolithic LED stack 20 may then be deposited on the active layer 22 on the side of the active layer 22 opposite the monolithically grown stack 10. For example, Figure 5 As shown, a p-type semiconductor layer 24 is then formed on the active layer 22 .

[0124] like Figure 5 As shown, a p-type semiconductor layer 24 is disposed on the active layer 22. The p-type semiconductor layer 24 comprises a Group III nitride. The p-type semiconductor layer 24 is doped with a suitable electron acceptor, such as Mg. The p-type semiconductor layer 24 can be formed as a substantially continuous layer covering a majority (e.g., the entirety) of the exposed surface of the active layer 24. The p-type semiconductor layer can be formed using any suitable process for manufacturing Group III nitride thin films, such as MOCVD or MBE.

[0125] like Figure 5As shown, the p-type semiconductor layer 24 is formed on the exposed surface of the active layer 22. Figure 5 In the embodiment of the present invention, the p-type semiconductor layer 24 is a substantially continuous layer. Of course, in other embodiments, the p-type semiconductor layer 24 can be formed as a discontinuous layer.

[0126] The p-type semiconductor layer 24 may have a thickness of at least 50 nm, 60 nm, 70 nm, 80 nm, or 100 nm (in the thickness direction perpendicular to the platform surface 30). In addition, the p-type semiconductor layer 24 may have a thickness of no greater than 300 nm, 250 nm, or 200 nm. For example, in Figure 5 In the embodiment of FIG. 5 , the p-type semiconductor layer 24 may have a thickness of approximately 100 nm.

[0127] The p-type semiconductor layer 24 of each LED precursor can include a p-type terrace portion 25 and one or more p-type sidewall portions 26. The p-type terrace portion 25 can be substantially aligned with the terrace surface 30 of the monolithically grown stack 10. The p-type sidewall portion 26 surrounds the p-type terrace portion 25 and extends from the p-type terrace portion 25 toward the porous semiconductor layer 14'. In this way, the p-type sidewall portion 26 is substantially aligned with the sloped sidewall portion 42 of the fourth semiconductor layer. The p-type semiconductor layer 24 can also include a p-type body portion 27 that extends over the active layer body portion 29 between the p-type sidewall portions 26 of each monolithic LED precursor 1.

[0128] therefore, Figure 5 An embodiment of an LED array precursor according to the present disclosure is shown. The LED array precursor can be manufactured according to the method described above. According to the definition of the term precursor in the present disclosure, it should be understood that Figure 5 The LED array precursor may be subjected to further manufacturing steps in order to form electrical contacts to each LED precursor. It will therefore be appreciated that the LED array precursor may be subjected to further manufacturing steps in order to provide an LED and / or LED array.

[0129] For example, to provide independent control of one of the monolithic LED precursors according to the first embodiment, at least a portion of the p-type terrace portion 25, or a portion of the p-type sidewall portion 26 surrounding the terrace surface 30, can be selectively removed. Thus, the p-type terrace portion 25 of each monolithic LED precursor 1 can be supplied with power (i.e., current / voltage) independently of the other p-type terrace portions 25. This selective removal process can be performed as part of a process for forming electrical contacts with the monolithic LED precursor 1.

[0130] Specifically, in some embodiments, the monolithically grown stack 10 can be sized to provide a micro-LED precursor and / or a micro-LED array precursor. For example, in some embodiments, the monolithic LED stack 20 of each micro-LED precursor can have a footprint of less than 100 μm x 100 μm on the first semiconductor layer 12. Thus, each LED precursor can be a micro-LED precursor, wherein the monolithic LED stack 20 has a surface area dimension of less than 100 μm x 100 μm in a plane aligned with the first semiconductor layer 12.

[0131] According to the reference Figures 1 to 5 The method described above provides an LED precursor 1. Thus, according to an embodiment of the present disclosure, the LED precursor 1 is Figure 5 Shown in. Figure 5 The LED precursor 1 includes a monolithically grown stack 10 and a monolithic LED stack 20. The monolithically grown stack 10 includes a first semiconductor layer 12, a second semiconductor layer 14, and a third semiconductor layer 16. The monolithic LED stack includes an active layer 22 and a p-type semiconductor layer 24. Each layer in the monolithically grown stack 10 and the monolithic LED stack 20 can have properties according to the discussion of the method of forming the LED precursor 1 above.

[0132] According to a second embodiment of the present disclosure, an LED precursor 1 is provided. In some embodiments, a plurality of LED precursors 1 arranged to form an LED array precursor may be provided. For example, a LED precursor 1 may be provided as shown in FIG. Figure 3 、 6 The method shown in FIG. 7 forms an LED array precursor including a plurality of LED precursors according to the second embodiment.

[0133] The method according to the second embodiment of the present disclosure includes forming a monolithic growth stack 10 and a monolithic LED stack 20 for each LED precursor 1. Similar to the first embodiment, the monolithic LED stack 20 is formed on the growth surface 11 of the corresponding monolithic growth stack 10. Similar features of the first and second embodiments have corresponding reference numerals. Figure 3 Schematic diagram of the layers used to form the monolithic growth stack 10 of the second embodiment is shown. Figure 3 As shown, the monolithic growth stack 10 is formed by the first semiconductor layer 12, the porous semiconductor layer 14' and the third semiconductor layer 16. As previously discussed, Figure 3 The porous semiconductor layer 14' in FIG. 1 is formed from the second semiconductor layer 14, which has undergone a porosity treatment process.

[0134] Similar to the method of the first embodiment, the third semiconductor layer 16 undergoes a selective removal step prior to the heat treatment step to form a plurality of terrace structures. Each terrace structure formed using the selective removal step can be used to define an LED precursor of an LED array precursor. The terrace structures can be arranged in a two-dimensional array, as discussed above in the first embodiment. The method of the second embodiment differs from the method of the first embodiment in that the selective removal step removes a portion of the third semiconductor layer 16 surrounding each terrace structure and a portion of the porous semiconductor layer 14'.

[0135] For example, Figure 6 As shown, the selective removal process selectively removes a portion of the third semiconductor layer 16 from the growth surface 11 through the thickness of the third semiconductor layer 16 (in a thickness direction perpendicular to the terrace surface 30) and through the thickness of the porous semiconductor layer 14'. Therefore, the growth surface 11 of each monolithic growth stack 10 includes the terrace surface of the third semiconductor layer 16, the sidewall surface 32 of the third semiconductor layer 16, and the porous sidewall surface 34 of the porous semiconductor layer 14'. Therefore, as shown in FIG. Figure 6 As shown, the third semiconductor layer 16 and the porous semiconductor layer 14' are selectively removed throughout their thickness, so that the first surface 13 of the first semiconductor layer 12 is exposed between each terrace structure. The selective removal process can be performed using an etchant in a manner similar to the selective removal process of the first embodiment described above. In some embodiments, the selective removal process can also selectively remove portions of the first semiconductor layer 12. In this way, the terrace structure can be defined by the monolithic growth stack 10 (in Figure 6 indicated by dotted lines).

[0136] Similar to the first embodiment, the shape of the platform surface 30 in the third embodiment can have any suitable shape. In addition, the sidewall surface 32 and the porous sidewall surface 34 can be formed to have any inclination angle relative to the platform surface 30. In this way, the platform structure formed by the third semiconductor layer 16 and the porous semiconductor layer 14' can have a trapezoidal cross-section in a plane perpendicular to the platform surface 30.

[0137] After the terrace structure is formed, a heat treatment process is performed. The heat treatment process can be performed substantially as described in the first embodiment. The heat treatment process allows the third semiconductor layer 16 to relax strain, wherein the in-plane lattice constant of the growth surface increases. After strain relaxation, the interface between the third semiconductor layer 16 and the porous semiconductor layer 14' is no longer coherent.

[0138] Next, a monolithic LED stack 20 may be formed on the growth surface 11 of each monolithically grown stack 10 .

[0139] In some embodiments, the monolithic LED stack 20 can be grown as a substantially continuous layer, for example as described above with respect to the first embodiment.

[0140] In other embodiments, such as shown in the second embodiment, the monolithically grown stack 20 may be formed as a generally discontinuous layer.

[0141] like Figure 6 As shown, after forming the monolithic growth stacks 10, a mask layer 50 is provided over the exposed surface of the porous semiconductor layer 14'. The mask layer 50 is configured to prevent or significantly reduce the growth of the fourth semiconductor layer 40 nucleating on (i.e., starting on) the mask layer 50. The mask layer is configured to limit the growth surface 11 of each monolithic growth stack 10 to the terrace surface 30 and sidewall surfaces of the monolithic growth stack 10. Thus, the mask layer 50 in the second embodiment is configured to reduce or prevent the formation of the bulk portion 46 of the fourth semiconductor layer 40. Therefore, the use of the mask layer 50 is one example of a method of forming a discontinuous monolithic LED stack 20.

[0142] In some embodiments, the mask layer 50 may be made of SiO2, SiN X or any other suitable mask material such as a dielectric material (i.e., a dielectric layer). In some embodiments, the mask layer 50 may have a thickness of at least 50 nm in a direction perpendicular to the platform surface 30. In some embodiments, the mask layer 50 may have a thickness of no greater than 500 nm in a direction perpendicular to the platform surface 30.

[0143] Next, a monolithic LED stack 20 may be formed on the (discontinuous) growth surface 11 of the array of monolithically grown stacks 10. The resulting structure may be as shown in FIG. Figure 7 As shown. The fourth semiconductor layer 40 is formed on the growth surface 11 so that it forms a generally inclined sidewall portion 42 extending from a terrace portion 44 of the fourth semiconductor layer 40 on the terrace surface 30 of the third semiconductor layer 16 toward the porous semiconductor layer 14'. The fourth semiconductor layer 40 does not grow on the mask layer 50, or grows at a significantly reduced rate. It should be understood that the region of the fourth semiconductor layer 40 that overlaps with the mask layer 50 is produced by the growth of the fourth semiconductor layer 40 extending from the sidewall surface 32 of the terrace structure.

[0144] Thus, the fourth semiconductor layer 40 can be overgrown on the terrace structure of the third semiconductor layer 16 to provide a III-nitride semiconductor layer including a fourth semiconductor layer terrace surface 44 surrounded by an inclined sidewall surface 42. In this way, the fourth semiconductor layer 40 can be overgrown on the terrace structure of the third semiconductor layer 16 to form a column having a regular trapezoidal cross-section in a plane perpendicular to the terrace surface 30, wherein the fourth semiconductor layer terrace surface 44 forms a substantially flat upper surface of the trapezoidal cross-section. A regular trapezoidal cross-section means that the top of the column is narrower than the bottom and has a substantially flat upper surface with a slope on the side. This may result in a frustroconical shape, or a frustropyramidal shape having three or more sides, typically six sides.

[0145] The fourth semiconductor layer 40 may be formed of similar materials and using similar processes as described above as used in the first embodiment.

[0146] The active layer 22 and the p-type semiconductor layer 25 may then be formed on the fourth semiconductor layer 40 .

[0147] like Figure 7 As shown, for each monolithic LED precursor 1, the active layer 22 includes an active layer terrace portion 23 and an active layer sidewall portion 28. The active layer 22 can be formed using a similar process as described in the first embodiment.

[0148] like Figure 7 As shown, the p-type semiconductor layer 24 includes a p-type terrace portion 25 and a p-type sidewall portion 26. The p-type semiconductor layer 24 can be formed using a similar process as described in the first embodiment.

[0149] Therefore, the LED array precursor including the plurality of LED precursors 1 according to the second embodiment of the present disclosure can be formed by the above method.

[0150] According to a third embodiment of the present disclosure, there is provided a method of forming an LED array precursor including a plurality of LED precursors 1 . Figure 3 、 8 9 show schematic diagrams explaining the process of forming an LED array precursor according to a third embodiment. The method according to the third embodiment includes forming a monolithic growth stack 10 and a monolithic LED stack 20 for each LED precursor. Similar to the first and second embodiments, the monolithic LED stack 20 is formed on the growth surface 11 of the corresponding monolithic growth stack 10. Similar features of the first, second, and third embodiments have corresponding reference numerals. As previously described, Figure 3 A schematic diagram of the layers used to form the monolithic growth stack 10 is shown. Figure 3As shown, the second semiconductor layer 14 has undergone a porosity treatment process such that the second semiconductor layer 14 is a porous semiconductor layer 14 ′.

[0151] In the method according to the third embodiment, the third semiconductor layer 16 is further processed to define a terrace structure for each LED precursor. The method according to the third embodiment can be performed substantially as described with respect to the present disclosure. Figure 4 and as described in the first embodiment, or substantially as described with respect to Figure 6 The following description will focus on the process according to the first embodiment and the second embodiment. Figure 4 The selective removal process is shown as being performed, although the skilled person will appreciate that the method of the fourth embodiment is equally applicable to the selective removal process described in relation to the third embodiment.

[0152] After the selective removal step, the monolithically grown stack 10 is subjected to a heat treatment process in order to relax the strain of the third semiconductor layer 16. The heat treatment process may be performed substantially as described above with respect to other embodiments of the present disclosure.

[0153] After the heat treatment step, a mask layer can be selectively formed on the growth surface 11 of the monolithically grown stack 10, wherein the mask layer 50 includes holes aligned with the terrace surface 30 of each monolithically grown stack 10. In this way, the mask layer 50 is provided to cover the sidewall surface 32 of each terrace structure, but does not cover the terrace surface 30 of the third semiconductor layer 16. In effect, the mask layer serves to restrict the growth of the monolithic LED stack to the exposed terrace surface 30 of each monolithically grown stack 10.

[0154] For example, Figure 8 As shown, the mask layer 50 is formed on the sidewall surface 32 of the third semiconductor layer and also on the porous surface 15 of the porous semiconductor layer 14'. Therefore, the mask layer 50 includes: a sidewall portion 52 that covers the sidewall portion of the third semiconductor layer 16; and a filling portion 54 that extends over the previously exposed surface of the porous semiconductor surface 15. It should be understood that Figure 8 In some embodiments, the mask layer 50 can be a single continuous layer including a plurality of openings for each platform surface 30 of the platform structure. The openings for each platform surface 30 can be formed by using a mask layer to prevent the mask layer 50 from being formed on the platform surface 30. For example, in some embodiments, a platform-defining mask layer (not shown) used to define each platform structure can also be used to define the openings of the mask layer 50. That is, both the selective removal process (for forming the platform structure) and the formation of the mask layer 50 can be performed before removing the platform-defining mask layer. Alternatively, a separate platform-defining mask layer can be used for both the selective removal process and the formation of the mask layer 50.

[0155] In some embodiments, the mask layer 50 may be made of SiO2, SiN X or any other suitable mask material such as a dielectric material (i.e., a dielectric layer). In some embodiments, the fill portion 54 of the mask layer 50 can have a thickness of at least 50 nm in a direction perpendicular to the platform surface. In some embodiments, the fill portion 54 of the mask layer 50 can have a thickness of no greater than 500 nm in a direction perpendicular to the platform surface 30. It should be understood that the thickness of the sidewall portions 52 of the mask layer 50 (perpendicular to the surface on which they are formed) can be similar to the thickness of the fill portion 54. Of course, it should be understood that the thickness of the sidewall portions 54 of the mask layer 50 can be slightly different, being thicker or thinner than the fill portion 52 due to different orientations of the sidewall portions 54.

[0156] Next, a monolithic LED stack 20 may be formed on the growth surface of the monolithic growth stack 10. Figure 9 As shown, the growth surface 11 for each monolithically grown stack 10 is confined to the terrace surface 30. The presence of the mask layer 50 prevents or significantly reduces the growth of the monolithic LED stack 20 on the mask layer 50.

[0157] Therefore, if Figure 9 As shown, a monolithic growth stack 20 is formed on each growth surface 11 of the monolithic growth stack 10. Figure 9 As shown, the monolithic LED stack 20 covers each platform surface 30. Compared to the second and third embodiments, the monolithic LED stack 20 does not extend above the sidewall surface 32 of the third semiconductor layer 16. Similar to the first, second, and third embodiments, the monolithic LED stack 20 includes multiple layers. Each layer of the monolithic LED stack 20 includes a group III nitride. Some embodiments of the group III nitride layer include one or more of AlInGaN, AlGaN, InGaN, and GaN. Figure 9 In the fourth embodiment shown, a monolithic LED stack 20 includes an active layer 20 and a p-type semiconductor layer 24 .

[0158] The active layer 22 may be formed using a method similar to that described with respect to the first, second, and third embodiments.

[0159] The p-type semiconductor layer 24 may be formed in a manner similar to the p-type layer 24 described in the first, second, and third embodiments.

[0160] Thus, an LED array precursor comprising a plurality of LED precursors can be formed according to the method of the fourth embodiment. According to the method of the fourth embodiment, a monolithic LED stack is selectively formed on the terrace surface 30 of the monolithic growth stack 10, rather than on the region of the growth surface 11 covered by the mask layer 50.

Claims

1. A method for manufacturing an LED precursor, comprising: forming a monolithic growth stack having a growth surface; as well as forming a monolithic LED stack on a growth surface of the monolithic growth stack, in: a) forming the monolithic growth stack comprising: forming a first semiconductor layer including a Group III nitride; A second semiconductor layer is formed on the first semiconductor layer, wherein the second semiconductor layer includes a first group III nitride containing a donor dopant, so that the second semiconductor layer has a thickness of at least 5×10 18 cm -3 donor density; forming a third semiconductor layer on a side of the second semiconductor layer opposite the first semiconductor layer, wherein the third semiconductor layer provides a growth surface for the monolithic growth stack, the third semiconductor layer comprising a second Group III nitride different from the first Group III nitride, such that the third semiconductor layer is formed on the second semiconductor layer under compressive strain; and selectively removing a portion of the third semiconductor layer from the growth surface through the thickness of the third semiconductor layer so that the growth surface of the monolithic growth stack includes a terrace surface of the third semiconductor layer and sidewall surfaces of the third semiconductor layer surrounding the terrace surface, Wherein, after forming the third semiconductor layer: performing a porosity treatment on the second semiconductor layer to increase the area porosity of the second semiconductor layer to at least 15%; and heating the third semiconductor layer to a strain relaxation temperature so that the third semiconductor layer relaxes, thereby increasing the in-plane lattice constant of the terrace surface; and b) forming the monolithic LED stack comprising: forming a fourth semiconductor layer comprising a Group III nitride on a growth surface of the monolithic growth stack such that the fourth semiconductor layer covers a terrace surface of the third semiconductor layer; forming an active layer on the fourth semiconductor layer, wherein the active layer comprises a plurality of quantum well layers, each quantum well layer comprising a group III nitride; A p-type semiconductor layer including Group III nitride is formed on the active layer.

2. The method according to claim 1, wherein The second semiconductor layer includes GaN.

3. The method according to claim 1, wherein The third semiconductor layer includes In X Ga 1-X N, where 0<X≤1。 4. The method according to claim 1, wherein Each quantum well layer of the active layer includes In Z Ga 1-Z N, where 0.2<Z≤0.5。 5. The method according to any one of claims 1 to 4, wherein The second semiconductor layer is subjected to a porosity treatment before selectively removing a portion of the third semiconductor layer from the growth surface.

6. The method according to any one of claims 1 to 4, wherein The third semiconductor layer is selectively removed such that a growth surface of the monolithic growth stack includes a surface of the second semiconductor layer.

7. The method according to any one of claims 1 to 4, wherein Forming the monolithic growth stack further comprises: A portion of the second semiconductor layer aligned with the selectively removed portion of the third semiconductor layer is selectively removed such that a growth surface of the monolithic growth stack includes sidewall surfaces of the second semiconductor layer.

8. The method according to claim 7, wherein The second semiconductor layer is selectively removed so that a sidewall surface of the second semiconductor layer is aligned with a sidewall surface of the third semiconductor layer.

9. The method according to claim 7, wherein The second semiconductor layer is selectively removed so that the growth surface includes a portion of a surface of the first semiconductor layer.

10. The method according to any one of claims 1 to 4, wherein The fourth semiconductor layer includes GaN.

11. The method according to any one of claims 1 to 4, wherein The fourth semiconductor layer is formed on the growth surface to provide an inclined sidewall portion extending from a terrace portion of the fourth semiconductor layer on a terrace surface of the third semiconductor layer toward the second semiconductor layer.

12. The method according to claim 5, wherein: Forming the monolithic growth stack further comprises: A mask layer is selectively formed on a growth surface of the monolithic growth stack, the mask layer including openings aligned with terrace surfaces of the monolithic growth stack.

13. The method according to claim 12, wherein The monolithic LED stack is selectively formed on a terrace surface of the monolithic growth stack, but not on the growth surface covered by the mask layer.

14. An LED precursor, comprising: a monolithic growth stack having a growth surface; as well as a monolithic LED stack disposed on a growth surface of said monolithic growth stack, in: a) The monolithic growth stack comprises: a first semiconductor layer comprising a Group III nitride; A second semiconductor layer is provided on the first semiconductor layer, wherein the second semiconductor layer comprises a first group III nitride containing a donor dopant, so that the second semiconductor layer has a thickness of at least 5×10 18 cm -3 A donor density of 100 nm, wherein the second semiconductor layer has an area porosity of at least 15% and a first in-plane lattice constant; and a third semiconductor layer disposed on a side of the second semiconductor layer opposite to the first semiconductor layer, the third semiconductor layer including a second Group III nitride different from the first Group III nitride, wherein the monolithic growth stack includes a platform structure, the platform structure includes the third semiconductor layer, so that the growth surface includes a platform surface of the third semiconductor layer and a sidewall surface of the third semiconductor layer surrounding the platform surface, and the sidewall surface of the third semiconductor layer is inclined relative to the platform surface, wherein the terrace surface of the third semiconductor layer has a second in-plane lattice constant greater than the first in-plane lattice constant; and b) The monolithic LED stack comprises: a fourth semiconductor layer disposed on the growth surface of the monolithic growth stack such that the fourth semiconductor layer covers the terrace surface of the third semiconductor layer and the sidewall surfaces of the third semiconductor layer; an active layer disposed on the fourth semiconductor layer, the active layer comprising a plurality of quantum well layers, each quantum well layer comprising a Group III nitride; and A p-type semiconductor layer including group III nitride is disposed on the active layer.

15. The LED precursor according to claim 14, wherein The second semiconductor layer includes GaN.

16. The LED precursor according to claim 14, wherein The third semiconductor layer includes In X Ga 1-X N, where 0<X≤1。 17. The LED precursor according to claim 14, wherein Each quantum well layer of the active layer includes In Z Ga 1-Z N, where 0.2<Z≤0.5。 18. The LED precursor according to any one of claims 14 to 17, wherein A sidewall surface of the third semiconductor layer is inclined in a direction transverse to the terrace surface.

19. The LED precursor according to any one of claims 14 to 17, wherein The mesa structure extends from the second semiconductor layer such that the growth surface includes the second semiconductor layer.

20. The LED precursor according to any one of claims 14 to 17, wherein A growth surface of the monolithic growth stack includes sidewall surfaces of the second semiconductor layer aligned with sidewall surfaces of the third semiconductor layer.

21. The LED precursor according to claim 20, wherein The mesa structure extends from the first semiconductor layer such that the growth surface includes a portion of a surface of the first semiconductor layer.

22. The LED precursor according to any one of claims 14 to 17, wherein The fourth semiconductor layer includes GaN.

23. The LED precursor according to any one of claims 14 to 17, wherein The fourth semiconductor layer is provided on the growth surface to provide an inclined sidewall portion extending from a terrace portion of the fourth semiconductor layer on a terrace surface of the third semiconductor layer toward the second semiconductor layer.

24. The LED precursor according to claim 18, wherein The monolithic growth stack further comprises: A mask layer is disposed on the growth surface of the monolithic growth stack, the mask layer including openings aligned with the terrace surfaces of the monolithic growth stack.

25. The LED precursor according to claim 24, wherein The monolithic LED stack is selectively disposed only on the platform surface of the monolithic growth stack.

26. The LED precursor according to any one of claims 14 to 17, wherein The LED precursor is a micro-LED precursor, wherein The surface area of ​​the monolithic LED stack in a plane aligned with the first semiconductor layer has dimensions less than 100 μm by 100 μm.

27. An LED array precursor, comprising: A plurality of LED precursors according to any one of claims 14 to 26, wherein the plurality of LED precursors are arranged in a two-dimensional array.

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