circuit board

Abstract

A printed circuit board according to an embodiment includes: an insulating layer; a circuit pattern disposed on a top surface of the insulating layer; a first solder resist disposed on the top surface of the insulating layer and having a height less than that of the circuit pattern; and a second solder resist disposed on the top surface of the first solder resist and including a first portion and a second portion, the first portion having a top surface lower than that of the circuit pattern, and the second portion having a top surface higher than that of the circuit pattern, wherein the circuit pattern includes: a plurality of first circuit patterns disposed on the top surface of a first region of the insulating layer; and a plurality of second circuit patterns disposed on the top surface of a second region of the insulating layer, the first portion of the second solder resist having a top surface lower than that of the first circuit patterns and being disposed between the plurality of first circuit patterns, and the second portion of the second solder resist having a top surface higher than that of the second circuit patterns between the plurality of second circuit patterns and being disposed to cover the plurality of second circuit patterns.

Description

Technical Field

[0001] The embodiments relate to a circuit board, and more specifically, to a circuit board in which the outermost circuit pattern can be supported by using solder resist. Background Technology

[0002] As electronic components become increasingly miniaturized, lighter, and more integrated, circuit linewidths are becoming smaller. In particular, with semiconductor chip design rules being integrated at the nanometer scale, the linewidths of packaging substrates or circuit boards on which semiconductor chips are mounted are decreasing to a few micrometers or smaller.

[0003] To increase the circuit integration of circuit boards, various methods have been proposed to miniaturize circuit linewidth. To prevent linewidth loss during the etching step of patterning after copper plating, semi-additive process (SAP) and improved semi-additive process (MSAP) methods have been proposed.

[0004] Subsequently, the embedded trace substrate (hereinafter referred to as "ETS") method, in which copper foil is embedded in an insulating layer to achieve finer circuit patterns, has been used in the art. The ETS method is fabricated by embedding copper foil circuits in an insulating layer, rather than by forming copper foil circuits on the surface of the insulating layer. Therefore, there is no circuit loss due to etching, which is beneficial for finer circuit spacing.

[0005] Meanwhile, efforts are underway to develop and improve fifth-generation (5G) communication systems, or pre-5G communication systems, to meet the demands for wireless data services. Here, 5G communication systems utilize ultra-high frequency (mm wave) bands (sub-6 gigabit (6GHz), 28 gigabit (28GHz), 38 gigabit (38GHz), or higher frequencies) to achieve high data rates.

[0006] Furthermore, to mitigate path loss and increase propagation distance of radio waves in the VHF band, convergence technologies such as beamforming, massive MIMO, and array antennas are being developed for 5G communication systems. Considering that these frequency bands can be composed of hundreds of active antennas of different wavelengths, the antenna system becomes relatively large.

[0007] Because these antennas and AP modules are patterned or mounted on a circuit board, low loss of the circuit board is very important. This means that the several substrates that make up the active antenna system (i.e., antenna substrate, antenna feed substrate, transceiver substrate, and baseband substrate) must be integrated into a compact unit.

[0008] Furthermore, as described above, circuit boards used in 5G communication systems are manufactured with a trend towards thinness and compactness, resulting in increasingly intricate circuit patterns.

[0009] However, traditional circuit boards, including those with fine circuit patterns, have a structure where the outermost circuit pattern protrudes from the insulating layer, and therefore, the outermost circuit pattern is prone to collapse. Summary of the Invention

[0010] [Technical Issues]

[0011] The embodiments provide a circuit board with a novel structure and a method for manufacturing the circuit board.

[0012] Furthermore, the embodiments provide a circuit board and a method of manufacturing the circuit board, which can improve reliability by providing a structure including solder resist capable of supporting the circuit pattern arranged at the outermost portion.

[0013] Furthermore, the embodiments provide a circuit board and a method of manufacturing the circuit board, the circuit board being able to provide a structure including a solder resist that is able to support the circuit pattern in the SR exposed area of ​​the circuit pattern arranged at the outermost portion.

[0014] Furthermore, the embodiments provide a circuit board and a method of manufacturing the circuit board, which minimizes the occurrence of circuit board warping by forming the solder resist in a multilayer form when forming the solder resist for supporting the circuit pattern arranged at the outermost portion.

[0015] Furthermore, the embodiments provide a circuit board and a method for manufacturing the circuit board, which can improve the reliability of the substrate by including multiple solder resists with different material properties during the formation of multilayer solder resists.

[0016] Furthermore, the embodiments provide a circuit board and a method for manufacturing the circuit board, which can address reliability issues that may be caused by fillers by removing surface-exposed fillers that penetrate the solder resist.

[0017] The technical problems to be solved by the embodiments are not limited to those mentioned above, and another technical problem not mentioned will be clearly understood by those skilled in the art through the following description.

[0018] [Technical Solution]

[0019] A circuit board according to an embodiment includes: an insulating layer; a circuit pattern disposed on an upper surface of the insulating layer; a first solder resist disposed on the upper surface of the insulating layer and having a height less than that of the circuit pattern; and a second solder resist disposed on the upper surface of the first solder resist and including a first portion and a second portion, the first portion having an upper surface lower than that of the upper surface of the circuit pattern, and the second portion having an upper surface higher than that of the upper surface of the circuit pattern, wherein the circuit pattern includes: a plurality of first circuit patterns and a plurality of second circuit patterns, the plurality of first circuit patterns being disposed on the upper surface of a first region of the insulating layer, and the plurality of second circuit patterns being disposed on the upper surface of a second region of the insulating layer; wherein the first portion of the second solder resist is disposed between the plurality of first circuit patterns to have an upper surface lower than that of the upper surface of the first circuit patterns; and wherein the second portion of the second solder resist has an upper surface higher than that of the upper surface of the second circuit patterns and is disposed to cover the plurality of second circuit patterns between them.

[0020] Furthermore, the first region is an open area for solder resist, and the second region is an area for placing solder resist.

[0021] Furthermore, the material properties of the first solder resist are different from those of the second solder resist.

[0022] Furthermore, the coefficient of thermal expansion of the first solder resist is less than that of the second solder resist.

[0023] Furthermore, the filler content in the first solder resist is greater than the filler content in the second solder resist.

[0024] Furthermore, the filler content in the first solder resist is 50 wt% to 65 wt%, and the filler content in the second solder resist is 20 wt% to 35 wt%.

[0025] Furthermore, the height of the upper surface of the first solder resist is 30% to 50% of the height of the upper surface of the first circuit pattern.

[0026] Furthermore, the height of the upper surface of the first portion of the second solder resist is 70% to 90% of the height of the upper surface of the first circuit pattern.

[0027] Furthermore, the insulating layer comprises a plurality of insulating layers, and the first circuit pattern and the second circuit pattern are arranged to protrude from the upper surface of the outermost insulating layer among the plurality of insulating layers.

[0028] In addition, the circuit board also includes a primer layer disposed between the upper surface of the insulating layer and the first solder resist, the first circuit pattern and the second circuit pattern.

[0029] Furthermore, the first circuit pattern includes traces and pads, and the traces have a line width of 10 μm or less and a spacing of 10 μm or less and are arranged on the upper surface of the first region.

[0030] On the other hand, a method for manufacturing a circuit board according to an embodiment includes: manufacturing an inner layer substrate; forming an uppermost insulating layer on the inner layer substrate, disposing a primer layer on the upper surface of the uppermost insulating layer, forming a circuit pattern on the primer layer of the uppermost insulating layer, and forming a first solder resist layer covering the circuit pattern on the primer layer; exposing and developing the first solder resist layer to form a first solder resist having a height smaller than the height of the circuit pattern; forming a second solder resist layer on the first solder resist; partially exposing and developing the second solder resist layer to form a second solder resist; wherein forming the second solder resist includes forming a second solder resist comprising a first portion and a second portion, the first portion being disposed on the upper surface of the first solder resist and having an upper surface lower than the upper surface of the circuit pattern, the second portion having an upper surface higher than the upper surface of the circuit pattern, and wherein the first portion is disposed on a solder resist open area in the upper region of the uppermost insulating layer.

[0031] Furthermore, the material properties of the first solder resist layer are different from those of the second solder resist layer.

[0032] In addition, the coefficient of thermal expansion of the first solder resist layer is smaller than that of the second solder resist layer.

[0033] In addition, the filler content in the first solder resist layer is greater than the filler content in the second solder resist layer.

[0034] In addition, the filler content in the first solder resist layer is 50 wt% to 65 wt%, and the filler content in the second solder resist layer is 20 wt% to 35 wt%.

[0035] In addition, the height of the upper surface of the first solder resist is 30% to 50% of the height of the upper surface of the circuit pattern.

[0036] In addition, the height of the upper surface of the first part of the second solder resist meets 70% to 90% of the height of the upper surface of the circuit pattern.

[0037] In addition, the circuit pattern includes traces and pads, wherein the traces are arranged with a line width of 10 μm or less and a spacing of 10 μm or less, a portion of the side surface of the trace is in direct contact with the side surface of the second portion of the second solder resist, and the remainder of the side surface of the trace is exposed to the outside.

[0038] [Beneficial Effects]

[0039] The circuit board of this embodiment is a multilayer circuit board with eight or more layers, and includes an outer layer circuit pattern disposed on the uppermost outer insulating layer of the multilayer and protruding from the surface of the outer insulating layer. In this case, the outer layer circuit pattern includes: a second-first circuit pattern disposed in a second region of the upper region of the outer insulating layer where solder resist (SR) is disposed; and a second-second circuit pattern disposed in a first region that is an open region without solder resist. In this case, the second-first circuit pattern can be supported by being surrounded by solder resist, but because the second-second circuit pattern does not have a support layer capable of supporting the second-first circuit pattern, it may be prone to collapse due to various factors.

[0040] Therefore, a support layer capable of supporting the second-second circuit pattern in this embodiment is formed on the first insulating layer corresponding to the outer insulating layer. In this case, the support layer in the embodiment can be implemented using a solder resist with a multilayer structure. Preferably, the multilayer solder resist in this embodiment is arranged between multiple second-second circuit patterns, simultaneously covering the second-first circuit pattern and exposing the second-second circuit pattern.

[0041] Therefore, this embodiment can address problems such as collapse or wear of protruding outer layer circuit patterns by miniaturizing the outer layer circuit patterns, thereby improving product reliability. Specifically, this embodiment can address problems such as collapse or friction of the outer layer circuit patterns in the first region, thereby improving product reliability.

[0042] In this embodiment, the solder resist may include a first solder resist and a second solder resist. Furthermore, the first solder resist may be disposed in the first and second regions at a height lower than the height of the second-second circuit pattern. Preferably, the upper surface of the first solder resist may be positioned lower than the upper surface of the second circuit pattern in the first and second regions. Additionally, the second solder resist is disposed on the first solder resist, and therefore may have a different height for each region. That is, the upper surface of the second solder resist in the first region is disposed at a height lower than the upper surface of the second-first and second-second circuit patterns, and the upper surface of the second solder resist in the second region may be disposed at a height higher than the upper surface of the second-first and second-second circuit patterns. In this case, the first and second solder resists may have different material properties. Preferably, the first solder resist may include a material having a high filler content while having a lower CTE compared to the second solder resist.

[0043] Therefore, this embodiment allows for mitigation of CTE in the circuit board's stack-up structure by applying a first solder resist and a second solder resist with different CTEs, minimizing the occurrence of circuit board warpage. Furthermore, the embodiment can prevent filler residue on the surface of the second-to-second circuit pattern by using a second solder resist with a lower filler content than the first solder resist, thus improving reliability.

[0044] Furthermore, when removing the first and second solder resists in this embodiment, exposure and development methods are used instead of sandblasting or plasma methods. When removing the solder resist using sandblasting or plasma methods, the outer layer circuit pattern may be deformed, and in some cases, the cross-section of the outer layer circuit pattern may have a triangular shape. Furthermore, when the cross-section of the outer layer circuit pattern is triangular, the adhesive members may not be stably arranged on the outer layer circuit pattern, potentially leading to reliability issues. In contrast, the first and second solder resists in this embodiment can be removed without deforming the outer layer circuit pattern, thus improving reliability.

[0045] Furthermore, the circuit board of the embodiment can be applied to 5G communication systems, and therefore, reliability can be further improved by minimizing transmission loss at high frequencies. Specifically, the circuit board of the embodiment can be used at high frequencies and can reduce propagation loss. Attached Figure Description

[0046] Figure 1 is a view showing a circuit board manufactured using the SAP method according to a comparative example.

[0047] Figure 2 This is a view showing a circuit board manufactured using the ETS method in a comparative example.

[0048] Figure 3 This is a view showing a circuit board according to an embodiment.

[0049] Figure 4 yes Figure 3 A magnified view of region B.

[0050] Figure 5 This is a view showing a circuit board including a protective layer according to an embodiment.

[0051] Figure 6a This is a view showing the outer circuit pattern according to the comparison example.

[0052] Figure 6b This is a view showing the second outer layer circuit pattern according to an embodiment.

[0053] Figure 6c This is a view showing the surfaces of the first and second solder resists according to an embodiment.

[0054] Figures 7 to 16 It is shown in the order of the processes. Figure 2 A view showing the manufacturing method of the circuit board. Detailed Implementation

[0055] In the following description, embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Identical or similar elements are designated by the same reference numerals and, regardless of the reference numerals, repeated descriptions thereof will be omitted. The suffixes “module” and “part” used for components in the following description are given only for ease of writing and may be used interchangeably, and they do not inherently have a meaning or function that distinguishes them from each other. Furthermore, in describing embodiments disclosed herein, detailed descriptions of relevant known art will be omitted if it is determined that such detailed descriptions may obscure the subject matter of the embodiments disclosed herein. Moreover, the drawings are provided only for ease of understanding of the embodiments disclosed herein, and the technical ideas disclosed herein are not limited by the drawings and should be understood to include all variations, equivalents, or alternatives within the spirit and scope of the invention.

[0056] Terms including ordinal numbers (such as first and second) can be used to describe various elements, but these elements are not limited by these terms. The terms mentioned above are used only for the purpose of distinguishing one component from another.

[0057] When a component is described as being "in contact" or "connected" to another component, it can be directly connected to or linked to other components, but other components may exist in between. On the other hand, when a component is described as being "in direct contact" or "directly connected" to another component, it should be understood that no other components exist in between.

[0058] Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0059] In this application, terms such as “comprising” or “having” are intended to specify the presence of features, quantities, steps, actions, components, parts, or combinations thereof described in the specification, but one or more other features. It should be understood that the presence or addition of elements or quantities, steps, actions, components, parts, or combinations thereof does not preclude the possibility of exclusion.

[0060] In the following, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0061] Before describing the embodiments, comparative examples will be described compared to the embodiments.

[0062] Figure 1 is a view showing a circuit board according to a comparative example.

[0063] Referring to Figure 1, as shown in (a), the circuit board according to the comparative example includes a circuit pattern manufactured by a general SAP method.

[0064] Specifically, the circuit board includes an insulating layer 10, a circuit pattern 20, and a protective layer 30.

[0065] The circuit pattern 20 is arranged on the upper and lower surfaces of the insulating layer 10, respectively.

[0066] In this case, at least one of the circuit patterns 20 arranged on the surface of the insulating layer 10 includes a fine circuit pattern.

[0067] Referring to Figure 1, the circuit pattern 20 arranged on the upper surface of the insulating layer 10 includes a fine circuit pattern. The fine circuit pattern includes traces 21 as signal transmission wiring and pads 22 for chip mounting, etc.

[0068] At this point, for the purpose of protecting the fine circuit pattern, the embodiment uses solder resist to form a support layer, and therefore, in the comparative example, the structure in the area where the fine circuit pattern is formed will be described.

[0069] In addition, a protective layer 30 for protecting the circuit pattern 20 is disposed on the surface of the insulating layer 10.

[0070] In this case, the upper region of the insulation layer 10 includes a first region where the protective layer 30 is disposed and a second region that is an open region where the protective layer 30 is not disposed.

[0071] Therefore, a portion of the circuit pattern 20 arranged on the upper surface of the insulating layer 10 is covered by the protective layer 30, while the remainder is exposed to the outside and not covered by the protective layer 30.

[0072] In this case, traces 21 and pads 22 corresponding to the fine circuit pattern described above are arranged in a second region that serves as an open area of ​​the protective layer 30.

[0073] For example, at least one of trace 21 and pad 22 has a width / spacing of 15μm / 15μm or less.

[0074] In this case, when the circuit pattern formed in the open area of ​​the protective layer 30 is a pattern with a width of more than 15 μm rather than a fine circuit pattern, it can strongly resist external impacts.

[0075] However, as shown in Figure 1(b), the width and spacing of the traces 21 and pads 22 of the outermost fine circuit pattern become smaller as the circuit pattern becomes finer. When the fine circuit pattern protruding on the upper surface of the insulating layer 10 is arranged in the second region of the open area that serves as the protective layer, the fine circuit pattern is prone to collapse due to external impact.

[0076] That is, as shown in B of Figure 1(b), the trace 21 corresponding to the fine circuit pattern of the outermost layer has an extremely fine pattern shape, and therefore it is easy to collapse or be swept away by small external impacts.

[0077] On the other hand, recently, the ETS method has been used to form fine circuit patterns arranged in open areas of the protective layer while having structures embedded in the insulating layer.

[0078] Figure 2 This is a view showing a circuit board manufactured using the ETS method in a comparative example.

[0079] refer to Figure 2 Specifically, the circuit board includes an insulating layer 10A, a circuit pattern 20A, and a protective layer 30A.

[0080] The circuit pattern 20A is arranged on the upper and lower surfaces of the insulating layer 10A.

[0081] In this case, at least one of the circuit patterns 20A arranged on the surface of the insulating layer 10A includes a fine circuit pattern.

[0082] Here, when a circuit pattern is formed using the ETS method, the first circuit pattern formed has a structure embedded in the insulating layer 10A. Therefore, even in the comparative example, when the initially formed circuit pattern is formed as a fine circuit pattern, the fine circuit pattern can have a structure where the fine circuit pattern is embedded in the insulating layer 10A.

[0083] That is, the circuit board manufactured by the ETS method includes a fine circuit pattern with a structure embedded in the surface of the insulating layer 10A. Specifically, the fine circuit pattern includes traces 21A as signal transmission wiring and pads 22A for mounting chips, etc.

[0084] Furthermore, when a circuit board is manufactured using the ETS method described above, the fine circuit pattern is protected from external impacts because it has a structure embedded in the insulating layer.

[0085] At this time, as Figure 2 As shown, there are no major problems when manufacturing substrates with a two-layer structure (based on the number of layers in the circuit pattern) using the ETS method. However, when manufacturing circuit boards with 8 or more layers (especially 10 or more layers) using the ETS method, the delivery cycle for manufacturing such circuit boards is at least 2 months or more, resulting in reduced productivity.

[0086] Furthermore, a fine circuit pattern must first be formed during the manufacturing process of a multilayer circuit board to enable the fabrication of the embedded structure using the ETS method. Moreover, for application in recent high-integration / high-specification AP modules, 8 to 10-layer circuit boards are required. In this case, when subsequent multilayer lamination processes are performed while the fine circuit pattern has been formed during the ETS process, thermal stress and other factors can damage the fine circuit pattern, making it difficult to achieve the desired fine circuit pattern.

[0087] Furthermore, when manufacturing circuit boards using the ETS method, a separate ETS core layer is required. In this case, an additional process is needed for the final removal of the ETS core layer when manufacturing circuit boards using the ETS method.

[0088] Furthermore, when manufacturing circuit boards using the ETS method, the yield rate decreases due to the cumulative tolerances caused by stacking more than a certain number of layers, thus increasing product costs. Additionally, the stress caused by lamination processes on both sides of the ETS core layer leads to increased pattern damage.

[0089] Furthermore, there is increasing attention recently on circuit boards that reflect the development of 5G technology. Currently, for 5G technology to be applied, circuit boards must have a high multilayer structure, and therefore the circuit patterns must be miniaturized. However, although fine patterns can be formed in comparative examples, there is a problem with the inability to stably protect these fine patterns.

[0090] Therefore, the embodiments provide a circuit board with a novel structure capable of solving the reliability problem of the outermost fine pattern, and a method for controlling the circuit board.

[0091] Figure 3This is a view showing a circuit board according to an embodiment, and Figure 4 yes Figure 3 A magnified view of region B.

[0092] In description Figure 3 and Figure 4 Previously, the circuit board according to the embodiment could have a multi-layer structure. Preferably, the circuit board according to the embodiment could have a structure of 10 or more layers based on the number of layers in the circuit pattern. However, this is only an example and is not limited thereto. That is, the circuit board according to the embodiment could have fewer than 10 layers, or alternatively, could have more than 10 layers.

[0093] However, the circuit board in the embodiment is used to address the problems of the ETS method in the comparative example. At this point, the ETS method in the comparative example has many problems when manufacturing circuit boards with 8 or more layers, and therefore, for comparison, the embodiment is described as having a 10-layer structure.

[0094] refer to Figure 3 and Figure 4 The circuit board 100 includes an insulating layer 110.

[0095] Preferably, the circuit board 100 may include a first insulating layer to a ninth insulating layer 111, 112, 113, 114, 115, 116, 117, 118 and 119 to achieve a 10-layer structure.

[0096] In this case, the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, the sixth insulating layer 116, and the seventh insulating layer 117 can be inner insulating layers arranged inside the stacked structure of insulating layers, the eighth insulating layer 118 can be the uppermost insulating layer (first outermost insulating layer) arranged on the upper portion of the inner insulating layer, and the ninth insulating layer 119 can be the lowermost insulating layer (second outermost insulating layer) arranged below the lower portion of the inner insulating layer.

[0097] The first insulating layer 111 may be a core insulating layer disposed at the center of the laminated structure of the insulating layer 110. The second insulating layer 112, the fourth insulating layer 114, the sixth insulating layer 116, and the eighth insulating layer 118 may be upper insulating layers arranged sequentially on the first insulating layer 111. In addition, the third insulating layer 113, the fifth insulating layer 115, the seventh insulating layer 117, and the ninth insulating layer 119 may be lower insulating layers arranged sequentially below the first insulating layer 111.

[0098] The insulating layer 110 is a substrate on which circuitry capable of altering wiring is formed, and may include the entirety of a printed circuit board and an insulating substrate made of an insulating material capable of forming circuit patterns on its surface.

[0099] For example, at least the insulating layer 110 can be rigid or flexible. For example, at least the insulating layer 110 can include glass or plastic. In detail, at least the insulating layer 110 can include chemically strengthened / semi-tempered glass (such as soda-lime glass or aluminosilicate glass) or strengthened or flexible plastic (such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG) and polycarbonate (PC)) or sapphire.

[0100] In addition, at least the insulating layer 110 may include an optically isotropic film. For example, at least one of the first insulating layer 111, the second insulating layer 112, and at least the insulating layer 110 may include COC (cyclic olefin copolymer), COP (cyclic olefin polymer), optically isotropic polycarbonate (polycarbonate, PC), or optically isotropic polymethyl methacrylate (PMMA).

[0101] Furthermore, at least the insulating layer 110 can be bent while having a partially curved surface. That is, at least the insulating layer 110 can be bent while having a partially flat surface and a partially curved surface. In detail, at least the insulating layer 110 can have curved ends and curved surfaces, or it can have a surface with random curvature and can be bent or flexed.

[0102] Furthermore, at least the insulating layer 110 can be a flexible substrate with flexible properties. Moreover, at least the insulating layer 110 can be a bent or buckled substrate. In this case, at least one of the insulating layers 110 can represent electrical wiring connecting circuit components based on a circuit design as a wiring diagram, and electrical conductors can be reproduced on the insulating material. Furthermore, at least one of the insulating layers 110 can form wiring for mounting electrical components and connecting them to circuits, and can mechanically fix components beyond their electrical connection function.

[0103] The circuit pattern can be arranged on the surface of the insulating layer 110.

[0104] That is, the circuit pattern can be arranged on the corresponding surfaces of the first to ninth insulating layers 111, 112, 113, 114, 115, 116, 117, 118 and 119 constituting the insulating layer 110.

[0105] Here, the circuit pattern may include an inner layer circuit pattern 120 and outer layer circuit patterns 130 and 140. The inner layer circuit pattern 120 may be a circuit pattern inside the insulating layer 110 arranged in the stacked structure of the circuit board, and the outer layer circuit patterns 130 and 140 may be circuit patterns arranged at the outermost edge of the insulating layer 110 in the stacked structure of the circuit board.

[0106] The inner circuit pattern 120 may include a first circuit pattern 121, a second circuit pattern 122, a third circuit pattern 123, a fourth circuit pattern 124, a fifth circuit pattern 125, a sixth circuit pattern 126, and a seventh circuit pattern 127.

[0107] The first circuit pattern 121 can be arranged on the upper surface of the first insulating layer 111, and therefore can be covered by the second insulating layer 112. The second circuit pattern 122 can be arranged on the lower surface of the first insulating layer 111, and therefore can be covered by the third insulating layer 113. The third circuit pattern 123 can be arranged on the upper surface of the second insulating layer 112, and therefore can be covered by the fourth insulating layer 114. The fourth circuit pattern 124 can be arranged on the lower surface of the third insulating layer 113, and therefore can be covered by the fifth insulating layer 115. The fifth circuit pattern 125 can be arranged on the upper surface of the fourth insulating layer 114, and therefore can be covered by the sixth insulating layer 116. The sixth circuit pattern 126 can be arranged on the lower surface of the fifth insulating layer 115, and therefore can be covered by the seventh insulating layer 117. The seventh circuit pattern 127 can be arranged on the upper surface of the sixth insulating layer 116, and therefore can be covered by the eighth insulating layer 118. The eighth circuit pattern 128 can be arranged on the lower surface of the seventh insulating layer 117, and therefore can be covered by the ninth insulating layer.

[0108] The outer circuit pattern can be arranged on the surface of the outermost insulating layer, which is located at the outermost portion of the insulating layer 110. Preferably, the outer circuit pattern can include a first outer circuit pattern 130, which is arranged on the lower surface of the ninth insulating layer 119, which is located at the lowermost portion of the insulating layer 110.

[0109] In addition, the outer circuit pattern may include a second outer circuit pattern 140, which is disposed on the upper surface of the eighth insulating layer 118, which is disposed at the uppermost portion of the insulating layer 110.

[0110] In this configuration, at least one of the first outer layer circuit pattern 130 and the second outer layer circuit pattern 140 may be formed to protrude from the surface of the insulating layer. Preferably, the first outer layer circuit pattern 130 may be formed to protrude below the lower surface of the ninth insulating layer 119. Furthermore, the second outer layer circuit pattern 140 may be formed to protrude above the upper surface of the eighth insulating layer 118.

[0111] That is, the upper surface of the first outer layer circuit pattern 130 can be positioned on the same plane as the lower surface of the ninth insulating layer 119. In addition, the second outer layer circuit pattern 140 can have a lower surface positioned on the same plane as the upper surface of the primer layer 150 disposed on the upper surface of the eighth insulating layer 180.

[0112] In other words, the primer layer 150 can be disposed on the upper surface of the second outer circuit pattern 140 and the eighth insulating layer 180.

[0113] That is, the second outer layer circuit pattern 140 may include a fine circuit pattern. Preferably, the second outer layer circuit pattern 140 may be a fine circuit pattern having a linewidth of 10 μm or less and a spacing between patterns of 10 μm or less. Therefore, when the second outer layer circuit pattern 140 is directly disposed on the eighth insulating layer 118, the contact area between the eighth insulating layer 118 and the second outer layer circuit pattern 140 is small, which may result in the second outer layer circuit pattern 150 separating from the eighth insulating layer 118.

[0114] Therefore, in this embodiment, the primer layer 150 is disposed between the second outer layer circuit pattern 140 and the eighth insulating layer 118. The primer layer 150 can improve the adhesion between the second outer layer circuit pattern 140 and the eighth insulating layer 118. The primer layer 150 can be disposed to completely cover the upper surface of the eighth insulating layer 118. Furthermore, the second outer layer circuit pattern 140 can be partially disposed on the primer layer 150. Therefore, the upper surface of the primer layer 150 in this embodiment can include a first portion contacting the second outer layer circuit pattern 140 and a second portion contacting the lower surface of the first solder resist 160, which will be described later. That is, when the second outer layer circuit pattern 140 is formed by the SAP process, the primer layer 150 can be used to enhance the adhesion between the eighth insulating layer 118 and the second outer layer circuit pattern 140. This primer layer 150 can include, but is not limited to, a polyurethane-based resin, an acrylic resin, or a silicone-based resin.

[0115] At the same time, Figure 3 The diagram shows that the primer layer is not disposed between the ninth insulating layer 119 and the first outer layer circuit pattern 130. The primer layer may also be disposed between the ninth insulating layer 119 and the first outer layer circuit pattern 130. However, the first outer layer circuit pattern 130 may not be a fine circuit pattern, and therefore, the primer layer between the ninth insulating layer 119 and the first outer layer circuit pattern 130 may be selectively omitted.

[0116] Therefore, when the fine circuit pattern is arranged on the inner layer, the primer layer can be omitted because it is covered by at least one of the insulating layers 110. On the other hand, when the fine circuit pattern in the embodiment is arranged on the outermost layer, there is no insulating layer covering the fine circuit pattern, and the primer layer 150 can be arranged to improve the bonding strength between the fine circuit pattern and the insulating layer.

[0117] In the following description, the second outer layer circuit pattern 140 will be formed as a fine circuit pattern. However, the embodiments are not limited thereto, and the first outer layer circuit pattern 130 can also be formed as a fine circuit pattern. Therefore, it is apparent that structures for improving reliability (such as those for enhancing the bonding strength of the second outer layer circuit pattern 140 and preventing collapse, as described below) can also be applied to the first outer layer circuit pattern 130.

[0118] Meanwhile, the inner layer circuit pattern 120, the first outer layer circuit pattern 130, and the second outer layer circuit pattern 140 are conductors for transmitting electrical signals and can be formed from a highly conductive metallic material. Therefore, the inner layer circuit pattern 120, the first outer layer circuit pattern 130, and the second outer layer circuit pattern 140 can be formed from at least one metallic material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Furthermore, the circuit pattern 120 can be formed from a paste or solder paste containing at least one metallic material with excellent bonding strength selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the inner layer circuit pattern 120, the first outer layer circuit pattern 130, and the second outer layer circuit pattern 140 can be formed from copper (Cu), which has high conductivity and a relatively low price.

[0119] The inner layer circuit pattern 120, the first outer layer circuit pattern 130, and the second outer layer circuit pattern 140 can be formed by additive processes, subtractive processes, modified semi-additive processes (MSAP), and semi-additive processes (SAP). These are typical circuit board manufacturing processes, and detailed descriptions of them will be omitted here.

[0120] Preferably, the first outer layer circuit pattern 130 and the second outer layer circuit pattern 140 are the outermost circuit patterns arranged on the outermost side of the circuit board, and therefore they can be formed by the SAP (semi-additive process) method.

[0121] Meanwhile, vias V can be arranged in insulating layer 110. Vias V are arranged in each insulating layer and can therefore be used to electrically connect circuit patterns arranged in different layers to each other.

[0122] The first through hole V1 can be arranged in the first insulating layer 111. The first through hole V1 can electrically connect the first circuit pattern 121 arranged on the upper surface of the first insulating layer 111 and the second circuit pattern 122 arranged on the lower surface of the first insulating layer 111.

[0123] The second through-hole V2 can be arranged in the second insulating layer 112. The second through-hole V2 can be electrically connected between the first circuit pattern 121 arranged on the upper surface of the first insulating layer 111 and the third circuit pattern 123 arranged on the upper surface of the second insulating layer 112.

[0124] The third through-hole V3 can be arranged in the third insulating layer 113. The third through-hole V3 can electrically connect the second circuit pattern 122 arranged on the lower surface of the first insulating layer 111 and the fourth circuit pattern 124 arranged on the lower surface of the third insulating layer 113.

[0125] The fourth through-hole V4 can be arranged in the fourth insulating layer 114. The fourth through-hole V4 can electrically connect the third circuit pattern 123 arranged on the upper surface of the second insulating layer 111 and the fifth circuit pattern 125 arranged on the upper surface of the fourth insulating layer 114.

[0126] The fifth through hole V5 can be arranged in the fifth insulating layer 115. The fifth through hole V5 can electrically connect the fourth circuit pattern 124 arranged on the lower surface of the third insulating layer 113 and the sixth circuit pattern 126 arranged on the lower surface of the fifth insulating layer 115.

[0127] The sixth through-hole V6 can be arranged in the sixth insulating layer 116. The sixth through-hole V6 can electrically connect the fifth circuit pattern 125 arranged on the upper surface of the fourth insulating layer 114 and the seventh circuit pattern 127 arranged on the upper surface of the sixth insulating layer 116.

[0128] The seventh through hole V7 can be arranged in the seventh insulating layer 117. The seventh through hole V7 can electrically connect the sixth circuit pattern 126 arranged on the lower surface of the fifth insulating layer 115 and the eighth circuit pattern 128 arranged on the lower surface of the seventh insulating layer 117.

[0129] The eighth through-hole V1 can be arranged in the eighth insulating layer 118. The eighth through-hole V8 can electrically connect the seventh circuit pattern 127 arranged on the upper surface of the sixth insulating layer 116 and the second outer layer circuit pattern 140 arranged on the upper surface of the primer layer 150.

[0130] The ninth through-hole V9 can be arranged in the ninth insulating layer 119. The ninth through-hole V9 can electrically connect the eighth circuit pattern 128 arranged on the lower surface of the seventh insulating layer 117 and the first outer layer circuit pattern 130 arranged on the lower surface of the ninth insulating layer 119.

[0131] A via V can be formed by filling the interior of a via hole (not shown) formed in each insulating layer with a conductive material.

[0132] Through holes can be formed through machining, laser processing, and chemical processing. When forming through holes by machining, methods such as milling, drilling, and routing can be used, and when forming through laser processing, UV or CO2 laser methods can be used. Furthermore, when forming through chemical processing, chemicals containing aminosilanes, ketones, etc., can be used. Therefore, at least one of the multiple insulating layers can be open.

[0133] Meanwhile, laser processing is a cutting method that concentrates light energy on a surface to melt and evaporate part of the material into a desired shape. Therefore, complex structures can be easily processed by computer programs, and even composite materials that are difficult to cut by other methods can be processed.

[0134] In addition, laser processing has a cutting diameter of at least 0.005 mm and a wide range of possible thicknesses.

[0135] For laser processing drill bits, YAG (yttrium aluminum garnet) lasers, CO2 lasers, or ultraviolet (UV) lasers are preferred. YAG lasers can process both copper foil layers and insulating layers, while CO2 lasers can only process insulating layers.

[0136] When forming through holes, the first to ninth through holes V1, V2, V3, V4, V5, V6, V7, V8, and V9 can be formed by filling the interior of the through holes with a conductive material. The metallic material used to form the first to ninth through holes V1, V2, V3, V4, V5, V6, V7, V8, and V9 can be any material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). Furthermore, the filling of the conductive material can be done using any or a combination of electroless plating, electrolytic plating, screen printing, sputtering, vapor deposition, inkjet printing, and dispensing.

[0137] Meanwhile, the protective layer can be disposed on the outermost side of the circuit board 100. Preferably, the first protective layers 160 and 170 can be disposed on the eighth insulating layer 118 (preferably on the primer layer 150). In addition, the second protective layer 175 can be disposed below the ninth insulating layer 119.

[0138] The first protective layers 160 and 170 and the second protective layer 175 may be formed from at least one layer using any one or more of solder resist (SR), oxide, and Au. Preferably, the first protective layers 160 and 170 and the second protective layer 175 may be solder resist.

[0139] Meanwhile, first protective layers 160 and 170 are disposed on primer layer 150. First protective layers 160 and 170 can be used to support second outer layer circuit pattern 140 disposed on primer layer 150.

[0140] That is, the first protective layers 160 and 170 may partially overlap with the second outer layer circuit pattern 140 disposed on the primer layer 150. The area of ​​the first protective layers 160 and 170 may be smaller than the area of ​​the eighth insulating layer 118. The area of ​​the first protective layers 160 and 170 may be smaller than the area of ​​the primer layer 150. The first protective layers 160 and 170 are partially or entirely disposed on the primer layer 150 and the second outer layer circuit pattern 140, and therefore, the first protective layer may include an open area exposing the surface of the second outer layer circuit pattern 140.

[0141] The first protective layers 160 and 170 may include an open area or a first region R1 having a groove shape. The first region R1 may represent the area on the surface of the second outer layer circuit pattern 140 exposed through the first protective layers 160 and 170 in the upper region of the primer layer 150 and the second outer layer circuit pattern 140.

[0142] That is, the circuit board includes a first region R1 and a second region R2. The first region R1 is an open region where the surface of the second outer layer circuit pattern 140 must be exposed through the first protective layers 160 and 170, and the second region R2 may be a buried region where the surface of the second outer layer circuit pattern 140 is covered by the first passivation layers 160 and 170.

[0143] That is, the first region R1 can be an un-arranged area of ​​the first protective layers 160 and 170 for electrically connecting the second outer layer circuit pattern 140 to a component (such as a chip). Therefore, the second outer layer circuit pattern 140 arranged on the first region R1 can be exposed to the outside in the absence of a protective layer protecting the second outer layer circuit pattern 140.

[0144] Furthermore, the second outer layer circuit pattern 140 arranged in the first region R1 as described above may have reliability issues such as collapse or friction due to various factors. Moreover, the second outer layer circuit pattern 140 is a fine circuit pattern, and therefore has a linewidth of 10 μm or less and a spacing of 10 μm or less, and is arranged on the primer layer 150. Therefore, the second outer layer circuit pattern 140 disposed in the first region R1 may be easily collapsed or rubbed by various small external impacts.

[0145] Therefore, the first protective layers 160 and 170 in the embodiment are also arranged on the primer layer 150 corresponding to the first region R1 to improve the reliability of the second outer layer circuit pattern 140 arranged on the first region R1.

[0146] That is, the first protective layers 160 and 170 can be disposed on the upper surface of the primer layer 150 in the area where the second outer layer circuit pattern 140 is not disposed. For example, the first protective layers 160 and 170 are disposed on the upper surface of the primer layer 150 and can therefore be disposed between the second outer layer circuit patterns 140 on the first region R1.

[0147] In this case, the second outer layer circuit pattern 140 includes a second-first outer layer circuit pattern formed in the first region R1 and a second-second outer layer circuit pattern formed in the second region R2.

[0148] The upper surface of the primer layer 150 includes a first upper surface corresponding to the first region R1 and a second upper surface corresponding to the second region R2.

[0149] At this time, as Figure 3 and Figure 4 As shown, the first protective layers 160 and 170 are completely disposed on the primer layer 150 without separating the first region R1 and the second region R2, and can be disposed in the region between the second and first outer layer circuit patterns and the region between the second and second outer layer circuit patterns, respectively.

[0150] Therefore, the first protective layers 160 and 170 include a first portion disposed in the first region R1 and a second portion disposed in the second region R2.

[0151] In this case, the first protective layers 160 and 170 can have different heights for each area.

[0152] For example, the first protective layers 160 and 170 may include a first portion disposed in the first region R1 and a second portion disposed in the second region R2.

[0153] At this time, the surface of the second outer layer circuit pattern 140 in the first region R1 should be exposed to the outside, and the surface of the second outer layer circuit pattern 140 in the second region R2 should be covered by a protective layer.

[0154] Therefore, the upper surface of the first portion of the first protective layers 160 and 170 arranged in the first region R1 may be lower than the upper surface of the second outer layer circuit pattern 140. Preferably, the height or thickness of the first portion of the first protective layers 160 and 170 may be less than the height or thickness of the second outer layer circuit pattern 140.

[0155] Furthermore, the upper surface of the second portion of the first protective layers 160 and 170 arranged in the second region R2 can be positioned higher than the upper surface of the second outer layer circuit pattern 140. Preferably, the height or thickness of the second portion of the first protective layers 160 and 170 can be greater than the height or thickness of the second outer layer circuit pattern 140.

[0156] Therefore, due to the low height of the first protective layers 160 and 170, the surface of the second outer layer circuit pattern 140 arranged in the first region R1 can be exposed to the outside, and due to the high height of the first protective layers 160 and 170, the second outer layer circuit pattern 140 arranged in the second region R2 can be embedded in the first protective layers 160 and 170.

[0157] The first protective layers 160 and 170 will be described in detail below.

[0158] The first protective layers 160 and 170 may be disposed on the primer layer 150. Preferably, the first protective layers 160 and 170 may be disposed between the second outer layer circuit patterns 140 on the primer layer 150. That is, the second outer layer circuit patterns 140 may be arranged to be spaced apart from each other at a predetermined interval on the primer layer 150, and therefore, the first protective layers 160 and 170 may be disposed on the area of ​​the upper surface of the primer layer 150 where the second outer layer circuit patterns 140 are not disposed.

[0159] Preferably, the first protective layers 160 and 170 may include a first solder resist 160 and a second solder resist 170.

[0160] In addition, the first solder resist 160 can be disposed on the area on the upper surface of the primer layer 150 where the second outer layer circuit pattern 140 is not disposed.

[0161] Therefore, the lower surface of the first solder resist 160 can directly contact the upper surface of the primer layer 150. Furthermore, the side surface of the first solder resist 160 can have a structure that directly contacts the second outer layer circuit pattern 140. For example, the side surface of the first solder resist 160 can directly contact the side surface of the second outer layer circuit pattern 140.

[0162] In this configuration, the height of the first solder resist 160 can be less than the height of the second outer layer circuit pattern 140. Preferably, the upper surface of the first solder resist 160 can be positioned below the upper surface of the second outer layer circuit pattern 140. Therefore, a portion of the side surface of the second outer layer circuit pattern 140 can contact the first solder resist 160, and the remainder can be exposed.

[0163] In this configuration, the first solder resist 160 can be arranged to have the same height in the first region R1 and the second region R2. That is, the first solder resist 160 can include a first portion arranged in the first region R1 and a second portion arranged in the second region R2. Furthermore, the first portion and the second portion of the first solder resist 160 can have substantially the same height.

[0164] Here, the first solder resist 160 is arranged primarily around the second outer layer circuit pattern 140, and thus, the second outer layer circuit pattern 140 can be prevented from collapsing or rubbing.

[0165] The first solder resist 160 can be a photoresist film. The first solder resist 160 can have a structure in which resin and filler are mixed.

[0166] In an embodiment, as described above, the first solder resist 160 surrounds the second outer layer circuit pattern 140 on the primer layer 150 and is in direct contact with and preferentially disposed on the side surface of the second outer layer circuit pattern 140. Furthermore, the second outer layer circuit pattern 140, with its fine circuitry, can be supported by the first solder resist 160. Preferably, in an embodiment, the second outer layer circuit pattern 140 disposed in the first region R1 is primarily supported by the first solder resist 160, and therefore, can stably protect the second outer layer circuit pattern 140 from external impacts.

[0167] Simultaneously, a second solder resist 170 can be disposed on the first solder resist 160. Like the first solder resist 160, the second solder resist 170 can be implemented as a photoresist film. The second solder resist 170 can also have a structure in which resin and filler are mixed.

[0168] However, in this embodiment, the material properties of the first solder resist 160 may differ from those of the second solder resist 170. Here, material properties may include the coefficient of thermal expansion (CTE) and filler content.

[0169] Furthermore, the coefficient of thermal expansion of the first solder resist 160 may differ from that of the second solder resist 170. Additionally, the filler content of the first solder resist 160 may differ from that of the second solder resist 170.

[0170] The second solder resist 170 can be applied over the first solder resist 160 to provide secondary protection for the second outer layer circuit pattern 140 in the first region R1.

[0171] In this case, the second solder resist 170 can have a different height for each area.

[0172] That is, the second solder resist 170 may include a first portion disposed in the first region R1 and a second portion disposed in the second region R2.

[0173] Furthermore, the first portion of the second solder resist 170 may have a first height. Additionally, the second portion of the second solder resist 170 may have a second height greater than the first height.

[0174] Therefore, the upper surface of the first portion of the second solder resist 170 can be positioned below the upper surface of the second outer layer circuit pattern 140. Preferably, the first portion of the second solder resist 170 can be formed to expose a portion of the upper and side surfaces of the second outer layer circuit pattern 140.

[0175] Furthermore, the upper surface of the second portion of the second solder resist 170 can be positioned above the upper surface of the second outer layer circuit pattern 140. Preferably, the second portion of the second solder resist 170 can have a structure protruding above the upper surface of the second outer layer circuit pattern 140. Therefore, the second outer layer circuit pattern 140 arranged in the second region R2 can be embedded in the second portion of the second solder resist 170.

[0176] Here, when the second solder resist 170 is exposed and developed, the second solder resist 170 can have a different height for each region by selectively removing only the second portion of the second solder resist 170 disposed in the first region R1.

[0177] In this case, the first protective layer may consist only of the second solder resist 170 and exclude the first solder resist 160. For example, by applying the second solder resist onto the primer layer 150 and selectively removing the second solder resist 170 for each area, the support layer supporting the second outer layer circuit pattern 140 can be formed using only the second solder resist 170. However, when the support layer is formed from only one layer of solder resist, depending on the material properties of the solder resist, the following problems may arise. For example, when the support layer is formed from only one layer of solder resist, reliability issues arise where the circuit board warps according to the coefficient of thermal expansion of the solder resist. For example, when the support layer is formed from only one layer of solder resist, the second outer layer circuit pattern 140 may have problems with filler residue remaining on the surface of the second outer layer circuit pattern due to the filler content contained in the solder resist, and thus reliability issues may occur.

[0178] The embodiments use multiple solder resists with different material properties as described above to form a multilayer support layer to prevent warping due to relaxation according to the coefficient of thermal expansion (CTE) and improve reliability.

[0179] In this case, the coefficient of thermal expansion of the first solder resist 160 can be less than that of the second solder resist 170. For example, the first solder resist 160 can have a coefficient of thermal expansion of 10 to 25 ppm (@alpha 1). For example, the second solder resist 170 can have a coefficient of thermal expansion of 30 to 50 ppm (@alpha 1). That is, the embodiment allows for minimizing the occurrence of circuit board warping due to CTE relaxation by preferentially distributing the first solder resist 160 with a low coefficient of thermal expansion on the primer layer 150 and distributing the second solder resist 170 with a high coefficient of thermal expansion on the first solder resist 160.

[0180] Meanwhile, the filler content in the first solder resist 160 may differ from the filler content in the second solder resist 170. Preferably, the filler content in the first solder resist 160 may be higher than the filler content in the second solder resist 170.

[0181] That is, the upper surface of the second solder resist 170 is positioned adjacent to the upper surface of the second outer layer circuit pattern 140, and therefore, a portion of the filler contained in the second solder resist 170 may remain on the upper surface of the second outer layer circuit pattern 140. Therefore, the filler content in the second solder resist 170 is lower than the filler content in the first solder resist 160 to prevent this.

[0182] Furthermore, the filler content in the first solder resist 160 is relatively higher than the filler content in the second solder resist 170. In this case, the upper surface of the first solder resist 160 is spaced apart from the upper surface of the second outer layer circuit pattern 140 by a predetermined distance. Therefore, the filler contained in the first solder resist 160 will not remain on the second outer layer circuit pattern 140 during the process of forming the first solder resist 160.

[0183] For example, SiO2 filler may be included in the first solder resist 160, and its content may be from 50 wt% to 65 wt%.

[0184] In addition, the second solder resist 170 may include fillers such as BaSO4, SiO2, talc, etc., and its content may be from 20wt% to 35wt%.

[0185] As described above, in the embodiment, while using a first solder resist 160 and a second solder resist 170 with different material properties to support the second outer layer circuit pattern 140 of the first region R1, a protective layer capable of covering the second outer layer circuit pattern 140 of the second region R2 is formed.

[0186] Simultaneously, depending on the function, the second outer layer circuit pattern 140 may include traces 141 and pads 142. Pads 142 may be areas with adhesive members (not shown) arranged for connection to electronic components (such as chips). Furthermore, traces 141 may be wiring connecting different pads. Here, the width of the pads 142 is generally greater than the width of the traces, and therefore the pads 142 can have strong resistance to external shocks. However, as mentioned above, the traces 141 are arranged with widths and spacing corresponding to fine circuit patterns, and therefore may have weak resistance to external shocks. Therefore, the first solder resist 160 and the second solder resist 170 can be used to stably support the second outer layer circuit pattern 140 arranged in the first region R1, more specifically, to support the traces 141 and the second outer layer circuit pattern 140 in the first region R1.

[0187] At the same time, such as Figure 4 As shown, the second outer layer circuit pattern 140 may have a first height H1 and may be arranged on the primer layer 150.

[0188] In addition, the first solder resist 160 may have a second height H2 and be disposed on the primer layer 150.

[0189] In this case, the first height H1 is greater than the second height H2. Preferably, the first solder resist 160 can be disposed among a plurality of second outer layer circuit patterns 140, contacting the side surfaces of the second outer layer circuit patterns 140, while having a height smaller than the height of the second outer layer circuit patterns 140. In this case, the second height H2 can be 30% to 50% of the first height H1. For example, when the second height H2 is less than 30% of the first height H1, the second outer layer circuit pattern 140 may not be stably supported by the first solder resist 160. For example, when the second height H2 is less than 30% of the first height H1, there may be difficulties in the process of forming the first solder resist 160. For example, when the second height H2 is greater than 50% of the first height H1, a portion of the filler contained in the first solder resist 160 may remain on the second outer layer circuit pattern 140. For example, when the second height H2 is greater than 50% of the first height H1, there may be difficulties in the process of forming the second solder resist 170.

[0190] Meanwhile, the second solder resist 170 can be applied on the first solder resist 160 to have a different height for each area.

[0191] The second solder resist 170 may include a first portion disposed in the first region R1 and a second portion disposed in the second region R2.

[0192] In this configuration, the first portion of the second solder resist 170 may have a third height H3 and be disposed on the first solder resist 160. Furthermore, the second portion of the second solder resist 170 may have a fourth height H4 and be disposed on the first solder resist 160.

[0193] In this case, the third height H3 is greater than the first height H1 and the second height H2. Preferably, a first portion of the second solder resist 170 can be disposed on the first solder resist 160, while having a height smaller than that of the second outer layer circuit pattern 140. In this case, the third height H3 can be 70% to 90% of the first height H1. For example, when the third height H3 is less than 70% of the first height H1, the second outer layer circuit pattern 140 may not be stably supported by the second solder resist 170. For example, when the third height H3 is less than 70% of the first height H1, difficulties may arise in the process of forming the second solder resist 160. For example, when the third height H3 is greater than 90% of the first height H1, a portion of the filler contained in the second solder resist 170 may remain on the second outer layer circuit pattern 140. For example, when the third height H3 is greater than 90% of the first height H1, due to deviations in the process of forming the second solder resist 170, the surface of the second outer layer circuit pattern 140 may be covered by the second solder resist 170.

[0194] Meanwhile, the fourth height H4 can be greater than the first height H1, the second height H2, and the third height H3. Preferably, the fourth height H4 can be 120% to 200% of the first height H1. For example, when the fourth height H4 is less than 120% of the first height H1, the surface of the second outer layer circuit pattern 140 of the second region R2 may not be stably protected by the second solder resist 170. For example, when the fourth height H4 is greater than 200% of the first height H1, the overall thickness of the circuit board may increase.

[0195] Figure 5 This is a view showing a circuit board including a protective layer according to an embodiment.

[0196] Reference Figure 5 The description includes a protective layer comprising a first solder resist 160 and a second solder resist 170 according to an embodiment. Here, the first solder resist 160 and the second solder resist 170 may be a protective layer protecting the surface of the second outer circuit pattern 140 in the second region R2, or they may be a support layer supporting the second outer circuit pattern 140 in the first region R1.

[0197] In this case, the circuit pattern in the comparative example is arranged on an insulating layer with a protruding structure. Furthermore, the circuit pattern can be arranged independently on the insulating layer without being supported by another support layer. The circuit pattern in the area corresponding to the fine pattern in the comparative example collapses or wears away.

[0198] This can occur in the outermost layer of circuit patterns on a circuit board, including those manufactured using the SAP method.

[0199] Alternatively, in an embodiment, a primer layer 150 is disposed on an eighth insulating layer 118, and a second outer layer circuit pattern 140 is disposed on the primer layer 150.

[0200] In addition, a first solder resist 160 and a second solder resist 170 are disposed on the primer layer 150 to serve as a support layer and a protective layer disposed around the second outer layer circuit pattern 140.

[0201] In this case, the first solder resist 160 and the second solder resist 170 can be arranged in the first region R1 and the second region R2, respectively.

[0202] In this case, the first solder resist 160 and the second solder resist 170 can support the second outer layer circuit pattern 140 arranged on the outermost layer of the circuit board 100, especially the traces 141 and pads 142 of the second outer layer circuit pattern 140 arranged in the first region R1, and thereby protect the second outer layer circuit pattern 140 from external impacts.

[0203] Figure 6a This is a view showing the outer circuit pattern according to the comparative example. Figure 6b This is a view showing the second outer layer circuit pattern according to an embodiment, and Figure 6c This is a view showing the surfaces of the first and second solder resists according to an embodiment.

[0204] Simultaneously, during the formation of the protective layer, various methods can be used to remove a portion of the protective layer in the first region R1. For example, a portion of the protective layer can be removed by physical or chemical methods. For instance, the protective layer can be removed by methods such as plasma or sandblasting.

[0205] However, as Figure 6a As shown, when the protective layer is physically or chemically removed, the circuit pattern is also removed during the removal process, causing the circuit pattern to deform. For example, because a portion of the circuit pattern is removed along with the protective layer during the removal process, the circuit pattern may have a triangular cross-section. Furthermore, when the upper portion of the circuit pattern has a triangular shape, adhesive components (such as solder balls) cannot be stably placed on the circuit pattern, which may lead to reliability issues. In addition, removing the protective layer by physical or chemical methods requires expensive equipment, and therefore manufacturing costs may increase.

[0206] On the other hand, Figure 6bIn the illustrated embodiment, the first solder resist 160 and the second solder resist 170 can be removed to achieve the desired height by using an exposure and development process. Furthermore, the deformation of the second outer layer circuit pattern 140 does not occur during the exposure and development process, and the cross-sectional shape of the second outer layer circuit pattern 140 can remain rectangular.

[0207] In addition, refer to Figure 6c The first solder resist 160 and the second solder resist 170 have different material properties. In this case, the material properties include the filler content.

[0208] At this point, it can be seen that there is a significant difference between the filler content contained in the first solder resist 160 and the filler content contained in the second solder resist 170, such as... Figure 6c As shown in (a). Furthermore, in an embodiment, by combining two materials for buffering the coefficient of thermal expansion to form the first solder resist 160 and the second solder resist 170, the coefficient of thermal expansion can be compensated, and thus the warping of the circuit board can be prevented.

[0209] Furthermore, the first solder resist 160 may have Dk 3.3 and Df 0.01@1GHz, and the second solder resist 170 may have Dk 3.5 and Df 0.015@1GHz. Therefore, since the dielectric constant can be reduced, the dielectric constant caused by the branching effect can be increased.

[0210] Figures 7 to 16 It is shown in the order of the processes. Figure 2 A view showing the manufacturing method of the circuit board.

[0211] refer to Figure 7 In this embodiment, the manufacturing process of the inner layer substrate 100-1 used to manufacture the internal portion of the circuit board 100 can be prioritized.

[0212] The process used to manufacture the inner layer substrate 100-1 will be briefly described.

[0213] The inner substrate 100-1 may include an insulating layer, or alternatively include multiple insulating layers.

[0214] exist Figure 7 In the diagram, the inner layer substrate 100-1 is shown as having a seven-layer insulating structure, but is not limited thereto. For example, the inner layer substrate 100-1 may include fewer than seven insulating layers, or alternatively, may include more than seven insulating layers.

[0215] The inner layer substrate 100-1 may include insulating layers other than the insulating layer disposed on the outermost layer of the circuit board 100. For example, the inner layer substrate 100-1 may include an insulating layer disposed on the uppermost portion of the circuit board 100 and other insulating layers other than the insulating layer disposed on the lowermost portion of the circuit board 100.

[0216] Briefly describe the process of manufacturing the inner layer substrate 100-1. First, the first insulating layer 111 is prepared.

[0217] Furthermore, when the first insulating layer 111 is prepared, a first through hole (V1) is formed in the first insulating layer (111), and a first circuit pattern 121 and a second circuit pattern 122 are formed on the upper and lower surfaces of the first insulating layer 111, respectively.

[0218] Subsequently, a second insulating layer 112 is formed on the first insulating layer 111, and a third insulating layer 113 is formed below the first insulating layer 111.

[0219] Next, a second through-hole V2 is formed in the second insulating layer 112, and a third circuit pattern 123 is formed on the upper surface of the second insulating layer 112. Furthermore, a third through-hole V3 is formed in the third insulating layer 113, and a fourth circuit pattern 124 is formed below the lower surface of the third insulating layer 113.

[0220] Subsequently, a fourth insulating layer 114 is formed on the second insulating layer 112, and a fifth insulating layer 115 is formed below the third insulating layer 113.

[0221] Next, a fourth through-hole V4 is formed in the fourth insulating layer 114, and a fifth circuit pattern 125 is formed on the upper surface of the fourth insulating layer 114. Furthermore, a fifth through-hole V5 is formed in the fifth insulating layer 115, and a sixth circuit pattern 126 is formed below the lower surface of the fifth insulating layer 115.

[0222] Subsequently, a sixth insulating layer 116 is formed on the fourth insulating layer 114, and a seventh insulating layer 117 is formed below the fifth insulating layer 115.

[0223] Next, a sixth through-hole V6 is formed in the sixth insulating layer 116, and a seventh circuit pattern 127 is formed on the upper surface of the sixth insulating layer 116. In addition, a seventh through-hole V7 is formed in the seventh insulating layer 117, and an eighth circuit pattern 128 is formed below the lower surface of the seventh insulating layer 117.

[0224] Since the process for manufacturing the inner layer substrate 100-1 is a known technology in the field to which this invention pertains, its detailed description will be omitted.

[0225] refer to Figure 8 When manufacturing the inner layer substrate 100-1, an eighth insulating layer 118 corresponding to the first outermost insulating layer is formed on the upper surface of the inner layer substrate 100-1. In addition, a ninth insulating layer 119 corresponding to the second outermost insulating layer is formed below the lower surface of the inner layer substrate 100-1.

[0226] At this time, when the eighth insulating layer 118 and the ninth insulating layer 119 are stacked, the primer layer 150 is disposed on each of the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119, and the metal layer 155 may be disposed on the primer layer 150. The metal layer 155 may be used to planarize the eighth insulating layer 118 and the ninth insulating layer 119 to have a uniform height. For example, the metal layer 155 may be arranged to improve the stacking reliability of the eighth insulating layer 118 and the ninth insulating layer 119.

[0227] The primer layer 150 can be used to increase the bonding strength between each of the eighth insulating layer 118 and the ninth insulating layer 119 and the first outer layer circuit pattern 130 and the second outer layer circuit pattern 140 disposed below and above them. That is, when the first outer layer circuit pattern 130 and the second outer layer circuit pattern 140 are not disposed of with the primer layer 150, they may separate from each other due to the low bonding strength between the eighth insulating layer 118 and the second outer layer circuit pattern 140.

[0228] At the same time, despite Figure 8 The diagram shows a primer layer 150 disposed on the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119, but the invention is not limited thereto. For example, the primer layer 150 can be selectively disposed on the surface of the insulating layer where a fine circuit pattern is to be disposed. That is, when only the first outer layer circuit pattern 130 is a fine circuit pattern, the primer layer 150 can be disposed only on the lower surface of the ninth insulating layer 119. Furthermore, when only the second outer layer circuit pattern 140 is a fine circuit pattern, the primer layer 150 can be disposed only on the upper surface of the eighth insulating layer 118. Furthermore, when both the first outer layer circuit pattern 130 and the second outer layer circuit pattern 140 are fine circuit patterns, the primer layer 150 can be disposed on the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119.

[0229] refer to Figure 9 When the eighth insulating layer 118 and the ninth insulating layer 119 are arranged, a through-hole VH is formed in each of the eighth insulating layer 118 and the ninth insulating layer 119. In this case, the through-hole VH can be formed not only in the eighth insulating layer 118 and the ninth insulating layer 119, but also in the primer layer 150 and the metal layer 155, respectively.

[0230] Next, refer to Figure 10When a via VH is formed, an etching process can be performed to remove the metal layer 155 disposed on the primer layer 150. For example, a flash etching process can be performed after the via VH is formed to remove the metal layer 155, and thus a process for exposing the surface of the primer layer 150 can be performed.

[0231] Next, refer to Figure 11 A via (V) forming process for filling via holes (VH) can be performed. Therefore, the second outer layer circuit pattern 140 is formed on the upper surface of the eighth insulating layer 118, and the first outer layer circuit pattern 130 can be formed on the lower surface of the ninth insulating layer 119. In this case, in the embodiment, the first outer layer circuit pattern 130 is shown as a general circuit pattern rather than a fine circuit pattern. However, the invention is not limited thereto, and both the first outer layer circuit pattern 130 and the second outer layer circuit pattern can be fine circuit patterns. Therefore, when the first outer layer circuit pattern 130 is a general circuit pattern, the primer layer 150 between the ninth insulating layer 119 and the first outer layer circuit pattern 130 can be omitted.

[0232] The second outer layer circuit pattern 140 is disposed on the upper surface of the eighth insulating layer 118. In this case, the second outer layer circuit pattern 140 disposed on the upper surface of the eighth insulating layer 118 may include a portion disposed in the open region R1 of the first protective layer 170 and a portion disposed in the disposal region R2 of the first passivation layer 170. Furthermore, each of the above portions may include a trace 141 as wiring for signal transmission and a pad 142 corresponding to the end of the trace 141 to which the component will be attached.

[0233] Next, refer to Figure 12 A first solder resist 160 is disposed on a primer layer 150 to cover the second outer layer circuit pattern 140. The first solder resist 160 formed at this time can be disposed in both the first region R1 and the second region R2, and can be formed to have a greater height than the second outer layer circuit pattern 140.

[0234] When the first solder resist 160 is formed, the first solder resist 160 is exposed and developed. By exposing and developing the first solder resist 160, the first solder resist 160 can have a lower height than the second outer layer circuit pattern 140.

[0235] Therefore, UV exposure is performed by only masking the desired area on the first solder resist 160, and then, by immersing in an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline), a process can be performed to adjust the height of the first solder resist 160 in the unexposed area.

[0236] Furthermore, refer to Figure 13 When the above process is performed, the first solder resist 160 can be formed to have a height that is lower than that of the second outer layer circuit pattern 140.

[0237] The first solder resist 160 may have a second height H2 and be disposed on the primer layer 150.

[0238] In this case, the first height H1 is greater than the second height H2. Preferably, the first solder resist 160 can be disposed among a plurality of second outer layer circuit patterns 140, contacting the side surfaces of the second outer layer circuit patterns 140, while having a height smaller than the height of the second outer layer circuit patterns 140. In this case, the second height H2 can be 30% to 50% of the first height H1. For example, when the second height H2 is less than 30% of the first height H1, the second outer layer circuit pattern 140 may not be stably supported by the first solder resist 160. For example, when the second height H2 is less than 30% of the first height H1, there may be difficulties in the process of forming the first solder resist 160. For example, when the second height H2 is greater than 50% of the first height H1, a portion of the filler contained in the first solder resist 160 may remain in the second outer layer circuit pattern 140. For example, when the second height H2 is greater than 50% of the first height H1, there may be difficulties in the process of forming the second solder resist 170.

[0239] Next, as Figure 14 As shown, the second solder resist 170 is disposed on the first solder resist 160. In this case, the second solder resist 170 can be disposed such that it has a height greater than the height of the second outer layer circuit pattern 140 in both the first region R1 and the second region R2.

[0240] After that, as Figure 15 As shown, UV exposure is performed by masking only the desired area on the second solder resist 170, and then, by immersing in an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline), a process can be performed to adjust the height of the second solder resist 170 in the unexposed area.

[0241] In other words, a process to remove a portion of the second solder resist 170 can be performed by performing an exposure and development process on the second solder resist 170, such that the height in the first region R1 and the height in the second region R2 are different from each other.

[0242] Next, as Figure 16 As shown, the second solder resist 170 includes a first portion disposed in a first region R1 and a second portion disposed in a second region R2 and having a different height from the first portion by performing an exposure and development process of the second solder resist 170.

[0243] That is, through the above process, the second solder resist 170 can be arranged on the first solder resist 160 to have different heights for each area.

[0244] The second solder resist 170 may include a first portion disposed in the first region R1 and a second portion disposed in the second region R2.

[0245] In this configuration, the first portion of the second solder resist 170 may have a third height H3 and be disposed on the first solder resist 160. Furthermore, the second portion of the second solder resist 170 may have a fourth height H4 and be disposed on the first solder resist 160.

[0246] In this case, the third height H3 is greater than the first height H1 and the second height H2. Preferably, a first portion of the second solder resist 170 can be disposed on the first solder resist 160, while having a height smaller than that of the second outer layer circuit pattern 140. In this case, the third height H3 can be 70% to 90% of the first height H1. For example, when the third height H3 is less than 70% of the first height H1, the second outer layer circuit pattern 140 may not be stably supported by the second solder resist 170. For example, when the third height H3 is less than 70% of the first height H1, difficulties may arise in the process of forming the second solder resist 160. For example, when the third height H3 is greater than 90% of the first height H1, a portion of the filler contained in the second solder resist 170 may remain on the second outer layer circuit pattern 140. For example, when the third height H3 is greater than 90% of the first height H1, due to deviations in the process of forming the second solder resist 170, the surface of the second outer layer circuit pattern 140 may be covered by the second solder resist 170.

[0247] Meanwhile, the fourth height H4 can be greater than the first height H1, the second height H2, and the third height H3. Preferably, the fourth height H4 can be 120% to 200% of the first height H1. For example, when the fourth height H4 is less than 120% of the first height H1, the surface of the second outer layer circuit pattern 140 of the second region R2 may not be stably protected by the second solder resist 170. For example, when the fourth height H4 is greater than 200% of the first height H1, the overall thickness of the circuit board may increase.

[0248] The coefficient of thermal expansion of the first solder resist 160 can be less than that of the second solder resist 170. For example, the first solder resist 160 can have a coefficient of thermal expansion of 10 to 25 ppm (@alpha 1). For example, the second solder resist 170 can have a coefficient of thermal expansion of 30 to 50 ppm (@alpha 1). That is, the embodiment allows for minimizing the occurrence of circuit board warping due to CTE relaxation by preferentially distributing the first solder resist 160 with a low coefficient of thermal expansion on the primer layer 150 and distributing the second solder resist 170 with a high coefficient of thermal expansion on the first solder resist 160.

[0249] Meanwhile, the filler content in the first solder resist 160 may differ from the filler content in the second solder resist 170. Preferably, the filler content in the first solder resist 160 may be higher than the filler content in the second solder resist 170.

[0250] That is, the upper surface of the second solder resist 170 is positioned adjacent to the upper surface of the second outer layer circuit pattern 140, and therefore, a portion of the filler contained in the second solder resist 170 may remain on the upper surface of the second outer layer circuit pattern 140. Therefore, the filler content in the second solder resist 170 is lower than the filler content in the first solder resist 160 to prevent this.

[0251] Furthermore, the filler content in the first solder resist 160 is relatively higher than the filler content in the second solder resist 170. In this case, the upper surface of the first solder resist 160 is spaced apart from the upper surface of the second outer layer circuit pattern 140 by a predetermined distance. Therefore, the filler contained in the first solder resist 160 will not remain on the second outer layer circuit pattern 140 during the process of forming the first solder resist 160.

[0252] For example, SiO2 filler may be included in the first solder resist 160, and its content may be from 50 wt% to 65 wt%.

[0253] In addition, the second solder resist 170 may include fillers such as BaSO4, SiO2, talc, etc., and its content may be from 20wt% to 35wt%.

[0254] In the above embodiments, by adjusting the filler content in the second solder resist 170 included in the embodiments described above, the situation of filler residue on the surface of the second outer layer circuit pattern 140 is prevented in advance, and thus the reliability of the circuit board is improved.

[0255] The circuit board of the embodiment is a multilayer circuit board with eight or more layers, and includes an outer layer circuit pattern disposed on the uppermost outer insulating layer of the multilayer and protruding from the surface of the outer insulating layer. In this case, the outer layer circuit pattern includes: a second-first circuit pattern disposed in a second region of the upper region of the outer insulating layer where solder resist (SR) is disposed; and a second-second circuit pattern disposed in a first region that is an open region where no solder resist is disposed. In this case, the second-first circuit pattern can be supported by being surrounded by solder resist, but since the second-second circuit pattern does not have a support layer capable of supporting the second-first circuit pattern, it may be prone to collapse due to various factors.

[0256] Therefore, a support layer capable of supporting the second-second circuit pattern of the embodiment is formed on the first insulating layer corresponding to the outer insulating layer. In this case, the support layer in the embodiment can be implemented using a solder resist with a multilayer structure. Preferably, the multilayer solder resist in the embodiment is arranged between multiple second-second circuit patterns, while simultaneously covering the second-first circuit pattern and exposing the second-second circuit pattern.

[0257] Therefore, embodiments can address problems such as collapse or wear of protruding outer layer circuit patterns by miniaturizing the outer layer circuit patterns, thereby improving product reliability. In particular, embodiments can address problems such as collapse or friction of outer layer circuit patterns in the first region, thereby improving product reliability.

[0258] In this embodiment, the solder resist may include a first solder resist and a second solder resist. Furthermore, the first solder resist may be disposed in the first and second regions at a height lower than the height of the second-second circuit pattern. Preferably, the upper surface of the first solder resist may be positioned lower than the upper surface of the second circuit pattern in the first and second regions. Furthermore, the second solder resist is disposed on the first solder resist, and therefore may have a different height for each region. That is, the upper surface of the second solder resist in the first region is disposed at a height lower than the upper surface of the second-first and second-second circuit patterns, and the upper surface of the second solder resist in the second region may be disposed at a height higher than the upper surface of the second-first and second-second circuit patterns. In this case, the first and second solder resists may have different material properties. Preferably, the first solder resist may include a material having a high filler content while having a lower CTE compared to the second solder resist.

[0259] Therefore, embodiments can mitigate CTE in the circuit board stack-up structure by applying a first solder resist and a second solder resist with different CTEs, minimizing the occurrence of circuit board warpage. Furthermore, embodiments can prevent filler residue on the surface of the second-to-second circuit pattern by using a second solder resist with a lower filler content than the first solder resist, thus improving reliability.

[0260] Furthermore, when removing the first and second solder resists in this embodiment, exposure and development methods are used instead of sandblasting or plasma methods. When removing the solder resist using sandblasting or plasma methods, the outer layer circuit pattern may be deformed, and in some cases, the cross-section of the outer layer circuit pattern may have a triangular shape. Moreover, when the cross-section of the outer layer circuit pattern is triangular, the adhesive members may not be stably arranged on the outer layer circuit pattern, potentially leading to reliability issues. In contrast, the first and second solder resists in this embodiment can be removed without deforming the outer layer circuit pattern, thus improving reliability.

[0261] Furthermore, the circuit board of the embodiment can be applied to 5G communication systems, and therefore, reliability can be further improved by minimizing transmission loss at high frequencies. Specifically, the circuit board of the embodiment can be used at high frequencies and can reduce propagation loss.

[0262] The features, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. Furthermore, those skilled in the art to which the embodiments pertain can combine or modify the features, structures, effects, etc., shown in each embodiment relative to other embodiments. Therefore, content related to such combinations and modifications is also included within the scope of the embodiments.

[0263] The above description focuses on embodiments, but it is illustrative only and does not limit the embodiments. Those skilled in the art will understand that various modifications and applications not shown above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically represented in the embodiments can be modified and implemented. Furthermore, it should be understood that differences associated with these changes and applications are included within the scope of the invention as defined by the appended claims.

Claims

1. A circuit board comprising: an insulating layer; a circuit pattern arranged on the insulating layer; and a protective layer arranged on the insulating layer; wherein the protective layer comprises: a first layer arranged on the insulating layer; and a second layer arranged on the first layer of the protective layer; wherein the second layer comprises a first portion having a first height and a second portion having a second height greater than the first height with respect to an upper surface of the insulating layer and a step with respect to the first portion, and wherein the circuit pattern comprises a first circuit pattern in contact with the first portion of the second layer and a second circuit pattern in contact with the second portion of the second layer, and wherein an upper surface of the first portion of the second layer is positioned lower than an upper surface of the first circuit pattern with respect to an upper surface of the insulating layer, and wherein an upper surface of the second portion of the second layer is positioned higher than an upper surface of the second circuit pattern with respect to the upper surface of the insulating layer. a thickness of the first layer of the protective layer is less than a thickness of the circuit pattern.

2. The circuit board of claim 1, wherein, a thickness of the first layer in an area vertically overlapping the first portion of the second layer is equal to a thickness of the first layer in an area vertically overlapping the second portion of the second layer.

3. The circuit board of claim 2, wherein, an upper surface of the first circuit pattern does not contact the first layer and the second layer, and an upper surface of the second circuit pattern is covered by the second layer.

4. The circuit board of claim 1, wherein, a width of the second portion is less than a width of the first portion.

5. The circuit board of claim 4, wherein, an upper surface of the first portion of the second layer is positioned lower than an upper surface of each of the first circuit pattern and the second circuit pattern.

6. The circuit board of claim 5, wherein, an upper surface of the second portion of the second layer is positioned higher than an upper surface of each of the first circuit pattern and the second circuit pattern.

7. The circuit board of claim 5, wherein, a sum of a thickness of the first layer and a thickness of the first portion of the second layer is less than a thickness of the first circuit pattern.

8. The circuit board of claim 6, wherein, side surfaces of the first circuit pattern comprise:

9. The circuit board of claim 4, wherein, a first side surface in contact with the first layer of the protective layer; a second side surface in contact with the first portion of the second layer of the protective layer; and a third side surface not in contact with the protective layer. the second portion of the second layer of the protective layer completely covers side surfaces of the second circuit pattern.

10. The circuit board of claim 7, wherein, the first layer and the second layer of the protective layer comprise a solder resist.

11. The circuit board of claim 1, wherein, material properties of the first layer of the protective layer are different from material properties of the second layer.

12. The circuit board of claim 1, wherein, a coefficient of thermal expansion of the first layer is less than a coefficient of thermal expansion of the second layer.

13. The circuit board of claim 12, wherein, each of the first layer and the second layer comprises a filler, and 14. The circuit board of claim 13, wherein, wherein a filler content in the first layer is greater than a filler content in the second layer. the filler content in the first layer is 50w% to 65w%, and 15. The circuit board of claim 14, wherein, wherein the filler content in the second layer is 20w% to 35w%. ​ 16. The circuit board of claim 2, wherein, A thickness of the first layer of the protective layer satisfies 30% to 50% of a thickness of each of the first circuit pattern and the second circuit pattern.

17. The circuit board of claim 6, wherein, A height from a lower surface of the first layer of the protective layer to an upper surface of the first portion of the second layer satisfies 70% to 90% of a height from a lower surface of the first circuit pattern to an upper surface of the first circuit pattern.

18. The circuit board of claim 1, wherein, The insulating layer includes a plurality of insulating layers, and The circuit pattern protrudes on an upper surface of an uppermost insulating layer among the plurality of insulating layers.

19. The circuit board of claim 1, further comprising: a primer layer disposed in an area between the first layer of the protective layer and an upper surface of the insulating layer and in an area between the circuit pattern and the upper surface of the insulating layer; and a via hole passing through the insulating layer and the primer layer.

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