System and method for modeling through-hole defects and storage medium

Abstract

A method and system for modeling via defects, and a non-transitory computer-readable storage medium, are disclosed. The method includes obtaining a design layout of a standard cell, extracting characteristic information of one or more vias in the standard cell from the design layout, performing circuit simulation on an input example by applying a first abnormal resistance value as a parasitic resistance value of a first via among the one or more vias to obtain a first simulation output of the standard cell, wherein the first abnormal resistance value is different from a nominal parasitic resistance value of the first via, determining whether the first simulation output of the standard cell for the input example matches a corresponding expected output, and, in response to one or more of the first simulation outputs not matching the corresponding expected output, recording one or more defect types of the first via having the first abnormal resistance value, the corresponding input example, and the corresponding simulation output.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method and system for modeling through-hole defects and a non-transitory computer-readable storage medium. Background Art

[0002] Semiconductor circuits can include various front-end-of-line (FEOL) layers and various middle-end-of-line (MEOL) and back-end-of-line (BEOL) layers. FEOL layers can include devices such as transistors, capacitors, resistors, etc., and MEOL / BEOL layers can include metal layers and vias that interconnect individual devices or units of the FEOL layer on the wafer. As logic designs in integrated circuits (ICs) become larger and more complex, the number of MEOL / FEOL layers is also increasing. Therefore, smarter testing of MEOL / FEOL layers is needed to ensure fault-free performance of the final IC. Summary of the Invention

[0003] According to one aspect of an embodiment of the present invention, a method for modeling a through-hole defect is provided, comprising: obtaining a design layout of a standard cell; extracting characteristic information of one or more through-holes in the standard cell from the design layout; performing a circuit simulation on an input example to obtain a first simulation output of the standard cell by applying a first abnormal resistance value as a parasitic resistance value of a first through-hole among the one or more through-holes, the first abnormal resistance value being different from a nominal parasitic resistance value of the first through-hole; determining whether the first simulation output of the standard cell for the input example matches a corresponding expected output; and in response to one or more simulation outputs among the first simulation outputs not matching the corresponding expected output, recording one or more defect types of the first through-hole having the first abnormal resistance value, as well as the corresponding input example and the corresponding simulation output.

[0004] According to another aspect of an embodiment of the present invention, a system for modeling through-hole defects is provided, comprising: a processor; and one or more memories storing instructions of one or more programs executable by the processor to perform operations, the operations comprising: obtaining a design layout of a target cell, the target cell comprising a first standard cell and a second standard cell, the first standard cell comprising a first through-hole, and the second standard cell comprising a second through-hole; and generating a test case for the target cell, the test case enabling detection of a first defect type recorded for the first standard cell and a second defect type recorded for the second standard cell, the first defect type being associated with a first through-hole, a first input case, and a first abnormal resistance value that is different from a parasitic resistance value of the first through-hole, and the second defect type being associated with a second through-hole, a second input case, and a second abnormal resistance value that is different from a parasitic resistance value of the second through-hole, wherein the test case is generated based on the first input case and the second input case.

[0005] According to another aspect of an embodiment of the present invention, a non-transitory computer-readable storage medium is provided, storing a set of instructions that can be executed by one or more processors of a device to enable the device to perform a method, the method comprising: obtaining a design layout of a target cell, the target cell comprising a standard cell, the standard cell comprising one or more through-holes; and generating a test case for the target cell, the test case enabling detection of one or more defect types recorded for the standard cell, the one or more defect types comprising a defect type associated with a selected through-hole among the one or more through-holes and an input case and an abnormal resistance value different from the parasitic resistance value of the selected through-hole, wherein the test case is generated based on the input case. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various components are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A A layout diagram of a portion of a circuit according to some embodiments of the present disclosure is illustrated.

[0008] Figure 1B A circuit diagram illustrating a portion of a circuit according to some embodiments of the present disclosure is illustrated.

[0009] Figure 2A-2C An example of a via defect according to some embodiments of the present disclosure is illustrated.

[0010] Figure 3 is a flow chart illustrating a method of modeling and correcting through-hole defects according to some embodiments of the present disclosure.

[0011] Figure 4A A simplified standard cell layout design according to some embodiments of the present disclosure is illustrated.

[0012] Figure 4B The diagram illustrates some embodiments of the present disclosure along Figure 4A Cross-sectional view along line AA'.

[0013] Figure 4C Illustrated is example position information of a through-hole according to some embodiments of the present disclosure.

[0014] Figure 5 is an example through-hole feature table according to some embodiments of the present disclosure.

[0015] Figure 6A is a flow chart illustrating a method of modeling a through-hole defect according to some embodiments of the present disclosure.

[0016] Figure 6B is a circuit diagram of an example standard cell according to some embodiments of the present disclosure.

[0017] Figure 6C is a table of example simulation results according to some embodiments of the present disclosure.

[0018] Figure 6D is an example defect model table according to some embodiments of the present disclosure.

[0019] Figure 7 Illustrated are example testing paradigms for example target units according to some embodiments of the present disclosure.

[0020] Figure 8 is an example test result analysis table according to some embodiments of the present disclosure.

[0021] Figure 9 is an example computing device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which each term is used. The use of examples in this specification (including examples of any term discussed herein) is illustrative only and in no way limits the scope and meaning of the present disclosure or any exemplified term. Likewise, the present disclosure is not limited to the various embodiments given in this specification.

[0024] Although the terms "first," "second," and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] Furthermore, for ease of description, spacing terms such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. Spacing terms are intended to encompass different orientations of the device in use or during operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and spacing descriptors used herein should be interpreted accordingly.

[0026] Herein, the term “coupled” may also be referred to as “electrically coupled,” and the term “connected” may be referred to as “electrically connected.” “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

[0027] Semiconductor circuits may include various front-end-of-line (FEOL) layers and various middle-end-of-line (MEOL) and back-end-of-line (BEOL) layers. FEOL layers may include devices such as transistors, capacitors, resistors, etc., and MEOL / BEOL layers may include metal layers and vias that interconnect individual devices or units of the FEOL layers on the wafer. As logic designs in integrated circuits (ICs) become larger and more complex, the number of MEOL / FEOL layers is also increasing. Therefore, smarter testing of the MEOL / FEOL layers is needed to ensure fault-free performance of the final IC. However, using traditional physical failure analysis, it is difficult to identify defects and defect locations in the MEOL / BEOL layers, at least in part because defects in the MEOL / BEOL layers do not create hot spots for electron-hole combinations.

[0028] Figure 1A 1 illustrates a layout diagram of a portion of a circuit according to some embodiments of the present disclosure. Figure 1A In FIG, NMOS (N-type metal oxide semiconductor) devices and PMOS (P-type metal oxide semiconductor) devices correspond to devices of the FEOL layer. Figure 1A As shown, NMOS devices and PMOS devices are interconnected with various metal layers and through-holes. In some embodiments, the semiconductor circuit may include an array of cells, each of which includes a logic circuit. Figure 1A As shown, portion 100 of the circuit may correspond to one unit of the circuit. Figure 1B A circuit diagram of unit 100 is shown, which is provided as an example for illustration purposes. Figure 1B As shown, Figure 1A The unit 100 includes two AND gates 110 and 120 and a NOR gate 130 .

[0029] To detect circuits (e.g. Figure 1B Defects in metal layers and vias of the cell 100) can typically be detected by applying test inputs to the circuit (e.g., Figure 1B Input bits I0 to I3) and observing the output of the circuit (e.g., Figure 1B However, many defects located within the cell 100 may result in the same output value O, so identifying the defect location or the root cause of the defect may be very challenging. Figure 1A As shown, metal layers in semiconductor circuits can span large areas and even extend beyond cell boundaries, resulting in very ambiguous defect boundaries. Consequently, modeling a circuit's metal layers or metal sections may not effectively identify or specify defects or their locations within the circuit. To improve defect diagnosis and isolation processes, effective techniques for modeling MEOL / BEOL defects are needed.

[0030] like Figure 1A As shown, while the number of vias continues to increase, the number of vias in a circuit unit is limited. In addition, defects in the metal segments associated with the vias may appear as via defects. Some embodiments provided herein model MEOL / BEOL defects based on vias, without estimating the metal line layout polygon shape. Via defects are typically high-resistance defects, rather than hard defects such as electrical disconnects, which can cause very short timing effects on the circuit and are therefore difficult to diagnose and isolate.

[0031] Figure 2A-2C An example of a via defect according to some embodiments of the present disclosure is shown. Figure 2A An example 210 of a via defect 211 caused by an under-etch in the metal layer M0 connected to the first via VIA0 is shown. Although the first via VIA0 is not completely connected to the metal layer M0 due to the under-etch, the first via VIA0 may exhibit a high resistance rather than being electrically disconnected from the metal layer M0 due to the very short gap therebetween. Figure 2B An example of a via defect 220 caused by an anomaly in metal layer M0 is shown. For example, an additional segment 221 of a material different from that of metal layer M0 is included in metal layer M0. When the electrical conductivity of the material of additional segment 221 is lower than that of metal layer M0, this defect in metal layer M0 may manifest as a defect having a high resistance on first via VIA0. Figure 2C An example 230 of a via defect 231 caused by a partial loss of the second via VIA1 is shown. For example, the metal material is not completely filled in the second via VIA1. The second via VIA1 may have a higher resistance than the nominal resistance.

[0032] As discussed above, vias are often a common source of continuous resistance in standard cells, and therefore defective vias are often high-resistance defects. Some embodiments of the present disclosure may provide methods for modeling MEOL / BEOL defects based on vias in a circuit. According to some embodiments of the present disclosure, via defects can be modeled as either abnormal resistance defects or high-resistance defects.

[0033] Figure 3 is a flow chart illustrating a method 300 for modeling and correcting through-hole defects according to some embodiments of the present disclosure. According to some embodiments of the present disclosure, at least part of the steps in the method 300 may be implemented using a computing device, for example, Figure 9 The computing device shown.

[0034] According to some embodiments of the present disclosure, in step S310, a standard cell design layout is obtained. In some embodiments, the standard cell design layout can be received from a cell library 311. The cell library 311 can be a storage of the design layout of the standard cells of the circuit. In some embodiments, the standard cell design layout can be in a Graphic Database System (GDS) format, a Graphic Database System II (GDS II) format, an Open Image System Interchange Standard (OASIS) format, or the like. In some embodiments, the standard cell can be a group of transistors and interconnect structures that provide Boolean logic functions, such as AND, OR, NOR, XOR, XNOR, inverters, etc., or a group of transistors and interconnect structures that provide storage functions, such as flip-flops or latches. Some simple cells can be direct representations of basic NAND, NOR, and XOR Boolean functions, although other cells that are much more complex are often used.

[0035] Figure 4A A simplified standard cell layout design according to some embodiments of the present disclosure is illustrated. Figure 4A The layout design of the standard cell 400 shown is a simplified layout design corresponding to an AND gate, which is an example provided for illustration purposes. Figure 4A As shown, the layout design of the standard cell 400 includes a plurality of vias such as VIA1 to VIA6 and a plurality of metal sections represented as metal layers. Figure 4A In the OD layer, it refers to the "oxide definition (OD) region" of the active area of ​​the transistor, that is, the region where the channel below the source, drain and gate of the transistor is formed. Figure 4A In the embodiment, a polysilicon layer may be provided to provide electrical connectivity between the OD layer and the metal layer.

[0036] Return Reference Figure 3In step S320, information about the standard cell may be extracted. In some embodiments, layout features of the standard cell 400 may be extracted to extract via information about the standard cell 400. In some embodiments, a netlist describing the connectivity of various electronic components of the standard cell 400 may be extracted. For example, the netlist may include a list of electronic components in the standard cell 400 and a list of nodes to which the electronic components are connected. In some embodiments, the via information about the standard cell 400 may be obtained based on the layout features or the netlist of the standard cell.

[0037] According to some embodiments, the via information may include layer information, location information, resistance information, etc. In some embodiments, the via in the standard cell may be identified by a node in the standard cell. In some embodiments, a node may be associated with a via, and the via location and via type may be determined based on the node information. For example, Figure 4A As shown, the vias are located where two metal sections intersect. In this example, six vias VIA1 to VIA6 can be identified from the standard cell 400 .

[0038] In some embodiments, layer information of the identified via may be extracted from the layout features or the netlist of the standard cell 400. In some embodiments, the layer information of the via may be layer mapping information about the layer to which the via is connected. Figure 4B Shown along Figure 4A The cross-sectional view of the line A-A'. Figure 4B As shown, a first via VIA1 extends between a first layer L1 and a second layer L2, a second via VIA2 extends between a first layer L1 and a third layer L3, and a third via VIA3 extends between a third layer L3 and a fourth layer L4. In some embodiments, the layer information for the first via VIA1 may be layer numbers L1 and L2, the layer information for the second via VIA2 may be layer numbers L1 and L3, and the layer information for the third via VIA3 may be layer numbers L3 and L4. In some embodiments, the first layer L1 to the third layer L3 may be metal layers. Although the layer mapping of the vias has been explained based on metal layers, it should be understood that layer mapping based on different layering systems may also be employed.

[0039] In some embodiments, the position information of the identified vias may be extracted from the layout features or netlist of the standard cell 400. In some embodiments, the position information of the vias may be the relative XY positions of the corresponding vias in the standard cell layout. Figure 4C 1 shows example location information of through holes according to some embodiments of the present disclosure. Figure 4C As shown in FIG, the through hole can be an area rather than a point. Therefore, the position information that can define the position together with the area of ​​the through hole can be used as the position information of the through hole. Figure 4CIn the example, the xy coordinates (x1, y1, x2, y2) of the upper left and lower right corners can be used to define the position of the through hole. It should be understood that different formats of position information can be used. For example, when the area of ​​the through hole has a circular shape, the position information of the through hole can be defined as the xy coordinates and radius of the through hole center.

[0040] In some embodiments, resistance information of the identified through-hole can be extracted. In some embodiments, the resistance information can be the parasitic resistance of the identified through-hole. In some embodiments, the parasitic resistance of the through-hole can be determined based on the material information of the through-hole and the PVT (process, voltage and temperature) operating conditions that can be provided by the user. In some embodiments, the parasitic resistance determined in this step is referred to as the nominal parasitic resistance in this disclosure. The nominal parasitic resistance of the through-hole can be the resistance value that the through-hole can have in normal operation by the through-hole design. In the present disclosure, the nominal parasitic resistance values ​​of the first through-hole VIA1 to the third through-hole VIA3 can be expressed as R1 to R3. It should be understood that the nominal parasitic resistance values ​​R1 to R3 can be different from each other or the same.

[0041] Figure 5 is an example of a through-hole feature table 500 according to some embodiments of the present disclosure. In some embodiments, it may be as follows Figure 5 The through hole feature information is organized as shown. Figure 5 As shown in FIG, for each through hole in a standard cell, layer information, position information, and parasitic resistance information can be extracted and recorded. Figure 5 Only three vias VIA1 to VIA3 are shown, but it should be understood that the via feature information of all vias in the standard cell can be similarly extracted and organized. Although the extraction of the via feature information of one standard cell (e.g., standard cell 400) is explained, it should be understood that the extraction of the via feature information of other standard cells can also be performed in a similar manner, and the recording of the via feature information of other standard cells can also be performed in a similar manner. For example, the via feature information of one or more standard cells representing OR, NOR, XOR, XNOR, inverter, flip-flop, or latch can also be extracted and recorded.

[0042] Return Reference Figure 3 In step S330, according to some embodiments of the present disclosure, a via defect may be modeled for a standard cell. In some embodiments, the via defect may be modeled based on a simulation by applying an abnormal resistance to the via. In some embodiments, the abnormal resistance may be a resistance value of the via that is different from the nominal parasitic resistance value of the via. For example, Figure 5A resistance value different from the nominal parasitic resistance value R1 in the first through-hole VIA1 is applied to the first through-hole VIA1. According to some embodiments of the present disclosure, a set of abnormal resistance values ​​of the through-hole can be determined based on the nominal parasitic resistance value of the corresponding through-hole. For example, for the first through-hole VIA1, one or more abnormal resistance values ​​different from the nominal parasitic resistance value R1 can be determined. In some embodiments, the abnormal resistance value can be less than or greater than the nominal resistance value. In some embodiments, the abnormal resistance value can be a value outside a predetermined error margin. In some embodiments, the error margin can be determined, for example, based on experiments, simulations, system requirements, etc.

[0043] In some embodiments, the abnormal resistance value of a particular through-hole can be determined based on the node and material properties of the corresponding through-hole. For example, through-holes may have different error margins, depending on the node and material properties of the corresponding through-hole. In the present disclosure, for illustrative purposes, a set of abnormal resistance values ​​may include values ​​such as 10 ohms, 100 ohms, 1000 ohms, 10,000 ohms, 100,000 ohms, etc. In this example, for illustrative purposes only, it is assumed that the nominal resistance value of the first through-hole VIA1 is 50 ohms and the error margin is set to + / - 10%. Although some embodiments are described with respect to a set of abnormal resistance values ​​such as 10 ohms, 100 ohms, 1000 ohms, 10,000 ohms, 100,000 ohms, etc., it should be understood that other sets of abnormal resistance values ​​selected outside the error margin of a particular through-hole may be used in the present disclosure. In some embodiments, different sets of abnormal resistance values ​​may be set and used for other through-holes, such as the second through-hole VIA2 or the third through-hole VIA3.

[0044] According to some embodiments, for each via, a circuit-level simulation can be performed for all input examples of the standard cell to estimate the output of the standard cell by changing the parasitic resistance value to a set of abnormal resistance values. In some embodiments, the circuit-level simulation can be performed using simulation software such as SPICE (Simulation Program with Integrated Circuit Emphasis). The modeling of via defects according to some embodiments of the present disclosure will be described in detail below.

[0045] Figure 6A is a flow chart illustrating a method of modeling a via defect according to some embodiments of the present disclosure. In the present disclosure, the method of modeling a via defect will be explained by referring to a standard cell representing an AND gate. Figure 6B FIG. 6 is a circuit diagram 610 showing an example standard cell 400 of an AND gate. Figure 6BAs shown, AND gate 611 receives two inputs I0 and I1 and outputs output 0. In this disclosure, it will be assumed that AND gate 611 includes a first through-hole VIA1 and a second through-hole VIA2 in a cell. In some embodiments, input examples of AND gate 611 can be 00, 01, 10, and 11.

[0046] Return Reference Figure 6A , for each through-hole, an abnormal resistance value may be set in step S601. According to some embodiments of the present disclosure, the abnormal resistance value may be applied to one through-hole at a time. In some embodiments, when the abnormal resistance value of the first through-hole VIA1 is applied for simulation, the nominal parasitic resistance value of the second through-hole VIA2 is applied to estimate the impact of the abnormal resistance value of the first through-hole VIA1. Similarly, when the abnormal resistance value of the second through-hole VIA2 is applied for simulation, the nominal parasitic resistance value of the first through-hole VIA1 is applied. In some embodiments, one abnormal resistance value from a set of abnormal resistance values ​​of the first through-hole VIA1 may be set for simulation. In this example, the first abnormal resistance value of the first through-hole VIA1 is 10 ohms.

[0047] In step S602, a simulation may be run for all input cases of the standard cell 400 for the set of abnormal resistance values ​​of the selected vias. In some embodiments, a circuit-level simulation of the standard cell 400 is performed for all input cases, i.e., 00, 10, 10, and 11, to obtain output values ​​for each input case.

[0048] In step S603, the analog output value of the standard cell 400 is estimated for each input case. In some embodiments, the analog output value is estimated to determine whether the analog output value matches the expected output value of the standard cell 400 for the corresponding input case. The expected output value is the output value of the standard cell for the input case when the standard cell is implemented without defects. For input case 00, the expected output of the standard cell 400 representing an AND gate is a value of 0, for input case 01, the expected output of the standard cell 400 is a value of 0, for input case 10, the expected output of the standard cell 400 is a value of 0, and for input case 11, the expected output of the standard cell 400 is a value of 1. Figure 6C is an example simulation results table 620 according to some embodiments of the present disclosure. Figure 6C The first row of FIG shows the simulation results when the first abnormal resistance value of 10 ohms is applied. Figure 6C As shown, when the first abnormal resistance value of 10 ohms is applied, the simulated outputs for the input examples respectively match the expected outputs. Therefore, there is no defect type to be recorded or reported.

[0049] According to some embodiments of the present disclosure, steps S601 to S603 may be repeated for all abnormal resistance values ​​in the set of abnormal resistance values ​​of the first via VIA1 . For example, steps S601 to S603 may be repeated for abnormal resistance values ​​of 100 to 100,000 ohms.

[0050] According to some embodiments, when a mismatch between the expected output and the simulated output is observed, step S604 may be performed. Figure 6C As shown, when the third abnormal resistance value of 1000 ohms is applied, the simulated output of input example 10 differs from the expected output indicated by the box. Similarly, when the fourth and fifth abnormal resistance values ​​of 10,000 ohms and 100,000 ohms are applied, there is a mismatch between the expected output and the simulated output of input example 10. In some embodiments, a mismatch between the simulated output and the expected output can be determined when the simulated output deviates from the expected output by a predetermined threshold.

[0051] In step S604, when there is a mismatch between the simulated output and the expected output, the defect type is recorded. Figure 6C As shown, for the first through hole VIA 1, the defect types D11 to D15 are listed in the table 620 corresponding to abnormal resistance values ​​of 10 to 100,000 ohms. In some embodiments, when the simulation output does not match the expected output, the corresponding defect type can be reported and / or recorded as a defect model table, which will be referenced by Figure 6D To explain.

[0052] Figure 6D is an example defect model table 630 according to some embodiments of the present disclosure. Figure 6D As shown, the defect model table 630 may include a defect type (e.g., D13, D14, or D15), a corresponding via identifier (e.g., VIA1 or VIA2), corresponding via feature information (e.g., via layer information, via location information, etc.), corresponding abnormal resistance value, a detection example for detecting the corresponding defect type, etc. In some embodiments, each row of the defect model table 630 may represent a defect model for a via. In some embodiments, the detection example may be an input example that causes a mismatch between the simulated output and the expected output. For example, in Figure 6C In Table 620, for the defect type D13 in which the third abnormal resistance value 1000 ohms is applied to the first through hole VIA1, the simulation output of the input example 10 is different from the expected output. Figure 6D In the defect model table 630, the detection example of defect type D13 is listed as example 10. Similarly, the detection examples of defect types D14 and D15 can be determined as example 10. According to some embodiments of the present disclosure, the detection examples can be test examples to detect defects related to the corresponding defect type.

[0053] According to some embodiments of the present disclosure, steps S601 to S603 or steps S601 to S604 may be repeated for all other vias in the standard cell. For example, steps S601 to S603 or steps S601 to S604 may be performed on the second via VIA2 and other vias in the standard cell. Figure 6D The defect model table 630 lists the defect type D23 of the second through hole VIA2 and the detection examples 00 and 01. It should be understood that the method 600 can be performed for additional standard cells, and a similar method can be established for each standard cell. Figure 6D The defect model table 630 is a defect model table.

[0054] Return Reference Figure 3 In step S340, a target cell design layout is obtained according to some embodiments of the present disclosure. In some embodiments, the target cell design layout may be a design layout of a semiconductor cell to be inspected for through-hole defects. In some embodiments, the target cell design layout may be in a Graphic Database System (GDS) format, a Graphic Database System II (GDS II) format, an Open Image System Interchange Standard (OASIS) format, or the like. In some embodiments, the target cell design layout may be different from a standard cell design layout. In some embodiments, the target cell design layout may include one or more standard cells. In the present disclosure, reference will be made to a target cell as Figure 1B The unit 100 is shown to explain some embodiments of the present disclosure.

[0055] In step S350, according to some embodiments of the present disclosure, a test case is generated to detect a via defect in the target cell. In some embodiments, the test case can be generated based on the defect model generated in step S330. In this example, it should be understood that it is assumed that the target cell 100 includes two vias VIA1 and VIA2 in each of the first AND gate 110 and the second AND gate 120 of the target cell 100. As discussed, Figure 6D FIG. 6 shows a defect model table 630 representing a standard cell of an AND gate. Figure 6D As shown, the detection example 10 can be applied to detect defect types D13 to D15 of the first via VIA1 in the AND gate standard cell. Similarly, the detection examples 00 and 01 can be applied to detect defect type D23 of the second via VIA2 in the AND gate standard cell.

[0056] According to some embodiments of the present disclosure, to detect all defect types listed in defect model table 630 in a target cell, all scouting examples for each defect model can be applied as test examples. For example, to detect defect types D13, D14, D15, and D23 in first AND gate 110, each of scouting examples 10, 00, and 01 can be applied as inputs I0 and I1. Similarly, to detect defect types D13, D14, D15, and D23 in second AND gate 120, each of scouting examples 10, 00, and 01 can be applied as inputs I2 and I3. In some embodiments, all possible combinations of scouting examples for detecting all possible defect types listed as defect models in defect model table 630 can be determined as test examples for the target cell.

[0057] Figure 7 An example test example 700 of an example target unit according to some embodiments of the present disclosure is illustrated. Figure 7 As shown, the first example TP#1 may be 1010 to detect defect types D13, D14, and D15 of the first through-via VIA1 in each of the first AND gate 110 and the second AND gate 120. The second example TP#2 may be 1000 to detect defect types D13, D14, and D15 of the first through-via VIA1 in the first AND gate 110 and detect defect type D23 of the second through-via VIA2 in the second AND gate 120. The third example TP#3 may be 1001 to detect defect types D13, D14, and D15 of the first through-via VIA1 in the first AND gate 110 and detect defect type D23 of the second through-via VIA2 in the second AND gate 120. Similarly, other test examples may be generated by combining detection examples corresponding to each defect type. For example, the fourth to sixth test cases TP#4 to TP#6 may be 0010, 0000, and 0001, and the seventh to ninth test cases TP#7 to TP#9 may be 0110, 0100, and 0101. While the generation of test cases for the target cell is explained with respect to two AND gates and two vias per AND gate, it should be understood that any number of vias and any other type of standard cell may be considered when generating the test cases.

[0058] According to some embodiments of the present disclosure, test cases for the target cell to detect the defect type modeled in step S330 can be generated by a software program such as ATPG (Automatic Test Case Generator). In some embodiments, the target cell design layout and netlist of the target cell can be provided to ATPG. In some embodiments, the defect model table (e.g., Figure 6DThe defect model table 630 in the target cell is provided to the ATPG. In some embodiments, information about all defect types associated with the target cell can be extracted and provided to the ATPG. For example, when the target cell 100 includes an AND gate standard cell and a NOR gate standard cell, the defect type of the AND gate standard cell and the defect type of the NOR gate standard cell included in the reconnaissance example can be provided to the ATPG. Based on the provided information, the ATPG can generate a test example for the target cell.

[0059] According to some embodiments of the present disclosure, when the target cell has the design layout of a standard cell, the test case generation step can be skipped, such as Figure 3 In this example, the corresponding standard cell detection model table (for example, Figure 6D The detection examples of the defect types identified in the defect model table 630) can be directly used as test examples for the target unit.

[0060] Return Reference Figure 3 In step S360, according to some embodiments of the present disclosure, wafer testing may be performed based on the generated test case. In some embodiments, the target unit is tested after being manufactured on the wafer. In some embodiments, ATE (automatic test equipment) may be used to test the device of the target unit manufactured on the wafer. According to some embodiments of the present disclosure, the test case generated in step S350 may be applied to the device and a test result may be obtained. According to some embodiments of the present disclosure, the test result of the device may be recorded for each input test case.

[0061] In step S370, according to some embodiments of the present disclosure, defect candidates may be selected based on the test results obtained in step S360. In some embodiments, the test results for the input test case may be compared with the expected output of the target unit for the same input case. In some embodiments, when a mismatch exists between the test results and the expected output value, the test case may be recorded.

[0062] Figure 8 is an example test result analysis table 800 according to some embodiments of the present disclosure. For the first test case TP#1, Figure 8 The test output of the target unit is different from the expected output. Figure 1B For the target unit 100, the expected output value of the first test case TP#1 1010 is 0, while the test output value is 1. In some embodiments, based on the test case that causes the mismatch, Figure 6DPossible defect candidates are determined using the defect model table 630. For example, the first two bits 10 in the first test case TP#1 are used to detect defect types D13, D14, and D15 of the first via VIA1 in the first AND gate 110, and the last two bits 10 are used to detect defect types D13, D14, and D15 of the first via VIA1 in the second AND gate 120. In some embodiments, the first via VIA1 in the first AND gate 110 and the first via VIA1 in the second AND gate 120 may be determined as defect candidates because the test output of the first test case TP#1 does not match the expected output.

[0063] Similarly, for the second test case TP#2, Figure 8 The test output of the target unit is different from the expected output. Figure 1B For the target cell 100, the expected output value of the second test case TP#1 1000 is 1, while the test output value is 0. In this example, the first two bits 10 in the second test case TP#2 are used to detect the defect types D13, D14, and D15 of the first through hole VIA1 in the first AND gate 110, and the last two bits 00 are used to detect the defect type D23 of the second through hole VIA2 in the second AND gate 120, which can be seen from Figure 6D The defect model table 630 is derived. In this example, the first via VIA1 in the first AND gate 110 and the second via VIA2 in the second AND gate 120 can be determined as defect candidates because the test output of the second test case TP#2 does not match the expected output. Similarly, test result analysis can be performed for each failed test result to determine candidate defects for the corresponding test case.

[0064] According to some embodiments of the present disclosure, the defect candidates identified by the test result analysis may be determined as defect candidates for the target unit for further diagnosis. In some embodiments, all defect candidates listed in the rightmost column of the test result analysis table 800 may be determined as defect candidates for the target unit. In some embodiments, the defect candidates listed in the test result analysis table 800 may be sorted according to confidence scores. For example, the through-holes that appear most frequently as defect candidates in the test result analysis table 800 may have the highest confidence score for being a defect. In some embodiments, a specific number of through-holes among the defect candidates listed in the test result analysis table 800 may be selected as defect candidates for the target unit. For example, a specific number of through-holes with higher confidence scores may be selected as defect candidates for the target unit. In some embodiments, through-holes that are common defect sources for most defect types may be selected as defect candidates for the target unit for further diagnosis.

[0065] Return Reference Figure 3 According to some embodiments of the present disclosure, the root cause may be determined based on the diagnosis of the defect candidate selected in step S370. In some embodiments, the defect candidate may be diagnosed to determine whether there are defects associated with the defect candidate. In some embodiments, defect candidate diagnosis may be performed by physical failure analysis (PFA) techniques that evaluate the construction quality of the electronic device to verify that the quality meets specific requirements of the device. In some embodiments, PFA techniques may include, but are not limited to, micro- and nanostructure imaging, X-ray analysis, scanning electron microscopy (SEM) analysis, optical microscopy analysis, cross-sectional analysis, structural analysis, energy dispersive spectroscopy (EDS) analysis, focused ion beam (FIB) analysis, and the like.

[0066] According to some embodiments of the present disclosure, the root cause of a defect can be determined based on the diagnosis of the defect candidate and can be corrected. In some embodiments, the chip design layout of the target unit can be modified to address the identified root cause. For example, the chip design layout can be changed to minimize or remove the type of through-holes that cause chip failure. In some embodiments, the chip design layout can be further modified to add other types of through-holes to compensate for minimizing or removing the specific through-hole types that cause failure. In some embodiments, the cell design of the target unit can be modified to minimize or remove through-holes that are susceptible to defects. In some embodiments, the process recipe for implementing the target unit on the wafer can be adjusted so that a strong through-hole can be manufactured.

[0067] Figure 9 is an example computing device 900 according to some embodiments of the present disclosure. According to some embodiments of the present disclosure, at least part of the steps in method 300 may be performed using Figure 9 The computing device 900 shown in FIG. 1 is implemented as shown. The computing device 900 includes a processor 910, one or more memories 920, an input / output (I / O) interface 930, and a bus 940. In some embodiments, the processor 910 is communicatively coupled to the memory 920 and the I / O interface 930 via the bus 940. In various embodiments, the processor 910 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a multiprocessor, a distributed processing system, or other suitable processor. Various circuits or units that implement the processor 910 are within the intended scope of the present disclosure.

[0068] The memory 920 stores one or more program codes for facilitating circuit-level simulation of standard cells of devices manufactured on a wafer, generation of defect models for standard cells, generation of test cases for target cells, testing and diagnosis of target cells, etc. For example, the memory unit 920 may store instructions of one or more programs that are executed by the processor 910 to perform operations.

[0069] In some embodiments, memory 920 may be a non-transitory computer-readable storage medium that encodes (e.g., stores) a set of executable instructions for performing the operations described herein. In some embodiments, the computer-readable storage medium is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or device). For example, a computer-readable storage medium includes a semiconductor or solid-state memory, a magnetic tape, a removable computer floppy disk, a random access memory (RAM), a read-only memory (ROM), a hard disk, and / or an optical disk. In one or more embodiments using an optical disk, the computer-readable storage medium includes a compact disk read-only memory (CD-ROM), a compact disk reader / writer (CD-R / W), a digital video disk (DVD), a flash memory, and / or other media now known or later developed that can store code or data. The hardware modules or devices described in this disclosure include, but are not limited to, application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), dedicated or shared processors, and / or other hardware modules or devices now known or later developed.

[0070] The I / O interface 930 is configured to receive input or commands from various control devices, such as those operated by a user. Thus, the computing device 900 can be controlled using the input or commands received by the I / O interface 930. In some embodiments, the I / O interface 930 can be communicatively coupled to one or more peripheral devices 942, 944, 946, which can be a storage device configured to display the execution status of program code, a server, a display (e.g., a cathode ray tube (CRT), a liquid crystal display (LCD), a touch screen, etc.), or an input device (e.g., a keyboard, a keypad, a mouse, a trackball, a touch pad, a touch screen, cursor direction keys, or a combination thereof) for transmitting information and commands to the processor 910. In some embodiments, the peripheral device 942 is a storage device that stores the standard cell library 311 and the target cell design layout. The computing device 900 can also transmit data to or communicate with peripheral devices or other terminal devices via a network 948 (such as a local network, an internet service provider, the internet, or any combination thereof).

[0071] The above description includes exemplary operations, but these operations are not necessarily performed in the order shown. Without departing from the spirit and scope of the present disclosure, operations can be appropriately added, replaced, changed in order and / or eliminated.

[0072] According to some embodiments of the present disclosure, MEOL / BEOL defects can be modeled based on the vias of the circuit without modeling the traditional metal layer multi-line shape. According to some embodiments of the present disclosure, the via defects can be modeled as abnormal resistance defects or high resistance defects with respect to the standard cell. According to some embodiments of the present disclosure, by comparing the wafer-level test results with the defect models organized in the lookup table, the defective vias of the target cell can be identified with high accuracy. According to some embodiments of the present disclosure, by generating test examples for the target cell to detect the defect type, the defect type listed as the defect model of the standard cell can be detected from the target cell including the standard cell. According to some embodiments of the present disclosure, the identification of defects and defect locations can be facilitated because the via locations that are well defined and limited are used to model the defects. Although some embodiments for identifying defects within the cell are explained, it should be understood that the present disclosure can be used to identify defects outside the cell.

[0073] Some embodiments provide a method, including: obtaining a design layout of a standard cell; extracting characteristic information of one or more through-holes in the standard cell from the design layout; performing circuit simulation on an input example by applying a first abnormal resistance value as a parasitic resistance value of a first through-hole among the one or more through-holes to obtain a first simulation output of the standard cell, the first abnormal resistance value being different from a nominal parasitic resistance value of the first through-hole; determining whether the first simulation output of the standard cell for the input example matches a corresponding expected output; and in response to one or more simulation outputs among the first simulation outputs not matching the corresponding expected output, recording one or more defect types of the first through-hole having the first abnormal resistance value, as well as the corresponding input example and the corresponding simulation output.

[0074] In some embodiments, performing the circuit simulation includes performing the circuit simulation while applying a nominal parasitic resistance value of a second via among the one or more vias as the parasitic resistance value of the second via.

[0075] In some embodiments, the circuit simulation is a first circuit simulation, and the method further includes: performing a second circuit simulation on an input example by applying a second abnormal resistance value as a parasitic resistance value of the first through-hole to obtain a second simulation output of the standard cell; determining whether the second simulation output for the input example matches a corresponding expected output of the standard cell; and in response to one or more simulation outputs among the second simulation outputs not matching the corresponding expected output, recording one or more defect types of the first through-hole having the second abnormal resistance value and the corresponding input example and the corresponding simulation output.

[0076] In some embodiments, the circuit simulation is a first circuit simulation, and the method further includes: performing a second circuit simulation on an input example by applying a second abnormal resistance value as a parasitic resistance value of a second through-hole among the one or more through-holes to obtain a second simulation output of the standard cell; determining whether the second simulation output for the input example matches a corresponding expected output of the standard cell; and in response to one or more simulation outputs among the second simulation outputs not matching the corresponding expected output, recording one or more defect types of the second through-hole having the second abnormal resistance value and the corresponding input example and the corresponding simulation output.

[0077] In some embodiments, the characteristic information includes one or more of via position information, via layer information, or via nominal parasitic resistance information.

[0078] In some embodiments, the method further includes: obtaining a design layout of a target cell, the target cell comprising a standard cell; and generating a test case, the test case enabling detection of one or more recorded defect types from the target cell, the test case comprising a combination of corresponding input cases.

[0079] In some embodiments, the method further includes: testing devices of the target unit manufactured on the wafer based on the test example.

[0080] In some embodiments, the method further includes determining the first through-hole as a defect candidate based on the test results, the test examples, the recorded one or more defect types, and the corresponding input examples and the corresponding simulation output.

[0081] In some embodiments, a system is also disclosed, comprising a processor and one or more memories storing instructions of one or more programs executable by the processor to perform operations. The operations include: obtaining a design layout of a target cell, the target cell comprising a first standard cell and a second standard cell, the first standard cell comprising a first through-hole, and the second standard cell comprising a second through-hole; and generating a test case for the target cell, the test case enabling detection of a first defect type recorded for the first standard cell and a second defect type recorded for the second standard cell, the first defect type being associated with a first through-hole, a first input case, and a first abnormal resistance value that is different from a parasitic resistance value of the first through-hole, and the second defect type being associated with a second through-hole, a second input case, and a second abnormal resistance value that is different from a parasitic resistance value of the second through-hole, wherein the test case is generated based on the first input case and the second input case.

[0082] In some embodiments, the test case includes a combination of a first input case and a second input case.

[0083] In some embodiments, the operation further includes: obtaining a design layout of a first standard cell; extracting characteristic information of a first through-hole from the design layout of the first standard cell; performing a circuit simulation for a first input example by applying a first abnormal resistance value as a parasitic resistance value of the first through-hole to obtain a first simulation output of the first standard cell; determining whether the first simulation output for the first input example matches a first expected output of the first standard cell; and recording a first defect type in response to the first simulation output not matching the first expected output.

[0084] In some embodiments, the first defect type is recorded in a table for the first via along with the first input example, the first abnormal resistance value, and the first simulation output.

[0085] In some embodiments, the first standard cell includes an additional via and the operations further include performing a circuit simulation when applying a nominal parasitic resistance value of the additional via as the parasitic resistance value of the additional via.

[0086] In some embodiments, the characteristic information includes one or more of via position information, via layer information, or via nominal parasitic resistance information.

[0087] In some embodiments, the operations further include testing devices of the target unit fabricated on the wafer based on the test case.

[0088] In some embodiments, the operations further include determining the first through-hole or the second through-hole as a defect candidate based on the test result, the test example, the recorded first defect type and second defect type, and the first input example and the second input example.

[0089] In some embodiments, a non-transitory computer-readable storage medium is also disclosed. The non-transitory computer-readable storage medium stores a set of instructions that can be executed by one or more processors of a device to enable the device to perform a method. The method includes: obtaining a design layout of a target cell, the target cell including a standard cell, the standard cell including one or more through-holes; and generating a test case for the target cell, the test case enabling detection of one or more defect types recorded for the standard cell, the one or more defect types including a defect type associated with a selected through-hole from among the one or more through-holes and an input case and an abnormal resistance value different from the parasitic resistance value of the selected through-hole, wherein the test case is generated based on the input case.

[0090] In some embodiments, the defect type is further associated with a simulated output of the standard cell, the simulated output for the input example being obtained by performing circuit simulation applying the input example and the abnormal resistance value, and the simulated output being different from an expected output of the standard cell.

[0091] In some embodiments, the method further includes testing devices of the target unit manufactured on the wafer based on the test case.

[0092] In some embodiments, the method further includes determining the selected via as a defect candidate based on the test results, the test examples, and the one or more defect types, and the corresponding input examples and the corresponding simulation output.

[0093] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications in the present invention without departing from the spirit and scope of the present invention.

Claims

1. A method for modeling a through-hole defect, comprising: Get the design layout of standard cells; Extracting characteristic information of one or more through-holes in the standard cell from the design layout, the characteristic information including one or more of through-hole position information, through-hole layer information, or through-hole nominal parasitic resistance information; performing a circuit simulation on an input example to obtain a first simulation output of the standard cell by applying a first abnormal resistance value as a parasitic resistance value of a first via among the one or more vias, the first abnormal resistance value being different from a nominal parasitic resistance value of the first via; determining whether the first simulated output of the standard cell for the input example matches a corresponding expected output; and In response to one or more of the first simulation outputs not matching the corresponding expected output, one or more defect types of the first through-hole having the first abnormal resistance value and corresponding input examples and corresponding simulation outputs are recorded.

2. The method according to claim 1, wherein Performing the circuit simulation includes: The circuit simulation is performed while applying a nominal parasitic resistance value of a second via among the one or more vias as a parasitic resistance value of the second via.

3. The method according to claim 1, wherein The circuit simulation is a first circuit simulation, and the method further includes: performing a second circuit simulation on the input example by applying a second abnormal resistance value as a parasitic resistance value of the first via to obtain a second simulation output of the standard cell; determining whether the second simulated output for the input example matches the corresponding expected output of the standard cell; and In response to one or more of the second simulation outputs not matching the corresponding expected output, one or more defect types of the first through-hole having the second abnormal resistance value and corresponding input examples and corresponding simulation outputs are recorded.

4. The method according to claim 1, wherein The circuit simulation is a first circuit simulation, and the method further includes: performing a second circuit simulation on the input example by applying a second abnormal resistance value as a parasitic resistance value of a second via among the one or more vias to obtain a second simulation output of the standard cell; determining whether the second simulated output for the input example matches the corresponding expected output of the standard cell; and In response to one or more of the second simulation outputs not matching the corresponding expected output, one or more defect types of the second through-hole having the second abnormal resistance value and corresponding input examples and corresponding simulation outputs are recorded.

5. The method according to claim 1, wherein The one or more defect types include an abnormal resistance defect.

6. The method according to claim 1, further comprising: Acquire a design layout of a target cell, wherein the target cell includes the standard cell; and A test case is generated that enables detection of the recorded one or more defect types from the target unit, the test case comprising a combination of the corresponding input cases.

7. The method according to claim 6, further comprising: The devices of the target unit manufactured on a wafer are tested based on the test example.

8. The method according to claim 7, further comprising: The first through-hole is determined to be a defect candidate based on the test results, the test examples and the recorded one or more defect types, and the corresponding input examples and the corresponding simulation output.

9. A system for modeling through-hole defects, comprising: processor; and One or more memories storing instructions of one or more programs executable by the processor to perform operations including: Acquire a design layout of a target cell, the target cell comprising a first standard cell and a second standard cell, the first standard cell comprising a first through-hole, the second standard cell comprising a second through-hole; and generating a test case for the target cell, the test case enabling detection of a first defect type recorded for the first standard cell and a second defect type recorded for the second standard cell, the first defect type being associated with the first via, a first input case, and a first abnormal resistance value that is different from a parasitic resistance value of the first via, and the second defect type being associated with the second via, a second input case, and a second abnormal resistance value that is different from a parasitic resistance value of the second via; Extracting characteristic information of the first through-hole from the design layout of the first standard cell, the characteristic information including one or more of through-hole position information, through-hole layer information, or through-hole nominal parasitic resistance information; performing a circuit simulation for the first input example by applying the first abnormal resistance value as the parasitic resistance value of the first via to obtain a first simulation output of the first standard cell; determining whether the first simulated output for the first input example matches a first expected output of the first standard cell; In response to the first simulated output not matching the first expected output, recording the first defect type, The test example is generated based on the first input example and the second input example.

10. The system according to claim 9, wherein: The test pattern includes a combination of the first input pattern and the second input pattern.

11. The system according to claim 9, wherein: The test case is generated by an automatic test case generator.

12. The system according to claim 9, wherein: The first defect type is recorded in a table for the first through-hole along with the first input example, the first abnormal resistance value, and the first simulation output.

13. The system according to claim 9, wherein: The first standard cell includes an additional via and the operations further include: The circuit simulation is performed while applying a nominal parasitic resistance value of the additional via as the parasitic resistance value of the additional via.

14. The system according to claim 9, wherein: The first defect type includes an abnormal resistance defect.

15. The system of claim 9, the operations further comprising: The devices of the target unit manufactured on a wafer are tested based on the test example.

16. The system of claim 15, wherein the operations further comprise: The first through-hole or the second through-hole is determined to be a defect candidate based on a test result, the test example, the recorded first defect type and the second defect type, and the first input example and the second input example.

17. A non-transitory computer-readable storage medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method, the method comprising: Acquire a design layout of a target cell, wherein the target cell includes a standard cell, and the standard cell includes one or more through holes; generating a test case for the target cell, the test case enabling detection of one or more defect types recorded for the standard cell, the one or more defect types including a defect type associated with a selected via among the one or more vias and an input case and an abnormal resistance value different from a parasitic resistance value of the selected via, the defect type further being associated with a simulated output of the standard cell, the simulated output for the input case being obtained by performing a circuit simulation applying the input case and the abnormal resistance value, and the simulated output being different from an expected output of the standard cell, wherein the test case is generated based on the input case; determining the selected via as a defect candidate based on test results, the test examples and the one or more defect types and the corresponding input examples and the corresponding simulation output; and The devices of the target unit manufactured on a wafer are tested based on the test example.

18. The non-transitory computer-readable storage medium of claim 17, wherein: The one or more defect types include an abnormal resistance defect.

19. The non-transitory computer-readable storage medium of claim 17, wherein: The test case is generated by an automatic test case generator.

20. The non-transitory computer-readable storage medium of claim 19, wherein: The standard cell includes an AND gate, and the one or more through holes are through holes of the AND gate.

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