Array substrate, protection circuit and display panel

Abstract

The embodiment of the present application provides an array substrate, a protection circuit and a display panel. The array substrate comprises a substrate, a signal trace, a metal layer and a plurality of thin film transistors. The thin film transistor comprises an active layer, a second metal layer and a first metal layer. The active layers of different thin film transistors are overlapped at one end and are connected to the same place, forming a common part. When static current appears in the device, the static current is released through the common part and the signal trace, so that the anti-static performance of the display panel is effectively improved, and a narrow frame panel is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panels, and in particular to an array substrate, a protection circuit and a display panel. BACKGROUND

[0002] With the development of display panel technology, people have put forward higher requirements on the display effect and comprehensive performance of display panels and display devices.

[0003] For large-size, high-resolution display panels, the display effect and narrow-frame design are becoming increasingly important. In order to further improve the comprehensive performance of the display panel, the array substrate in the display panel needs to be optimized in design. When optimizing the design, the shape structure and spatial layout of different devices provided on the array substrate need to be optimized. In addition, the anti-static performance of the optimized array substrate also needs to be considered. Once static problems occur during use, it will affect the normal use of the display panel, and even seriously reduce the comprehensive performance of the panel. In the prior art, in order to prevent the problem of static accumulation inside the display panel during normal operation, multiple anti-static structures are often provided inside the array substrate. However, with the further improvement of the requirement for large size of the display panel and the demand for narrow-frame display panels, the design of the anti-static structure in the existing display panel has defects, which cannot meet the demand of narrow frame, hindering the further development of narrow-frame display panels.

[0004] In summary, the anti-static structure provided on the array substrate of the existing display panel is not reasonable in design, which cannot meet the demand of narrow-frame high-performance display panels and is not conducive to the improvement of the comprehensive performance of the display panel. SUMMARY

[0005] Embodiments of the present application provide an array substrate, a protection circuit and a display panel. The internal anti-static structure of the display panel is effectively improved, and the comprehensive performance of the narrow-frame display panel is improved.

[0006] To solve the above technical problems, the present application provides an array substrate, comprising a display area and a non-display area located on one side of the display area, the array substrate comprising:

[0007] a substrate, the substrate comprising a first area and a second area provided on one side of the first area;

[0008] a plurality of signal traces provided on the substrate corresponding to the non-display area; and

[0009] a plurality of metal layers provided on the plurality of signal traces, the metal layers corresponding to a plurality of thin film transistors;

[0010] The thin film transistor comprises an active layer, a first metal layer insulatively arranged on the active layer, and a second metal layer insulatively arranged on the first metal layer, and the active layer is electrically connected with the second metal layer.

[0011] The active layer comprises non-overlapping parts and a common part, the non-overlapping parts are arranged in the first region, the common part is arranged in the second region, each non-overlapping part extends towards the second region and is connected with the common part at the same position.

[0012] According to an embodiment of the present application, the array substrate further comprises a display region arranged on one side of the first region and the second region, the display region comprises a plurality of array-arranged sub-pixels, each signal wire is electrically connected with the sub-pixels, and the signal wires comprise a first signal wire, a second signal wire and a third signal wire, the second metal layer of the thin film transistor has three branches, and each branch is electrically connected with the signal wire.

[0013] The branches comprise a first branch, a second branch and a third branch, the first branch corresponds to the first thin film transistor, the second branch corresponds to the second thin film transistor, and the third branch corresponds to the third thin film transistor.

[0014] The first signal wire is electrically connected with the second metal layer of the first thin film transistor, the second signal wire is electrically connected with the second metal layer of the second thin film transistor, and the third signal wire is electrically connected with the second metal layer of the third thin film transistor.

[0015] According to an embodiment of the present application, the common part and the non-overlapping part are arranged in the same layer.

[0016] According to an embodiment of the present application, in the first region, the active layer of the first thin film transistor, the active layer of the second thin film transistor and the active layer of the third thin film transistor are arranged in parallel.

[0017] According to an embodiment of the present application, the widths of the active layers corresponding to different thin film transistors are the same.

[0018] According to an embodiment of the present application, the thin film transistor further comprises a via hole, and the active layer is electrically connected with the second metal layer through the via hole.

[0019] According to an embodiment of the present application, the first metal layer of each thin film transistor is arranged directly above the active layer, and the width of the first metal layer is greater than the width of the active layer.

[0020] According to an embodiment of the present application, the active layer is an active layer of the thin film transistor, the second metal layer is a source / drain electrode, and the first metal layer is a gate electrode.

[0021] According to an embodiment of the present application, the gate metal layer of the first thin film transistor and the source / drain electrode form a first capacitor, the gate metal layer of the second thin film transistor and the source / drain electrode form a second capacitor, and the gate metal layer of the third thin film transistor and the source / drain electrode form a third capacitor.

[0022] The first capacitor, the second capacitor, and the third capacitor are connected in parallel.

[0023] According to an embodiment of the present application, the sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel having different colors.

[0024] The first sub-pixel, the second sub-pixel, and the third sub-pixel are electrically connected to corresponding signal lines, and each thin film transistor is configured to provide a control signal to the first sub-pixel, the second sub-pixel, and the third sub-pixel through the corresponding signal line.

[0025] According to an embodiment of the present application, the array substrate further includes a common electrode layer disposed in the second region.

[0026] According to an embodiment of the present application, in the second region, the thin film transistors share the same second metal layer.

[0027] According to an embodiment of the present application, the non-display region has a width of 20-300 um and a length of 3-100 um.

[0028] According to a second aspect of the embodiments of the present application, a protection circuit is provided, which includes:

[0029] a common electrode;

[0030] a thin film transistor, a source electrode of the thin film transistor being electrically connected to the common electrode;

[0031] a capacitor and a signal line, the signal line being electrically connected to a drain metal layer of the thin film transistor, and the capacitor including a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;

[0032] One end of the first capacitor is electrically connected to a gate metal layer of the thin film transistor, and the other end of the first capacitor is electrically connected to the signal line;

[0033] One end of the second capacitor is electrically connected to the gate metal layer of the thin film transistor, and the other end of the second capacitor is electrically connected to the signal line.

[0034] One end of the third capacitor is electrically connected with the gate metal layer of the thin film transistor, and the other end of the third capacitor is electrically connected with the signal wire;

[0035] One end of the fourth capacitor is electrically connected with the gate metal layer of the thin film transistor, and the other end of the fourth capacitor is electrically connected with the source metal layer of the thin film transistor and the common electrode.

[0036] According to an embodiment of the present application, the signal wire includes a first signal wire, a second signal wire and a third signal wire, the first signal wire is connected with the other end of the first capacitor, the second signal wire is connected with the other end of the second capacitor, and the third signal wire is connected with the other end of the third capacitor.

[0037] According to the third aspect of the embodiment of the present application, the display panel includes the array substrate and the protection circuit provided in the embodiment of the present application, so that the comprehensive performance of the display panel is effectively improved, and the narrow frame setting of the display panel is realized.

[0038] The embodiment of the present application has the following advantages: compared with the prior art, the embodiment of the present application provides an array substrate, a protection circuit and a display panel. The array substrate includes a substrate, a signal wire and a plurality of metal layers. A plurality of thin film transistors are arranged. The thin film transistor includes an active layer, a second metal layer and a first metal layer. In the embodiment of the present application, the active layers of different thin film transistors are overlapped at one end and connected at the same place to form a common part. A floating gate and a plurality of capacitors are formed. The internal static electricity is discharged through the plurality of signal wires. The arrangement space between the devices in the region is effectively reduced, the narrow frame setting of the display panel is further realized, and the comprehensive performance of the display panel is effectively improved. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0040] Figure 1 It is a wiring structure schematic diagram of the array substrate provided in the prior art;

[0041] Figure 2 It is a plane wiring structure schematic diagram of the display panel provided in the embodiment of the present application;

[0042] Figure 3A schematic diagram of a wiring structure of an array substrate provided in an embodiment of the present application is shown in the following figure.

[0043] Figure 4 A schematic diagram of an electrostatic protection circuit provided in an embodiment of the present application is shown in the following figure.

[0044] Figure 5 A schematic diagram of a film layer structure of an array substrate provided in an embodiment of the present application is shown in the following figure.

[0045] Figure 6 A schematic diagram of a preparation process provided in an embodiment of the present application is shown in the following figure.

[0046] Figures 7-11 A schematic diagram of a wiring corresponding to a preparation process provided in an embodiment of the present application is shown in the following figure. DETAILED DESCRIPTION

[0047] The following disclosure provides different embodiments or examples to realize different structures of the present application, with reference to the accompanying drawings in the embodiments of the present application. In order to simplify the present application, the components and settings of specific examples are described below. In addition, the present application provides various specific examples of processes and materials, which can be realized by those skilled in the art. All other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0048] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0049] With the continuous development of display panel preparation technology, people have put forward higher requirements on the performance and display effect of display panels and display devices.

[0050] As shown in the following figure, Figure 1 Figure 1 ​This is a schematic diagram of the wiring structure of an array substrate provided in the prior art. For high-resolution electronic products, electronic devices generate a certain amount of static electricity during normal operation. When this static electricity cannot be released or discharged, it can easily affect the normal operation of the devices. In order to reduce the influence of internal static electricity in thin-film transistor devices during operation, in the prior art, multiple electrostatic shielding units 104 are usually set on the array substrate, such as three electrostatic shielding units. Each electrostatic shielding unit 104 is electrically connected to the signal line 101. At the same time, the active layer 103 in the electrostatic shielding unit 104 extends downward and is electrically connected to the common electrode 102. When a static electricity problem occurs inside the array substrate, it is protected by the electrostatic shielding unit 104. However, when setting the above-mentioned electrostatic shielding unit 104, a large bezel area needs to be reserved on the display panel to arrange it. This results in a large non-display area on the display panel, which is not conducive to the improvement and development of the overall performance of narrow bezel display panels.

[0051] This application provides an array substrate and an electrostatic protection circuit to effectively improve the anti-static structure inside existing display panels and enhance the overall performance of narrow bezel display panels.

[0052] like Figure 2 As shown, Figure 2 This is a schematic diagram of the planar wiring structure of a display panel provided in an embodiment of this application. The display panel 200 includes a display area 201 and a non-display area 204. The non-display area 204 is at least disposed on one side of the display area 201. In this embodiment, the non-display area 204 may be disposed around the display area 201.

[0053] Furthermore, within the display area 201, multiple pixel units are arranged in an array. Figure 2 The location of each pixel unit is not specifically shown. When configuring, you can follow the pixel unit settings found on a standard display panel.

[0054] In this embodiment, an electrostatic discharge (ESD) protection structure 202 and a driving circuit 205 are also provided in the non-display area. Specifically, the ESD protection structure 202 is electrically connected to the driving circuit 205, and each signal line in the driving circuit 205 is electrically connected to each pixel unit in the display area. The driving circuit 205 provides control signals to each sub-pixel within the pixel unit.

[0055] In this embodiment of the application, the electrostatic protection structure 202 is provided with a plurality of electrostatic shielding units 104. When the display panel is working normally, the electrostatic shielding unit 104 can effectively release the static electricity in the display panel and ensure the normal operation of the display panel.

[0056] like Figure 3 As shown, Figure 3 This is a schematic diagram of the wiring structure of the array substrate provided in an embodiment of this application. The wiring structure of the array substrate corresponds to the area of ​​the electrostatic shielding unit 104. In this embodiment, one electrostatic shielding unit 104 is used as an example. The electrostatic shielding unit 104 has multiple signal traces disposed on the substrate of the array substrate, and these signal traces are electrically connected to sub-pixels within the display area of ​​the display panel. Specifically, the signal traces include a first signal trace 321, a second signal trace 322, and a third signal trace 323.

[0057] Specifically, the first signal trace 321 is electrically connected to the first sub-pixel within the display area, such as when the first signal trace 321 is connected to the red sub-pixel; the second signal trace 322 is electrically connected to the second sub-pixel within the display area, such as when the second signal trace 322 is connected to the blue sub-pixel; and the third signal trace 323 is electrically connected to the third sub-pixel within the display area, such as when the third signal trace 323 is connected to the green sub-pixel. Control signals are then provided to each sub-pixel through these corresponding signal traces.

[0058] Furthermore, in this embodiment, multiple metal layers are also disposed on the array substrate. Each metal layer corresponds to a thin-film transistor layer on the array substrate, and multiple thin-film transistors are formed from these metal layers. Specifically, the electrostatic shielding unit 104 includes multiple thin-film transistors. Each thin-film transistor is electrically connected to a signal trace. Each thin-film transistor includes an active layer, a first metal layer, and a second metal layer. Specifically, the second metal layer is disposed above the active layer, and the first metal layer is disposed above the active layer.

[0059] Each metal layer is disposed within a first region 37 and a second region 39, with the first region 37 potentially located on one side of the second region 39. Specifically, in this embodiment, the first region 37 and the second region 39 correspond to the non-display area 204 of the display panel. The active layer includes a common portion and a non-overlapping portion, with the non-overlapping portion disposed in the first region 37 and the common portion disposed in the second region 39. Each thin-film transistor within the first region 37 corresponds to a second metal layer. Each non-overlapping portion extends towards the second region 39, is cross-linked at the same location, and is electrically connected to the common portion. This forms a structure as follows: Figure 3 The “mountain”-shaped branching connection structure in the text.

[0060] Specifically, in the following embodiments, the second metal layer is described in detail using the source 302 and drain 303 as examples, and the first metal layer is described in detail using the gate metal layer 301 as an example.

[0061] Meanwhile, in this embodiment, when the second metal layer is provided, the source 302 corresponding to the second metal layer has three branches, each branch being electrically connected to a corresponding signal line. In the following embodiments, the three branches are described as the first branch, the second branch, and the third branch. The three branches and the drain 303 on the other side can be similarly equivalent to three thin-film transistors. Specifically, the first branch corresponds to the first thin-film transistor 311, the second branch corresponds to the second thin-film transistor 312, and the third branch corresponds to the third thin-film transistor 313. Among them, the first thin-film transistor 311 is electrically connected to the first signal line 321, the second thin-film transistor 312 is electrically connected to the second signal line 322, and the third thin-film transistor 313 is electrically connected to the third signal line 323. When the above-mentioned thin-film transistors are electrically connected to the corresponding signal lines, they are connected through the connection portion 400 provided on one side of each signal line.

[0062] Meanwhile, in this embodiment, the length of the connection portion 400 can be set as needed. For example, the extension direction of the connection portion 400 can be perpendicular to the signal trace. Furthermore, the source 302 of the thin-film transistor is disposed on the film layer of the connection portion 400.

[0063] Furthermore, when the connection portion 400 is connected to the source electrode 302, the connection is achieved through a corresponding via structure. Specifically, vias, such as a first via 350, a second via 351, and a third via 352, are provided on the film layer structure corresponding to each thin-film transistor. This enables the signal trace to be electrically connected to the source electrode 302 of the thin-film transistor.

[0064] Furthermore, in this embodiment, the gate metal layer 301 of the thin-film transistor is disposed on the active layer 30. Preferably, the gate metal layer 301 can be disposed directly above the active layer 30. The source 302 of each thin-film transistor is disposed on one side of the array substrate, such as within the first region 37, while the drain 303 of the thin-film transistor is disposed on the other side, such as within the second region 39. The first thin-film transistor 311, the second thin-film transistor 312, and the third thin-film transistor 313 share a portion of the drain 303, a portion of the gate metal layer 301, and a portion of the active layer 30. See also... Figure 3 The wiring structure diagram shows that the source 302 of each thin-film transistor is also electrically connected to the active layer 30 through a corresponding via 353.

[0065] Furthermore, in this embodiment, when the active layer 30 and gate metal layer 301 corresponding to the thin-film transistor are provided, the active layer 30 includes a common portion 34 and a non-overlapping portion 35. The non-overlapping portion 35 is located near the source 302 of the thin-film transistor, i.e., it is disposed in the first region 37, and the common portion 34 is located near the drain 303 of the thin-film transistor, i.e., it is disposed in the second region 39. In this embodiment, when the gate metal layer 301 of the thin-film transistor is provided, since the gate metal layer 301 is disposed above the active layer, the gate metal layer 301 also has a common portion and a non-overlapping portion. The following embodiments will use the structure of the active layer 30 as an example for explanation.

[0066] Meanwhile, in this embodiment, within the first region 37 corresponding to the non-overlapping portion 35, the active layers of each thin-film transistor can be arranged parallel to each other. For example, the active layers 31 of the first thin-film transistor, 32 of the second thin-film transistor, and 33 of the third thin-film transistor can be arranged parallel to each other. Furthermore, during arrangement, the active layers corresponding to the first thin-film transistor 311, the second thin-film transistor 312, and the third thin-film transistor 313 can be arranged in the same layer. Preferably, the width of the active layer of each thin-film transistor can be set to the same width, thereby ensuring that they have the same effect on current.

[0067] Preferably, within the first region 37, the length of each active layer can be set to be the same, thereby ensuring the consistency of the performance of the corresponding thin-film transistors. Simultaneously, when setting the gate metal layer 301 of the thin-film transistor, it can be set correspondingly to the active layer 30. For example, if it is set directly above the corresponding active layer, preferably, the width of the gate metal layer 301 can be greater than the width of the active layer 30.

[0068] Meanwhile, in this embodiment, the gate metal layer 301 also includes a common portion and a non-overlapping portion, and the common portion and the non-overlapping portion together constitute the gate metal layer of each thin film transistor. In this way, the gate metal layer is equivalent to a floating gate, thereby ensuring the normal operation of the thin film transistor. In specific settings, the active layer can be configured accordingly, which will not be elaborated here.

[0069] In this embodiment, the active layer 30 and the gate metal layer 301 both extend to a side away from the first via 350, the second via 351 and the third via 352, and overlap in the common region 36, forming a common portion 34 in the common region 36.

[0070] In this embodiment, the non-overlapping portion 35 corresponding to the active layer 30 of each thin-film transistor is electrically connected to the common portion 34. When static electricity accumulates inside the device and generates a current effect, the current can be released through the signal traces electrically connected to each thin-film transistor, thereby ensuring that the device has good electrostatic protection. In this embodiment, during the electrostatic discharge process, the electrostatic current is released simultaneously through multiple signal traces, thereby effectively improving the discharge effect and ensuring the performance of the device.

[0071] Furthermore, in this embodiment, the gate metal layer 301 is disposed on the film layer of the active layer 30, and the width of the gate metal layer 301 is greater than the width of the active layer 30.

[0072] Furthermore, a common electrode 102 is also provided on the array substrate in this embodiment. When providing the common electrode 102, it can be correspondingly disposed within the second region 39.

[0073] like Figure 4 As shown, Figure 4 This is a schematic diagram of an electrostatic discharge (ESD) protection circuit provided in an embodiment of this application. The ESD protection circuit corresponds to... Figure 3 The wiring in the process. Combined with... Figure 3 In the wiring diagram of this application embodiment, in the corresponding film layer structure, a first capacitor C1 is formed between the gate metal layer of the first thin-film transistor 311 and its corresponding source 302; a second capacitor C2 is formed between the gate metal layer of the second thin-film transistor 312 and its corresponding source 302; and a third capacitor C3 is formed between the gate metal layer of the third thin-film transistor 313 and its corresponding source 302. In this application embodiment, the first capacitor C1, the second capacitor C2, and the third capacitor C3 are connected in parallel. Simultaneously, in this application embodiment, within the first region, the gate metal layer and the corresponding drain 303 form a fourth capacitor C4.

[0074] In this embodiment, the electrostatic discharge protection circuit includes a common electrode 102, a thin-film transistor T connected to the common electrode, and multiple capacitors and signal traces.

[0075] Specifically, the capacitors include a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4, and the signal traces include a first signal trace 321, a second signal trace 322, and a third signal trace 323. Each of the above capacitors and signal traces is connected to... Figure 3 The capacitors and signal traces in the circuit correspond to each other.

[0076] The common electrode 102 is electrically connected to the source metal layer of the thin-film transistor T, one end of the first capacitor C1 is electrically connected to the gate metal layer of the thin-film transistor T, and the other end of the first capacitor C1 is electrically connected to the drain metal layer of the thin-film transistor T and the first signal line 321.

[0077] One end of the second capacitor C2 is electrically connected to the gate metal layer of the thin-film transistor T, and the other end of the second capacitor C2 is electrically connected to the drain metal layer of the thin-film transistor T and the second signal trace 322.

[0078] One end of the third capacitor C3 is electrically connected to the gate metal layer of the thin-film transistor T, and the other end of the third capacitor C3 is electrically connected to the drain metal layer of the thin-film transistor T and the third signal trace 323.

[0079] Simultaneously, one end of the first capacitor C1, one end of the second capacitor C2, one end of the third capacitor C3, and one end of the fourth capacitor C4 are connected together. This forms a parallel structure among the capacitors, and the gate metal layer of the thin-film transistor forms a floating gate. When electrostatic current is generated inside the device, the current can be released through multiple signal traces, effectively protecting the device. Furthermore, in this embodiment, the electrostatic protection circuit is integrated, effectively saving its layout area on the array substrate and realizing narrow-bezel and ultra-narrow-bezel display panels.

[0080] In this embodiment of the application, when setting the electrostatic protection unit corresponding to the non-display area, the width of the first area 37 can be set to 20um-300um and the length can be set to 3um-100um.

[0081] like Figure 5 As shown, Figure 5 This is a schematic diagram of the film layer structure of the array substrate provided in the embodiments of this application. (Combined with...) Figure 3 A schematic diagram of planar wiring is shown. In this embodiment, the array substrate includes a substrate 500, a buffer layer 501 disposed on the substrate 500, and a light-shielding layer 502 disposed on the substrate 500. In this embodiment, the light-shielding layer 502 is a metal light-shielding layer, and the light-shielding layer 502 corresponds to the first signal trace, the second signal trace, and the third signal trace. The light-shielding layer 502 is used to transmit signals and protect the display panel.

[0082] The array substrate also includes an active layer 30, a gate metal layer 301, a source 302, a drain 303, and a passivation layer 504 disposed on the buffer layer. Specifically, the source 302 and drain 303 are electrically connected to the active layer 30 of the thin-film transistor through corresponding vias. Simultaneously, the source 302 is also electrically connected to the light-shielding layer 502 through a via structure. When excessive static electricity occurs in the internal components of the display panel, it can be released through the light-shielding layer 502, thereby protecting the normal operation of the internal components.

[0083] Furthermore, embodiments of this application also provide a method for fabricating an array substrate. Specifically, as shown... Figure 6 As shown, Figure 6 This is a schematic diagram of the preparation process provided for embodiments of this application. It includes the following preparation process:

[0084] S100: Provide a substrate and form a light-shielding layer on the substrate;

[0085] S101: A buffer layer is prepared on the light-shielding layer, and an active layer of a thin-film transistor is prepared on the buffer layer, wherein the active layer of each thin-film transistor extends and overlaps in the first region.

[0086] S102: An insulating layer is prepared on the active layer, and a gate metal layer is prepared on the insulating layer;

[0087] S103: A passivation layer is prepared on the gate metal layer, and holes are made at the corresponding positions of the light-shielding layer and the active layer;

[0088] S104: Prepare a source / drain electrode on the passivation layer, and electrically connect the source / drain electrode to the active layer and the light-shielding layer through the via.

[0089] Specifically, in combination Figure 3 ,as well as Figures 7-11 As shown, Figures 7-11 This is a wiring diagram corresponding to the fabrication process provided in the embodiments of this application. In the embodiments of this application, a light-shielding layer is provided in the non-display area of ​​the array substrate. In the embodiments of this application, the light-shielding layer is multiple signal traces, such as a first signal trace 321, a second signal trace 322, and a third signal trace 323. A connection portion 400 is provided on one side of each signal trace.

[0090] After the light-shielding layer is fabricated, a buffer layer is fabricated on the light-shielding layer, and simultaneously, the active layer 30 of the thin-film transistor is fabricated on the buffer layer. The active layer 30 of the thin-film transistor includes a common portion 34 and a non-overlapping portion 35. Furthermore, the non-overlapping portion 35 includes multiple different active layers 31, 32, and 33. Specifically, active layer 31 corresponds to a first thin-film transistor, active layer 32 corresponds to a second thin-film transistor, and active layer 33 corresponds to a third thin-film transistor.

[0091] In this embodiment, the active layer 31, the active layer 32, and the active layer 33 continue to extend and overlap at the same location, forming the common portion 34 in the overlapping area.

[0092] Furthermore, after the active layer 30 is fabricated, an insulating layer is fabricated on the active layer, and a gate metal layer 301 is fabricated on the insulating layer. A passivation layer is fabricated on the gate metal layer 301. Simultaneously, a first via 350, a second via 351, and a third via 352 are respectively formed at positions corresponding to the first thin-film transistor 311, the second thin-film transistor 312, and the third thin-film transistor 313.

[0093] Furthermore, in this embodiment, a source electrode 302, a drain electrode 303, and a common electrode 102 are fabricated on the passivation layer. The source / drain electrode is electrically connected to the light-shielding layer and the active layer through corresponding vias. When a large amount of static electricity occurs inside the display panel during operation, the multiple light-shielding layers 502 release the electrostatic current, thereby effectively protecting the display panel.

[0094] Furthermore, in this embodiment, a display panel is also provided, in which the aforementioned array substrate is disposed. The active layers of multiple thin-film transistors on the array substrate overlap on one side in the same area, forming a common portion. The display panel can be any product or component with display and touch functions, such as a mobile phone, computer, electronic paper, monitor, laptop computer, or digital photo frame; its specific type is not specifically limited.

[0095] In summary, the array substrate, protection circuit, and display panel provided by the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solution and core ideas of the present invention. Although the present invention has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is based on the scope defined by the claims.

Claims

1. An array substrate, characterized in that, include: A substrate, the substrate including a first region and a second region disposed on one side of the first region; Multiple signal traces are disposed on the substrate; and, A multilayer metal layer is disposed on the multiple signal traces and electrically connected to the signal traces, and the metal layer corresponds to multiple thin-film transistors; The thin-film transistor includes an active layer, a first metal layer insulated on the active layer, and a second metal layer insulated on the first metal layer, wherein the active layer and the second metal layer are electrically connected. The active layer includes a non-overlapping portion and a common portion. The non-overlapping portion is disposed in the first region, and the common portion is disposed in the second region. Each non-overlapping portion extends toward the second region and is cross-linked at the same location, and is electrically connected to the common portion. The array substrate further includes a display area disposed on one side of the first area and the second area. The display area includes a plurality of sub-pixels arranged in an array. Each signal trace is electrically connected to the sub-pixel. The signal trace includes a first signal trace, a second signal trace, and a third signal trace. The drain of the second metal layer of the thin film transistor is disposed in the second area. The source of the second metal layer of the thin film transistor is disposed in the first area and has three branches. Each branch is electrically connected to the signal trace. The branch includes a first branch, a second branch, and a third branch, wherein the first branch corresponds to a first thin-film transistor, the second branch corresponds to a second thin-film transistor, and the third branch corresponds to a third thin-film transistor; The first signal trace is electrically connected to the second metal layer of the first thin-film transistor, the second signal trace is electrically connected to the second metal layer of the second thin-film transistor, and the third signal trace is electrically connected to the second metal layer of the third thin-film transistor.

2. The array substrate according to claim 1, characterized in that, The shared portion and the non-overlapping portion are arranged on the same layer.

3. The array substrate according to claim 2, characterized in that, Within the first region, the active layers of the first thin-film transistor, the second thin-film transistor, and the third thin-film transistor are arranged parallel to each other.

4. The array substrate according to claim 2, characterized in that, The active layer has the same width for different thin-film transistors.

5. The array substrate according to claim 1, characterized in that, The thin-film transistor further includes a via, through which the active layer is electrically connected to the second metal layer.

6. The array substrate according to claim 5, characterized in that, The first metal layer of each thin-film transistor is disposed directly above the active layer, and the width of the first metal layer is greater than the width of the active layer.

7. The array substrate according to claim 1, characterized in that, Within the second region, the thin-film transistors share the same second metal layer.

8. The array substrate according to any one of claims 1-7, characterized in that, The second metal layer is the source / drain, and the first metal layer is the gate.

9. The array substrate according to claim 8, characterized in that, The gate metal layer of the first thin-film transistor forms a first capacitor with the source / drain, the gate metal layer of the second thin-film transistor forms a second capacitor with the source / drain, and the gate metal layer of the third thin-film transistor forms a third capacitor with the source / drain. The first capacitor, the second capacitor, and the third capacitor are connected in parallel.

10. The array substrate according to claim 1, characterized in that, The sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, each with a different color. The first sub-pixel, the second sub-pixel, and the third sub-pixel are electrically connected to their corresponding signal traces, and each thin-film transistor provides control signals to the first sub-pixel, the second sub-pixel, and the third sub-pixel respectively through its corresponding signal trace.

11. The array substrate according to claim 1, characterized in that, The array substrate further includes a common electrode layer disposed in the second region.

12. The array substrate according to claim 1, characterized in that, The width of the first region is set to 20um-300um, and the length is set to 3um-100um.

13. A protection circuit for electrostatic protection of an array substrate as described in any one of claims 1 to 12, characterized in that, The protection circuit includes: Common electrode; A thin-film transistor, wherein the source of the thin-film transistor is electrically connected to the common electrode; The capacitor and signal traces are electrically connected to the drain metal layer of the thin-film transistor. The capacitors include a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. Wherein, one end of the first capacitor is electrically connected to the gate metal layer of the thin-film transistor, and the other end of the first capacitor is electrically connected to the signal trace; One end of the second capacitor is electrically connected to the gate metal layer of the thin-film transistor, and the other end of the second capacitor is electrically connected to the signal trace; One end of the third capacitor is electrically connected to the gate metal layer of the thin-film transistor, and the other end of the third capacitor is electrically connected to the signal trace. One end of the fourth capacitor is electrically connected to the gate metal layer of the thin-film transistor, and the other end of the fourth capacitor is electrically connected to the source metal layer of the thin-film transistor and the common electrode.

14. The protection circuit according to claim 13, characterized in that, The signal traces include a first signal trace, a second signal trace, and a third signal trace. The first signal trace is connected to the other end of the first capacitor, the second signal trace is connected to the other end of the second capacitor, and the third signal trace is connected to the other end of the third capacitor.

15. A display panel, characterized in that, It includes the array substrate as described in any one of claims 1-12, or the protection circuit as described in any one of claims 13 and 14.

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