tc module inside a chip and integrated chip applied to ate testing

Abstract

The present disclosure provides a TC module applied to the inside of a chip for ATE testing and an integrated chip, wherein the TC module applied to the inside of the chip for ATE testing comprises: a logic control circuit, configured to convert a specified test instruction into a test program through a local AHB master protocol; a JTAG interface, connected to an input end of the logic control circuit, configured to receive the specified test instruction transmitted based on a JTAG protocol and transmit the specified test instruction to the input end; and an AHB bus interface, connected to an output end of the logic control circuit, and further connected to a bus matrix of the chip, configured to send the specified test program to the bus matrix for testing. Through the embodiments of the present disclosure, the time expenditure of ATE testing is reduced, in addition, the efficient testing of the chip by the special test instruction is realized, and the reliability and efficiency of the chip testing are further improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of chip testing, and in particular, to a TC module inside a chip applied to ATE testing and an integrated chip. BACKGROUND

[0002] Currently, in all electronic device manufacturing processes, there is a need to distinguish between true and false, which is actually a trial process. In order to realize this process, various test equipment is needed, and such equipment is called ATE (Automatic Test Equipment) equipment. The electronic device DUT (Device Under Test) mentioned here includes IC, discrete components and semiconductor devices.

[0003] In related technologies, ATE testing exists in each link of the front-end and back-end, which depends on the requirements of process design.

[0004] However, the traditional ATE test needs the tester to manually input the CPU execution, so a lot of time is wasted in the process of CPU instruction input. In addition, the traditional ATE test does not have specially customized test instructions, and needs to convert the ATE test behavior into CPU general instructions, and after conversion, the relevant modules can be accessed through the CPU to complete the entire test.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to provide a TC module inside a chip applied to ATE testing and an integrated chip, which at least partially overcomes the problem of low test efficiency caused by the limitations and defects of related technologies.

[0007] According to a first aspect of an embodiment of the present disclosure, a TC module inside a chip applied to ATE testing is provided, comprising: a logic control circuit, configured to convert a specified test instruction into a test program through a local AHB master protocol; a JTAG interface connected to an input end of the logic control circuit, configured to receive the specified test instruction transmitted based on a JTAG protocol, and transmit the specified test instruction to the input end; and an AHB bus interface connected to an output end of the logic control circuit, the AHB bus interface is also connected to a bus matrix of a chip, configured to send the specified test program to the bus matrix for testing.

[0008] In an example embodiment of the present disclosure, the logic control circuit comprises: an instruction command unit, a first end of the instruction command unit being connected to the JTAG interface, a second end of the instruction command unit being connected to the AHB bus interface, the instruction command unit being predefined with corresponding instruction names and instruction codes.

[0009] In an example embodiment of the present disclosure, the logic control circuit further comprises: a special control command unit, a first end of the special control command unit being connected to the JTAG interface, a second end of the special control command unit being connected to the AHB bus interface, the special control command unit being predefined with an ATE test special protocol, the ATE test special protocol being used to define the input mode of the test vector based on the input control signal.

[0010] In an example embodiment of the present disclosure, the logic control circuit further comprises: an instruction execution data unit, a first end of the instruction execution data unit being connected to the JTAG interface, a second end of the instruction execution data unit being connected to the AHB bus interface, the instruction execution data unit storing data used to execute the specified test instruction.

[0011] In an example embodiment of the present disclosure, the logic control circuit further comprises: a control logic state machine, a first end of the control logic state machine being connected to the instruction command unit, a second end of the control logic state machine being connected to the special control command unit, a third end of the control logic state machine being connected to the instruction execution data unit, a fourth end of the control logic state machine being connected to the AHB bus interface, the control logic state machine being used to control the test program execution according to the input variables, output variables and state number of the TC module.

[0012] In an example embodiment of the present disclosure, the JTAG interface is connected to the relevant interface of the input variables, the relevant interface of the input variables comprising at least one of a TCK interface, a TDI interface, a TMS interface, a TRST_N interface and a TDO interface.

[0013] In an example embodiment of the present disclosure, the AHB bus interface is connected to the relevant interface of the output variables, the relevant interface of the output variables comprising at least one of an HSEL interface, an HADDR interface, an HTRANS interface, an HWRITE interface, an HSIZE interface, an HBURST interface, an HWDATA interface, an HRDATA interface and an HRESP interface.

[0014] According to a second aspect of the embodiments of the present disclosure, an integrated chip is provided, comprising: a functional module configured to perform operation processing on data; and a bus matrix, an input end of the bus matrix being capable of accessing a TC module inside the chip for ATE testing, the TC module being capable of accessing the functional module via the bus matrix.

[0015] In an exemplary embodiment of the present disclosure, the TC module and the bus matrix exchange data via an AHB bus interface.

[0016] In an exemplary embodiment of the present disclosure, the functional module comprises at least one of a system sub-module, a nand_phy, a pcie, and an efuse.

[0017] In the embodiments of the present disclosure, the TC module comprises a logic control circuit, a JTAG interface and an AHB bus interface, and the specified test instruction is converted into a test program by the logic control circuit via a local AHB master protocol. In addition, the specified test instruction transmitted based on the JTAG protocol is received via the JTAG interface, and the specified test instruction is transmitted to the input end. Furthermore, the specified test program is sent to the bus matrix via the AHB bus interface for testing. Thus, the time expenditure of ATE testing is reduced, and the efficient testing of the chip by the special test instruction is realized, further improving the reliability and efficiency of chip testing.

[0018] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and are not limiting to the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is apparent that the accompanying drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor based on these drawings.

[0020] Figure 1 is a schematic diagram of a TC module inside a chip for ATE testing in an exemplary embodiment of the present disclosure;

[0021] Figure 2 is a schematic diagram of another TC module inside a chip for ATE testing in an exemplary embodiment of the present disclosure;

[0022] Figure 3 is a schematic diagram of another TC module inside a chip for ATE testing in an exemplary embodiment of the present disclosure;

[0023] Figure 4 is a schematic diagram of an integrated chip in an exemplary embodiment of the present disclosure;

[0024] Figure 5 is a schematic diagram of another integrated chip in an exemplary embodiment of the present disclosure

[0025] Figure 6 is a schematic diagram of another integrated chip in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any

[0027] In addition, the accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate various embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0028] Example implementations of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0029] Figures 1 to 3 is a schematic diagram of a TC module inside a chip applied to ATE testing in an exemplary embodiment of the present disclosure.

[0030] Referring to Figure 1 , the TC module 100 inside a chip applied to ATE testing can include:

[0031] a logic control circuit 102 for converting a designated test instruction into a test program through a local AHB master protocol.

[0032] Among them, the AHB bus protocol (AHB master protocol) is adopted by most SoC (System-on-a-Chip) designs, which specifies AHB (Advanced High-performance Bus), ASB (Advanced System Bus), APB (Advanced Peripheral Bus), etc., for high-performance, high-clock-frequency system structure.

[0033] The JTAG interface 104 is connected to the input end of the logic control circuit 102, and is used to receive the specified test instruction transmitted based on the JTAG protocol and transmit the specified test instruction to the input end.

[0034] Among them, JTAG (Joint Test Action Group) is to define a TAP (Test Access Port) inside the device to test the internal nodes through a dedicated JTAG test tool. JTAG testing allows multiple devices to be connected in series through the JTAG interface to form a JTAG chain, which can realize separate testing of each device. The JTAG interface is also commonly used to implement ISP (In-System Programmer) to program FLASH devices and the like.

[0035] The AHB bus interface 106 is connected to the output end of the logic control circuit 102, and the AHB bus interface 106 is also connected to the bus matrix of the chip, and is used to send the specified test program to the bus matrix for testing.

[0036] In the embodiments of the present disclosure, the TC module 100 includes the logic control circuit 102, the JTAG interface 104 and the AHB bus interface 106, and the specified test instruction is converted into a test program by the logic control circuit 102 through the local AHB master protocol. In addition, the JTAG interface 104 receives the specified test instruction transmitted based on the JTAG protocol and transmits the specified test instruction to the input end, and the AHB bus interface 106 sends the specified test program to the bus matrix for testing. This reduces the time expenditure of ATE testing, and also realizes efficient testing of the chip by the special test instruction, further improving the reliability and efficiency of chip testing.

[0037] Specifically, the TC module 100 is a chip internal module specially applied to ATE testing. It can receive user-defined instructions transmitted from the JTAG interface 104 and the controller inside the TC module 100 can generate AHB transmission protocol outside. Since the AHB master (i.e. the AHB bus interface 106) of the TC module 100 has been connected to the bus matrix inside the chip, the TC module 100 can easily access important internal modules such as PCIE, NAND_PHY and EFUSE. Since the TC module 100 has user-defined ATE testing instructions, these instructions can quickly complete the ATE testing program of the relevant high-speed interface module through the AHB master inside the TC module 100, which maximally reduces the testing time and saves a large amount of ATE testing expenses while ensuring the testing completion degree. The TC module 100 can receive instructions from the JTAG interface 104 outside the chip and generate corresponding AHB master protocol through the internal logic control circuit 102 to access the relevant internal modules of the chip while keeping the minimum hardware overhead.

[0038] Next, the parts of the TC module 100 inside the chip applied to ATE testing will be described in detail.

[0039] In an exemplary embodiment of the present disclosure, as shown in Figure 2 The logic control circuit 102 comprises:

[0040] The instruction command unit 1022 (CMD INSTRUCTION) has a first end connected to the JTAG interface 104 and a second end connected to the AHB bus interface 106. The instruction command unit 1022 is pre-defined with corresponding instruction names and instruction codes.

[0041] In an exemplary embodiment of the present disclosure, as shown in Figure 2 The logic control circuit 102 further comprises:

[0042] The special control command unit 1024 (TMS INSTRUCTION) has a first end connected to the JTAG interface 104 and a second end connected to the AHB bus interface 106. The special control command unit 1024 is pre-defined with ATE testing special protocol, which is used to define the input method of the test vector based on the input control signal.

[0043] In an exemplary embodiment of the present disclosure, as shown in Figure 2As shown, the logic control circuit 102 further comprises:

[0044] An instruction execution data unit 1026, a first end of the instruction execution data unit 1026 is connected to the JTAG interface 104, a second end of the instruction execution data unit 1026 is connected to the AHB bus interface 106, and the instruction execution data unit 1026 stores data for executing the specified test instruction.

[0045] In an exemplary embodiment of the present disclosure, an ATE test dedicated protocol is defined based on the JTAG protocol, and the input mode of some test vectors is defined by the input of TMS as shown in Table 1.

[0046] Table 1

[0047] tms 100001 : cmd start tms 111111 : cmd end tms 100011 : cmd instruction tms 100101 : cmd d0 tms 100111 : cmd d1 tms 101001 : cmd d2 tms 101011 : cmd d3 tms 101101 : cmd d4 tms 101111 : cmd d5 tms 110001 : cmd d6 tms 110011 : cmd d7

[0048] In an exemplary embodiment of the present disclosure, as Figure 2 shown, the logic control circuit 102 further comprises:

[0049] A control logic state machine 1028, a first end of the control logic state machine 1028 is connected to the instruction command unit, a second end of the control logic state machine 1028 is connected to the dedicated control command unit, a third end of the control logic state machine 1028 is connected to the instruction execution data unit, and a fourth end of the control logic state machine 1028 is connected to the AHB bus interface 106, and the control logic state machine 1028 is used for test control of the test program execution according to the input variables, output variables and state number of the TC module 100.

[0050] In an exemplary embodiment of the present disclosure, as Figure 3 shown, the JTAG interface 104 is connected to the relevant interface of the input variable, and the relevant interface of the input variable comprises at least one of a TCK interface, a TDI interface, a TMS interface, a TRST_N interface and a TDO interface.

[0051] Among them, the TCK interface is the interface of the external input clock corresponding to the JTAG interface, the TDI interface is the interface of the external data input signal corresponding to the JTAG interface, the TDO interface is the interface of the external output signal corresponding to the JTAG interface, the TMS interface is the interface of the mode selection signal corresponding to the JTAG interface, and the TRST_N interface is usually connected to an audio device connection plug for balanced signal transmission (at this time the function is the same as the canon plug) or for unbalanced stereo signal transmission.

[0052] In an exemplary embodiment of the present disclosure, instruction names and instruction codes are defined for internal test commands as shown in Table 2.

[0053] Table 2

[0054]

[0055] In an exemplary embodiment of the present disclosure, as shown in Figure 3 the AHB bus interface 106 is connected to the relevant interface of the output variable, and the relevant interface of the output variable includes at least one of an HSEL interface, an HADDR interface, an HTRANS interface, an HWRITE interface, an HSIZE interface, an HBURST interface, an HWDATA interface, an HRDATA interface, and an HRESP interface.

[0056] Figures 4 to 6 FIG. 1 is a schematic diagram of an integrated chip according to an exemplary embodiment of the present disclosure.

[0057] Referring to Figure 4 , an integrated chip according to an exemplary embodiment of the present disclosure includes:

[0058] a functional module 202 configured to perform operation processing on data.

[0059] a system bus matrix 204, an input end of the system bus matrix 204 being capable of accessing the TC module 100 inside the chip for ATE test as described above, and the TC module 100 being capable of accessing the functional module 202 through the system bus matrix 204.

[0060] In an exemplary embodiment of the present disclosure, as shown in Figure 5 the TC module 100 and the system bus matrix interact with each other through the AHB bus interface 106. In the SOC interconnection structure inside the integrated chip, the TC module 100 can be regarded as a simple CPU to access most of the modules in the SOC interconnection structure, and the TC module 100 is connected to the system bus matrix (i.e., the system bus matrix 204) inside the integrated chip through its own AHB master. The system bus matrix (i.e., the system bus matrix 204) can also be connected to N CPUs, denoted as CPU 0, …, CPU N, N being an integer greater than or equal to 0.

[0061] In an exemplary embodiment of the present disclosure, as shown in Figure 6As shown, the function module 202 includes at least one of a system sub-module, a nand_phy, a pcie, and an efuse.

[0062] It should be noted that although several modules or units of the device for action execution are mentioned in the foregoing detailed description, such a division is not mandatory. Indeed, according to embodiments of the disclosure, the features and functionalities of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functionalities of one module or unit described above can be further divided into embodied by a plurality of modules or units.

[0063] In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above-described method is also provided.

[0064] Those skilled in the art can understand that various aspects of the present disclosure can be implemented as a system, a method or a program product. Therefore, various aspects of the present disclosure can be embodied in the form of a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation of hardware and software in combination, which can be collectively referred to as "circuitry", "module" or "system" herein.

[0065] From the above description of the embodiments, those skilled in the art can easily understand that the example embodiments described herein can be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a U disk, a mobile hard disk, etc.) or a network, and includes a number of instructions to make a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) execute the methods according to the embodiments of the present disclosure.

[0066] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the above-described method of the present specification is stored. In some possible embodiments, various aspects of the present disclosure can also be implemented in the form of a program product, which includes program codes for causing a terminal device to perform the steps described in the "example method" section of the present specification according to various example embodiments of the present disclosure when the program product is run on the terminal device.

[0067] A program product for implementing the above-described method according to the embodiments of the present application can take a portable compact disc read only memory (CD-ROM) and include a program code, and can be executed on a terminal device such as a personal computer. However, the program product of the present application is not limited thereto, and in the present document, a readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device.

[0068] The program product can take any combination of one or more readable media. The readable media can be a readable signal medium or a readable storage medium. The readable storage medium, for example, can be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the above. More specific examples (a non-exhaustive list) of the readable storage medium include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM or flash memory), an optical fiber, a portable compact disc read only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0069] The computer readable signal medium can include a data signal propagated in baseband or propagated as a carrier wave, in which the readable program code is embodied. Such propagated data signal can take multiple forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The readable signal medium can also be any readable medium that is not a readable storage medium and that can transmit, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or device.

[0070] The program code contained on the readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, and the like, or any suitable combination of the above.

[0071] The program code may, for example, be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's computing device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device or entirely on the remote computing device or server. In the latter scenario, the remote computing device can be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computing device, for example, through the Internet using an Internet Service Provider.

[0072] Furthermore, the above-described diagrams are merely schematic illustrations of the processes included in the method according to the exemplary embodiments of the present application, and are not intended to be limiting. It is readily understood that the processes shown in the above-described diagrams do not indicate or limit the time sequence of the processes. In addition, it is readily understood that the processes can be executed synchronously or asynchronously, for example, in a plurality of modules.

[0073] Other embodiments of the disclosure will be apparent to those of ordinary skill in the art from a consideration of the specification and practice of the disclosure disclosed herein. The specification and examples given herein are intended as illustrative only and are not intended to limit the true scope and spirit of the present disclosure. The true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A TC module inside a chip used for ATE testing, characterized in that, include: The logic control circuit is used to convert specified test instructions into test programs via the local AHB master protocol; A JTAG interface is connected to the input terminal of the logic control circuit, used to receive the specified test command transmitted based on the JTAG protocol, and to transmit the specified test command to the input terminal. The AHB bus interface is connected to the output of the logic control circuit. The AHB bus interface is also connected to the chip's bus matrix for sending the test program to the bus matrix for testing.

2. The TC module inside the chip used for ATE testing as described in claim 1, characterized in that, The logic control circuit includes: The instruction command unit has its first end connected to the JTAG interface and its second end connected to the AHB bus interface. The instruction command unit is predefined with corresponding instruction names and instruction codes.

3. The TC module inside the chip used for ATE testing as described in claim 1, characterized in that, The logic control circuit also includes: A dedicated control command unit, the first end of which is connected to the JTAG interface, and the second end of which is connected to the AHB bus interface, the dedicated control command unit is predefined with an ATE test dedicated protocol, the ATE test dedicated protocol is used to define the input mode of the test vector based on the input control signal.

4. The TC module inside the chip used for ATE testing as described in claim 1, characterized in that, The logic control circuit also includes: The instruction execution data unit has a first end connected to the JTAG interface and a second end connected to the AHB bus interface. The instruction execution data unit stores data for executing the specified test instruction.

5. The TC module inside a chip used for ATE testing as described in any one of claims 1-4, characterized in that, The logic control circuit also includes: A control logic state machine is provided, wherein the first terminal of the control logic state machine is connected to the instruction command unit in the logic control circuit, the second terminal of the control logic state machine is connected to the dedicated control command unit in the logic control circuit, the third terminal of the control logic state machine is connected to the instruction execution data unit in the logic control circuit, and the fourth terminal of the control logic state machine is connected to the AHB bus interface. The control logic state machine is used to control the execution of the test program according to the input variables, output variables, and state number of the TC module.

6. The TC module inside the chip used for ATE testing as described in claim 5, characterized in that, The JTAG interface is connected to the relevant interface of the input variable, which includes at least one of the following: TCK interface, TDI interface, TMS interface, TRST_N interface, and TDO interface.

7. The TC module inside the chip used for ATE testing as described in claim 5, characterized in that, The AHB bus interface is connected to the relevant interface of the output variable, which includes at least one of the following interfaces: HSEL interface, HADDR interface, HTRANS interface, HWRITE interface, HSIZE interface, HBURST interface, HWDATA interface, HRDATA interface, and HRESP interface.

8. An integrated chip, characterized in that, include: Functional modules are used to perform calculations and processing on data; A bus matrix, wherein the input terminal of the bus matrix can be connected to the TC module inside the chip used for ATE testing as described in any one of claims 1-7, and the TC module can access the functional module via the bus matrix.

9. The integrated chip as described in claim 8, characterized in that, The TC module and the bus matrix exchange data via the AHB bus interface.

10. The integrated chip as described in claim 8 or 9, characterized in that, The functional modules include at least one of system sub-modules, nand_phy, pcie, and efuse.

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