Neuron computing core and system

Abstract

The application discloses a neuron computing core and system. The computing core comprises a storage module, a computing module, a pulse generation module and a core control module. The computing module is used for performing operation on coarse-grained data, pulse data and weight data previously set in the storage module, and the operation result is sent to the pulse generation module. The pulse generation module is used for sending the operation result to a target address. The computing core can support operation with different precisions without two repeated computing resources, and can reuse the same hardware resources, thereby ensuring high operation efficiency and saving hardware resources. The application can be widely applied in the field of artificial neural network computing technology.

Description

Technical Field

[0001] This invention relates to the field of artificial neural network computing technology, and in particular to a neuron computing kernel and system. Background Technology

[0002] Traditional computers mostly adopt the von Neumann architecture. However, on the one hand, the separation of storage and computing modules in the von Neumann architecture leads to huge energy consumption and latency in data transmission. On the other hand, traditional computing architectures are not optimized for existing neural networks, resulting in relatively low hardware efficiency.

[0003] In summary, the problems existing in the relevant technologies urgently need to be solved. Summary of the Invention

[0004] The purpose of this invention is to at least partially solve one of the technical problems existing in the prior art.

[0005] Therefore, one object of the present invention is to provide a neuron computing kernel and system.

[0006] To achieve the above-mentioned technical objectives, the technical solutions adopted in the embodiments of the present invention include:

[0007] On one hand, embodiments of the present invention provide a neuron computing kernel, including: a storage module, a computing module, a pulse generation module, and a kernel control module;

[0008] The storage module is used to store coarse-grained data, fine-grained data, pulse data, and weight data;

[0009] The calculation module is used to perform calculations based on the coarse and fine granular data, the pulse data, and the weight data, and send the calculation results to the pulse generation module.

[0010] The pulse generation module is used to send the calculation result output by the calculation module to the target address and send a data processing completion flag for this frame to the core control module.

[0011] The core control module is used to control the working status of the storage module, the computing module, and the pulse generation module.

[0012] Furthermore, the storage module also includes: a decoding unit;

[0013] The decoding unit is used to receive and parse the coarse-grained data, the pulse data, and the weight data.

[0014] Furthermore, the pulse generation module includes a comparison unit;

[0015] The comparison unit is used to compare the calculation result output by the calculation module with a preset threshold, and send the calculation result output by the calculation module to the target address according to the comparison result.

[0016] Furthermore, the comparison unit is also used for:

[0017] If the calculation result is less than a preset threshold, the calculation result is sent to the target address;

[0018] If the calculation result is greater than a preset threshold, the calculation result is cleared to zero and sent to the target address.

[0019] Furthermore, the comparison unit is also used for:

[0020] When the calculation result is greater than a preset threshold, a pulse is generated, which is used to clear the calculation result to zero.

[0021] Furthermore, the coarse and fine granularity data includes 16-bit granularity and 32-bit granularity.

[0022] Furthermore, the computing core also includes: an attenuation module;

[0023] The attenuation module is used to attenuate the weight data.

[0024] Furthermore, the attenuation process includes multiplicative attenuation, shift-subtraction attenuation, subtraction attenuation, and exponential attenuation.

[0025] Furthermore, the computing module includes: a data selector;

[0026] The data selector is used to control the calculation accuracy of the calculation module based on the coarse-grained data.

[0027] On the other hand, this embodiment provides a neural network system including at least one neuron computing kernel as mentioned above.

[0028] This invention discloses a neuron computational kernel and system. The computational kernel includes a storage module, a computation module, a pulse generation module, and a kernel control module. The computation module performs calculations on pre-set coarse-grained data, pulse data, and weight data in the storage module, and sends the calculation results to the pulse generation module, which then sends the calculation results to a target address. This computational kernel supports operations of different precisions without requiring two duplicate computational resources; furthermore, it can reuse the same hardware resources, ensuring high computational efficiency while saving hardware resources. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0030] Figure 1 This is a schematic diagram of the structure of a neuronal computational kernel provided in an embodiment of the present invention;

[0031] Figure 2 A circuit structure diagram of a neuron computing kernel provided in an embodiment of the present invention.

[0032] Figure 3 A circuit structure diagram of a pulse generation module for a neuronal computation kernel provided in an embodiment of the present invention;

[0033] Figure 4 A circuit structure diagram of a decay module for a neuron computing kernel provided in an embodiment of the present invention;

[0034] Figure 5 A circuit structure diagram of a computation module for a neuron computation kernel provided in an embodiment of the present invention;

[0035] Figure 6 A circuit diagram of an addition unit of a neuron computing kernel provided in an embodiment of the present invention;

[0036] Figure 7 This is a circuit diagram of the multiplication unit of a neuron computing kernel provided in an embodiment of the present invention. Detailed Implementation

[0037] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

[0038] In the description of this invention, "multiple" means two or more. The use of "first" and "second" is for distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or the order in which the indicated technical features are presented. Furthermore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and not for limiting the invention.

[0039] Reference Figure 1 and Figure 2 This invention discloses a neuron computation kernel and system, including a storage module, a computation module, a pulse generation module, and a kernel control module. The storage module is used to store coarse-grained data, pulse data, and weight data. The computation module is used to perform calculations based on the coarse-grained data, the pulse data, and the weight data, and send the calculation results to the pulse generation module. The pulse generation module is used to send the calculation results output by the computation module to a target address and send a data processing completion flag for this frame to the kernel control module. The kernel control module is used to control the working states of the storage module, the computation module, and the pulse generation module.

[0040] Specifically, the workflow of a neuron computation kernel is as follows: Considering the characteristics of spiking neural networks and different needs, the coarse-grained nature of the computation must first be determined, and the required coarse-grained and fine-grained data are input into the storage module. In the fine-grained mode, the kernel control module can call the multipliers and adders in the computation module for calculation. If the network does not require high precision but is for edge devices with high power consumption requirements, the computation kernel can be configured in coarse-grained mode. In this mode, the multiplier will be disabled, and coarse-grained multiplication, exponentiation, and division operations will be implemented using shifters with extremely low hardware resources and power consumption.

[0041] This embodiment uses a calculation module to perform calculations on pre-set coarse-grained data, pulse data, and weight data in the storage module, and sends the calculation results to a pulse generation module, which then sends the results to the target address. This calculation core supports calculations of different precisions without requiring two redundant computing resources; furthermore, it reuses identical hardware resources, ensuring high computational efficiency while conserving hardware resources.

[0042] As an optional implementation, the storage module further includes: a decoding unit;

[0043] The decoding unit is used to receive and parse the coarse-grained data, the pulse data, and the weight data.

[0044] The decoding unit receives and parses neural network information. The neural network information includes weight data and impulse data, wherein the weight data includes the addresses of the weights. The decoding unit sends the addresses of the weights to the storage module and the impulse data to the calculation module.

[0045] The storage module stores a list of address weight pairs to match input address information. If the input address matches a stored address, the storage module outputs the corresponding weight value to the calculation module; this weight value varies within a certain range. If the input address does not match a stored address, the storage module outputs a zero value. Furthermore, the storage module can set the address validity flag state based on the matching result. Specifically, if the input address matches a stored address, the storage module issues an address validity flag; if it does not match, the storage module does not change the address validity flag state.

[0046] As a further optional implementation, the pulse generation module includes a comparison unit;

[0047] The comparison unit is used to compare the calculation result output by the calculation module with a preset threshold, and send the calculation result output by the calculation module to the target address according to the comparison result.

[0048] refer to Figure 3 In this embodiment, the comparison unit of the pulse generation module compares the calculation result output by the calculation module with a preset threshold, and sends the calculation result output by the calculation module to the target address according to the comparison result. Specifically, after completing the calculation, the neuron calculation kernel updates the neuron membrane potential to form a new neuron membrane potential, and this neuron membrane potential value serves as the calculation result of the neuron calculation kernel. The preset threshold is a voltage value pre-set in the pulse generation module.

[0049] As a further optional implementation, the comparison unit is also used for:

[0050] If the calculation result is less than a preset threshold, the calculation result is sent to the target address;

[0051] If the calculation result is greater than a preset threshold, the calculation result is cleared to zero and sent to the target address.

[0052] As a further optional implementation, the comparison unit is also used for:

[0053] When the calculation result is greater than a preset threshold, a pulse is generated, which is used to clear the calculation result to zero.

[0054] Specifically, in this embodiment, after completing a calculation, the comparison unit compares the updated neuronal membrane potential with the threshold voltage. If the membrane potential is less than the threshold voltage, the neuron will not generate a pulse, and the membrane potential value at that moment will be stored in the storage module for the neuron to calculate the next timestamp. If the membrane potential exceeds the threshold voltage, the neuron will be activated and emit a pulse. At this time, the membrane potential will be reset to the resting potential, and the membrane potential value restored to the resting potential will be stored in the storage module.

[0055] As an optional further implementation, the computing core also includes: an attenuation module;

[0056] refer to Figure 4 In this embodiment, an attenuation module is used to avoid overfitting, meaning the model's training error is much smaller than its error on the test set. While increasing the training dataset may alleviate overfitting, acquiring additional training data is often costly. Therefore, setting an attenuation module can effectively reduce training costs.

[0057] The attenuation module is used to attenuate the weight data.

[0058] As a further optional implementation, the attenuation process includes multiplicative attenuation, shift-subtraction attenuation, subtraction attenuation, and exponential attenuation.

[0059] Specifically, in this embodiment, the attenuation module has multiple attenuation calculation modes to cope with different application scenarios, including multiplicative attenuation, shift subtraction attenuation, subtraction attenuation, exponential attenuation, etc., all of which are supported in hardware, and also support attenuation with different granularities and different precisions.

[0060] As a further optional implementation, the computing module includes: a data selector;

[0061] The data selector is used to control the calculation accuracy of the calculation module based on the coarse-grained data.

[0062] refer to Figure 5 In this embodiment, the calculation unit can perform addition, subtraction, multiplication, and division operations with different precisions through a data selector, and can also perform shift and comparison operations. The calculation unit can achieve calculations with different operational precisions by integrating its addition, subtraction, and multiplication units.

[0063] refer to Figure 6 The addition module of the computing unit can perform single 16-bit addition or subtraction through mode control signals, i.e., coarse-grained data, or 32-bit addition or subtraction through concatenation logic. The subtraction module is completed by the addition module in conjunction with the two's complement circuit.

[0064] refer to Figure 7 The multiplication module of the computing unit can implement single 16-bit coarse-grained multiplication through mode control signals, or it can implement 32-bit fine-grained multiplication by splicing logic circuits and reusing the addition module. Coarse-grained multiplication is a specific multiplication implemented through shifters and adders, which can reduce power consumption.

[0065] Specifically, the core control module can select different chip select outputs based on the calculation results of different modes, and can also switch between coarse-grained and fine-grained algorithms by controlling different calculation modes according to different demand scenarios.

[0066] As a further optional implementation, the coarse-grained data includes 16-bit granularity and 32-bit granularity.

[0067] Specifically, the data in this embodiment includes both 16-bit and 32-bit granularity data. It can be understood that the calculation module can output two different final payment data; correspondingly, the storage module also supports both 32-bit and 16-bit storage modes to handle different computational precision scenarios. In the 16-bit mode, one address in the storage module corresponds to two 16-bit data points. After the data is read, the core control module performs data splitting and matching.

[0068] On the other hand, this embodiment provides a neural network system including at least one neuron computing kernel as mentioned above.

[0069] It is understood that, compared with the prior art, the embodiments of the present invention also have the following advantages:

[0070] This embodiment provides a low-cost neural network computation kernel with variable precision, offering the advantages of flexible configuration and support for different computational precisions. The different precision operations supported by this invention are achieved through unique control logic, eliminating the need for two redundant computational resources. Reusing the same hardware resources ensures both high computational efficiency and conserves hardware resources.

[0071] This embodiment designs a configurable, highly flexible, and scalable computational core for spiking neural network (SNN) computation. By configuring a series of registers of the computational core, various computational modes can be achieved to support SNN algorithms of different types and scales.

[0072] To adapt to larger-scale applications, this invention binds storage resources to computing cores, forming distributed storage that is more bio-realistic, improves computing efficiency, and is easy to expand.

[0073] It should be recognized that embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium. The methods described above can be implemented using standard programming techniques—including implementation in a computer program on a non-transitory computer-readable storage medium configured to allow the computer to operate in a specific and predefined manner—according to the methods and drawings described in the specific embodiments. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Furthermore, for this purpose, the program can run on a programmed application-specific integrated circuit (ASIC).

[0074] Furthermore, the procedures described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The procedures described herein (or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions, and may be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The aforementioned computer programs include a plurality of instructions executable by one or more processors.

[0075] Furthermore, the above methods can be implemented in any suitable type of computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or in communication with charged particle tools or other imaging devices, etc. Aspects of the invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it is readable by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. Furthermore, the machine-readable code, or portions thereof, can be transmitted via wired or wireless networks. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media comprises instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. When programmed according to the methods and techniques described in the invention, the invention also includes the computer itself.

[0076] A computer program can be applied to input data to perform the functions described herein, thereby transforming the input data to generate output data stored in non-volatile memory. The output information can also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including a specific visual depiction of physical and tangible objects generated on the display.

[0077] The above description is merely a preferred embodiment of the present invention. The present invention is not limited to the above-described embodiments. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention, as long as they achieve the technical effects of the present invention by the same means, should be included within the scope of protection of the present invention. Within the scope of protection of the present invention, the technical solutions and / or implementation methods can have various modifications and variations.

Claims

1. A neuronal computational kernel, characterized in that, include: Storage module, computing module, pulse generation module, and core control module; The storage module is used to store coarse-grained data, fine-grained data, pulse data, and weight data; The calculation module is used to perform calculations based on the coarse and fine granular data, the pulse data, and the weight data, and send the calculation results to the pulse generation module. The pulse generation module is used to send the calculation result output by the calculation module to the target address and send a data processing completion flag for this frame to the core control module. The core control module is used to control the working status of the storage module, the computing module and the pulse generation module; The coarse and fine granularity data include 16-bit granularity and 32-bit granularity; The computing module includes: a data selector; The data selector is used to control the calculation accuracy of the calculation module based on coarse-grained data; The calculation module performs addition, subtraction, multiplication, and division operations with different precisions through the data selector, as well as shift and comparison operations; the calculation module achieves calculations with different precisions by integrating the addition, subtraction, and multiplication units. The addition unit can perform single 16-bit addition or subtraction through mode control signals, i.e. coarse and fine granular data, and can perform 32-bit addition or subtraction through concatenation logic. The subtraction unit is completed by the addition unit in conjunction with the two's complement circuit; The multiplication unit implements single 16-bit coarse-grained multiplication through mode control signals, and implements 32-bit fine-grained multiplication through splicing logic circuits and reusing the addition unit. Coarse-grained multiplication is a specific type of multiplication implemented using shifters and adders; The core control module selects different chip select outputs based on the calculation results of different modes, and switches between coarse-grained and fine-grained algorithms by controlling different calculation modes according to different demand scenarios.

2. The neuronal computational kernel according to claim 1, characterized in that, The storage module further includes: a decoding unit; The decoding unit is used to receive and parse the coarse-grained data, the pulse data, and the weight data.

3. The neuronal computational kernel according to claim 1, characterized in that, The pulse generation module includes a comparison unit; The comparison unit is used to compare the calculation result output by the calculation module with a preset threshold, and send the calculation result output by the calculation module to the target address according to the comparison result.

4. The neuronal computational kernel according to claim 3, characterized in that, The comparison unit is also used for: If the calculation result is less than the preset threshold, the calculation result is sent to the target address; If the calculation result is greater than the preset threshold, the calculation result is cleared to zero and sent to the target address.

5. The neuronal computational kernel according to claim 4, characterized in that, The comparison unit is also used for: When the calculation result is greater than a preset threshold, a pulse is generated, which is used to clear the calculation result to zero.

6. The neuronal computational kernel according to claim 1, characterized in that, The computing core also includes: an attenuation module; The attenuation module is used to attenuate the weight data.

7. The neuronal computational kernel according to claim 6, characterized in that, The attenuation process includes multiplicative attenuation, shift-subtraction attenuation, subtraction attenuation, and exponential attenuation.

8. A neural network system, characterized in that, It includes at least one neuronal computational kernel as described in any one of claims 1-7.

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