Failure point positioning method and device, computer device, medium and program product

Abstract

The application relates to a failure point positioning method and device, computer equipment, a storage medium and a computer program product. The method comprises the following steps: obtaining a thermal imaging picture of a surface of a to-be-tested chip subjected to a test signal by scanning the to-be-tested chip subjected to the test signal through an infrared thermal imaging device, and analyzing the thermal imaging picture to obtain a phase angle of each point on the surface of the to-be-tested chip; obtaining a three-dimensional image of the surface of the to-be-tested chip subjected to the test signal by scanning the to-be-tested chip subjected to the test signal through an image scanning device, and analyzing the three-dimensional image to obtain a three-dimensional coordinate of each point on the surface of the to-be-tested chip; and calculating a three-dimensional coordinate of a failure point in the to-be-tested chip according to the phase angle and the three-dimensional coordinate of each point on the surface of the to-be-tested chip. The method can improve the positioning precision of the failure point in the chip.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a method, apparatus, computer equipment, medium, and program product for locating failure points. Background Technology

[0002] As electronic products evolve towards miniaturization, high density, high reliability, and low power consumption, advanced 3D packaging, which integrates multiple chips and devices into a single package, has become a new direction to meet technological advancements. Stacked 3D packaging, with its high integration, light weight, small package size, and low manufacturing cost, has broad application prospects in emerging industries such as artificial intelligence, autonomous driving, 5G networks, and the Internet of Things.

[0003] However, in multi-layered 3D packaging structures, due to increased process complexity, failures can occur at traces, vias, or interconnects within any component. As package thickness increases and feature sizes shrink, new challenges arise for failure localization in 3D packaging. First, the geometry in 3D packaging is highly complex and increasingly smaller, making the accuracy of failure localization even more critical. Currently, existing technologies offer very low accuracy in locating failure points in multi-layered chips, particularly in the depth direction. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, computer equipment, medium, and program product for locating failure points that can improve the accuracy of locating failure points inside a chip, in order to address the above-mentioned technical problems.

[0005] Firstly, this application provides a method for locating failure points. The method includes:

[0006] A thermal imaging image of the surface of the chip under test is obtained by scanning the chip under test with a test signal through a thermal imaging device, and the phase angle of each point on the surface of the chip under test is obtained by analyzing the thermal imaging image.

[0007] A three-dimensional image of the surface of the chip under test is obtained by scanning the chip under test with the applied test signal using an image scanning device, and the three-dimensional image is analyzed to obtain the three-dimensional coordinates of each point on the surface of the chip under test.

[0008] The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test.

[0009] In one embodiment,

[0010] The step of acquiring a thermal image of the chip under test by scanning it with an infrared thermal imaging device to obtain a thermal image of the surface of the chip under test, and analyzing the thermal image to obtain the phase angle of each point on the surface of the chip under test, includes:

[0011] The chip under test is scanned using an infrared thermal imaging device to obtain a thermal image of the surface of the chip under test.

[0012] The thermal imaging image is digitally phase-locked signal coherently processed using a sinusoidal function reference signal with the same phase-locked frequency as the test signal to obtain the corresponding linear average function;

[0013] The phase angle of each point on the surface of the chip under test is calculated based on the sinusoidal function reference signal and the linear average function.

[0014] In one embodiment, after performing digital phase-locked signal coherent processing on the thermal image using a sinusoidal function reference signal with the same phase-locked frequency as the test signal to obtain the corresponding linear average function, the method further includes:

[0015] The temperature amplitude at each point on the surface of the chip under test is calculated based on the sinusoidal function reference signal and the linear average function.

[0016] In one embodiment, calculating the three-dimensional coordinates of the failure point in the chip under test based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test includes:

[0017] The location of the failure point can be determined in the horizontal direction by the amplitude of vibration at each point on the surface of the chip under test.

[0018] The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle of each point on the chip surface and the three-dimensional coordinates of each point in the region.

[0019] In one embodiment, the three-dimensional coordinates of the failure point in the chip under test are calculated using the following formula:

[0020]

[0021] Where Φ is the phase angle, z eff The equivalent distance from the failure point to each point on the surface of the chip under test is Λ, where Λ is the thermal diffusion length of the chip material under test, the three-dimensional coordinates of any point on the surface of the chip under test are (x, y, z), and the three-dimensional coordinates of the failure point are (x0, y0, z0).

[0022] In one embodiment, calculating the three-dimensional coordinates of the failure point in the chip under test based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test includes:

[0023] The phase angle and three-dimensional coordinates of each point on the surface of the chip under test are substituted into the formula for parameter fitting to obtain the three-dimensional coordinates of the failure point in the chip under test.

[0024] Secondly, this application also provides a device for locating failure points. The device includes:

[0025] The phase angle acquisition module is used to acquire thermal imaging images of the surface of the chip under test by scanning the chip under test with an infrared thermal imaging device and applying a test signal, and to analyze the thermal imaging images to obtain the phase angle of each point on the surface of the chip under test.

[0026] The three-dimensional coordinate acquisition module is used to acquire a three-dimensional image of the surface of the chip under test obtained by scanning the chip under test with the applied test signal through an image scanning device, and to analyze the three-dimensional image to obtain the three-dimensional coordinates of each point on the surface of the chip under test.

[0027] The failure point location module is used to calculate the three-dimensional coordinates of the failure point in the chip under test based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test.

[0028] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to perform the following steps:

[0029] A thermal imaging image of the surface of the chip under test is obtained by scanning the chip under test with an infrared thermal imaging device and the thermal imaging image is analyzed to obtain the phase angle of each point on the surface of the chip under test.

[0030] A three-dimensional image of the surface of the chip under test is obtained by scanning the chip under test with the applied test signal using an image scanning device, and the three-dimensional image is analyzed to obtain the three-dimensional coordinates of each point on the surface of the chip under test.

[0031] The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test.

[0032] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, performs the following steps:

[0033] A thermal imaging image of the surface of the chip under test is obtained by scanning the chip under test with an infrared thermal imaging device and the thermal imaging image is analyzed to obtain the phase angle of each point on the surface of the chip under test.

[0034] A three-dimensional image of the surface of the chip under test is obtained by scanning the chip under test with the applied test signal using an image scanning device, and the three-dimensional image is analyzed to obtain the three-dimensional coordinates of each point on the surface of the chip under test.

[0035] The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test.

[0036] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, performs the following steps:

[0037] A thermal imaging image of the surface of the chip under test is obtained by scanning the chip under test with an infrared thermal imaging device and the thermal imaging image is analyzed to obtain the phase angle of each point on the surface of the chip under test.

[0038] A three-dimensional image of the surface of the chip under test is obtained by scanning the chip under test with the applied test signal using an image scanning device, and the three-dimensional image is analyzed to obtain the three-dimensional coordinates of each point on the surface of the chip under test.

[0039] The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test.

[0040] The aforementioned failure point localization method, apparatus, computer equipment, storage medium, and computer program product acquire a thermal image of the surface of the chip under test obtained by scanning the chip under test with an infrared thermal imaging device and applying a test signal, and analyze the thermal image to obtain the phase angle of each point on the surface of the chip under test; acquire a three-dimensional image of the surface of the chip under test obtained by scanning the chip under test with an image scanning device and analyze the three-dimensional image to obtain the three-dimensional coordinates of each point on the surface of the chip under test; and calculate the three-dimensional coordinates of the failure point in the chip under test based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test. Through the above method, this application achieves spatial localization by combining the phase angle and three-dimensional coordinates of each point on the surface of the chip under test. This invention enables rapid failure point localization and is not affected by the chip's geometry, thus achieving high localization accuracy. Attached Figure Description

[0041] Figure 1 This is an application environment diagram of a failure point location method in one embodiment;

[0042] Figure 2 This is a flowchart illustrating a method for locating failure points in one embodiment;

[0043] Figure 3 This is a structural block diagram of a failure point location device in one embodiment;

[0044] Figure 4 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0046] The failure point location method provided in this application embodiment can be applied to, for example... Figure 1 In the illustrated application environment, the system includes an infrared thermal imaging device 102, an image scanning device 103, and a computing device 104. The infrared thermal imaging device 102 and the image scanning device 103 can communicate with the server 104 via wired or wireless means. A data storage system can store the data that the server 104 needs to process. The data storage system can be integrated onto the server 104 or placed in the cloud or on another network server. The infrared thermal imaging device 102 scans the chip under test to obtain a thermal image. The image scanning device 103 scans the chip under test to obtain the three-dimensional coordinates of each point on the surface of the chip. The infrared thermal imaging device 102 sends the obtained thermal image to the computing device 104, and the image scanning device 103 sends the obtained three-dimensional coordinates of each point on the surface of the chip under test to the computing device 104. The computing device 104 calculates the three-dimensional coordinates of the failure point in the chip under test based on the thermal image and the three-dimensional coordinates of each point on its surface. The infrared thermal imaging device 102 can be, but is not limited to, various infrared cameras, infrared imagers, etc., and the image scanning device 103 can be, but is not limited to, various LiDAR scanners, portable scanners, etc. The computing device 104 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can be smart speakers, smart TVs, smart air conditioners, etc. Portable wearable devices can be smartwatches, smart bracelets, head-mounted devices, etc.

[0047] In one embodiment, such as Figure 2As shown, a method for locating failure points is provided, including the following steps:

[0048] Step S200: Obtain a thermal image of the chip under test by scanning the chip under test with an infrared thermal imaging device and analyzing the thermal image to obtain the phase angle of each point on the surface of the chip under test.

[0049] In existing technologies (such as Lock-In Thermography, LIT) for failure localization of 3D packaged chips, the thermal wave propagation at the failure point exhibits a strong damping effect, which is exponentially related to the transmission distance. While the detection capability, i.e., the surface temperature rises, increases with the LIT frequency. Therefore, increasing the LIT frequency increases heat transfer from the failure point's heat source towards the z-axis, improving detection capability. However, increasing the frequency also increases heat transfer from the failure point's heat source towards the x and y axes, increasing the failure point's diameter and compromising the accuracy of the results.

[0050] In this embodiment, the method is applied to Figure 1 Taking a computing device as an example, the computer device can control an infrared thermal imaging device to scan the chip under test that has been given a test signal. The infrared thermal imaging device sends the thermal image of the surface of the chip under test obtained by scanning to the computer device. The computer device analyzes the received thermal image using the method described above, thereby obtaining the phase angle Φ of each point on the surface of the chip under test.

[0051] Specifically, in one embodiment, step S200 may include:

[0052] Step S201: Scan the chip under test using an infrared thermal imaging device to obtain a thermal image of the chip under test;

[0053] Step S202: Perform digital phase-locked signal coherent processing on the thermal imaging image to obtain the corresponding linear average function;

[0054] Step S203: Calculate the phase angle of each point on the surface of the chip under test based on the first voltage, the second voltage, and the linear average function.

[0055] During the failure point location process, a test signal needs to be applied to the chip under test (DUT). After the test signal is applied to the DUT, the failure point and other hot spots (it should be noted that the failure point described in this application refers to the hot spot with abnormal heat generation in the DUT) will generate heat. The heat generated by each hot spot and failure point is transmitted to the surface of the DUT in the form of a heat wave, which can be represented by a heat wave function.

[0056] F(t) = A sin(2πf)lock-in t+Φ) (1)

[0057] Where A is the surface temperature amplitude; Φ is the phase angle (phase shift); and f lock-in The phase-locked frequency of the test signal is t, where t is time.

[0058] The test signal is generally an electrical excitation signal, which is typically a square wave (in practice, it can also be an electrical excitation signal of other shapes). Of course, in practice, the electrical excitation signal can also be a sine wave, a cosine wave, a triangle wave, etc.

[0059] A sinusoidal function reference signal with the same phase-locked frequency as the test signal is applied to the chip under test. As one embodiment, the sinusoidal function reference signal is S... 0° S -90° S 0° This represents a sinusoidal reference signal with a phase angle of 0°, S -90° This represents a sinusoidal reference signal with a phase angle of -90°. In specific implementations, S can also be used. 0° S 90° These two sinusoidal reference signals only need to satisfy the condition that the phase relationship between the sinusoidal reference signals and the test signals is equal (which can also be understood as the phase relationship between the two signals differing by 90°). After applying the sinusoidal reference signals, the digital phase-locked signal is coherently processed by a computer (after coherent processing, noise points can be removed, leaving only the hot spots of the phase-locked frequency), resulting in a linear average within the integral application period:

[0060]

[0061] Where i∈[1,N], j∈[1,n], n is the number of digitized signals in each phase-locked period of the two sinusoidal function reference signals, N is the number of phase-locked periods, and F j K i，j These represent the temperature fluctuations on the surface of the chip under test when two sinusoidal reference signals are applied.

[0062] Calculate the phase angle Φ image of the surface of the chip under test based on the outputs of two sinusoidal reference signals:

[0063]

[0064] Based on the surface thermal convection boundary conditions, the phase angle of the surface temperature sinusoidal function can be expressed as a function of the distance between the heat source and the detection location, the material properties, and the phase-locked frequency:

[0065]

[0066] Where z is the distance between the heat source and the failure point; Λ is the thermal diffusion length of the material.

[0067] The thermal diffusion length Λ of the chip material under test is a fixed property of the chip material. In practical applications, the thermal diffusion length Λ can be pre-stored and used when needed. Alternatively, it can be obtained in the following ways:

[0068] Based on the phase-locked frequency f lock-in The thermal diffusion length is calculated.

[0069] Specifically, it is calculated using the following formula:

[0070]

[0071] Where 'a' represents the thermal diffusivity of the material. 'a' is determined based on the thermal parameters of the chip under test, including thermal conductivity λ and specific heat capacity C. p The density ρ is obtained through calculation.

[0072] The thermal extension length can also be determined based on thermal parameters such as thermal conductivity λ and specific heat capacity C. p Density ρ and phase-locked frequency f lock-in Obtained through calculation.

[0073] The calculation is performed using the following formula:

[0074]

[0075] It is understood that those skilled in the art will know that the function of analyzing thermal images to obtain the phase angle of each point on the surface of the chip under test can also be integrated into an infrared thermal imaging device. In this embodiment, LIT technology can be used to obtain the phase angle of the chip under test. In specific implementations, other algorithms can also be used, such as pulsed thermography (PT) or pulsed phase thermography (PPT), as long as the technology can obtain the phase angle Φ of each point on the surface of the chip under test. No limitation is made here.

[0076] It should be noted that, in order to improve the accuracy of the results, in practical applications, multiple excitation signals with different phase-locked frequencies can be applied to the chip under test. Based on the test results corresponding to the multiple excitation signals, the excitation signal with the best test result is selected as the test signal. The phase angle Φ of each point on the surface of the chip under test corresponding to the selected test signal is then used for subsequent processing.

[0077] Step S210: Obtain a three-dimensional image of the surface of the chip under test by scanning the chip under test with the applied test signal using an image scanning device, and analyze the three-dimensional image to obtain the three-dimensional coordinates of each point on the surface of the chip under test.

[0078] Computer equipment can control an image scanning device to scan and analyze the chip under test, and then receive the image from the scanning device to obtain a three-dimensional image of the surface of the chip under test. The received three-dimensional image is analyzed to obtain the three-dimensional coordinates of each point on the surface of the chip under test. This step can be performed after obtaining the phase angle Φ of each point on the surface of the chip under test, or before obtaining the phase angle Φ, or even simultaneously with obtaining the phase angle Φ of each point on the surface of the chip under test; no limitation is made here.

[0079] It is understood that those skilled in the art will know that the function of analyzing three-dimensional images to obtain the three-dimensional coordinates of various points on the surface of the chip under test can also be integrated into an image scanning device. Furthermore, it should be noted that, to ensure the accuracy of the results, the position of the chip under test is kept unchanged during the scanning process to obtain the phase angle and three-dimensional coordinates.

[0080] Step S220: Calculate the three-dimensional coordinates of the failure point in the chip under test based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test.

[0081] After obtaining the phase angle Φ of each point on the surface of the chip under test, and the three-dimensional coordinates of each point on the surface of the chip under test, the three-dimensional coordinates of the failure point in the chip under test can be calculated based on the phase angle and three-dimensional coordinates of each point.

[0082] The specific process may include:

[0083] Assuming the coordinates of the failure point are known, they can be represented as (x0, y0, z0). It should be noted that the coordinate system of the failure point is the same as the coordinate system of the three-dimensional coordinates obtained in the above steps.

[0084] The spatial distance from the failure point Defect(x0,y0,z0) to any point (x,y,z) on the surface is defined as the equivalent distance Zeff, which can be obtained as follows:

[0085]

[0086] Combining the above formula (5), the phase angle

[0087]

[0088] Based on the phase angles and three-dimensional coordinates of each point on the surface of the chip under test, substitute them into the above formula (5) to perform parameter fitting, and the coordinates of the failure point can be obtained. The specific implementation method of parameter fitting can adopt existing parameter fitting methods.

[0089] The aforementioned method for locating failure points involves acquiring a thermal image of the chip under test (TBT) by scanning it with an infrared thermal imaging device, and analyzing the thermal image to obtain the phase angle of each point on the TBT surface. It also involves acquiring a three-dimensional image of the TBT by scanning it with an image scanning device, and analyzing the three-dimensional image to obtain the three-dimensional coordinates of each point on the TBT surface. Finally, it calculates the three-dimensional coordinates of the failure point in the TBT based on the phase angle and three-dimensional coordinates of each point on the TBT surface. By combining the phase angle and three-dimensional coordinates of each point on the TBT surface, this invention achieves spatial positioning. This allows for rapid failure point location without being affected by the chip's geometry, resulting in high positioning accuracy.

[0090] In one embodiment, based on the above embodiments, after performing digital phase-locked signal coherent processing on the thermal imaging image to obtain the corresponding linear average function, the method further includes:

[0091] The temperature amplitude at each point on the surface of the chip under test is calculated based on the sinusoidal function reference signal and the linear average function.

[0092] Calculate the temperature amplitude A image on the surface of the chip under test based on the outputs of two sinusoidal reference signals:

[0093]

[0094] In one embodiment, based on the above embodiments, the step of calculating the three-dimensional coordinates of the failure point in the chip under test according to the phase angle and three-dimensional coordinates of each point on the surface of the chip under test may include:

[0095] Step S221: Based on the amplitude of each point on the surface of the chip under test, the location of the failure point can be determined in the horizontal direction.

[0096] Step S222: Calculate the three-dimensional coordinates of the failure point in the chip under test based on the phase angle of each point on the chip surface and the three-dimensional coordinates of each point in the region.

[0097] As one embodiment, this embodiment can also obtain the temperature amplitude A image obtained above. Based on the obtained temperature amplitude A image, the region where the failure point is located in the horizontal direction can be determined, that is, the region where the failure point is located on the surface of the chip under test can be determined. Then, the three-dimensional coordinates of the failure point can be calculated using the three-dimensional coordinates and phase angles corresponding to each surface point in this region.

[0098] In this embodiment, the temperature amplitude image of each point on the surface of the chip under test is first calculated to determine the region where the failure point is located. Then, the phase angle and three-dimensional coordinates of each point in the region are used to calculate the three-dimensional coordinates of the failure point, which can improve the accuracy of the three-dimensional coordinates of the failure point.

[0099] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0100] Based on the same inventive concept, this application also provides a failure point location device for implementing the failure point location method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more failure point location device embodiments provided below can be found in the limitations of the failure point location method described above, and will not be repeated here.

[0101] In one embodiment, such as Figure 3 As shown, a failure point location device is provided, comprising:

[0102] The phase angle acquisition module 310 is used to acquire a thermal image of the chip under test obtained by scanning the chip under test with an infrared thermal imaging device and applying a test signal, and to analyze the thermal image to obtain the phase angle of each point on the surface of the chip under test.

[0103] The three-dimensional coordinate acquisition module 320 is used to acquire a three-dimensional image of the surface of the chip under test obtained by scanning the chip under test with the applied test signal through an image scanning device, and to analyze the three-dimensional image to obtain the three-dimensional coordinates of each point on the surface of the chip under test.

[0104] The failure point location module 330 is used to calculate the three-dimensional coordinates of the failure point in the chip under test based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test.

[0105] In one embodiment, the test signal includes a first voltage and a second voltage that are orthogonal to each other, and the phase angle acquisition module 310 is further used for:

[0106] The chip under test is scanned using an infrared thermal imaging device to obtain a thermal image of the surface of the chip under test.

[0107] The thermal imaging image is digitally phase-locked signal coherently processed using a sinusoidal function reference signal with the same phase-locked frequency as the test signal to obtain the corresponding linear average function;

[0108] The phase angle of each point on the surface of the chip under test is calculated based on the sinusoidal function reference signal and the linear average function.

[0109] In one embodiment, the failure point location device further includes:

[0110] The temperature amplitude acquisition module (not shown in the figure) is used to calculate the temperature amplitude at each point on the surface of the chip under test based on the sinusoidal function reference signal and the linear average function.

[0111] In one embodiment, the failure point location module 330 is further configured to:

[0112] The location of the failure point can be determined in the horizontal direction by the amplitude of vibration at each point on the surface of the chip under test.

[0113] The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle of each point on the chip surface and the three-dimensional coordinates of each point in the region.

[0114] In one embodiment, the failure point location module 330 is further configured to:

[0115] The three-dimensional coordinates of the failure point in the chip under test are calculated using the following formula:

[0116]

[0117] Where Φ is the phase angle, z effThe equivalent distance from the failure point to each point on the surface of the chip under test is Λ, where Λ is the thermal diffusion length of the material of the chip under test, the three-dimensional coordinates of any point on the surface of the chip under test are (x, y, z), and the three-dimensional coordinates of the failure point are (x0, y0, z0).

[0118] In one embodiment, the failure point location module 330 is further configured to:

[0119] The phase angle and three-dimensional coordinates of each point on the surface of the chip under test are substituted into the formula for parameter fitting to obtain the three-dimensional coordinates of the failure point in the chip under test.

[0120] Each module in the aforementioned failure point location device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0121] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 4 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computational and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage medium. The database can store the phase angles of various points on the surface of the chip under test, the three-dimensional coordinates of these points, as well as thermal images and three-dimensional images of the chip under test. The network interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements a method for locating the failure point.

[0122] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0123] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0124] A thermal imaging image of the surface of the chip under test is obtained by scanning the chip under test with an infrared thermal imaging device and the thermal imaging image is analyzed to obtain the phase angle of each point on the surface of the chip under test.

[0125] A three-dimensional image of the surface of the chip under test is obtained by scanning the chip under test with the applied test signal using an image scanning device, and the three-dimensional image is analyzed to obtain the three-dimensional coordinates of each point on the surface of the chip under test.

[0126] The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test.

[0127] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0128] The test signal includes a first voltage and a second voltage that are orthogonal to each other. The process involves scanning the chip under test using an infrared thermal imaging device to obtain a thermal image of the chip, and analyzing the thermal image to obtain the phase angle of each point on the surface of the chip under test, including:

[0129] The chip under test is scanned using an infrared thermal imaging device to obtain a thermal image of the chip under test.

[0130] The thermal imaging image is digitally phase-locked signal coherently processed using a sinusoidal function reference signal with the same phase-locked frequency as the test signal to obtain the corresponding linear average function;

[0131] The phase angle of each point on the surface of the chip under test is calculated based on the sinusoidal function reference signal and the linear average function.

[0132] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0133] After performing digital phase-locked signal coherent processing on the thermal imaging image to obtain the corresponding linear averaging function, the method further includes:

[0134] The temperature amplitude at each point on the surface of the chip under test is calculated based on the sinusoidal function reference signal and the linear average function.

[0135] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0136] The location of the failure point can be determined in the horizontal direction by the amplitude of vibration at each point on the surface of the chip under test.

[0137] The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle of each point on the chip surface and the three-dimensional coordinates of each point in the region.

[0138] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0139] The three-dimensional coordinates of the failure point in the chip under test are calculated using the following formula:

[0140]

[0141] Where Φ is the phase angle, z eff The equivalent distance from the failure point to each point on the surface of the chip under test is Λ, where Λ is the thermal diffusion length of the chip under test. The three-dimensional coordinates of any point on the surface of the chip under test are (x, y, z), and the three-dimensional coordinates of the failure point are (x0, y0, z0).

[0142] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0143] The phase angle and three-dimensional coordinates of each point on the surface of the chip under test are substituted into the formula for parameter fitting to obtain the three-dimensional coordinates of the failure point in the chip under test.

[0144] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0145] A thermal imaging image of the surface of the chip under test is obtained by scanning the chip under test with an infrared thermal imaging device and the thermal imaging image is analyzed to obtain the phase angle of each point on the surface of the chip under test.

[0146] A three-dimensional image of the surface of the chip under test is obtained by scanning the chip under test with the applied test signal using an image scanning device, and the three-dimensional image is analyzed to obtain the three-dimensional coordinates of each point on the surface of the chip under test.

[0147] The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test.

[0148] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0149] The test signal includes a first voltage and a second voltage that are orthogonal to each other. The process involves scanning the chip under test using an infrared thermal imaging device to obtain a thermal image of the chip, and analyzing the thermal image to obtain the phase angle of each point on the surface of the chip under test, including:

[0150] The chip under test is scanned using an infrared thermal imaging device to obtain a thermal image of the surface of the chip under test.

[0151] The thermal imaging image is digitally phase-locked signal coherently processed using a sinusoidal function reference signal with the same phase-locked frequency as the test signal to obtain the corresponding linear average function;

[0152] The phase angle of each point on the surface of the chip under test is calculated based on the sinusoidal function reference signal and the linear average function.

[0153] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0154] The temperature amplitude at each point on the surface of the chip under test is calculated based on the sinusoidal function reference signal and the linear average function.

[0155] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0156] The location of the failure point can be determined in the horizontal direction by the amplitude of vibration at each point on the surface of the chip under test.

[0157] The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle of each point on the chip surface and the three-dimensional coordinates of each point in the region.

[0158] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0159] The three-dimensional coordinates of the failure point in the chip under test are calculated using the following formula:

[0160]

[0161] Where Φ is the phase angle, z eff The equivalent distance from the failure point to each point on the surface of the chip under test is Λ, where Λ is the thermal diffusion length of the chip under test. The three-dimensional coordinates of any point on the surface of the chip under test are (x, y, z), and the three-dimensional coordinates of the failure point are (x0, y0, z0).

[0162] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0163] The phase angle and three-dimensional coordinates of each point on the surface of the chip under test are substituted into the formula for parameter fitting to obtain the three-dimensional coordinates of the failure point in the chip under test.

[0164] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0165] A thermal image of the chip under test is obtained by scanning the chip under test with an infrared thermal imaging device and the test signal is applied. The thermal image is then analyzed to obtain the phase angle of each point on the surface of the chip under test.

[0166] A three-dimensional image of the surface of the chip under test is obtained by scanning the chip under test with the applied test signal using an image scanning device, and the three-dimensional image is analyzed to obtain the three-dimensional coordinates of each point on the surface of the chip under test.

[0167] The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test.

[0168] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0169] The chip under test is scanned by an infrared thermal imaging device to obtain a thermal image of the surface of the chip under test.

[0170] The thermal imaging image is digitally phase-locked signal coherently processed using a sinusoidal function reference signal with the same phase-locked frequency as the test signal to obtain the corresponding linear average function;

[0171] The phase angle of each point on the surface of the chip under test is calculated based on the sinusoidal function reference signal and the linear average function.

[0172] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0173] The temperature amplitude at each point on the surface of the chip under test is calculated based on the sinusoidal function reference signal and the linear average function.

[0174] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0175] The location of the failure point can be determined in the horizontal direction by the amplitude of vibration at each point on the surface of the chip under test.

[0176] The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle of each point on the chip surface and the three-dimensional coordinates of each point in the region.

[0177] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0178] The three-dimensional coordinates of the failure point in the chip under test are calculated using the following formula:

[0179]

[0180] Where Φ is the phase angle, z eff The equivalent distance from the failure point to each point on the surface of the chip under test is Λ, where Λ is the thermal diffusion length of the chip under test. The three-dimensional coordinates of any point on the surface of the chip under test are (x, y, z), and the three-dimensional coordinates of the failure point are (x0, y0, z0).

[0181] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0182] The phase angle and three-dimensional coordinates of each point on the surface of the chip under test are substituted into the formula for parameter fitting to obtain the three-dimensional coordinates of the failure point in the chip under test.

[0183] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0184] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0185] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for locating a failure point, characterized in that, The method includes: A thermal imaging image of the surface of the chip under test is obtained by scanning the chip under test with an infrared thermal imaging device and the thermal imaging image is analyzed to obtain the phase angle of each point on the surface of the chip under test. A three-dimensional image of the surface of the chip under test is obtained by scanning the chip under test with the applied test signal using an image scanning device, and the three-dimensional image is analyzed to obtain the three-dimensional coordinates of each point on the surface of the chip under test. The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test; wherein, the three-dimensional coordinates of the failure point in the chip under test are calculated using the following formula: in, The phase angle, The distance from the failure point to each point on the surface of the chip under test. The thermal diffusion length of the material of the chip under test is given, the three-dimensional coordinates of any point on the surface of the chip under test are (x, y, z), and the three-dimensional coordinates of the failure point are (x, y, z). , , ).

2. The method according to claim 1, characterized in that, The step of acquiring a thermal image of the chip under test by scanning it with an infrared thermal imaging device to obtain a thermal image of the surface of the chip under test, and analyzing the thermal image to obtain the phase angle of each point on the surface of the chip under test, includes: The chip under test is scanned by an infrared thermal imaging device to obtain a thermal image of the surface of the chip under test. The thermal imaging image is digitally phase-locked signal coherently processed using a sinusoidal function reference signal with the same phase-locked frequency as the test signal to obtain the corresponding linear average function; The phase angle of each point on the surface of the chip under test is calculated based on the sinusoidal function reference signal and the linear average function.

3. The method according to claim 2, characterized in that, After performing digital phase-locked signal coherent processing on the thermal imaging image using a sinusoidal function reference signal with the same phase-locked frequency as the test signal to obtain the corresponding linear average function, the process further includes: The temperature amplitude at each point on the surface of the chip under test is calculated based on the sinusoidal function reference signal and the linear average function.

4. The method according to claim 3, characterized in that, The step of calculating the three-dimensional coordinates of the failure point in the chip under test based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test includes: The location of the failure point can be determined in the horizontal direction by measuring the temperature amplitude at various points on the surface of the chip under test. The three-dimensional coordinates of the failure point in the chip under test are calculated based on the phase angle of each point on the chip surface and the three-dimensional coordinates of each point in the region.

5. The method according to claim 1, characterized in that, The step of calculating the three-dimensional coordinates of the failure point in the chip under test based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test includes: The phase angle and three-dimensional coordinates of each point on the surface of the chip under test are substituted into the formula for parameter fitting to obtain the three-dimensional coordinates of the failure point in the chip under test.

6. A device for locating failure points, characterized in that, The device includes: The phase angle acquisition module is used to acquire thermal imaging images of the surface of the chip under test by scanning the chip under test with an infrared thermal imaging device and applying a test signal, and to analyze the thermal imaging images to obtain the phase angle of each point on the surface of the chip under test. The three-dimensional coordinate acquisition module is used to acquire a three-dimensional image of the surface of the chip under test obtained by scanning the chip under test with the applied test signal through an image scanning device, and to analyze the three-dimensional image to obtain the three-dimensional coordinates of each point on the surface of the chip under test. The failure point location module is used to calculate the three-dimensional coordinates of the failure point in the chip under test based on the phase angle and three-dimensional coordinates of each point on the surface of the chip under test; wherein, the three-dimensional coordinates of the failure point in the chip under test are calculated using the following formula: in, The phase angle, The distance from the failure point to each point on the surface of the chip under test. The thermal diffusion length of the material of the chip under test is given, the three-dimensional coordinates of any point on the surface of the chip under test are (x, y, z), and the three-dimensional coordinates of the failure point are (x, y, z). , , ).

7. The apparatus according to claim 6, characterized in that, The phase angle acquisition module is also used for: The chip under test is scanned by an infrared thermal imaging device to obtain a thermal image of the surface of the chip under test. The thermal imaging image is digitally phase-locked signal coherently processed using a sinusoidal function reference signal with the same phase-locked frequency as the test signal to obtain the corresponding linear average function; The phase angle of each point on the surface of the chip under test is calculated based on the sinusoidal function reference signal and the linear average function.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

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