An insulated gate bipolar transistor and a method of manufacturing the same

Abstract

The application provides an insulated gate bipolar transistor and a preparation method thereof. The preparation method comprises the following steps: providing an insulated gate bipolar transistor wafer to be back ion implanted and front end formed with a passivation layer; performing ion implantation on a back surface layer of the wafer to form a second conductive type doping layer; placing the wafer in a cleaning tank containing a treatment reagent to be treated for a preset time; placing the treated wafer on a wafer boat and putting it into a furnace tube to activate the second conductive type doping layer by the furnace tube, and at least two adjacent wafers in the wafer boat are spaced apart by 2 separation teeth, and a plurality of separation teeth are arranged in the same direction and are arranged on two opposite side walls of the wafer boat; and forming a back electrode layer on the back surface of the wafer after activation. The application reduces the on-state voltage drop of the device by treating the wafer with the treatment reagent for a preset time after forming the second conductive type doping layer and increasing the distance between the two adjacent wafers during the furnace tube activation.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to an insulated gate bipolar transistor and its fabrication method. Background Technology

[0002] Power semiconductor devices, as core components in energy control, serve as a bridge for converting high voltage to low voltage. Insulated-gate bipolar transistors (IGBTs), as a type of gate-controlled bipolar device, possess advantages such as low conduction loss, fast switching speed, high input impedance, and strong current capability, making them increasingly important in the energy conversion and control market. To improve the device's withstand voltage and reduce its internal resistance, a lower forward voltage drop (V0.05) is required. dson Currently, non-punch-through insulated-gate bipolar transistors (NPT Planar IGBTs) reduce VL by adjusting the resistivity of their materials. dson However, the device breakdown voltage will also decrease. Similarly, by adjusting the back-side P-type implantation concentration and activation temperature, the contact resistance of the back electrode can be reduced, thereby lowering the voltage. dson However, switching losses will also increase.

[0003] Therefore, there is an urgent need to find a method for fabricating insulated gate bipolar transistors (IGBTs) that reduces the forward conduction voltage drop. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an insulated gate bipolar transistor and its fabrication method, which solves the problem of high forward voltage drop caused by high contact resistance of the back electrode layer in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating an insulated gate bipolar transistor, comprising the following steps:

[0006] An insulated gate bipolar transistor wafer is provided, which is to be back-side ion implanted and has a passivation layer formed at the front end. The conductivity type of the surface layer on the back side of the wafer is a first conductivity type.

[0007] Ion implantation is performed on the back surface of the wafer to form a doped layer of a second conductivity type;

[0008] The wafer is placed in a cleaning tank containing processing reagents and processed for a preset time;

[0009] The processed wafers are loaded into a crystal boat and placed in a furnace tube to activate the second conductivity type doped layer in the furnace tube. Two adjacent wafers in the crystal boat are spaced apart by at least two spacer teeth, and a plurality of spacer teeth are arranged at intervals along the same direction on two opposite sidewalls of the crystal boat.

[0010] A back electrode layer is formed on the back side of the activated wafer.

[0011] Optionally, before ion implantation of the wafer, the process further includes cleaning the wafer with a cleaning agent.

[0012] Optionally, the treatment reagent includes a dilute hydrofluoric acid solution.

[0013] Optionally, the concentration of the dilute hydrofluoric acid ranges from 0.5% to 2%.

[0014] Optionally, the preset time is not less than 1 minute.

[0015] Optionally, the wafer is cleaned using the processing reagent at room temperature.

[0016] Optionally, after the treatment with the processing reagent and before the back-side furnace tube is activated, a step of re-cleaning the wafer is included to remove any residual processing reagent from the wafer.

[0017] Optionally, during the back-side furnace tube activation process, the back side of the wafer is placed facing the same direction.

[0018] Optionally, the time range for activating the second conductivity type doped layer with the back furnace tube is 30 min to 50 min, and the temperature range for activating the second conductivity type doped layer with the back furnace tube is 300℃ to 400℃.

[0019] The present invention also provides an insulated gate bipolar transistor, which is prepared by the insulated gate bipolar transistor preparation method described above.

[0020] As described above, the insulated gate bipolar transistor and its fabrication method of the present invention, after forming the second conductivity type doped layer, treats the wafer with the processing reagent for a preset time. The processing reagent removes the dense layer generated on the back side of the wafer during the blue film removal process, thereby reducing the influence of the dense layer on the contact resistance between the back electrode layer and the second conductivity type doped layer, lowering the contact resistance between the back electrode layer and the second conductivity type doped layer, and reducing the on-resistance of the device from a process perspective, thereby reducing the on-voltage drop of the device. The treated wafer is placed in the wafer boat, and the wafer boat is placed in a furnace tube for activation of the second conductivity type doped layer. At least two separator teeth are spaced between adjacent wafers to increase the distance between adjacent wafers, reducing the influence of the vaporized passivation layer on the back side of the wafer from an activation process perspective, reducing the amount of vaporized passivation layer adhering to the back side of the wafer, lowering the contact resistance between the back electrode layer and the second conductivity type doped layer, further reducing the on-resistance of the device from a process perspective, and thereby further reducing the on-voltage drop of the device. This method has high industrial application value. Attached Figure Description

[0021] Figure 1 The diagram shows a process flow diagram of the fabrication method of the insulated gate bipolar transistor of the present invention.

[0022] Figure 2 The diagram shows a planar structure of a wafer used in the fabrication method of the insulated gate bipolar transistor of the present invention.

[0023] Figure 3 The diagram shows a planar structure of a crystal boat used in the fabrication method of the insulated gate bipolar transistor of the present invention.

[0024] Figure 4 The graph shows the on-state voltage drop of the insulated gate bipolar transistor of the present invention on wafers treated with and untreated under different spacing conditions.

[0025] Figure 5 The graph shows the on-state voltage drop of the insulated gate bipolar transistor of the present invention on wafers treated with and untreated with a processing reagent under conditions of two spaced-out teeth.

[0026] Explanation of icon numbers

[0027] 1. Wafer

[0028] 2 Crystal Boat

[0029] 21. Separating teeth Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0032] Example 1

[0033] This embodiment provides a method for fabricating an insulated gate bipolar transistor, such as... Figure 1 The diagram shown is a process flow chart of the fabrication method of the insulated gate bipolar transistor, including the following steps:

[0034] S1: Provide an insulated gate bipolar transistor wafer to be back-side ion implanted and with a passivation layer formed at the front end, wherein the conductivity type of the surface layer on the back side of the wafer is a first conductivity type;

[0035] S2: Ion implantation is performed on the back surface of the wafer to form a doped layer of a second conductivity type;

[0036] S3: Place the wafer in a cleaning tank containing processing reagents and process for a preset time;

[0037] S4: The processed wafer is loaded into a crystal boat and placed into a furnace tube to activate the second conductivity type doped layer in the furnace tube. Two adjacent wafers in the crystal boat are spaced apart by at least two spacer teeth, and a plurality of spacer teeth are arranged at intervals along the same direction on two opposite sidewalls of the crystal boat.

[0038] S5: A back electrode layer is formed on the back side of the activated wafer.

[0039] Please see Figure 2 Perform steps S1 and S2: Provide an insulated gate bipolar transistor wafer 1 to be back-side ion implanted and with a passivation layer formed at the front end, wherein the conductivity type of the surface layer on the back side of the wafer 1 is a first conductivity type; perform ion implantation on the surface layer on the back side of the wafer 1 to form a doped layer of a second conductivity type.

[0040] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0041] Specifically, such as Figure 2 The diagram shown is a planar structural schematic of wafer 1. The material of wafer 1 includes silicon, germanium, silicon carbide, or other suitable semiconductor materials. In this embodiment, silicon is used as wafer 1.

[0042] Specifically, while ensuring device performance, the thickness of wafer 1 can be selected according to actual conditions and is not limited here; the doping concentration of the back surface of wafer 1 can be selected according to actual conditions and is not limited here.

[0043] Specifically, the passivation layer is made of polyimide or other suitable materials. In this embodiment, a polyimide layer is used as the passivation layer on the front side of the device.

[0044] Specifically, while ensuring device performance, the thickness of the passivation layer can be selected according to the actual situation, and is not limited here.

[0045] As an example, before performing ion implantation on the wafer 1, the method further includes a step of cleaning the wafer 1 with a cleaning agent.

[0046] Specifically, during the front-end process of the device, a blue film needs to be applied to the back side of the wafer 1 to prevent the etching process that forms the front-end structure of the device from damaging the back side of the wafer 1. After the front-end process of the device is completed, when performing the back-end process of the device, the blue film on the back side of the wafer 1 needs to be removed. Since blue film is easily left on the back side of the wafer 1 after removing the blue film, the wafer 1 needs to be cleaned with the cleaning reagent after removing the blue film to remove the blue film residue on the back side of the wafer 1.

[0047] Specifically, the process of cleaning the wafer 1 to remove blue film residue using the cleaning reagent needs to be carried out at a temperature of 40℃ to 60℃. While removing the blue film residue, the wafer 1 is prone to react with the cleaning reagent at this temperature, resulting in the formation of a dense layer on the back surface of the wafer 1.

[0048] Specifically, while ensuring device performance, the thickness of the second conductivity type doped layer can be set according to the actual situation, and is not limited here; the doping concentration of the second conductivity type doped layer can be selected according to the actual situation, and is not limited here.

[0049] Please see again Figure 3 The following steps are performed: Step S3, Step S4, and Step S5: The wafer 1 is placed in a cleaning tank containing a processing reagent and processed for a preset time; The processed wafer 1 is loaded into a crystal boat 2 and placed in a furnace tube to activate the second conductivity type doped layer in the furnace tube, and two adjacent wafers 1 located in the crystal boat 2 are spaced apart by at least two separating teeth 21, and a plurality of separating teeth 21 are arranged at intervals along the same direction on two opposite sidewalls of the crystal boat 2; A back electrode layer is formed on the back side of the activated wafer 1.

[0050] As an example, the treatment reagent includes a dilute hydrofluoric acid solution, but other suitable reagents may also be used.

[0051] Specifically, the treatment reagent is used to remove the dense layer generated when the blue film residue on the back side of the wafer 1 is removed, so as to eliminate the influence of the dense layer on the contact resistance between the back electrode layer and the second conductivity type doped layer.

[0052] As an example, the concentration range of the dilute hydrofluoric acid solution is 0.5% to 2%. In this embodiment, a 1% concentration of hydrofluoric acid is used as the treatment reagent.

[0053] Specifically, since dilute hydrofluoric acid solution is difficult to react with the wafer 1, using dilute hydrofluoric acid solution as the processing reagent to remove the dense layer facilitates the removal of the dense layer on the back side of the wafer while avoiding corrosion of the back side of the wafer 1 by the processing reagent, thus ensuring the performance of the device.

[0054] As an example, the preset time is not less than 1 minute, that is, the time for which the wafer 1 is placed in the processing reagent is not less than 1 minute.

[0055] Specifically, the treatment reagent is a dilute hydrofluoric acid solution. The wafer 1 is placed in the treatment reagent for no less than 1 minute so that the dense layer on the back side of the wafer 1 can fully react with the treatment reagent and completely remove the dense layer on the back side of the wafer 1. This is to avoid the dense layer affecting the contact resistance between the back electrode layer and the second conductivity type doped layer, thereby reducing the on-resistance of the insulated gate bipolar transistor from the process perspective.

[0056] As an example, the wafer 1 is cleaned using the treatment reagent at room temperature, where room temperature refers to 20°C to 30°C. In this embodiment, since the dense layer on the back side of the wafer 1 can react directly with hydrofluoric acid at room temperature, and dilute hydrofluoric acid hardly reacts with the wafer 1 at room temperature (the reaction rate is very small, and its impact on the wafer 1 is negligible), using dilute hydrofluoric acid solution as the treatment reagent can avoid the heating process during treatment and reduce costs.

[0057] Specifically, without affecting device performance, and when the dense layer on the back side of wafer 1 is completely removed, the processing time can be appropriately shortened when the concentration of the processing reagent is high. For example, when the back side of wafer 1 is treated with the processing reagent at a concentration of 3%, the processing time can be adjusted to 45 seconds.

[0058] As an example, after the treatment with the processing reagent and before the back furnace tube is activated, a step of cleaning the wafer 1 again is included to remove the processing reagent remaining on the wafer 1.

[0059] Specifically, the reagent used to clean the wafer 1 again can be distilled water or other suitable reagents.

[0060] Specifically, activating the second conductivity type doped layer includes the following steps: loading the cleaned wafer 1 into the crystal boat 2, with at least two spacer teeth 21 between adjacent wafers 1 loaded in the crystal boat 2; placing the loaded crystal boat 2 into the designated position of the activation furnace tube, setting the heating parameters of the furnace tube, and starting the furnace tube to activate the second conductivity type doped layer.

[0061] Specifically, such as Figure 3 The diagram shown is a structural schematic of the crystal boat 2. The size, spacing, and number of the separating teeth 21 in the crystal boat 2 that holds the wafer 1 can be set according to actual conditions, and are not limited here.

[0062] Specifically, the thickness of the separating teeth 21 along the arrangement direction can be selected according to the actual situation, and this is no longer limited.

[0063] As an example, during the back-side furnace tube activation process, the back sides of the wafer 1 are placed facing the same direction, that is, the front and back sides of two adjacent wafers 1 are placed opposite each other, so as to facilitate the mechanized loading of the wafers 1 into the crystal boat 2.

[0064] Specifically, the method of placing the wafer in the crystal boat 2 can be mechanical loading or manual loading. When mechanical loading is performed, control parameters need to be set so that when the wafer 1 is transferred, there is at least two spacer teeth 21 between two adjacent wafers 1.

[0065] As an example, the time range for back-side furnace tube activation of the second conductivity type doped layer is 30 min to 50 min, and the temperature range for back-side furnace tube activation of the second conductivity type doped layer is 300℃ to 400℃.

[0066] Specifically, due to the high activation temperature and long activation time during the back-side furnace activation process of the second conductivity type doped layer, a small amount of the passivation layer on the front side of the wafer 1 will vaporize at this temperature. The vaporized passivation layer diffuses to the back side of the wafer 1 and adheres to the back side of the wafer 1, resulting in poor dispersion of the contact resistance between the second conductivity type doped layer and the back electrode layer, which in turn leads to an increase in the forward conduction voltage drop of the device.

[0067] Specifically, by increasing the distance between two adjacent wafers 1 in the crystal boat 2, the probability of the vaporized passivation layer diffusing to the back side of the wafer 1 is reduced, thereby reducing the influence of the passivation layer on the contact resistance between the back side of the wafer and the back electrode layer during the activation of the second conductivity type doped layer, and avoiding the increase of the forward conduction voltage drop of the device.

[0068] Specifically, when the wafer 1 is manually loaded into the boat 2, the same sides of two adjacent wafers 1 can be placed face to face. Due to the obstruction of the wafer 1, the probability of the passivation layer diffusing to the back side of the wafer 1 is reduced, thereby reducing the impact of the passivation layer covering the front side of the wafer 1 on the back side of the wafer 1 during the activation of the second conductivity type doped layer.

[0069] Specifically, the method for forming the back electrode layer includes one of sputtering, evaporation, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal compound vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic vapor deposition (AVD), or atomic layer deposition (ALD), or other suitable methods.

[0070] Specifically, the material of the back electrode layer includes one of Ti (titanium), TiN (titanium nitride), Ag (silver), Au (gold), Cu (copper), Al (aluminum), and W (tungsten), or other suitable conductive materials.

[0071] Specifically, while ensuring device performance, the thickness of the back electrode layer can be selected according to the actual situation, and is not limited here.

[0072] Specifically, after forming the back electrode layer, the process further includes forming a back electrode passivation layer on the back side of the back electrode layer.

[0073] Specifically, after forming the back electrode passivation layer, the wafer 1 is further diced to obtain a single insulated gate bipolar transistor chip.

[0074] The fabrication method of the insulated gate bipolar transistor in this embodiment involves forming a second conductivity type dopant on the surface layer of the back side of wafer 1, and then placing wafer 1 in the processing reagent at room temperature for a preset time. This ensures that the processing reagent removes the dense layer on the back side of wafer 1, which is generated during the removal of residual blue film. The processing reagent has no effect on wafer 1 at room temperature, thus ensuring device performance and avoiding the increase in contact resistance between the second conductivity type dopant layer and the back electrode layer caused by the dense layer, thereby eliminating the problems caused by the front-end process. The increase in the forward conduction resistance of the device reduces the on-resistance of the device from a process perspective. During the activation of the second conductivity type doped layer, the wafer 1 is loaded into the crystal boat 2 with at least two of the separator teeth 21 spaced apart, and then the second conductivity type doped layer is activated. This reduces the impact of the vaporization of the passivation layer on the front side of the wafer 1 during the activation of the second conductivity type doped layer, which affects the contact resistance between the second conductivity type doped layer and the back electrode layer, thereby further reducing the on-state voltage drop of the device from a process perspective.

[0075] Example 2

[0076] This embodiment provides an insulated gate bipolar transistor (IGBT), which is prepared using the IGBT preparation method described in Embodiment 1.

[0077] Specifically, the second conductivity type doped layer on the back surface of the semiconductor structure of the insulated gate bipolar transistor is in electrical contact with the back electrode layer. Since the back surface of the semiconductor layer is treated with the processing reagent before the back electrode layer is formed, the contact resistance between the back surface of the semiconductor layer and the back electrode layer is reduced, thereby reducing the on-state voltage drop of the device. Here, the semiconductor structure refers to the portion of wafer 1 in Embodiment 1 after dicing, and does not include the back electrode layer.

[0078] Specifically, since the passivation layer vaporizes in small amounts and diffuses slowly at the activation temperature of the second conductivity type doped layer, the concentration of vaporized passivation layer gradually decreases as the distance from the passivation layer increases. During the activation of the second conductivity type doped layer, the distance between the back side and the front side of the semiconductor structure is increased, which can reduce the amount of passivation layer attached to the back side of the semiconductor structure, thereby reducing the impact on the contact resistance of the back side of the semiconductor structure, further reducing the contact resistance between the back electrode layer and the back side of the semiconductor layer, and reducing the on-state voltage drop of the device from a process perspective.

[0079] Specifically, when the distance between two adjacent wafers 1 is large, the concentration of the passivation layer at a distance from wafer 1 is low, and the amount of passivation layer attached to the back of wafer 1 does not change much. Therefore, as the distance between two adjacent wafers 1 is gradually increased, the forward voltage drop of the insulated gate bipolar transistor does not change much.

[0080] Specifically, such as Figure 4 and Figure 5 The figures show the on-state voltage drop statistics for multiple batches of the insulated gate bipolar transistor (IGBT) under several different processes, and the on-state voltage drop statistics for each batch of the IGBT between two adjacent wafers 1 separated by two separator teeth 21. In this experiment, the size and thickness of the separator teeth 21 in the wafer boat 2 are the same, meaning the specifications of the wafer boat 2 are the same, and the size of the wafers 1 tested are also the same. The online experiment shows that before the back furnace tube activation, the processing reagent was not performed on the batches. During back furnace tube activation, the on-state voltage drop of adjacent wafers... The two wafers 1 are spaced apart by one of the separator teeth 21. The forward conduction voltage drop of the insulated gate bipolar transistor is significantly higher than that of the wafers 1. The distance between two adjacent wafers 1 is not less than two of the separator teeth 21. The forward conduction voltage drop of the insulated gate bipolar transistor is low and does not change much. The two adjacent wafers 1 are spaced apart by two of the separator teeth 21 and are treated with the processing reagent. The forward conduction voltage drop of the insulated gate bipolar transistor fluctuates around 1.9V (the mark line between the upper and lower ends of each batch in the figure is the average conduction voltage drop of this batch).

[0081] The insulated gate bipolar transistor of this embodiment is fabricated using the insulated gate bipolar transistor fabrication method described in Embodiment 1. This process eliminates the influence of the passivation layer and the dense layer on the back side of wafer 1, reduces the contact resistance between the back electrode layer and the back side of the semiconductor structure, thereby reducing the on-resistance of the planar insulated gate bipolar transistor and consequently reducing the on-state voltage drop of the device.

[0082] In summary, the insulated-gate bipolar transistor and its fabrication method of the present invention, after forming a second conductivity type doped layer on the back side of the wafer, employs a processing reagent for a predetermined time to remove the dense layer generated during the removal of the blue film on the back side of the wafer. This prevents the dense layer from affecting the contact resistance between the back electrode layer and the second conductivity type doped layer, thereby reducing the on-resistance and on-state voltage drop of the device. Furthermore, the second conductivity type doped layer undergoes furnace tube activation. By appropriately increasing the distance between two adjacent wafers in the wafer boat, the amount of passivation layer vaporized during the furnace tube activation process of the second conductivity type doped layer and adhering to the back side of the wafer is reduced, thus reducing the impact of the passivation layer on the back side of the wafer. This further reduces the contact resistance between the back electrode layer and the second conductivity type doped layer, thereby reducing the on-resistance and on-state voltage drop of the device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an insulated gate bipolar transistor, characterized in that, Includes the following steps: An insulated gate bipolar transistor wafer is provided, which is to be back-side ion implanted and has a passivation layer formed at the front end. The conductivity type of the surface layer on the back side of the wafer is a first conductivity type. Ion implantation is performed on the back surface of the wafer to form a doped layer of a second conductivity type; The wafer is placed in a cleaning tank containing a processing reagent for a preset time. The processing reagent includes a dilute hydrofluoric acid solution with a concentration range of 0.5% to 2%. The processed wafers are loaded into a crystal boat and placed in a furnace tube to activate the second conductivity type doped layer in the furnace tube. Two adjacent wafers in the crystal boat are spaced apart by at least two spacer teeth, and a plurality of spacer teeth are arranged at intervals along the same direction on two opposite sidewalls of the crystal boat. A back electrode layer is formed on the back side of the activated wafer.

2. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that: Before ion implantation of the wafer, the process further includes a step of cleaning the wafer with a cleaning reagent.

3. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that: The preset time is no less than 1 minute.

4. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that: The wafer is cleaned using the aforementioned treatment reagent at room temperature.

5. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that: After the treatment with the processing reagent and before the back-side furnace tube is activated, the wafer is further cleaned to remove any residual processing reagent from the wafer.

6. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that: During the back-side furnace tube activation process, the back side of the wafer is placed facing the same direction.

7. The method for fabricating an insulated gate bipolar transistor according to claim 1, characterized in that: The activation time for the second conductivity type doped layer via the back furnace tube is 30 min to 50 min, and the activation temperature for the second conductivity type doped layer via the back furnace tube is 300℃ to 400℃.

8. An insulated-gate bipolar transistor, characterized in that, The insulated gate bipolar transistor is fabricated using the method for fabricating an insulated gate bipolar transistor as described in any one of claims 1 to 7.

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