Layer structure for direct intermetallic bonding at low temperatures in microelectronics

Abstract

The present disclosure relates to layer structures for direct intermetallic bonding at low temperatures in microelectronics. Layer structures for direct intermetallic bonding at low temperatures and shorter anneal durations in microelectronics are provided. Example bonding interface structures enable direct intermetallic bonding of interconnects at low anneal temperatures of 150 °C or below 150 °C and at lower energy budgets. Example structures provide a precise metal recess distance for bonded conductive pads and vias that can be achieved in high volume manufacturing. Example structures provide a vertical stack of conductive layers under the bonding interface that are designed in geometry and thermal expansion characteristics to vertically expand the stack within a precise recess distance at lower temperatures to enable direct intermetallic bonding. Further enhancements such as surface nano-texturing and copper grain selection can further facilitate direct intermetallic bonding at reduced anneal temperatures and shorter anneal durations.

Description

[0001] This application is a divisional application of the invention patent application with international application number PCT / US2019 / 047513, international application date August 21, 2019, entry into the Chinese national phase date April 26, 2021, Chinese national application number 201980070918.4, and invention title "Layer structure for direct intermetallic bonding at low temperature in microelectronics".

[0002] Cross-reference to related applications

[0003] This application claims priority to U.S. Nonprovisional Patent Application No. 16 / 218,769, filed December 13, 2018, and U.S. Provisional Patent Application No. 62 / 725,801, filed August 31, 2018, entitled “LAYER STRUCTURES FOR MAKING DIRECT METAL-TO-METALBONDS AT LOW TEMPERATURES IN MICROELECTRONICS,” the entire disclosure of which is incorporated herein by reference. Background Technology

[0004] Electrical connections at bonding interfaces have become crucial in microelectronics because the density of transistors that can be arranged in a given two-dimensional area has doubled every 18 to 24 months over the past few decades. Conventional flip-chip connectors between semiconductor dies and circuit boards provide 45 contact bump connections per square millimeter (sq.mm), with an average bonding pitch of 180 micrometers (μm) per connection. Conventional micropillar connectors improve upon conventional flip-chip connectors, providing 625 pillar connections per square millimeter, with an average bonding pitch of 40 μm per connection. Bond pad width can be considered as the size of the conductive pads to be bonded, while pitch refers to the distance between connections. A bonding pitch of 1 μm is required for 1,000,000 connections per square millimeter; for example, the pad size might be approximately 0.5 μm. For wafer-to-die or die-to-die bonding including electrical interconnects, direct bonding technologies, such as direct metal-to-metal bonding (e.g., "direct bonded interconnects"), are also relevant. Direct hybrid bonding can provide 100,000 to 1,000,000 connections per square millimeter, with an average spacing of 1 μm to 40 μm between each connection (Invensas Inc., a subsidiary of Xperi Corp., San Jose, California). Higher connection densities are also possible for connections with a spacing of less than 1 μm.

[0005] Direct hybrid bonding processes (such as) Direct hybrid bonding (CMP) presupposes an ultraflat bonding surface. Therefore, high-density connections achieved through such direct bonding rely on various chemical mechanical planarization (CMP) processes to planarize the surfaces to be bonded to within tens of thousands of micrometers (tens of nanometers) on a large surface. Various CMP processes can achieve depth-of-field flatness sufficient for photolithography or 22-nanometer node technologies.

[0006] To achieve such exceptionally fine 3D electrical interconnects at ultra-high densities, fine-tuning of the alignment and bonding processes is also necessary. The alignment and dielectric (non-metallic) bonding portions of the direct hybrid bonding process can be performed at room temperature. When the prepared surfaces are purchased together, the dielectric portions (e.g., silicon oxide) of the bonding surfaces spontaneously form interoxide bonds. However, metal pads or vias confined within the dielectric material are slightly recessed from the dielectric surface constituting the horizontal bonding interface, ensuring that the metal pads do not impede bonding of the dielectric surfaces when they come into contact with each other.

[0007] The conventional annealing stage of the direct hybrid bonding process is performed at elevated temperatures. At these higher annealing temperatures, the vertical expansion of the metal pads or vias is greater than that of the surrounding dielectric material due to the difference in the coefficients of thermal expansion (CTE) between the metal and the dielectric. If the recess is shallow enough, the metal vias or pads on each side of the bonded surfaces will expand to bridge the small gap between the two metal surfaces and form physical contact with each other under certain self-expansion conditions. At these higher annealing temperatures, the interoxide bonding of the dielectric surrounding the metal pads is further enhanced, allowing the metal pads to expand and permanently bond with each other. Bonding between metal pads begins when copper atoms at each surface (e.g., for copper pads) begin to form mutual metallic bonds with other copper atoms on the other side of the interface. In this way, no solder or other binder is used in the direct hybrid bonding process for electrical interconnects.

[0008] However, the temperatures used for direct hybrid bonding in conventional annealing steps can impose thermal stress on increasingly smaller semiconductor components used in microelectronics. While these annealing temperatures can be lowered, thermal expansion is limited at lower temperatures, and the placement of copper pads requires very precise control over the recess distance between the metal pads and the bonding interface relative to room temperature—a difficult feat to achieve in high-volume production. This recess distance, caused by the CMP step, results in a very narrow manufacturing window, which is impractical: any slight protrusion of the metal pads above the horizontal plane of the bonding interface, composed of dielectric surfaces, can hinder the spontaneous dielectric bonding phase of the direct hybrid bonding process occurring at room temperature, leading to overall bonding failure. For further development of 3D semiconductor packaging, a structure and process are desired that can reduce the annealing temperature for direct inter-metal bonding of interconnects. Summary of the Invention

[0009] Layer structures for direct intermetallic bonding in microelectronics at low temperatures and shorter annealing durations are provided. Example bonding interface structures enable direct intermetallic bonding of interconnects at low annealing temperatures of 150°C or lower, and with lower energy budgets due to shorter annealing times. Example structures provide precise metal recess distances for bonded conductive pads and vias that can be achieved in high-volume production. Example structures provide vertical stacks of conductive layers constrained by a surrounding dielectric with geometry and thermal expansion characteristics designed to allow the stack to expand vertically at lower temperatures and within precise recess distances for direct intermetallic bonding at the bonding interface without solder or binder. Further enhancements such as surface nanotexturing and copper crystal planarization can further facilitate direct intermetallic bonding at lower annealing temperatures and shorter annealing durations.

[0010] The content of this invention is neither intended to identify key or essential features of the claimed subject matter nor to help limit the scope of the claimed subject matter. Attached Figure Description

[0011] Certain embodiments of this disclosure will be described below with reference to the accompanying drawings, wherein like reference numerals denote like elements. However, it should be understood that the drawings illustrate various implementations described herein and are not intended to limit the scope of the various techniques described herein.

[0012] Figure 1 This is a diagram of an example layer structure applicable to direct intermetallic bonding in microelectronics, at low annealing temperatures and short annealing durations.

[0013] Figure 2 This is a diagram of an example device with an example layer structure for direct inter-metal bonding, the example layer structure including the recess distance for bonding pads available in high-volume production.

[0014] Figure 3 This is a diagram showing the geometry of thermal expansion of the metal bonding surfaces used for direct metal-to-metal bonding.

[0015] Figure 4 The graph shows the relationship between the maximum indentation distance from the bonding plane and temperature for thermally expanding metal contact parts of different thicknesses.

[0016] Figure 5 Two example diagrams of three conductive layers are shown, where the corresponding CTEs are within a vertically direct-bonded stack.

[0017] Figure 6An embedded metal bump or inlay of an organic material with high CTE is shown. The embedded metal bump or inlay provides vertical thermal expansion during an example direct hybrid bonding process to reduce annealing temperature and shorten annealing duration.

[0018] Figure 7 This diagram illustrates multiple parallel vias serving as a first or second conductive layer in direct intermetallic bonding.

[0019] Figure 8 This is a flowchart illustrating an example process for creating a bonding interface structure that enables direct intermetallic bonding at lower annealing temperatures and shorter annealing times than conventionally used methods.

[0020] Figure 9 This illustrates how, in an example direct hybrid bonding process, Figure 8 A diagram showing an example of structures joined together.

[0021] Figure 10 This is a diagram illustrating an example process for fabricating nanotextured surfaces in direct intermetallic bonding to reduce annealing temperature and shorten annealing time.

[0022] Figure 11 This is a flowchart illustrating an example process for fabricating structures suitable for forming direct intermetallic bonds at low annealing temperatures and short annealing durations. Detailed Implementation

[0023] Overview

[0024] This disclosure describes layer structures for direct intermetallic bonding in microelectronics at low temperatures and short annealing durations. Example bonding interface structures enable direct intermetallic bonding of interconnects at low annealing temperatures of 150°C or lower. Example structures provide precise metal recess specifications, such as 4 to 6 nanometers, achievable in high-volume production. In direct hybrid bonding, direct bonding of the dielectric surface first occurs across the bonding interface. Then, during the annealing stage, vias or pads recessed at precise recess distances can expand at lower annealing temperatures and shorter annealing durations to bridge gaps and form direct intermetallic bonds.

[0025] Reducing the energy budget, or “thermal budget,” for creating direct hybrid bonds (including intermetallic bonds of conductive interconnects) involves not only lowering the annealing temperature but also reducing the duration of the annealing phase in the hybrid bond. Example techniques for shortening the annealing duration are also described herein.

[0026] Importantly, the example structures enabling direct hybrid bonding with a reduced energy budget allow for the completion of hundreds of thousands or even over a million electrical interconnects per square millimeter in direct hybrid bonding of metal interconnects at lower temperatures and with a lower energy budget than conventionally applied temperatures. Direct bonding can be achieved through thermocompression bonding or hybrid bonding. This paper describes hybrid bonding as an example. The example cryogenic process is safer for semiconductor components and manufacturing equipment and is less costly to implement. The example cryogenic process also enables the application of direct hybrid bonding to components and products that cannot be annealed at conventional annealing temperatures of 250°C and above.

[0027] Example of a bonded interface structure

[0028] Low-temperature direct intermetallic bonding is attractive for certain applications. However, the vertical thermal expansion required to bond metals together in direct hybrid bonding processes is limited at lower temperatures compared to the vertical thermal expansion achievable at conventional annealing temperatures. This necessitates precise control over the structure of the bonding interface before bonding can occur at lower temperatures.

[0029] Specifically, such as Figure 1 As shown, performing direct hybrid bonding at lower temperatures requires careful control over how far the metal pads 100 and 100' to be bonded can be recessed from the bonding interface plane 102 itself. This recess of the metal pads 100 and 100' from the plane of the larger bonding interface 102 is referred to herein as the “maximum recess distance” 104 or simply “recess” 104, and ranges from 0 nanometers (nm) to the maximum allowable recess. Protrusion of the metal pads 100 above the horizontal plane 102 is generally not permitted or preferred prior to the annealing step. Furthermore, the lower tolerance imposed on this recess parameter 104 to achieve lower annealing temperatures necessitates careful control of the chemical mechanical planarization (CMP) operation for planarizing the die and wafer, thereby first establishing the planarity of the bonding interface 102 and the resulting recess distance 104 of the metal contacts.

[0030] In one implementation, to enable direct bonding of metal interconnects at low temperatures, the maximum recess distance 104 between the metal pads 100 to be bonded and the horizontal plane of the larger bonding interface 102 is designed to be only a few nanometers (per side), and the metal pads 100 and the structure 106 beneath them are designed to expand, with calculated thermal expansion sufficient to lift each metal pad 100 into the opposite metal pad 100' belonging to the other surface to be bonded, so that the metal pads 100 and 100' can be directly bonded to a single metal interconnect 110 after bonding. The maximum recess distance 104 between each metal pad 100 and its corresponding larger bonding interface 102 or 102' is critical for achieving low-temperature direct bonding. For example, if the recess distance 104 is too small, it becomes difficult to control the CMP process and increases the risk of the metal pads 100 protruding above the dielectric surface 102. If the metal pad 100 is slightly higher than the larger bonding interface 102, dielectric bonding in layer 108 does not occur around the raised pad. If a sufficient number of raised pads disrupt the bonding of the surrounding larger dielectric surface 102, bonding failure occurs.

[0031] On the other hand, if the recess distance 104 is too large, once the thermal expansion of the metal pads 100 and the underlying structure 106 is exhausted, the metal pads 100 and 100' will not expand sufficiently to contact each other at the bonding interface 102 at a lower annealing temperature. This results in inter-oxide bonding of the non-metallic portions 108 of the bonding interface 102, but the metal pads 100 and 100' are not bonded because they never contact each other across the bonding interface 102. Dielectric surface bonding occurs, but there are no electrical interconnects across the bonded surfaces.

[0032] When copper is the metal being directly bonded, the higher temperature of the annealing step can induce changes in the grain size of the copper metal on each side of the intermetallic bond. Low-temperature direct bonding also takes this into account well. Similarly, the metal surface 100 to be bonded can be intentionally modified to favor bonding at lower temperatures. Conventionally, CMP processes produce a surface of pure material where the planarized metal regions are free of oxides and impurities. The bonding surface can be activated using plasma to lower the activation energy required for bond formation and to create some charge balance disruption at surfaces favorable for bond formation. In the implementation described herein, the metal pads 100 to be directly bonded as interconnects can also exponentially increase the bonding surface area and physically catalyze or seed the direct metal bonding by creating nanoparticles of metal on the bonding surface, thus creating nanoparticles on top. In another implementation, the selection of copper crystal faces increases the rate at which copper atoms diffuse across the bonding interface to form permanent intermetallic bonds, thereby enabling a lower annealing temperature and shorter annealing duration.

[0033] Figure 2 An example layer structure 200 in a microelectronic device is shown, wherein metal pads 100 are recessed from the planar surface of bonding interface 102 by a distance 104. Figure 2 In the diagram, the recess distance 104 is disproportionate and exaggerated for descriptive purposes. The dielectric layer 108 of the bonding interface 102 has a surface in a horizontal plane. A via 202 is vertically disposed in the horizontal surface of the dielectric layer 108. A vertical stack 204 of conductive layers 206 and 208 is located within the via 202. The conductive layers 206 and 208 may have more than one metallic component, and each conductive layer 206 and 208 in the vertical stack 204 has a corresponding coefficient of thermal expansion (COE), denoted as α1 and α2.

[0034] The recess distance 104 of the top surface 210 of the first conductive layer 206 in the vertical stack 204 from the horizontal surface of the bonding interface 102 varies with temperature because conductive layers 206 and 208 expand or contract relative to temperature. For a given layer structure 200, the recess distance 104 at room temperature has a specific range for direct intermetallic bonding with respect to a given annealing temperature. The recess is related to the volume and geometry of the two conductors 206 and 208 in the vertical stack 204 and their corresponding coefficients of thermal expansion α1 and α2.

[0035] In one implementation, the vertical stack 204 thermally expands at an annealing temperature approximately 250°C below the conventional annealing temperature, causing at least a portion of the top surface 210 of the first conductive layer 206 to expand or protrude within a recess distance 104 onto the horizontal surface of the bonding interface 102, pushing the top surface 210 into place to enable direct intermetallic bonding at the bonding interface 102. Another example of vertical stack 204 is performed on the other side of the bonding interface. The actual annealing temperature can be between 150 and 200°C, or approximately 150°C, or even below 150°C. These approximate temperatures are much lower than the conventional annealing temperature (approximately 250°C) required for the annealing step in direct hybrid bonding.

[0036] In this implementation, the second conductive layer 208 of the vertically stacked 204 is located below the first conductive layer 206 and is electrically connected to the first conductive layer 206. The second conductive layer 208 may have a second coefficient of thermal expansion α2.

[0037] At least one bottom layer 212 below the vertical stack 204 is composed of a semiconductor die or wafer material or a substrate material such as glass, dielectric, conductor, etc.

[0038] A dielectric confinement layer 108, such as silicon dioxide, provides a confinement matrix surrounding the vertical conductive stack 204 and has a much lower CTE than the metal stack 204 to provide sufficient confinement of the horizontal expansion forces of the metal stack 204 and thereby generate substantially vertical expansion within the buried conductive layer 208. The dielectric layer 108 is rigid enough to confine most of the expansion of the vertical stack 204 substantially within the vertical stack 204 itself. Thus, by confining the expansion forces, the dielectric layer 108 converts the horizontal thermal expansion of the first conductive layer 206 and the second conductive layer 208 into vertical expansion within the vertical stack 204. For example, the following references... Figure 8 This describes an example process for constructing (multiple) dielectric layers 108 and an example vertical conductive stack 204.

[0039] like Figure 3 As shown, the combined vertical thermal expansion of the first conductive layer 206 and the second conductive layer 208 causes the top surface 210 to expand, such that at least a portion of the top surface 210 of the first conductive layer 206 protrudes, deforms, expands and / or moves a recess distance 104 at an annealing temperature of about 150°C or lower, until it reaches the horizontal plane of the bonding interface 102.

[0040] Refer again Figure 2 When made of, for example, silicon dioxide, the dielectric layer 108 has a diameter of approximately 0.55 × 10⁻⁶. -6 The coefficient of thermal expansion (CTE) is 7 °C and the Mohs hardness is 7. In some implementations, other materials can be used for the dielectric 108. A suitable dielectric 108 can have a CTE equal to or greater than that of, for example, silicon dioxide with a very low CTE.

[0041] In one implementation, the maximum indentation distance 104 is determined by equation (1):

[0042] δ=α * ×h×ΔT (1)

[0043] Where δ is the recess distance 104, α* is the effective CTE of the vertical stack 204 of conductive layers 206 and 208, h is the thickness of the vertical stack 204 of conductive layers 206 and 208, α* consists of three components: α*1, α*2 and α*3, and ΔT is the temperature change between room temperature and annealing temperature.

[0044] α * =α * 1+α * 2+α * 3 (2)

[0045] The first component (α) of the effective CTEα* of the entire vertical stack 204 of conductive layers 206 and 208 *1) represents the vertical component of the thermal expansion of stack 204, and can be approximated by the composite CTE of vertically stacked 204 layers 206 and 208. The composite CTE of vertically stacked 204 can be determined by equation (2):

[0046] α * 1=α1×h1 / (h1+h2)+α2×h2 / (h1+h2) (3)

[0047] Where α1 is the CTE of the first conductive layer 206 of the vertically stacked 204, α2 is the CTE of the second conductive layer 208 of the vertically stacked 204, h1 is the thickness 214 of the first conductive layer 206, and h2 is the thickness 216 of the second conductive layer 208. The total thickness of the metal in the stack 204, consisting of the first conductive layer 206, the second conductive layer 208, and any optional additional layers, increases thermal expansion beyond what can be achieved without a stacked structure (such as having only the first conductive layer 206). The combined thickness h = h1 + h2 of the metal stack 204 is greater than the thickness h1 of the first conductive layer 206 alone, and therefore reduces the annealing temperature for a given value of the metal recess distance 104.

[0048] The second component (α) of the effective CTEα* of the entire vertically stacked 204 * 2) is the horizontal expansion contribution (α) of the second buried metal layer 208. * 2) Due to the limitation of the dielectric 108, it is converted into vertical expansion. When the horizontal coverage area of ​​the buried metal layer 208 is larger than the horizontal coverage area of ​​the first buried conductive layer 206 above it, α * 2's contribution is even greater.

[0049] The third component (α) of the effective CTEα* of vertically stacked 204 * 3) Surface area with the top surface 210 of the first conductive layer 206 Regarding this, surface 210 can be a metal "pad" to be bonded. The movement of the outer edge of conductive layer 206 is constrained by the dielectric confining matrix 108 because the two are adjacent. During design, increasing the surface area of ​​the top surface 210 of the first conductive layer 206 provides less constraint on thermal expansion in the metal volume within the first conductive layer 206, further away from the interface between the first conductive layer 206 and the confining dielectric matrix 108. Therefore, at a given annealing temperature, the central portion of the top surface 210 on a large metal pad or conductive layer 206 expands further compared to a small pad with a smaller top surface 210. This facilitates the use of α in equation (2). * 3 to capture the effective CTEα of the entire vertical stack of 204 * .

[0050] Structural designs incorporating the following features and parameters (e.g., direct intermetallic bonding) can significantly reduce the annealing temperature of conductive vias 206 with an example recess 104 (greater than 1 to 2 nm) to below 200 °C, or even below 150 °C. The example structure has a relatively thick upper metal via 206, for example, a thickness of h1 greater than 0.5 μm, with an example range of 0.6 to 2.0 μm. The upper metal via 206 is conductively connected to one or more buried metal layers 208, such as one or more trace layers of a BEOL stack, to increase the effective total stack thickness h 204. When the buried metal layer 208 comprises a portion of a trace, the buried metal layer 208 can be intentionally thicker than a typical trace layer, for example, in the range of 0.5 to 1.5 μm. The example buried metal layer 208 has a larger coverage area (horizontal cross-section) than the via layer 206 above it. The larger area of ​​the upper via 206 compared to the typical top surface area 210 also allows for a lower annealing temperature to form intermetallic bonds. For example, a conventional circular upper via 206 has a top surface 210 with a diameter of 3 μm, while the example enlarged upper via 206 described herein for lowering the annealing temperature can have an upper circular pad surface 210 of 5 μm, 10 μm, or 15 μm.

[0051] Figure 4 It is using the overall effective CTEα* α * A theoretically calculated graph showing the difference in thermal expansion (i.e., minimum annealing temperature) between copper 206 and dielectric SiO2 108 as a function of annealing temperature and metal thickness 214, plotted using a single component (vertical thermal expansion). For a given metal thickness 214, if the combination of annealing temperature and metal depression 104 drops below the corresponding line of sight on the graph, theoretically, the two metal surfaces will not expand to contact each other and form intermetallic bonds. If the combination drops above this line, theoretically, intermetallic bonding will occur.

[0052] For a given annealing temperature, the larger the metal recess distance 104, the higher the required annealing temperature. The smaller the recess distance 104, the lower the annealing temperature required for intermetallic bonding. However, for CMP process control and high-volume production, very small recess dimensions are undesirable. By increasing the total metal thickness h1 214 below the via surface 210, the slope of the line decreases in the graph, and then for a given recess 104, the calculated annealing temperature decreases as the total thickness 214 of the upper metal via 206 increases.

[0053] The following example illustrates the effect of metal thickness 214 and other dimensions. For a 3μm diameter via 206 with a 6nm recess distance 104, if the vertical thickness (h1) 214 of the upper metal via 206 is 0.8μm and the vertical thickness (h2) 216 of the buried trace 208 connected to the upper metal via 206 is 0.2μm, and the total metal thickness h 204 is 1.0μm, the calculated annealing temperature is close to 300°C. However, when the buried metal trace 208 (which can be more than one layer) is increased to 0.8μm, resulting in a total metal stack thickness (h) 204 of 1.6μm, the calculated annealing temperature is reduced to 180°C. When the upper via layer 206 is increased to 1.3μm for a total metal stack thickness (h) 204 of 2.1μm, the calculated annealing temperature is reduced to 130°C. Further increasing the thickness (h) 204 of the (multiple) metal stacks can further reduce the calculated annealing temperature.

[0054] As described above, changing the metal recess distance parameter 104 reduces the annealing temperature. With a given total metal stack thickness (h) 204 of 1.6 μm, reducing the Cu recess distance 104 from 6 nm to 4 nm reduces the calculated annealing temperature from the nominal 180 °C to 121 °C.

[0055] In one implementation, the limitations of the dielectric 108 are optimized through appropriate design and combination of materials, resulting in an overall effective CTE component α. * 2 (converted to vertical horizontal thermal expansion) and α * The contribution of 3 (surface area of ​​the intermetallic bonding surface) reduces the annealing temperature to even below the calculated value. As shown above, with a metal stack thickness (h) of 1.6 μm, only the α value is considered. * The lowest annealing temperature calculated using the example parameters for one component is 180°C, a significant improvement compared to the conventional annealing temperature in direct-mix bonding. It turns out that due to α... * 2 (converted to vertical horizontal thermal expansion) and α * The additional contribution of 3 (surface area on top of metal vias or pads to be bonded) results in a total copper stack thickness (h)204 of 1.6 μm at 150 °C, compared to using only the improved α * 1 (Vertical thermal expansion) was calculated to be 180°C, and intermetallic bonding was successfully achieved at a lower annealing temperature.

[0056] In one implementation, the vertical thickness (h1) 214 of the first copper conductive layer 206 is 1.6 μm, and the CTEα1 is between 16.7 and 17.0 × 10⁻⁶. -6The second conductive layer 208 is also copper, with a vertical thickness (h2) 216 of approximately 0.5-1.0 μm, and CTEα2 is also within the range of 16.7-17.0 × 10⁻⁶. -6 Within the range of / ℃. In this case, the maximum indentation distance δ is approximately 6 nanometers (nm), and the annealing temperature is reduced to between 150-200℃.

[0057] The second “buried metal” conductive layer 208 of the vertically stacked 204 can be at least partially part of a redistribution layer (RDL) or trace of the fabricated microelectronic component. In one implementation, the size of the horizontal coverage area of ​​the RDL or trace constituting the second conductive buried metal layer 208 is at least larger than the corresponding horizontal size of the coverage area of ​​the first conductive layer 206. The lower second conductive layer 208 has a larger coverage area compared to the first conductive layer 206, which provides more thermal expansion through the larger volume of metal, including the horizontal thermal expansion that is converted into the vertical expansion of the vertically stacked 204 due to the limitation of the horizontal expansion provided by the dielectric-limited matrix 108. This increase in the volume of metal buried deeper below the bonding interface 102 and below the first metal via 206 is significant because only a few nanometers in the recess distance 104 reduces the annealing temperature required to lead to direct intermetallic bonding.

[0058] Besides pure copper, in several implementations, the first conductive layer 206 or the second conductive layer 208 of the vertically stacked 204 can be another material, such as CTE at 18-19×10⁻⁶. -6 Brass alloys within the / ℃ range, with a CTE of 21.2×10. -6 Manganese bronze alloy at / ℃, CTE at 21-24×10 -6 Aluminum metal or aluminum alloy within the range of / ℃, with a CTE of 30-35×10. -6 Zinc metal or zinc alloy, copper-nickel (e.g.), or other suitable conductors at / ℃.

[0059] Figure 5 Other example layered structures 500 and 500' for direct bonding at low annealing temperatures in microelectronics are shown. In these implementations, the vertical stack 502 may also include a third buried conductive layer 504 of the vertical stack 204, as in structure 500 between the second conductive layer 208 and the bottom layer 212, or as in structure 500' between the first conductive layer 206 and the second conductive layer 208. Although this example has three conductive layers in the vertical stack 502, the vertical stack 502 can contain, for example, up to twelve different layers. Moreover, the layers can have various widths and thicknesses to optimize the metal expansion effect.

[0060] The third conductive layer 504 increases the total stack thickness (h) 502 and can increase the effective CTEα* by providing a conductor with a higher CTE than copper metal in the vertical stack 502, for example, thereby providing greater vertical thermal expansion throughout the vertical stack 502. This reduces the annealing temperature required to form direct intermetallic bonds in direct hybrid bonding. When the horizontal coverage area is relatively large, such as in structure 500', the geometry of the third conductive layer 504 can also increase vertical expansion and effective CTEα*. Then, due to the confining dielectric matrix 108, the horizontal thermal expansion of the third conductive layer 504 at the annealing temperature tends to be converted into additional vertical expansion of the vertical stack 502. The third conductive layer 504 can be, for example, with a CTE of 18-19 × 10⁻⁶. -6 Brass alloys within the / ℃ range, with a CTE of 21.2×10. -6 Manganese bronze alloy at / ℃, CTE at 21-24×10 -6 Aluminum metal or aluminum alloy within the range of / ℃, with a CTE of 30-35×10. -6 Zinc metal or zinc alloy at / ℃, or other suitable conductor.

[0061] Figure 5 The example vertical stack 502 can be constrained on at least three sides; for example, the bottom and two sides of the trace are constrained, and the top surface is connected to the via 206. All sides adjacent to or constraining the dielectric matrix 108, either with a barrier layer or a hardened barrier layer, further contain lateral and horizontal expansion forces, which, when their temperature approaches the annealing temperature, are converted into vertical expansion forces, expanding the top surface 210 of the first conductive via 206 to the level of the bonding interface 102. This constraint, resulting in increased vertical expansion, lowers the annealing temperature required to form intermetallic bonds in direct hybrid bonding.

[0062] In one example implementation, the first conductive layer 206, serving as a direct bonding layer, has a top surface 210, which is a circular via with a diameter of 5 μm. For example, the diameter could also be 2 μm, 3 μm, 5 μm, 10 μm, 15 μm, or other sizes. The vertical thickness (h1) of the first conductive layer 206 can be approximately 1.5 μm, and the dimensions of the second conductive layer 208, which is an RDL layer, could be, for example, 20 μm × 20 μm × 0.5 μm. In this example, the metal volume of the first conductive layer 206 is, for example, 2.5 μm × 2.5 μm × 3.14 × 1.5 μm = 29 μm. 3 The volume of the second conductive layer 208 is, for example, 200 μm. 3The buried metal volume of the second conductive layer 208 is approximately seven times that of the buried metal volume of the first conductive layer 206. Even if a portion of the horizontal thermal expansion of the second conductive layer 208 deforms into the vertical expansion of the first conductive layer 206, this additional expansion will significantly increase the effective CTEα* and significantly reduce the annealing temperature used for intermetallic bonding.

[0063] In another example, for instance, the volume of the first conductive layer 206 is 265 μm. 3 Furthermore, the volume of the second conductive layer 208 "buried" is, for example, 327 μm. 3 In this case, assuming that the two layers have the same CTE, the contributions from the thermal expansion of layers 206 and 208 are approximately the same.

[0064] Figure 6 Another example layered structure 600 for direct bonding at low temperatures in microelectronics is shown. In this implementation, the vertical stack 602 may also include embedded bumps 604 or inlays 606 made of conductors or other materials, the bumps 604 or inlays 606 having a higher CTE than copper metal, for adding additional thermal vertical expansion to the vertical stack 602. The embedded bumps 604 or inlays 606 may be, for example, with a CTE of 21.2 × 10⁻⁶. -6 Manganese bronze alloy at / ℃, CTE at 21-24×10 -6 Aluminum metal or aluminum alloy within the range of / ℃, with a CTE of 30-35×10. -6 Materials of zinc metal or zinc alloy at / ℃, or other suitable metallic or non-metallic materials.

[0065] The embedded bump 604 or inlay 606 can also be a dielectric material, such as an organic material (non-metallic) with a very high CTE, provided that the bump 604 or inlay 606 does not obstruct the conductive path forming a direct intermetallic bond between, for example, a trace and a via 206 having a top surface 210. The buried layer 504 can also be an organic material with a high CTE, such as, provided that it does not obstruct the conductive path. Figure 5Layer 504 in structure 500. The organic material with high CTE used for burying layer 504 or embedded bump 604 or insert 606 may be polyimide with a CTE in the range of 30-60×10-6 / ℃, epoxy resin with a CTE in the range of 45-65×10-6 / ℃, chlorinated polyvinyl chloride (CPVC) with a CTE in the range of 63-66×10-6 / ℃, phenolic resin with a CTE in the range of 60-80×10-6 / ℃, nylon with a CTE in the range of 50-90×10-6 / ℃, ABS thermoplastic with a CTE in the range of 22-108×10-6 / ℃, polybutene with a CTE in the range of 130-139×10-6 / ℃, ethylene vinyl acetate with a CTE of 180×10-6 / ℃, and ethylene ethyl acrylate with a CTE of 205×10-6 / ℃.

[0066] refer to Figure 2 , Figure 5 and Figure 6 The thickness (h1) 214 of the first conductive layer 206 can be proportionally increased to be greater than the example nominal vertical dimension of 1.6 μm at a recess distance 104 of 6 nm, in order to further reduce the annealing temperature to below the nominal temperature of 200°C for the annealing step used for direct mix bonding. The larger thickness (h1) 214 of the first conductive layer 206 provides a larger vertical thermal expansion for the vertical stack 204, thereby enabling the same amount of vertical expansion to be obtained at a lower temperature as that provided by the smaller thickness 214 of the first conductive layer 206 at a higher temperature.

[0067] Figure 7 Additional example layered structures 700 and 702 for direct bonding at low temperatures in microelectronics are shown. In one implementation, a plurality of parallel conductive vias 704 and 706 and 708 form a first conductive layer 206 over a single second conductive layer 208, each surrounded by a dielectric confinement material 108. The first conductive layer 206 is a direct bonding layer having a top surface 210 recessed from a dielectric oxide surface 709. The plurality of parallel conductive vias 704 and 706 and 708 are each electrically coupled to a single second conductive layer 208, which may be an RDL (redistribution layer). The plurality of parallel conductive vias 704, 706, and 708 in the first conductive layer 206 provide multiple bonding opportunities for the same connection to improve yield and reliability through redundancy.

[0068] In another implementation, Figure 7Example structure 702 includes a second conductive layer 208 beneath a single first conductive layer 206, the second conductive layer 208 having a plurality of parallel conductive vias 712, 714, and 716 surrounded by a dielectric-confined filler 108. The second conductive layer 208 including the plurality of parallel conductive vias 712, 714, and 716 can be an RDL (redistribution layer) on a die or wafer. The plurality of parallel conductive vias 712, 714, and 716 are each electrically coupled to the single first conductive layer 206, the single first conductive layer 206 being a direct-bonded metal layer having a large-area top surface 210. This arrangement provides a larger direct-bonded surface area than a single via. This allows for direct bonding and enables direct intermetallic bonding at lower temperatures compared to conventional annealing processes, due to the increased surface area of ​​the top surface 210. The larger size allows the center of the larger top surface 210 to deform upwards more than the edge of the larger top surface 210.

[0069] Figure 8 The diagram illustrates the methods for creating bonding interface structures (such as...) Figure 5 An example process flow 800 of the structure 500 in the diagram shows a bonding interface structure that enables direct intermetallic bonding at lower annealing temperatures and shorter annealing times than conventional methods. The steps of the example process flow are shown as separate boxes and corresponding diagrams.

[0070] At frame 802, a dielectric material 804 is formed or deposited on a semiconductor or other substrate 806, and a trench 808 is formed in the dielectric material 804 to confine one or more metal layers. The trench may be, for example, an etched trench and / or a caulking cavity.

[0071] At frame 810, a barrier layer and / or adhesion layer, along with a metal seed layer, are applied to trench 808 for metal deposition. Trench 808 is then filled with one or more metals 812 and 814 in one or more layers, or may be filled with any other multilayer composition. The top surface 816 of the one or more metals is planarized using a CMP process to remove excess deposition.

[0072] At frame 818, another dielectric material layer 820 is deposited, and a trench 822 is formed or etched to confine the subsequently added bonding layer metal 824 (“conductive via”). The trench 822 is filled with the bonding layer metal 824, and CMP planarization is used to remove excess deposition. The finished surface 826 after CMP meets the specifications for dielectric surface roughness and metal recess 104 used in the example direct hybrid bonding process.

[0073] exist Figure 9 middle, Figure 8The process continues. Figure 8 Examples of structures and bonding surfaces manufactured in China are shown using a direct hybrid bonding process as an example.

[0074] At frame 828, two instances of the bonding interface structure are bonded together in the first stage of a direct hybrid bonding process. The first stage directly bonds the inorganic dielectric oxide surfaces 830 together. Surface bonding can occur in wafer-to-wafer (W2W), die-to-wafer (D2W), or die-to-die (D2D) processes.

[0075] At frame 832, in the second stage of the direct hybrid bonding process, the bonded structure is annealed. The increased temperature of the annealing process causes the buried metals 812 and 814 and the bond layer metal 824 to expand vertically, confined by the surrounding dielectric layers 804 and 820, to convert horizontal thermal expansion into vertical expansion. The vertical expansion of metals 812 and 814 and 824 results in at least a portion of the top surface 816 bridging the combined recess 104 at a lower annealing temperature. The respective top surfaces 834 of the bond layer metals 824 come into contact with each other, and metal atoms diffuse across the interface, thereby forming irreversible intermetallic bonds between the respective bond layer metals 824.

[0076] Lower annealing temperatures are a consideration for low-temperature bonding, and a second consideration is annealing duration, which in turn affects the thermal budget for annealing. A lower thermal (energy) budget is required. In the example direct mixed bonding process, the formation of direct copper-copper bonds involves two components: 1) the expansion of the two recessed surfaces to bridge the gap and bring them into physical contact with each other (thermodynamic considerations); 2) the diffusion of copper atoms across the interface to form a permanent bond (bonding kinetics considerations). It is well known that atomic diffusion along the 111 crystal plane is 3 to 4 orders of magnitude faster than diffusion along the 100 or 110 crystal planes (see below). Therefore, it is advantageous to have a majority of 111 crystal planes on surface 834 to shorten the annealing time for direct mixed bonding, especially at lower temperatures, because diffusion on the Cu surface slows down as the annealing temperature is lowered.

[0077] Table (1) shows the Cu surface diffusivity (cm²) calculated on the (111), (100), and (110) planes at various temperatures from 150 °C to 300 °C. 2 / sec). (Agrawal, PM et al., "Predicting trends in rate parameters for self-diffusion on FCC metal surfaces." Surf. Sci. 515, 21–35 (2003))

[0078] Table (1)

[0079] Diffusion rate Surf\temperature (111) face (100) face (110) face 300℃ 1.51×10-5 1.48×10-8 1.55×10-9 250℃ 1.22×10-5 4.74×10-9 3.56×10-10 200℃ 9.42×10-6 1.19×10-9 5.98×10-11 150℃ 6.85×10-6 2.15×10-10 6.61×10-12

[0080] Low-temperature direct copper-copper bonding is achieved via creep on the (111) surface of nanotwinned copper on the nanotextured surface 1004. The grain size of copper at the grain boundaries of the bonding surface 834 may also influence the annealing conditions that lower the annealing temperature. Copper grain size is smaller at lower temperatures, therefore, lower temperatures are also favorable for the formation of direct bonding in this respect compared to higher annealing temperatures.

[0081] Figure 10 A process for preparing or modifying the top surface 834 of the bonding layer metal 824 to facilitate direct intermetallic bonding at lower annealing temperatures and shorter annealing durations is illustrated. The lower annealing temperatures and shorter annealing durations reduce the overall thermal and energy budgets of the example direct hybrid bonding process.

[0082] The steps of the example process flow are shown as separate boxes and corresponding diagrams. The example process uses... Figure 8 The initial manufacturing steps are the same as those shown in the process.

[0083] exist Figure 10 In this example, a nanotextured surface 1004 can be created on top of the bonded metal layer 824. When the respective top surfaces 834 come into contact with each other during the example direct hybrid bonding process, the nanotextured surface 1004 significantly improves the rate of direct intermetallic bonding formation.

[0084] The bonding metal layer 834 itself can be formed using a process that involves plating copper metal (Cu) on a 111 crystal orientation (of copper). The copper metal can be deposited, for example, from a superfilled electroplating bath, and the electroplating chemistry can be selected to optimize the direct intermetallic bonding that occurs during the example direct mixed bonding. The microstructure of the deposited or coated bonding metal layer 824 can be stabilized, for example, by an annealing step that is separate from the annealing step of the subsequent example direct mixed bonding.

[0085] Example nanotextured surface 1004 can also be explicitly formed by applying a nanotexturing process to the top surface 834 of the bonded metal layer 824 to form a surface with a high refractive index plane and / or a lattice plane having, for example, a Miller index of 111.

[0086] In one implementation, the nanotextured surface 1004 can be made in several ways. For example, a very dilute acid rinsing solution can be applied to the top surface 834, and the surface can be spin-dried in an oxygen environment and rinsed with deionized water. Alternatively, the top surface 834 can be rinsed in a low-acid copper sulfate solution, dried in an oxygen environment, then rinsed with dilute acid, and then deionized.

[0087] These processes create a hexagonal network of helical dislocations in the copper metal surface 834 to create an example nano-surface texture 1004. This nano-surface texture 1004 promotes and accelerates the diffusion rate of copper atoms across the bonding interface, an atomic process that creates direct intermetallic bonding. Even at annealing temperatures lower than those used conventionally, this process of promoting and accelerating direct intermetallic bonding shortens the duration of the annealing step in direct hybrid bonding processes. The example annealing duration is even shorter than that of conventional annealing using microwave heating and bonding.

[0088] At box 1006, instances of exemplary bonding structures with nanotextured surface 1004 are joined, for example, by direct hybrid bonding. The nanotextured surface 1004 promotes faster diffusion of copper atoms across the bonding interface, resulting in promoted intermetallic bonding that occurs faster and at lower temperatures than conventional direct bonding processes.

[0089] Example Method

[0090] Figure 11 Example method 1100 is shown, which is used to fabricate structures suitable for forming direct intermetallic bonds at low annealing temperatures and short annealing durations. The operation of example method 1100 is shown in a separate box.

[0091] At frame 1102, a first confining matrix layer is applied to the substrate. The confining matrix may be silicon dioxide or another inorganic dielectric capable of forming direct bonds (such as oxide-to-oxide bonds) across the bonding interface.

[0092] At frame 1104, a first trench is formed in the first confining substrate. For example, the first trench may be etched and / or formed using a mosaic process.

[0093] At frame 1106, the first trench is filled with one or more metals. The first trench may be filled with 1-12 metal layers, characterized by providing a high CTE for relatively large thermal expansion. The filler may also be one or more metal alloys or compositions.

[0094] At frame 1108, a second confining matrix is ​​applied to the first confining matrix and one or more metals below it. The second confining matrix may be a different material from the first confining matrix, or it may be the same material but applied as discrete layers.

[0095] At frame 1110, a second trench is formed in the second confining substrate. For example, the second trench can be etched and / or formed using a mosaic process.

[0096] At frame 1112, the second trench is at least partially filled with a conductive via electrically connected to one or more metals. The conductive via can be copper, but it can also be other conductors. During the example direct hybrid bonding process, the metal material of the conductive via must be able to be directly bonded to a similar conductive via of the same metal.

[0097] At box 1114, at least the second limiting matrix is ​​planarized, for example using CMP, to create a bonding surface for direct mixing bonding, wherein the top surface of the conductive via is recessed 4-6 nanometers (nm) from the planarized bonding surface.

[0098] After fabricating the aforementioned structure suitable for forming direct intermetallic bonds at low annealing temperatures, a further process includes joining a first instance of the bonding surface with a second instance of the bonding surface to create a direct contact bond between the respective second confining matrices of the first and second bonding surfaces. In other words, in the first stage of the example direct hybrid bonding process, the flat, polished surfaces of the two instances of the bonding structure are joined together, and the dielectric portions of the surfaces spontaneously bond together upon contact.

[0099] In the second stage of the example direct hybrid bonding process, the bonded surfaces are annealed at a temperature equal to or less than 150°C, causing the corresponding metals in the first trench and the corresponding conductive vias in the second trench to thermally expand, thereby creating a direct intermetallic bond between the corresponding conductive vias at this low temperature. The vertical expansion of the metal stack causes the top surface of each conductive via to bridge a gap with a pre-designed recess distance that exists between the top surface and the bonding surface at room temperature.

[0100] The first trench can be formed with a larger cross-sectional area than the second trench to bury more metal beneath the conductive via that will undergo direct intermetallic bonding. At an annealing temperature equal to or less than 150°C, the substantial amount of buried metal creates increased vertical thermal expansion beneath the conductive via. The first confining matrix also converts the horizontal expansion of one or more buried metals into vertical expansion to expand the top of the conductive via to the bonding plane at a lower temperature.

[0101] In one implementation, the method may include filling a first trench with one or more metals, the overall vertical thickness (or height) of which is between approximately 0.5 and 1.5 μm. An example method also includes creating a second trench with dimensions suitable for forming a conductive via having a circular cross-section with a diameter of 5 μm or greater. The diameter can be larger, for example, 15 μm. The example method then includes filling the second trench with a conductive via, the vertical thickness (or height) of which can be between approximately 0.6 and 2.0 μm.

[0102] In one implementation, a nanostructured surface is created on the top surface of the conductive via to lower the annealing temperature and shorten the annealing duration. In another implementation, the nanotextured surface is a hexagonal network of helical dislocations in copper metal.

[0103] In the foregoing description and accompanying drawings, specific terms and reference numerals have been set forth to provide a thorough understanding of the disclosed embodiments. In some cases, terms and reference numerals may imply specific details that are not required for practicing those embodiments. For example, any particular size, quantity, material type, manufacturing steps, etc., may differ from those described above in the alternative embodiments. The term “coupled” is used herein to refer to both direct connections and connections via one or more intermediate circuits or structures. The terms “example,” “embodiment,” and “implementation” are used to indicate examples, not preferences or requirements. Similarly, the term “can / may” is used interchangeably to indicate optional (permitted) subject matter. The omission of any term should not be construed as implying a requirement for a given feature or technique.

[0104] Various modifications and changes can be made to the embodiments presented herein without departing from the broader spirit and scope of this disclosure. For example, features or aspects of any embodiment may be used in combination with or in place of corresponding features or aspects of any other embodiment. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0105] Although this disclosure has been made with respect to a limited number of embodiments, those skilled in the art who benefit from it will understand that various modifications and variations may be possible where the description is given. It is intended that the appended claims cover such modifications and variations that fall within the true spirit and scope of this disclosure.

Claims

1. A bonded structure comprising: a first microelectronic device comprising: a semiconductor layer; a first dielectric structure over the semiconductor layer, an upper surface of the first dielectric structure forming part of a first bonding surface of the first microelectronic device; a first buried conductive layer embedded in the first dielectric structure over the semiconductor layer, the first buried conductive layer having a first lateral dimension and a first thickness; a second buried conductive layer embedded in the first dielectric structure over the first buried conductive layer and electrically connected to the first buried conductive layer, the second buried conductive layer having a second lateral dimension smaller than the first lateral dimension and a second thickness greater than the second lateral dimension; and a third conductive layer comprising a contact pad over the second buried conductive layer and electrically connected to the second buried conductive layer, the bonding surface comprising an upper surface of the contact pad, the third conductive layer having a third lateral dimension greater than the second lateral dimension and smaller than the first lateral dimension; and a second microelectronic device directly hybrid bonded to the bonding surface along a bonding interface without an adhesive.

2. The bonded structure of claim 1, wherein the third conductive layer has a third thickness greater than 0.5 pm.

3. The bonded structure of claim 2, wherein the third thickness is in a range of 0.6 pm to 2 pm.

4. The bonded structure of claim 2, wherein the first thickness is in a range of 0.5 pm to 1.5 pm.

5. The bonded structure of claim 4, wherein the first thickness is in a range of 0.5 pm to 1 pm.

6. The bonded structure of claim 1, wherein the first dielectric structure comprises a plurality of dielectric layers of a back end of line (BEOL) stack.

7. The bonded structure of claim 1, wherein the first dielectric structure comprises silicon oxide.

8. The bonded structure of claim 1, wherein a surface of the third conductive layer comprises nanotwinned copper.

9. The bonded structure of claim 1, wherein a surface of the third conductive layer comprises copper metal having lattice planes that predominantly have a 111 Miller index orientation.

10. The bonded structure of claim 1, wherein the third lateral dimension is 2 pm or greater.

11. The bonded structure of claim 1, wherein the third lateral dimension is 5 pm or greater.

12. The bonded structure of claim 1, wherein at least the bonding surface of the third conductive layer comprises a nanotextured surface for forming direct intermetallic bonding at an anneal temperature of 150 °C or less.

13. The structure of claim 12, wherein the nanotextured surface comprises a hexagonal network of screw dislocations in the copper metal.

14. A bonded structure comprising: a first microelectronic device comprising: a semiconductor layer; ​ a first dielectric structure over the semiconductor layer, an upper surface of the first dielectric structure forming a portion of a first bonding surface of the first microelectronic device; a first buried conductive layer embedded in the first dielectric structure over the semiconductor layer, the first buried conductive layer having a first horizontal dimension and a first thickness in a range of 0.5 μm - 1.5 μm; a second buried conductive layer embedded in the first dielectric structure over the first buried conductive layer and electrically connected to the first buried conductive layer, the second buried conductive layer having a second horizontal dimension less than the first horizontal dimension and a second thickness greater than the second horizontal dimension; and a third conductive layer comprising a contact pad over the second buried conductive layer and electrically connected to the second buried conductive layer, the bonding surface comprising an upper surface of the contact pad, the third conductive layer having a third horizontal dimension greater than the second horizontal dimension and less than the first horizontal dimension, the third conductive layer having a third thickness in a range of 0.6 μm - 2 μm; and a second microelectronic device directly hybrid bonded to the bonding surface along a bonding interface without an adhesive.

15. The bonded structure of claim 14, wherein the third horizontal dimension is 2 μm or greater.

16. The bonded structure of claim 15, wherein the third horizontal dimension is 5 μm or greater.

17. The bonded structure of claim 14, wherein the first dielectric structure comprises a plurality of dielectric layers.

18. The bonded structure of claim 17, wherein the first dielectric structure comprises silicon oxide.

19. The bonded structure of claim 14, wherein a surface of the third conductive layer comprises nanotwinned copper.

20. The bonded structure of claim 14, wherein a surface of the third conductive layer comprises copper metal having a lattice plane having a majority 111 Miller index orientation for diffusion of copper atoms across the bonding interface.

21. A bonded structure, comprising: a first substrate having a dielectric material configured for direct hybrid bonding and a bonding pad at least partially embedded in the dielectric material, the dielectric material forming a first portion of a bonding surface of the first substrate and the bonding pad forming a second portion of the bonding surface, a surface of the bonding pad comprising nanotwinned copper; and a second substrate having a second bonding pad directly bonded to the surface of the bonding pad without an intervening adhesive and a second dielectric material directly bonded to the dielectric material.

22. The bonded structure of claim 21, wherein a second surface of the second bonding pad comprises nanotwinned copper.

23. The bonded structure of claim 21, further comprising a buried metal directly and electrically connected to the bonding pad.

24. The bonded structure of claim 23, wherein the buried metal has a vertical thickness of 0.5 pm - 1.5 pm.

25. The bonded structure of claim 21, wherein the bonding pad has a vertical thickness of 0.6 pm - 2.0 pm.

26. The bonded structure of claim 21, wherein the bonding pad has a width of 2 pm or greater.

27. The bonded structure of claim 21, wherein the bonding pad has a width of 5 pm or greater.

28. The bonded structure of claim 21, wherein a surface of the bonding pad comprises copper metal having a lattice plane that has a majority 111 Miller index orientation for diffusion of copper atoms across a bonding interface between the first substrate and the second substrate.

29. The bonded structure of claim 21, wherein the dielectric material comprises silicon oxide.

30. The bonded structure of claim 21, wherein the dielectric material comprises a plurality of dielectric layers of a back end of line (BEOL) stack.

31. A method of forming a bonded structure, comprising: providing a dielectric material of a first substrate configured for direct hybrid bonding, the dielectric material forming a first portion of a bonding surface of the first substrate; providing a bonding pad forming a second portion of the bonding surface, the bonding pad at least partially embedded within the dielectric material, the bonding pad comprising copper metal having a lattice plane that has a majority 111 Miller index orientation for direct intermetallic bonding, a buried metal directly and conductively connected to the bonding pad; directly bonding the dielectric material of the first substrate to a second substrate along a bonding interface without an intervening adhesive to form a bonded structure; and annealing the bonded structure at an annealing temperature below 250 °C to thermally expand the bonding pad such that the copper metal is in contact with a second bonding pad of the second substrate.

32. The method of claim 31, further comprising providing the buried metal such that a width of the buried metal is greater than a width of the bonding pad.

33. The method of claim 31, further comprising forming the buried metal to have a vertical thickness of 0.5 pm - 1.5 pm.

34. The method of claim 31, further comprising forming the bonding pad to have a vertical thickness of between 0.6 pm - 2.0 pm.

35. The method of claim 34, further comprising providing the bonding pad with a width of 2 pm or greater.

36. The method of claim 35, further comprising providing the bonding pad with a width of 5 pm or greater.

37. The method of claim 31, further comprising forming the bonding pad to have a nano-textured surface.

38. The method of claim 37, further comprising forming a hexagonal network of screw dislocations in the copper metal.

39. The method of claim 31, wherein annealing the bonded structure comprises annealing the bonded structure at an anneal temperature of 150 °C or less to form a direct intermetallic bond between the bonding pad and the second bonding pad.

40. The method of claim 31, wherein the buried metal is part of a trace configured to electrically connect the bonding pad to an electronic device on or within the first substrate.

41. The method of claim 31, further comprising providing a surface of the bonding pad comprising nanotwinned copper.

42. A method of forming a bonded structure, comprising: providing a first trench or a first via in a first dielectric structure of a first substrate, wherein the first trench or the first via has a first width; at least partially filling the first trench or the first via with one or more metals having a thickness of 0.5 μιη - 1.5 μιη; applying a second dielectric structure to the first dielectric structure and the one or more metals; forming a second trench or a second via in the second dielectric structure, the second trench or the second via having a second width that is less than the first width; at least partially filling the second trench or the second via with a first conductive material in direct contact with the one or more metals to form a first conductive via; applying a third dielectric structure to the second dielectric structure and the first conductive material; forming a third trench or a third via in the third dielectric structure, the third trench or the third via having a third width that is greater than the second width but less than the first width; at least partially filling the third trench or the third via with a second conductive material in direct contact with the first conductive material to form a metal pad over the conductive via; and preparing the second dielectric structure and the first conductive via to form a bonding surface for direct hybrid bonding to a second substrate.

43. The method of claim 42, wherein the first conductive via has a thickness of 0.6 μιη - 2.0 μιη over the first trench.

44. The method of claim 42, wherein preparing the second dielectric structure and the first conductive via comprises at least planarizing the second dielectric structure.

45. The method of claim 42, further comprising joining the bonding surface to the second substrate to create a direct contact bond between the second dielectric structure and the second substrate, the second substrate having a second conductive via.

46. The method of claim 45, further comprising annealing the bonded interface between the first substrate and the second substrate after joining at a temperature equal to or less than 150 °C to thermally expand the one or more metals in the first trench or the first via and the first and second conductive vias on the first and second substrates to create a direct intermetallic bond between the first and second conductive vias. ​ 47. The method of claim 42, wherein at least partially filling the second trench or the second via comprises forming the first conductive via having a cross-section of 5 pm or greater.

48. The method of claim 42, further comprising creating a nanostructured surface on the bonding surface of the first conductive via.

49. A method of forming a bonded structure, comprising: providing a first trench or a first via in a first dielectric structure of a first substrate, wherein the first trench or the first via has a first horizontal dimension and a first thickness; filling the first trench or the first via with one or more metals; applying a second dielectric structure onto the first dielectric structure and the one or more metals; forming a second trench or a second via in the second dielectric structure; at least partially filling the second trench or the second via with a conductive material in direct contact with the one or more metals to form a first conductive via having a second thickness over the first trench, the second thickness being greater than the first thickness and being at least 0.5 pm, wherein the first conductive via has a first portion and a second portion, wherein the first portion is between the second portion and the one or more metals and has a second horizontal dimension, wherein the second portion has a third horizontal dimension that is greater than the second horizontal dimension but less than the first horizontal dimension, wherein the second portion comprises a first metal pad, and wherein a second conductive via that is a closest conductive via in the second dielectric structure to the first conductive via comprises a second metal pad that is spaced apart from the first metal pad; and preparing the second dielectric structure, the first metal pad, and the second metal pad to form a bonding surface for direct hybrid bonding to a second substrate.

50. The method of claim 49, wherein the first thickness is 0.5 pm - 1.5 pm.

51. The method of claim 49, wherein the second dielectric structure comprises a plurality of dielectric layers.

52. The method of claim 49, wherein the first portion of the first conductive via has a different thickness than the second portion of the first conductive via.

53. The method of claim 49, wherein the first conductive via has a thickness over the first trench that is greater than 0.5 pm.

54. The method of claim 49, wherein the second thickness is 0.6 pm - 2.0 pm.

55. A method of forming a bonded structure, comprising: providing a dielectric material of a first substrate configured for direct hybrid bonding, the dielectric material forming a first portion of a bonding surface of the first substrate; providing a bonding pad forming a second portion of the bonding surface, the bonding pad being at least partially embedded within the dielectric material, a surface of the bonding pad comprising nano-twin copper; directly bonding the dielectric material of the first substrate to a second substrate along a bonding interface without an intervening adhesive to form a bonded structure; and directly bonding the bond pad to a second bond pad of the second substrate without interposing an adhesive, such that the surface of the bond pad is in direct contact with the second bond pad.

56. The method of claim 55, wherein the bond pad comprises copper metal having a lattice plane that has a majority of 111 Miller index orientation for diffusion of copper atoms across a bond interface for direct intermetallic bonding.

57. The method of claim 55, wherein directly bonding the bond pad to the second bond pad comprises annealing the bonded structure at an annealing temperature below 250 °C to thermally expand the bond pad such that the surface of the bond pad is in contact with the second bond pad of the second substrate.

58. The method of claim 55, wherein annealing the bonded structure comprises annealing the bonded structure at an annealing temperature of 150 °C or less to form a direct intermetallic bond between the bond pad and the second bond pad.

59. The method of claim 55, further comprising providing a buried metal directly and conductively connected to the bond pad.

60. The method of claim 59, wherein the buried metal has a vertical thickness of between 0.5 pm - 1.5 pm.

61. The method of claim 55, wherein the bond pad has a vertical thickness of between 0.6 pm - 2.0 pm.

62. The method of claim 55, wherein the bond pad has a width of 2 pm or greater.

63. The method of claim 55, wherein the bond pad has a width of 5 pm or greater.

64. The method of claim 55, wherein the bond pad comprises copper material having a hexagonal network of screw dislocations.

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