Test system and test method for mos devices

Abstract

The application provides a MOS device testing system and a testing method. In the testing system, a multi-gate testing structure comprises a first injection well and a plurality of main gates above the first injection well, a first source-drain contact hole is formed above the substrate on both sides of each main gate, an auxiliary testing structure comprises a second injection well and a plurality of auxiliary gates above the second injection well, a second source-drain contact hole is formed above the substrate on both sides of each auxiliary gate, the auxiliary gates correspond to the main gates one by one, and the number of the source-drain contact holes formed on both sides of the corresponding auxiliary gate and main gate is different. The testing system can extract the relationship between the parasitic capacitance from the gate to the source-drain contact hole and the number of the source-drain contact hole, and the structure of the testing system is simple, which is beneficial to saving the layout area. The testing method tests the parasitic capacitance from the gate to the source-drain contact hole of the MOS device by using the above testing system.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing and modeling technology, and in particular to a testing system and method for MOS devices. Background Technology

[0002] With the continuous development of integrated circuits and the shrinking feature size of devices, the parasitic capacitance of metal-oxide-semiconductor field-effect transistors (MOSFETs) accounts for an increasingly larger proportion of the total capacitance of the device, thus its impact on the overall circuit performance is becoming increasingly significant. Inaccurate extraction of parasitic capacitances in various parts during MOSFET device modeling can lead to significant deviations between simulated and actual values ​​of device structural performance parameters. Therefore, the accurate characterization of parasitic capacitances in various parts of the MOSFET device through the design of a series of specialized test structures is crucial.

[0003] Figure 1 This is a cross-sectional schematic diagram of an N-type MOS device. (Example) Figure 1 As shown, the MOS device includes a P-well. The parasitic capacitance of the MOS device mainly consists of the following parts: the parasitic capacitance from the gate 101 to the source / drain contact 102 (Cco), the parasitic capacitance from the gate 101 to the interconnect metal 103 (Cm), and the parasitic capacitance from the gate 101 to the source / drain doped region 104 (Cf). Cf is included in the device model; Cm can be accurately measured using a test structure with passive drain contact holes; the Cco capacitance value is related to the number of source / drain contact holes 102. Obtaining the Cco capacitance value corresponding to any number of source / drain contact holes within the design rules is particularly important in practical circuit design.

[0004] A common method for extracting the parasitic capacitance from the gate to the source / drain contacts is to determine the relationship between the Cco capacitance and the number of source / drain contacts by varying the number of source / drain contacts on the doped regions of a normal MOS structure. However, this method requires a large number of test structures and occupies a large layout area. Summary of the Invention

[0005] One of the objectives of this invention is to provide a test system and test method for MOS devices, which can test the parasitic capacitance from the gate to the source / drain contact hole using a small number of test structures, and the test system has a simple structure, which helps to save layout area.

[0006] To achieve the above objectives, the present invention provides a test system for a MOS device, used to test the parasitic capacitance from the gate to the source / drain contact in the MOS device, wherein the MOS device includes an injection well of a second conductivity type. The test system includes a multi-gate test structure and an auxiliary test structure. The multi-gate test structure includes a first injection well located in a substrate, the first injection well being an injection well of a first conductivity type opposite to the second conductivity type; a plurality of spaced-apart main gates are formed above the first injection well; a predetermined number of first source / drain contact holes are formed on the substrate on both sides of each main gate. The auxiliary test structure includes a second injection well located in a substrate, the second injection well being an injection well of the first conductivity type; a plurality of spaced-apart auxiliary gates are formed above the second injection well; a predetermined number of second source / drain contact holes are formed on the substrate on both sides of each auxiliary gate; one auxiliary gate corresponds to one main gate, and the number of second source / drain contact holes on both sides of each auxiliary gate is different from the number of first source / drain contact holes on both sides of the corresponding main gate.

[0007] Optionally, the number of first source-drain contact holes on both sides of a portion of the main gate may differ from the number of first source-drain contact holes on both sides of the remaining main gate, and / or, the number of second source-drain contact holes on both sides of a portion of the auxiliary gate may differ from the number of second source-drain contact holes on both sides of the remaining auxiliary gate.

[0008] Optionally, a first source / drain doped region is formed in the substrate on both sides of the main gate, the first source / drain doped region is located at the top of the first implantation well, and the first source / drain contact hole is located above the substrate of the first source / drain doped region; a second source / drain doped region is formed in the substrate on both sides of the auxiliary gate, the second source / drain doped region is located at the top of the second implantation well, and the second source / drain contact hole is located above the substrate of the second source / drain doped region; both the first source / drain doped region and the second source / drain doped region are of the first conductivity type.

[0009] Optionally, the plurality of main gates extend in the same direction, and a first source / drain doped region in the substrate between two adjacent main gates serves as a common source / drain doped region; the plurality of auxiliary gates extend in the same direction, and a second source / drain doped region in the substrate between two adjacent auxiliary gates serves as a common source / drain doped region.

[0010] This invention also provides a testing method for a MOS device, used to test the parasitic capacitance from the gate to the source / drain contact in the MOS device, wherein the MOS device includes an injection well of a second conductivity type. The testing method includes:

[0011] The aforementioned test system is provided, which includes a multi-gate test structure and an auxiliary test structure;

[0012] The multiple main gates in the multi-gate test structure are combined to form multiple main gate combinations, and the capacitance test from the main gate to the first source-drain contact hole is performed on the multiple main gate combinations to obtain multiple first capacitances.

[0013] Multiple auxiliary gates in the auxiliary test structure are combined to form multiple auxiliary gate combinations. Capacitance tests from the auxiliary gates to the second source / drain contact holes are performed on each of the multiple auxiliary gate combinations to obtain multiple second capacitors. Each auxiliary gate combination corresponds to one main gate combination, and each second capacitor corresponds to one first capacitor.

[0014] Subtracting each of the first capacitors from its corresponding second capacitor yields multiple parasitic capacitors, each parasitic capacitor corresponding to a number of source / drain contact holes; and

[0015] By fitting the parasitic capacitances and the corresponding number of source / drain contact holes, the relationship between the parasitic capacitance from the gate to the source / drain contact hole and the number of source / drain contact holes is obtained.

[0016] Optionally, for the corresponding main gate combination and auxiliary gate combination, the number of first source-drain contact holes corresponding to the main gate combination is A, the number of second source-drain contact holes corresponding to the auxiliary gate combination is B, and the number of source-drain contact holes corresponding to the parasitic capacitances of the main gate combination and the auxiliary gate combination is the value of A minus B.

[0017] Optionally, a first source / drain doped region is formed in the substrate on both sides of each main gate, the plurality of main gates extend in the same direction, and the first source / drain doped region in the substrate between two adjacent main gates is a shared source / drain doped region; a second source / drain doped region is formed in the substrate on both sides of each auxiliary gate, the plurality of auxiliary gates extend in the same direction, and the second source / drain doped region in the substrate between two adjacent auxiliary gates is a shared source / drain doped region.

[0018] Optionally, when a main gate assembly includes two or more main gates, if there is a common first source / drain doped region between the two or more main gates, the number of first source / drain contact holes corresponding to the main gate assembly is the sum of the number of first source / drain contact holes on the common first source / drain doped region and the non-common first source / drain doped region corresponding to the main gate assembly; if there is no common first source / drain doped region between the two or more main gates, the number of first source / drain contact holes corresponding to the main gate assembly is the sum of the number of first source / drain contact holes corresponding to each main gate in the main gate assembly.

[0019] Optionally, when an auxiliary gate assembly includes two or more auxiliary gates, if there is a shared second source / drain doped region between the two or more auxiliary gates, the number of second source / drain contact holes corresponding to the auxiliary gate assembly is the sum of the number of second source / drain contact holes on the shared second source / drain doped region and the non-shared second source / drain doped region corresponding to the auxiliary gate assembly; if there is no shared second source / drain doped region between the two or more auxiliary gates, the number of second source / drain contact holes corresponding to the auxiliary gate assembly is the sum of the number of second source / drain contact holes corresponding to each auxiliary gate in the auxiliary gate assembly.

[0020] Optionally, when performing the capacitance test from the main gate to the first source-drain contact hole for each of the main gate assemblies, a voltage is applied to all the main gates in the main gate assembly, and the capacitance between the main gate and the first source-drain contact hole is measured to obtain the first capacitance;

[0021] In the method of performing capacitance testing from the auxiliary gate to the second source-drain contact hole for each of the auxiliary gate assemblies, a voltage is applied to all the auxiliary gates in the auxiliary gate assembly, and the capacitance between the auxiliary gate and the second source-drain contact hole is measured to obtain the second capacitance.

[0022] The test system and method for MOS devices of the present invention are used to test the parasitic capacitance from the gate to the source / drain contact via in a MOS device. In the test system and method, the multi-gate test structure includes a first injection well located in the substrate. The first injection well is a first conductivity type injection well. Multiple main gates are formed on the top of the first injection well at intervals. A predetermined number of first source / drain contact vias are formed on the substrate on both sides of each main gate. The auxiliary test structure includes a second injection well located in the substrate. The second injection well is a first conductivity type injection well. Multiple auxiliary gates are formed on the top of the second injection well at intervals. A predetermined number of first source / drain contact vias are formed on the substrate on both sides of each auxiliary gate. A predetermined number of second source-drain contact holes are formed on the top. One auxiliary gate corresponds to one main gate. The number of second source-drain contact holes on both sides of an auxiliary gate is different from the number of first source-drain contact holes on both sides of the corresponding main gate. In this way, based on a pair of multi-gate test structures and auxiliary test structures, the relationship between the parasitic capacitance from the gate to the source-drain contact hole and the number of source-drain contact holes can be extracted by changing the number of main gates, the number of auxiliary gates, and the number of source-drain contact holes. The number of test structures used is small, and the multi-gate test structure and auxiliary test structure in the test system are simple, which greatly saves the layout area occupied by the test system. Attached Figure Description

[0023] Figure 1 This is a cross-sectional schematic diagram of an N-type MOS device.

[0024] Figure 2This is a cross-sectional schematic diagram of a multi-gate test structure according to an embodiment of the present invention.

[0025] Figure 3 This is a planar schematic diagram of a multi-gate test structure according to an embodiment of the present invention.

[0026] Figure 4 This is a planar schematic diagram of an auxiliary testing structure according to an embodiment of the present invention.

[0027] Figure 5 This is a flowchart of a testing method for a MOS device according to an embodiment of the present invention.

[0028] Figure 6 This is a diagram showing the relationship between the parasitic capacitance from the gate to the source / drain contact hole and the number of source / drain contact holes according to an embodiment of the present invention.

[0029] Explanation of reference numerals in the attached figures:

[0030] ( Figure 1 101 - Gate; 102 - Source / drain contact; 103 - Interconnect metal; 104 - Source / drain doped region;

[0031] ( Figures 2 to 4 201-Main gate; 201a-First main gate; 201b-Second main gate; 201c-Third main gate; 202-First source / drain contact hole; 203-First implantation well; 204-First source / drain doped region; 205-Sidewall; 206-Gate oxide layer; 207-Gate contact hole; 208-Interconnect metal; 301-Auxiliary gate; 301a-First auxiliary gate; 301b-Second auxiliary gate; 301c-Third auxiliary gate; 302-Second source / drain contact hole; 303-Second source / drain doped region. Detailed Implementation

[0032] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed account of the test system and test method for the MOS device proposed in this invention. The advantages and features of this application will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this application.

[0033] This application provides a test system for a MOS device (hereinafter referred to as the "test system"), which is used to test the parasitic capacitance from the gate to the source / drain contact in the MOS device. The MOS device includes an injection well of a second conductivity type, and the test system includes a multi-gate test structure and an auxiliary test structure.

[0034] Figure 2 This is a cross-sectional schematic diagram of a multi-gate test structure according to an embodiment of the present invention. Figure 3This is a planar schematic diagram (layout diagram) of a multi-gate test structure according to an embodiment of the present invention. Figure 2 and Figure 3 As shown, the multi-gate test structure includes a first injection well 203 located in the substrate. The first injection well 203 is a first conductivity type injection well, which is opposite to the second conductivity type. A plurality of main gates 201 are formed on the first injection well 203 at intervals. A set number of first source / drain contact holes 202 are formed on the substrate on both sides of each main gate 201.

[0035] refer to Figures 2 to 3 As shown, first source / drain doped regions 204 are formed in the substrate on both sides of the main gate 201. The first source / drain doped regions 204 are located on top of the first implantation well 203, and the first source / drain contact holes 202 are located above the substrate of the first source / drain doped regions 204. The first source / drain doped regions 204 are of a first conductivity type.

[0036] A gate oxide layer 206 may be formed between the main gate 201 and the substrate, and sidewalls 205 may be formed on the sidewalls of the main gate 201 and the gate oxide layer 206. A gate contact hole 207 may be formed on the main gate 201, and an interconnect metal 208 may be formed above the gate contact hole 207 and the first source / drain contact hole 202.

[0037] Figure 4 This is a planar schematic diagram of an auxiliary testing structure according to an embodiment of the present invention. Figure 4 As shown, the auxiliary test structure includes a second injection well (not shown) located in the substrate. The second injection well is a first conductivity type injection well. A plurality of auxiliary gates 301 are formed above the second injection well at intervals. A predetermined number of second source / drain contact holes 302 are formed above the substrate on both sides of each auxiliary gate 301. In this application, one auxiliary gate 301 corresponds to one main gate 201, and the number of second source / drain contact holes 302 on both sides of each auxiliary gate 301 is different from the number of first source / drain contact holes 202 on both sides of the corresponding main gate 201.

[0038] refer to Figure 4 As shown, a second source / drain doped region 303 is formed in the substrate on both sides of the auxiliary gate 301. The second source / drain doped region 303 is located on top of the second implantation well. The second source / drain contact hole 302 is located above the substrate of the second source / drain doped region 303. The conductivity type of the second source / drain doped region 303 is the first conductivity type.

[0039] It should be noted that the size of the main gate 201 and the auxiliary gate 301 can be the same, and the size of the first source-drain contact hole 202 and the second source-drain contact hole 302 can be the same. This helps to improve the testing accuracy of parasitic capacitance. The number distribution of the second source-drain contact hole 302 in the auxiliary test structure is different from the number distribution of the first source-drain contact hole 202 in the multi-gate test structure. Other settings in the auxiliary test structure can refer to the multi-gate test structure.

[0040] The test system of this application can be used to test the parasitic capacitance from the gate to the source / drain contact of an N-type MOS device, and it can also be used to test the parasitic capacitance from the gate to the source / drain contact of a P-type MOS device. As an example, when testing an N-type MOS device, both the first injection well 203 and the second injection well are N-wells, and both the first source / drain doped region 204 and the second source / drain doped region 303 are N-type injection regions; when testing a P-type MOS device, both the first injection well 203 and the second injection well are P-wells, and both the first source / drain doped region 204 and the second source / drain doped region 303 are P-type injection regions.

[0041] To reduce the footprint of the test system, refer to Figures 2 to 4 As shown, multiple main gates 201 extend in the same direction, and the first source / drain doped region 204 in the substrate between two adjacent main gates 201 serves as a common source / drain doped region. Multiple auxiliary gates 301 extend in the same direction, and the second source / drain doped region 204 in the substrate between two adjacent auxiliary gates 301 serves as a common source / drain doped region, but not limited thereto.

[0042] In this application, the number of first source-drain contact holes on both sides of a portion of the main gate 201 differs from the number of first source-drain contact holes on both sides of the remaining main gate 201, and / or, the number of second source-drain contact holes on both sides of a portion of the auxiliary gate 301 differs from the number of second source-drain contact holes on both sides of the remaining auxiliary gate 301. Thus, when multiple main gates 201 and multiple auxiliary gates 301 are subsequently combined, a larger number of combinations can be obtained, thereby obtaining a larger number of data sets on the parasitic capacitance and the number of source-drain contact holes. This is beneficial to improving the accuracy of the obtained relationship between the parasitic capacitance from the gate to the source-drain contact holes and the number of source-drain contact holes, that is, it is beneficial to improve the accuracy of the obtained parasitic capacitance from the gate to the source-drain contact holes.

[0043] Specifically, the number of first source-drain contact holes on both sides of each main gate 201 can be the same, and the number of second source-drain contact holes on both sides of some of the auxiliary gates 301 can be different from the number of second source-drain contact holes on both sides of the remaining auxiliary gates 301; or, the number of first source-drain contact holes on both sides of some of the main gates 201 can be different from the number of first source-drain contact holes on both sides of the remaining main gates 201, while the number of second source-drain contact holes on both sides of each auxiliary gate 301 can be the same; or, the number of first source-drain contact holes on both sides of some of the main gates 201 can be different from the number of first source-drain contact holes on both sides of the remaining main gates 201, and the number of second source-drain contact holes on both sides of some of the auxiliary gates 301 can be different from the number of second source-drain contact holes on both sides of the remaining auxiliary gates 301.

[0044] The following description uses an example of a multi-gate test structure with three main gates 201 and three auxiliary gates 301 in the auxiliary test structure, but it is not limited to this. The number of main gates 201 in the multi-gate test structure and the number of auxiliary gates 301 in the auxiliary test structure can be set according to actual needs.

[0045] As an example, the multiple main gates 201 include a first main gate 201a, a second main gate 201b, and a third main gate 201c. The number of first source / drain contact holes 202 on the left side of the first main gate 201a is four. The first source / drain doped region 204 between the first main gate 201a and the second main gate 201b, and the first source / drain doped region 204 between the second main gate 201b and the third main gate 201c are all shared first source / drain doped regions. The number of first source / drain contact holes 202 on the shared first source / drain doped regions is four. The number of first source / drain contact holes 202 on the right side of the third main gate 201c is four.

[0046] The multiple auxiliary gates 301 include a first auxiliary gate 301a, a second auxiliary gate 301b, and a third auxiliary gate 301c. The number of second source / drain contact holes 302 on the left side of the first auxiliary gate 301a is 4. The second source / drain doped region 303 between the first auxiliary gate 301a and the second auxiliary gate 301b, and the second source / drain doped region 303 between the second auxiliary gate 301b and the third auxiliary gate 301c are all shared second source / drain doped regions. The number of second source / drain contact holes 302 on the shared second source / drain doped regions is 0. The number of second source / drain contact holes 302 on the right side of the third auxiliary gate 301c is 0.

[0047] The first main gate 201a, the second main gate 201b, and the third main gate 201c correspond one-to-one with the first auxiliary gate 301a, the second auxiliary gate 301b, and the third auxiliary gate 301c. The number of first source-drain contact holes 202 provided on both sides of the first main gate 201a is 8, that is, the number of first source-drain contact holes 202 corresponding to the first main gate 201a is 8, and the number of second source-drain contact holes 202 provided on both sides of the first auxiliary gate 301a corresponding to the first main gate 201a is 4. The number of first source-drain contact holes 202 provided on both sides of the second main gate 201b is 8, and the number of second source-drain contact holes 302 provided on both sides of the second auxiliary gate 301b corresponding to the second main gate 201b is 0.

[0048] This application provides a test method for a MOS device (hereinafter referred to as the "test method"), which uses the above-described test system to test the parasitic capacitance from the gate to the source / drain contact in the MOS device.

[0049] Figure 5 This is a flowchart of a testing method for a MOS device according to an embodiment of the present invention. Figure 5 As shown, the test method includes:

[0050] S1, a test system for the above-mentioned MOS device is provided, the test system including a multi-gate test structure and an auxiliary test structure;

[0051] S2, combine the multiple main gates in the multi-gate test structure to form multiple main gate combinations, and perform capacitance tests from the main gate to the first source-drain contact hole on the multiple main gate combinations to obtain multiple first capacitors;

[0052] S3, the multiple auxiliary gates in the auxiliary test structure are combined to form multiple auxiliary gate combinations, and the capacitance test from the auxiliary gate to the second source / drain contact hole is performed on the multiple auxiliary gate combinations to obtain multiple second capacitors; one auxiliary gate combination corresponds to one main gate combination, and one second capacitor corresponds to one first capacitor;

[0053] S4, subtract each of the first capacitors from the corresponding second capacitors to obtain multiple parasitic capacitors, each of the parasitic capacitors corresponding to one source-drain contact hole number;

[0054] S5, fit the multiple parasitic capacitances and the corresponding number of source / drain contact holes to obtain the relationship between the parasitic capacitance from the gate to the source / drain contact hole and the number of source / drain contact holes.

[0055] It should be understood that, although Figure 5The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 5 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0056] The following combination Figures 2 to 4 The test method for the MOS device of this application is described.

[0057] In step S1, referring to the above, the test system includes a multi-gate test structure and an auxiliary test structure. The auxiliary gate 301 in the auxiliary test structure corresponds one-to-one with the main gate 201 in the multi-gate test structure. The number of second source-drain contact holes 302 on both sides of each auxiliary gate 301 is different from the number of first source-drain contact holes 202 on both sides of the corresponding main gate 201.

[0058] As an example, the number of first source-drain contact holes 202 provided on both sides of the first main gate 201a is 8, and the number of second source-drain contact holes 202 provided on both sides of the first auxiliary gate 301a corresponding to the first main gate 201a is 4; the number of first source-drain contact holes 202 provided on both sides of the second main gate 201b is 8, and the number of second source-drain contact holes 302 provided on both sides of the second auxiliary gate 301b corresponding to the second main gate 201b is 0.

[0059] like Figures 2 to 4 As shown, a first source / drain doped region 204 is formed in the substrate on both sides of each main gate 201, and a second source / drain doped region 303 is formed in the substrate on both sides of each auxiliary gate 301. The plurality of main gates 201 can extend in the same direction, and the first source / drain doped regions 204 in the substrate between two adjacent main gates 201 can be shared source / drain doped regions; the plurality of auxiliary gates 301 can extend in the same direction, and the second source / drain doped regions 303 in the substrate between two adjacent auxiliary gates 301 can be shared source / drain doped regions. This helps to save layout area, but is not limited to this.

[0060] In step S2, the multiple main gates 201 in the multi-gate test structure are first combined to form multiple main gate combinations. Then, the capacitance test from the main gate 201 to the first source-drain contact hole 202 is performed on the multiple main gate combinations to obtain multiple first capacitors.

[0061] When a main gate assembly includes only one main gate 201, the number of first source / drain contact holes corresponding to the main gate assembly is the number of first source / drain contact holes 202 disposed on both sides of the main gate 201. When a main gate assembly includes two or more main gates 201, if there is a shared first source / drain doped region 204 between the two or more main gates 201, the number of first source / drain contact holes corresponding to the main gate assembly is the sum of the number of first source / drain contact holes 202 on the shared first source / drain doped region and the non-shared first source / drain doped region corresponding to the main gate assembly; if there is no shared first source / drain doped region between the two or more main gates, the number of first source / drain contact holes corresponding to the main gate assembly is the sum of the number of first source / drain contact holes 202 corresponding to each main gate 201 in the main gate assembly.

[0062] As an example, refer to Figure 3 As shown, the multi-gate test structure includes three main gates 201. The main gate combination formed by combining multiple main gates 201 can include: (1) a first main gate combination, which includes only the first main gate 201a, and the number of corresponding first source / drain contact holes 202 is 8; (2) a second main gate combination, which includes only the second main gate 201b, and the number of corresponding first source / drain contact holes 202 is 8; (3) a third main gate combination, which includes only the third main gate 201c, and the number of corresponding first source / drain contact holes 202 is 8; (4) a fourth main gate combination, which includes the first main gate 201a and the second main gate 201b. At this time, there is a shared first source / drain doped region between the two main gates. The number of first source / drain contact holes 202 on the shared first source / drain doped region is 4. The corresponding two non-shared first source / drain doped regions (i.e., the first main source / drain doped regions) are 4. The number of first source / drain contact holes 202 on the first source / drain doped region to the left of gate 201a and the first source / drain doped region to the right of the second main gate 201b is 4, so the number of first source / drain contact holes 202 corresponding to the fourth main gate combination is 12; (5) the fifth main gate combination includes the first main gate 201a and the third main gate 201c. At this time, there is no shared source / drain doped region between the two main gates, and the number of first source / drain contact holes 202 corresponding to it is 16; (6) the sixth main gate combination includes the second main gate 201b and the third main gate 201c, and the number of first source / drain contact holes 202 corresponding to it is 12; (7) the seventh main gate combination includes the first main gate 201a, the second main gate 201b and the third main gate 201c, and the number of first source / drain contact holes 202 corresponding to it is 16; but not limited to this.

[0063] When performing a capacitance test on each main gate assembly from the main gate 201 to the first source-drain contact 202, a voltage is applied to all the main gates in the main gate assembly, and the capacitance between the main gate 201 and the first source-drain contact 202 is measured to obtain a first capacitance. Specifically, one first capacitance is obtained for each main gate assembly, meaning one main gate assembly corresponds to one first capacitance.

[0064] In step S3, the multiple auxiliary gates 301 in the auxiliary test structure are first combined to form multiple auxiliary gate combinations, and then the capacitance test from the auxiliary gate 301 to the second source-drain contact hole 302 is performed on the multiple auxiliary gate combinations to obtain multiple second capacitors.

[0065] In this configuration, one auxiliary gate assembly corresponds to one main gate assembly. For the corresponding auxiliary gate assembly and main gate assembly, the auxiliary gate 301 in the auxiliary gate assembly corresponds one-to-one with the main gate 201 in the main gate assembly, and one second capacitor corresponds to one first capacitor.

[0066] When an auxiliary gate assembly includes only one auxiliary gate 301, the number of second source / drain contact holes corresponding to the auxiliary gate assembly is the number of second source / drain contact holes 302 disposed on both sides of the auxiliary gate 301. When an auxiliary gate assembly includes two or more auxiliary gates 301, if there is a shared second source / drain heavily doped region 303 between the two or more auxiliary gates 301, then the number of second source / drain contact holes corresponding to the auxiliary gate assembly is the sum of the number of second source / drain contact holes 302 on the shared second source / drain doped region and the non-shared second source / drain doped region corresponding to the auxiliary gate assembly; if there is no shared second source / drain doped region between the two or more auxiliary gates 301, then the number of second source / drain contact holes corresponding to the auxiliary gate assembly is the sum of the number of second source / drain contact holes 302 corresponding to each auxiliary gate 301 in the auxiliary gate assembly.

[0067] As an example, refer to Figure 4As shown, the auxiliary gate 301 in the auxiliary test structure includes three auxiliary gates 301. The auxiliary gate combination formed by combining the multiple auxiliary gates 301 can include: (1) a first auxiliary gate combination, corresponding to the first main gate combination, including a first auxiliary gate 301a, and the number of corresponding second source / drain contact holes 302 is 4; (2) a second auxiliary gate combination, corresponding to the second main gate combination, including a second auxiliary gate 301b, and the number of corresponding second source / drain contact holes 302 is 0; (3) a third auxiliary gate combination, corresponding to the third main gate combination, including a third auxiliary gate 301c, and the number of corresponding second source / drain contact holes 302 is 0; (4) a fourth auxiliary gate combination, corresponding to the fourth main gate combination, including a first auxiliary gate 301a, a second auxiliary gate 301b, a third auxiliary gate 301c, and the number of corresponding second source / drain contact holes 302 is 0; (5) The fifth auxiliary gate assembly, corresponding to the fifth main gate assembly, includes the first auxiliary gate 301a and the third auxiliary gate 301c, and the number of the corresponding second source / drain contact holes 302 is 4; (6) The sixth auxiliary gate assembly, corresponding to the sixth auxiliary gate assembly, includes the second auxiliary gate 301b and the third auxiliary gate 301c, and the number of the corresponding second source / drain contact holes 302 is 0; (7) The seventh auxiliary gate assembly, corresponding to the seventh main gate assembly, includes the first auxiliary gate 301a, the second auxiliary gate 301b and the third auxiliary gate 301c, and the number of the corresponding second source / drain contact holes 302 is 4; but not limited to these.

[0068] When performing a capacitance test on each of the auxiliary gate 301 to the second source-drain contact 302, a voltage is applied to all the auxiliary gates 301 in the auxiliary gate assembly, and the capacitance between the auxiliary gate 301 and the second source-drain contact 302 is measured to obtain the second capacitance.

[0069] Specifically, testing one auxiliary gate combination yields one second capacitor; that is, one auxiliary gate combination corresponds to one second capacitor. The first and second capacitors obtained from testing the corresponding main gate combination and auxiliary gate combination are corresponding to each other.

[0070] In step S4, each of the first capacitors is subtracted from the corresponding second capacitor to obtain multiple parasitic capacitors, and each parasitic capacitor corresponds to one source-drain contact hole.

[0071] For the corresponding main gate combination and auxiliary gate combination, the number of first source-drain contact holes 202 corresponding to the main gate combination is A, the number of second source-drain contact holes 302 corresponding to the auxiliary gate combination is B, and the number of source-drain contact holes corresponding to the parasitic capacitances of the main gate combination and the auxiliary gate combination is the value of A minus B.

[0072] As an example, subtracting the first capacitance obtained from testing the first main gate assembly from the second capacitance obtained from testing the first auxiliary gate assembly yields the first parasitic capacitance, which corresponds to 8-4=4 source-drain contact holes; subtracting the first capacitance obtained from testing the second main gate assembly from the second capacitance obtained from testing the second auxiliary gate assembly yields the second parasitic capacitance, which corresponds to 8-0=8 source-drain contact holes; subtracting the first capacitance obtained from testing the third main gate assembly from the second capacitance obtained from testing the third auxiliary gate assembly yields the third parasitic capacitance, which corresponds to 8-0=4 source-drain contact holes; subtracting the first capacitance obtained from testing the fourth main gate assembly from the second capacitance obtained from testing the fourth auxiliary gate assembly yields the third parasitic capacitance; subtracting the first capacitance obtained from testing the fourth main gate assembly from the second capacitance obtained from testing the fourth auxiliary gate assembly yields the third parasitic capacitance. The fourth parasitic capacitance is obtained by subtracting the first capacitance obtained from the fifth main gate assembly from the second capacitance obtained from the fifth auxiliary gate assembly. The fifth parasitic capacitance is obtained by subtracting the first capacitance obtained from the fifth main gate assembly from the second capacitance obtained from the fifth auxiliary gate assembly. The fifth parasitic capacitance is obtained by subtracting the first capacitance obtained from the sixth main gate assembly from the second capacitance obtained from the sixth auxiliary gate assembly. The sixth parasitic capacitance is obtained by subtracting the first capacitance obtained from the seventh main gate assembly from the second capacitance obtained from the seventh auxiliary gate assembly. The seventh ...

[0073] As can be seen, since the number of second source-drain contact holes 302 on both sides of an auxiliary gate 301 is different from the number of first source-drain contact holes 202 on both sides of the corresponding main gate 201, the number of first source-drain contact holes on both sides of a portion of the main gate 201 is different from the number of first source-drain contact holes on both sides of the remaining main gate 201, and / or, the number of second source-drain contact holes on both sides of a portion of the auxiliary gate 301 is different from the number of second source-drain contact holes on both sides of the remaining auxiliary gate 301, at least a portion of the parasitic capacitances obtained correspond to a different number of source-drain contact holes than the number of source-drain contact holes corresponding to the remaining parasitic capacitances. Thus, based on a one-to-many gate test structure and an auxiliary test structure, by changing the number of main gates 201 and the number of auxiliary gates 301, the number of source-drain contact holes corresponding to the obtained parasitic capacitances can be changed, so that the relationship between the parasitic capacitance from the gate to the source-drain contact hole and the number of source-drain contact holes can be extracted subsequently.

[0074] After obtaining multiple parasitic capacitances, step S5 is executed to fit the multiple parasitic capacitances and the corresponding number of source / drain contact holes to obtain the relationship between the parasitic capacitance from the gate to the source / drain contact holes and the number of source / drain contact holes. Fitting methods known in the art can be used to fit the multiple parasitic capacitances and the corresponding number of source / drain contact holes.

[0075] Figure 6 This is a diagram showing the relationship between the parasitic capacitance from the gate to the source / drain contact and the number of source / drain contact holes according to an embodiment of the present invention. Figure 6 As shown, the parasitic capacitance (Cco) from the gate to the source / drain contact can be linearly related to the number of source / drain contacts (N), but it is not limited to this. By using the relationship between the parasitic capacitance and the number of source / drain contacts, the capacitance value of the parasitic capacitance from the gate to the source / drain contact can be obtained for any number of source / drain contacts within the design rules of the MOS device.

[0076] The test system and test method for MOS devices disclosed in this application are used to test the parasitic capacitance from the gate to the source / drain contact vias in a MOS device. In the test system and test method, the multi-gate test structure includes a first injection well 203 located in the substrate. The first injection well 203 is a first conductivity type injection well. A plurality of main gates 201 are formed above the first injection well 203 at intervals. A predetermined number of first source / drain contact vias 202 are formed on both sides of the substrate above each main gate 201. The auxiliary test structure includes a second injection well located in the substrate. The second injection well is a first conductivity type injection well. A plurality of auxiliary gates 301 are formed above the second injection well at intervals. A predetermined number of first source / drain contact vias 202 are formed on both sides of each auxiliary gate 301. A predetermined number of second source / drain contact holes 302 are formed on the substrate. One auxiliary gate 301 corresponds to one main gate 201. The number of second source / drain contact holes 302 on both sides of an auxiliary gate 301 is different from the number of first source / drain contact holes 202 on both sides of the corresponding main gate 201. In this way, based on a pair of multi-gate test structures and auxiliary test structures, the relationship between the parasitic capacitance from the gate to the source / drain contact hole and the number of source / drain contact holes can be extracted by changing the number of main gates, the number of auxiliary gates, and the number of source / drain contact holes. The number of test structures used is small, and the structure of the multi-gate test structure and auxiliary test structure in the test system is simple, which greatly saves the layout area occupied by the test system.

[0077] It should be noted that this application specification adopts a progressive description approach. The test methods for MOS devices described later focus on the differences between them and the test systems for MOS devices described earlier. For the same or similar parts, refer to each other.

[0078] Although this application uses terms such as "first," "second," and "third" to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part, and are not used to indicate logical or sequential relationships between various elements, components, areas, layers, or parts. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or part discussed in this application may be referred to as the second element, component, area, layer, or part.

[0079] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A test system for a MOS device, used to test the parasitic capacitance from the gate to the source / drain contact in the MOS device, said MOS device comprising an injection well of a second conductivity type, characterized in that, The testing system includes a multi-gate test structure and an auxiliary test structure; The multi-gate test structure includes a first injection well located in the substrate. The first injection well is an injection well of a first conductivity type, which is opposite to the second conductivity type. A plurality of main gates are formed above the first injection well at intervals. A first source-drain doped region of the first conductivity type is formed in the substrate on both sides of the main gate. The first source-drain doped region is located at the top of the first injection well. A set number of first source-drain contact holes are formed above the first source-drain doped region on both sides of each main gate. The auxiliary test structure includes a second injection well located in the substrate. The second injection well is an injection well of the first conductivity type. A plurality of auxiliary gates are formed above the second injection well at intervals. Second source-drain doped regions of the first conductivity type are formed in the substrate on both sides of the auxiliary gate. The second source-drain doped regions are located at the top of the second injection well. A set number of second source-drain contact holes are formed above the second source-drain doped regions on both sides of each auxiliary gate. Each auxiliary gate corresponds to one main gate, and the number of second source-drain contact holes on both sides of each auxiliary gate is different from the number of first source-drain contact holes on both sides of the corresponding main gate. A portion of the number of first source-drain contact holes on both sides of the main gate differs from the remaining number of first source-drain contact holes on both sides of the main gate, and / or a portion of the number of second source-drain contact holes on both sides of the auxiliary gate differs from the remaining number of second source-drain contact holes on both sides of the auxiliary gate.

2. The testing system as described in claim 1, characterized in that, The plurality of main gates extend in the same direction, and the first source / drain doped region in the substrate between two adjacent main gates serves as a common source / drain doped region; the plurality of auxiliary gates extend in the same direction, and the second source / drain doped region in the substrate between two adjacent auxiliary gates serves as a common source / drain doped region.

3. A testing method for a MOS device, used to test the parasitic capacitance from the gate to the source / drain contact in the MOS device, wherein the MOS device includes an injection well of a second conductivity type, characterized in that... The testing method includes: A test system as described in any one of claims 1 to 2 is provided, the test system comprising a multi-gate test structure and an auxiliary test structure; The multiple main gates in the multi-gate test structure are combined to form multiple main gate combinations, and the capacitance test from the main gate to the first source-drain contact hole is performed on the multiple main gate combinations to obtain multiple first capacitances. Multiple auxiliary gates in the auxiliary test structure are combined to form multiple auxiliary gate combinations. Capacitance tests from the auxiliary gates to the second source / drain contact holes are performed on each of the multiple auxiliary gate combinations to obtain multiple second capacitors. Each auxiliary gate combination corresponds to one main gate combination, and each second capacitor corresponds to one first capacitor. Subtracting each first capacitor from its corresponding second capacitor yields multiple parasitic capacitances, each parasitic capacitance corresponding to a number of source-drain contact holes. For corresponding main gate and auxiliary gate combinations, the number of first source-drain contact holes corresponding to the main gate combination is A, the number of second source-drain contact holes corresponding to the auxiliary gate combination is B, and the number of source-drain contact holes corresponding to the parasitic capacitances of the main gate and auxiliary gate combinations is A minus B. By fitting the parasitic capacitances and the corresponding number of source / drain contact holes, the relationship between the parasitic capacitance from the gate to the source / drain contact hole and the number of source / drain contact holes is obtained.

4. The test method as described in claim 3, characterized in that, A first source / drain doped region of the first conductivity type is formed in the substrate on both sides of each main gate. The plurality of main gates extend in the same direction, and the first source / drain doped regions in the substrate between two adjacent main gates are shared source / drain doped regions. A second source / drain doped region of the first conductivity type is formed in the substrate on both sides of each auxiliary gate. The plurality of auxiliary gates extend in the same direction, and the second source / drain doped regions in the substrate between two adjacent auxiliary gates are shared source / drain doped regions.

5. The test method as described in claim 3, characterized in that, When a main gate assembly includes two or more main gates, if there is a common first source / drain doped region between the two or more main gates, the number of first source / drain contact holes corresponding to the main gate assembly is the sum of the number of first source / drain contact holes on the common first source / drain doped region and the non-common first source / drain doped region corresponding to the main gate assembly. If there is no shared first source / drain doped region between the two or more main gates, then the number of first source / drain contact holes corresponding to the main gate combination is the sum of the number of first source / drain contact holes corresponding to each main gate in the main gate combination.

6. The test method as described in claim 3, characterized in that, When an auxiliary gate assembly includes two or more auxiliary gates, if there is a common second source / drain doped region between the two or more auxiliary gates, the number of second source / drain contact holes corresponding to the auxiliary gate assembly is the sum of the number of second source / drain contact holes on the common second source / drain doped region and the non-common second source / drain doped region corresponding to the auxiliary gate assembly; If there is no shared second source / drain doped region between the two or more auxiliary gates, then the number of second source / drain contact holes corresponding to the auxiliary gate combination is the sum of the number of second source / drain contact holes corresponding to each auxiliary gate in the auxiliary gate combination.

7. The test method as described in claim 3, characterized in that, When performing a capacitance test on each of the main gate assemblies from the main gate to the first source-drain contact, a voltage is applied to all the main gates in the main gate assembly, and the capacitance between the main gate and the first source-drain contact is measured to obtain the first capacitance. In the method of performing capacitance testing from the auxiliary gate to the second source-drain contact hole for each of the auxiliary gate assemblies, a voltage is applied to all the auxiliary gates in the auxiliary gate assembly, and the capacitance between the auxiliary gate and the second source-drain contact hole is measured to obtain the second capacitance.

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