Imaging Element, Stacked Imaging Element, and Solid-State Imaging Device

Abstract

The present invention relates to an imaging element, a stacked imaging element, and a solid-state imaging device. Among them, the imaging element may include: a photoelectric conversion unit, the photoelectric conversion unit including a stacked first electrode, a photoelectric conversion layer, and a second electrode, wherein the photoelectric conversion unit further includes a charge storage electrode, the charge storage electrode being arranged to be separated from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer, and the value of the dielectric constant of the insulating material included in the region between the first electrode and the charge storage electrode is higher than the value of the dielectric constant of the insulating material included in the region between the imaging element and an adjacent imaging element.

Description

[0001] This application is a divisional application of the patent application with application number 201880039926.8, application date of June 21, 2018, and invention title of "Imaging Element, Stacked Imaging Element, and Solid-State Imaging Device". Technical Field

[0002] The present invention relates to an imaging element, a stacked imaging element, and a solid-state imaging device. Background Art

[0003] An imaging element including an organic semiconductor material in a photoelectric conversion layer can perform photoelectric conversion for a specific color (wavelength band). Further, when the imaging element is used in a solid-state imaging device, this feature allows obtaining a structure including stacked sub-pixels (stacked imaging element) that is impossible in a conventional solid-state imaging device. In this structure, the sub-pixels include a combination of an on-chip color filter (OCCF) and an imaging element, and the sub-pixels are arranged two-dimensionally (for example, see Japanese Patent Laid-Open No. 2011-138927). Another advantage is that demosaicing is not required and false colors are not generated. Note that in the following description, for convenience, an imaging element including a photoelectric conversion unit provided on or above a semiconductor substrate may be referred to as a "first type of imaging element". For convenience, a photoelectric conversion element included in the first type of imaging element may be referred to as a "first type of photoelectric conversion unit". For convenience, an imaging element provided in a semiconductor substrate may be referred to as a "second type of imaging element". For convenience, a photoelectric conversion unit included in the second type of imaging element may be referred to as a "second type of photoelectric conversion unit".

[0004] Fig.102 An example of the structure of a conventional stacked imaging element (stacked solid-state imaging device) is shown. In Fig.102 the example shown, as the third photoelectric conversion unit 331 and the second photoelectric conversion unit 321 which are second type of photoelectric conversion units included in the third imaging element 330 and the second imaging element 320, they are stacked and formed in the semiconductor substrate 370. Further, a first photoelectric conversion unit 311 which is a first type of photoelectric conversion unit is disposed above the semiconductor substrate 370 (specifically, above the second imaging element 320). Here, the first photoelectric conversion unit 311 includes a first electrode 311, a photoelectric conversion layer 313 containing an organic material, and a second electrode 312. The first photoelectric conversion unit 311 is included in the first imaging element 310 which is a first type of imaging element. Based on the difference in absorption coefficients, the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 perform photoelectric conversion of blue light and red light, respectively. Further, the first photoelectric conversion unit 311 performs photoelectric conversion of, for example, green light.

[0005] The charges generated by the photoelectric conversion in the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331 are temporarily stored in the second photoelectric conversion unit 321 and the third photoelectric conversion unit 331. The vertical transistor (the gate portion 322 is shown) and the transfer transistor (the gate portion 332 is shown) transfer the charges to the second floating diffusion layer (Floating Diffusion) FD 2 and the third floating diffusion layer FD 3 . Further, the charges are output to an external reading circuit (not shown). The transistor and the floating diffusion layers FD 2 and FD 3 are also formed on the semiconductor substrate 370.

[0006] The charges generated by the photoelectric conversion in the first photoelectric conversion unit 311 are stored in the first floating diffusion layer FD formed on the semiconductor substrate 370 through the contact hole portion 361 and the wiring layer 362 1 . In addition, the first photoelectric conversion unit 311 is also connected to the gate portion 318 of the amplifying transistor through the contact hole portion 361 and the wiring layer 362, and the amplifying transistor converts the amount of charge into a voltage. Further, the first floating diffusion layer FD 1 includes a portion of the reset transistor (the gate portion 317 is shown). Note that the reference numeral 371 denotes an element isolation region. The reference numeral 372 denotes an oxide film formed on the surface of the semiconductor substrate 370. The reference numerals 376 and 381 denote interlayer insulating layers. The reference numeral 383 denotes a protective layer. The reference numeral 390 denotes an on-chip microlens.

[0007] Reference list

[0008] Patent document

[0009] Patent document 1: Japanese Patent Laid-Open No. 2011-138927 Summary of the invention

[0010] Technical problem to be solved by the present invention

[0011] Meanwhile, in the imaging element having such a structure and configuration, the charges generated by the photoelectric conversion may flow into adjacent imaging elements. A so-called blooming phenomenon may occur, and the quality of the captured video (image) may deteriorate.

[0012] Therefore, an object of the present disclosure is to provide an imaging element having a structure and configuration that is less likely to cause a deterioration in the quality of the captured video (image), a stacked imaging element including the imaging element, and a solid-state imaging device including the imaging element or the stacked imaging element.

[0013] Solution to the technical problem

[0014] Each imaging element according to the first to ninth aspects of the present disclosure for achieving this purpose includes a photoelectric conversion unit, the photoelectric conversion unit including a stacked first electrode, a photoelectric conversion layer, and a second electrode, wherein the photoelectric conversion unit further includes a charge storage electrode, the charge storage electrode being arranged to be separated from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer.

[0015] Furthermore, in the imaging element according to the first aspect, when light enters the photoelectric conversion layer and photoelectric conversion occurs in the photoelectric conversion layer, the absolute value of the electric potential applied to the portion of the photoelectric conversion layer facing the charge storage electrode is greater than the absolute value of the electric potential applied to the region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element.

[0016] Furthermore, in the imaging element according to the second aspect of the present disclosure, the width of the region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is narrower than the width of the region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element.

[0017] Furthermore, in the imaging element according to the third aspect of the present invention, a charge movement control electrode is formed in a region that faces, via an insulating layer, the region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element.

[0018] Furthermore, in the imaging element according to the fourth aspect of the present disclosure, instead of the second electrode, a charge movement control electrode is formed within the range of the region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element.

[0019] Furthermore, in the imaging element according to the fifth aspect of the present disclosure, the value of the dielectric constant of the insulating material included in the region between the first electrode and the charge storage electrode is higher than the value of the dielectric constant of the insulating material included in the region between the imaging element and an adjacent imaging element.

[0020] Furthermore, in the imaging element according to the sixth aspect of the present disclosure, the thickness of the region of the insulating layer located between the first electrode and the charge storage electrode is thinner than the thickness of the region of the insulating layer located between the imaging element and an adjacent imaging element.

[0021] Furthermore, in the imaging element according to the seventh aspect of the present disclosure, the thickness of the region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is thicker than the thickness of the region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element.

[0022] In addition, in the imaging element according to the eighth aspect of the present disclosure, the amount of fixed charge in the region of the interface between the photoelectric conversion layer and the insulating layer located between the first electrode and the charge storage electrode is less than the amount of fixed charge in the region of the interface between the photoelectric conversion layer and the insulating layer located between the imaging element and the adjacent imaging element.

[0023] In addition, in the imaging element according to the ninth aspect of the present invention, the value of the charge mobility in the region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is greater than the value of the charge mobility in the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element.

[0024] The stacked imaging element of the present disclosure for achieving the above object includes at least one imaging element according to the first to ninth aspects of the present disclosure.

[0025] The solid-state imaging device according to the first aspect of the present disclosure for achieving the above object includes a plurality of imaging elements according to the first to ninth aspects of the present disclosure. In addition, the solid-state imaging device according to the second aspect of the present invention for achieving the above object includes a plurality of stacked imaging elements according to the present invention.

[0026] Advantageous Effects of the Present Invention

[0027] In each of the imaging elements according to the first to ninth aspects of the present disclosure, the imaging elements according to the first to ninth aspects of the present disclosure included in the stacked imaging element, and the imaging elements according to the first to ninth aspects of the present disclosure included in the solid-state imaging devices according to the first and second aspects of the present disclosure (hereinafter, in some cases, the imaging elements are collectively referred to as "the imaging elements and the like of the present disclosure"), a charge storage electrode is provided which is arranged separately from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer, and when light is applied to the photoelectric conversion unit and is photoelectrically converted by the photoelectric conversion unit, charges can be stored in the photoelectric conversion layer. Therefore, it is possible to completely deplete the charge storage portion at the start of exposure to eliminate charges. This can suppress the phenomenon of deterioration of imaging quality caused by the increase in random noise due to the increase in kTC noise.

[0028] In addition, in each of an imaging element according to the first aspect of the present disclosure, an imaging element according to the first aspect of the present disclosure included in a stacked imaging element, and an imaging element according to the first aspect of the present disclosure included in a solid-state imaging device according to the first and second aspects of the present disclosure (hereinafter, in some cases, the imaging elements are collectively referred to as "imaging elements according to the first aspect of the present disclosure and the like"), when light enters the photoelectric conversion layer and photoelectric conversion occurs in the photoelectric conversion layer, the absolute value of the electric potential applied to the portion of the photoelectric conversion layer facing the charge storage electrode is greater than the absolute value of the electric potential applied to the region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element. Therefore, the charges generated by photoelectric conversion are strongly attracted to the portion of the photoelectric conversion layer facing the charge storage electrode. This can prevent the charges generated by photoelectric conversion from flowing into an adjacent imaging element, and the quality of the captured video (image) will not deteriorate.

[0029] In addition, in each of an imaging element according to the second aspect of the present disclosure, an imaging element according to the second aspect of the present disclosure included in a stacked imaging element, and an imaging element according to the second aspect of the present disclosure included in a solid-state imaging device according to the first and second aspects of the present disclosure (hereinafter, in some cases, the imaging elements are collectively referred to as "imaging elements according to the second aspect of the present disclosure and the like"), the width of the region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is narrower than the width of the region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element. In addition, in this case, the region between the first electrode and the charge storage electrode is less likely to be affected by the voltage of the second electrode (upper electrode) compared to the portion located between the imaging element and an adjacent imaging element. Therefore, the electric potential increases, and this can prevent the charges generated by photoelectric conversion from flowing into an adjacent imaging element, and the quality of the captured video (image) will not deteriorate.

[0030] In addition, in each of an imaging element according to the third aspect of the present disclosure, an imaging element according to the third aspect of the present disclosure included in a stacked imaging element, and an imaging element according to the third aspect of the present disclosure included in a solid-state imaging device according to the first and second aspects of the present disclosure (hereinafter, in some cases, the imaging elements are collectively referred to as "imaging elements according to the third aspect of the present disclosure and the like"), the charge movement control electrode is formed in a region that faces, via an insulating layer, the region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element. This can control the electric field and electric potential of the region of the photoelectric conversion layer located above the charge movement control electrode. As a result, the charge movement control electrode can prevent the charges generated by photoelectric conversion from flowing into an adjacent imaging element, and the quality of the captured video (image) will not deteriorate.

[0031] In addition, in each of an imaging element according to a fourth aspect of the present disclosure, an imaging element according to a fourth aspect of the present disclosure included in a stacked imaging element, and an imaging element according to a fourth aspect of the present disclosure included in a solid-state imaging device according to a first aspect and a second aspect of the present disclosure (hereinafter, in some cases, the imaging elements are collectively referred to as "imaging elements according to a fourth aspect of the present disclosure and the like"), a charge movement control electrode is formed instead of the second electrode on a region of the photoelectric conversion layer located between the imaging element and an adjacent imaging element. Therefore, the charge movement control electrode can prevent charges generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) is not degraded.

[0032] In addition, in each of an imaging element according to a fifth aspect of the present disclosure, an imaging element according to a fifth aspect of the present disclosure included in a stacked imaging element, and an imaging element according to a fifth aspect of the present disclosure included in a solid-state imaging device according to a first aspect and a second aspect of the present disclosure (hereinafter, in some cases, the imaging elements are collectively referred to as "imaging elements according to a fifth aspect of the present disclosure and the like"), the value of the dielectric constant of the insulating material included in the region between the first electrode and the charge storage electrode is higher than the value of the dielectric constant of the insulating material included in the region between the imaging element and an adjacent imaging element. Therefore, the capacitance of a capacitor (for convenience, referred to as "capacitor A") formed in the region of the charge storage electrode located between the first electrode and the charge storage electrode is larger than the capacitance of a capacitor (for convenience, referred to as "capacitor B") formed in the region of the charge storage electrode located between the imaging element and an adjacent imaging element. Compared with the region between the imaging element and an adjacent imaging element, charges are more attracted to the region between the first electrode and the charge storage electrode. This can prevent charges generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) is not degraded.

[0033] In addition, in each of the imaging elements according to the sixth aspect of the present disclosure, the imaging elements according to the sixth aspect included in the stacked imaging element, and the imaging elements according to the sixth aspect included in the solid-state imaging device according to the first aspect and the second aspect of the present disclosure (hereinafter, in some cases, the imaging elements are collectively referred to as "the imaging elements according to the sixth aspect of the present disclosure and the like"), the thickness of the region of the insulating layer located between the first electrode and the charge storage electrode is thinner than the thickness of the region of the insulating layer located between the imaging element and the adjacent imaging element. Therefore, the capacitance of capacitor A is greater than the capacitance of capacitor B, and compared with the region of the insulating layer facing between the imaging element and the adjacent imaging element, charges are more attracted to the region of the insulating layer located between the first electrode and the charge storage electrode. This can prevent the charges generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) will not deteriorate.

[0034] In addition, in each of the imaging elements according to the seventh aspect of the present disclosure, the imaging elements according to the seventh aspect included in the stacked imaging element, and the imaging elements according to the seventh aspect included in the solid-state imaging device according to the first aspect and the second aspect of the present disclosure (hereinafter, in some cases, the imaging elements are collectively referred to as "the imaging elements according to the seventh aspect of the present disclosure and the like"), the thickness of the region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is greater than the thickness of the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element. In addition, in this case, the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element is more affected by the voltage of the second electrode (upper electrode), and the electric potential becomes smaller. This can prevent the charges generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) will not deteriorate.

[0035] In addition, in each of the imaging elements according to the eighth aspect of the present disclosure, the imaging elements according to the eighth aspect included in the stacked imaging element, and the imaging elements according to the eighth aspect included in the solid-state imaging device according to the first aspect and the second aspect of the present disclosure (hereinafter, in some cases, the imaging elements are collectively referred to as "the imaging elements according to the eighth aspect of the present disclosure and the like"), the amount of fixed charges in the region of the interface between the photoelectric conversion layer and the insulating layer located between the first electrode and the charge storage electrode is smaller than the amount of fixed charges in the region of the interface between the photoelectric conversion layer and the insulating layer located between the imaging element and the adjacent imaging element. In addition, in this case, the electric potential of the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element changes more according to the amount of fixed charges. This can prevent the charges generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) will not deteriorate.

[0036] In addition, in each of an imaging element according to the ninth aspect of the present disclosure, an imaging element according to the ninth aspect of the present disclosure included in a stacked imaging element, and an imaging element according to the ninth aspect of the present disclosure included in a solid-state imaging device according to the first aspect and the second aspect of the present disclosure (hereinafter, in some cases, the imaging elements are collectively referred to as "imaging elements according to the ninth aspect of the present disclosure and the like"), the value of the charge mobility in the region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is greater than the value of the charge mobility in the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element. In this case, the charge is more likely to flow toward the first electrode than in the direction toward the adjacent imaging element. This can prevent the charge generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) will not deteriorate.

[0037] Note that the beneficial effects described in this specification are merely exemplary and are not limited. Additionally, there may be other beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1A and Figure 1B are a schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 1 and a schematic cross-sectional view of a modified example (Modified Example 6 of Example 1) of the imaging element (two imaging elements arranged side by side) of Example 1, respectively.

[0039] Figure 2 are schematic partial cross-sectional views of the imaging element of Example 1 and the stacked imaging element.

[0040] Figure 3 are equivalent circuit diagrams of the imaging element of Example 1 and the stacked imaging element.

[0041] Figure 4 are equivalent circuit diagrams of the imaging element of Example 1 and the stacked imaging element.

[0042] Figure 5 is a schematic layout diagram of the transistors of the first electrode, the charge storage electrode, and the control unit included in the imaging element of Example 1.

[0043] Figure 6 is a schematic layout diagram of the first electrode and the charge storage electrode included in the imaging element of Example 1.

[0044] Figure 7 is a schematic layout diagram of a modified example (a modified example of Example 1) of the first electrode and the charge storage electrode included in the imaging element of Example 1.

[0045] Figure 8 It is a diagram schematically showing the state of electric potential in each part during the operation of the imaging element of Example 1.

[0046] Fig. 9A 、 9B And 9C are equivalent circuit diagrams of the imaging element and the stacked imaging element of Example 1, Example 11, and Example 12, and are used to describe Figure 8 (Example 1), Fig.51 (Example 11), and Fig.58 (Example 12) of each part.

[0047] Fig.10 It is a conceptual diagram of the solid-state imaging device of Example 1.

[0048] Fig.11 It is an equivalent circuit diagram of a modified example (modified example 2 of Example 1) of the imaging element and the stacked imaging element of Example 1.

[0049] Fig.12 Is Fig.11 A schematic layout diagram of the transistors of the first electrode, the charge storage electrode, and the control unit included in the modified example (modified example 2 of Example 1) of the imaging element of Example 1 shown.

[0050] Fig.13 It is a schematic layout diagram of a modified example (modified example 3 of Example 1) of the first electrode and the charge storage electrode included in the imaging element of Example 1.

[0051] Fig.14A And 14B It is a schematic layout diagram of a modified example (modified example 4 of Example 1) of the first electrode and the charge storage electrode included in the imaging element of Example 1.

[0052] Fig.15A And 15B It is a schematic layout diagram of a modified example (modified example 5 of Example 1) of the first electrode and the charge storage electrode included in the imaging element of Example 1.

[0053] Fig.16A Is Fig. 15B A schematic cross-sectional view taken along the single dotted line B-B of the modified example 5 of Example 1 shown in Fig. 15B , and Fig. 16B Is when the charge movement control electrode is Fig.15A A schematic cross-sectional view taken along the single dotted line A-A when replaced by the discharge electrode in the modified example 5 of Example 1 shown in Fig.15A .

[0054] Fig.17A And 17BSchematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 2.

[0055] Fig.18A and 18B Schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 3.

[0056] Fig.19 Schematic plan view of a part of the imaging element (2×2 imaging elements arranged side by side) of Example 3.

[0057] Fig. 20 Schematic plan view of a part of a modified example (Modified Example 1 of Example 3) of the imaging element (2×2 imaging elements arranged side by side) of Example 3.

[0058] Fig.21A and 21B Schematic illustration of the change in the potential within the photoelectric conversion layer in the imaging element of Example 1 in which a charge storage electrode is provided on the lower side of the photoelectric conversion layer and the change in the potential within the photoelectric conversion layer in the imaging element of Example 3 in which a charge storage electrode is provided on the upper side of the photoelectric conversion layer.

[0059] Fig.22A and 22B Schematic plan view of a part of a modified example (Modified Example 2 of Example 3) of the imaging element of Example 3.

[0060] Fig.23A , 23B and 23C are schematic plan views of a part of a modified example (Modified Example 3 of Example 3) of the imaging element of Example 3.

[0061] Fig.24A and 24B Schematic cross-sectional view of a part of a modified example (Modified Examples 4A and 4B of Example 3) of the imaging element (two imaging elements arranged side by side) of Example 3.

[0062] Fig.25A and 25B Schematic plan view of a modified example (Modified Example 4A of Example 3) of the imaging element of Example 3.

[0063] Fig.26A and 26B Schematic plan view of a modified example (Modified Example 4B of Example 3) of the imaging element of Example 3.

[0064] Fig.27A and 27B Schematic plan view of a modified example (Modified Example 4C of Example 3) of the imaging element of Example 3.

[0065] Fig.28A and 28B is a schematic plan view of a modified example (modified example 4D of Example 3) of the imaging element of Example 3.

[0066] Fig.29A and 29B 29C are diagrams schematically showing the potential states of the respective parts in modified example 4B, modified example 4C, and modified example 4D of Example 3.

[0067] Fig.30 is a schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 4.

[0068] Fig.31 is a schematic cross-sectional view of a part of a modified example of the imaging element (two imaging elements arranged side by side) of Example 4.

[0069] Fig.32 is a schematic cross-sectional view of a part of another modified example of the imaging element (two imaging elements arranged side by side) of Example 4.

[0070] Fig.33 is a schematic cross-sectional view of a part of yet another modified example of the imaging element (two imaging elements arranged side by side) of Example 4.

[0071] Fig.34 is a schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 5.

[0072] Fig.35 is a schematic cross-sectional view of a part of a modified example of the imaging element (two imaging elements arranged side by side) of Example 5.

[0073] Fig.36 is a schematic cross-sectional view of a part of another modified example of the imaging element (two imaging elements arranged side by side) of Example 5.

[0074] Fig.37 is a schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 6.

[0075] Fig.38 is a schematic cross-sectional view of a part of a modified example of the imaging element (two imaging elements arranged side by side) of Example 6.

[0076] Fig.39 is a schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 7.

[0077] Fig.40Schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 8.

[0078] Fig.41 Schematic cross-sectional view of a part of a modified example of the imaging element (two imaging elements arranged side by side) of Example 8.

[0079] Fig.42 Schematic partial cross-sectional view of the imaging element of Example 9 and the stacked imaging element.

[0080] Fig.43 Schematic partial cross-sectional view of the imaging element of Example 10 and the stacked imaging element.

[0081] Fig.44 Schematic partial cross-sectional view of a modified example of the imaging element of Example 10 and the stacked imaging element.

[0082] Fig.45 Schematic partial cross-sectional view of another modified example of the imaging element of Example 10 and the stacked imaging element.

[0083] Fig.46 Schematic partial cross-sectional view of yet another modified example of the imaging element of Example 10 and the stacked imaging element.

[0084] Fig.47 Schematic partial cross-sectional view of the imaging element of Example 11 and the stacked imaging element.

[0085] Fig.48 Equivalent circuit diagram of the imaging element of Example 11 and the stacked imaging element.

[0086] Fig.49 Equivalent circuit diagram of the imaging element of Example 11 and the stacked imaging element.

[0087] Fig.50 Schematic layout diagram of the transistors of the first electrode, transfer control electrode, charge storage electrode, and control unit included in the imaging element of Example 11.

[0088] Fig.51 Diagram schematically showing the state of the electric potential in each part during the operation of the imaging element of Example 11.

[0089] Fig.52 Diagram schematically showing the state of the electric potential in each part during another operation of the imaging element of Example 11.

[0090] Fig.53Schematic layout diagram of transistors of the first electrode, transfer control electrode, charge storage electrode, and control unit included in a modified example of the imaging element of Example 11.

[0091] Fig.54 Schematic partial cross-sectional view of the imaging element of Example 12 and the stacked imaging element.

[0092] Fig.55 Equivalent circuit diagram of the imaging element of Example 12 and the stacked imaging element.

[0093] Fig.56 Equivalent circuit diagram of the imaging element of Example 12 and the stacked imaging element.

[0094] Fig.57 Schematic layout diagram of transistors of the first electrode, charge storage electrode, and control unit included in the imaging element of Example 12.

[0095] Fig.58 Diagram schematically illustrating the state of electric potential in each part during the operation of the imaging element of Example 12.

[0096] Fig.59 Diagram schematically illustrating the state of electric potential in each part during another operation period (charge transfer period) of the imaging element of Example 12.

[0097] Fig.60 Schematic layout diagram of the first electrode and charge storage electrode included in a modified example of the imaging element of Example 12.

[0098] Fig.61 Schematic partial cross-sectional view of the imaging element of Example 13 and the stacked imaging element.

[0099] Fig.62 Schematic partial enlarged cross-sectional view of the part where the charge storage electrode, photoelectric conversion layer, and second electrode are stacked in the imaging element of Example 13.

[0100] Fig.63 Schematic layout diagram of transistors of the first electrode, charge storage electrode, and control unit included in a modified example of the imaging element of Example 13.

[0101] Fig.64 Schematic partial enlarged cross-sectional view of the part where the charge storage electrode, photoelectric conversion layer, and second electrode are stacked in the imaging element of Example 14.

[0102] Fig.65 Schematic partial cross-sectional view of the imaging element of Example 15 and the stacked imaging element.

[0103] Fig.66 Schematic partial cross-sectional views of the imaging element and the stacked imaging element of Examples 16 and 17.

[0104] Fig.67A and 67B Schematic plan view of the charge storage electrode section in Example 17.

[0105] Fig.68A and 68B Schematic plan view of the charge storage electrode section in Example 17.

[0106] Fig.69 Schematic layout diagram of the transistors of the first electrode, the charge storage electrode, and the control unit included in the imaging element of Example 17.

[0107] Fig.70 Schematic layout diagram of the first electrode and the charge storage electrode included in a modified example of the imaging element of Example 17.

[0108] Fig.71 Schematic partial cross-sectional views of the imaging element and the stacked imaging element of Examples 18 and 17.

[0109] Fig.72A and 72B Schematic plan view of the charge storage electrode section in Example 18.

[0110] Fig.73 Schematic plan view of the first electrode and the charge storage electrode section in the solid-state imaging device of Example 19.

[0111] Fig.74 Schematic plan view of the first electrode and the charge storage electrode section in the first modified example of the solid-state imaging device of Example 19.

[0112] Fig.75 Schematic plan view of the first electrode and the charge storage electrode section in the second modified example of the solid-state imaging device of Example 19.

[0113] Fig.76 Schematic plan view of the first electrode and the charge storage electrode section in the third modified example of the solid-state imaging device of Example 19.

[0114] Fig.77 Schematic plan view of the first electrode and the charge storage electrode section in the fourth modified example of the solid-state imaging device of Example 19.

[0115] Fig.78 Schematic plan view of the first electrode and the charge storage electrode section in the fifth modified example of the solid-state imaging device of Example 19.

[0116] Fig.79 It is a schematic plan view of the first electrode and the charge storage electrode section in the sixth modified example of the solid-state imaging device of Embodiment 19.

[0117] Fig.80 It is a schematic plan view of the first electrode and the charge storage electrode section in the seventh modified example of the solid-state imaging device of Embodiment 19.

[0118] Fig.81 It is a schematic plan view of the first electrode and the charge storage electrode section in the eighth modified example of the solid-state imaging device of Embodiment 19.

[0119] Fig.82 It is a schematic plan view of the first electrode and the charge storage electrode section in the ninth modified example of the solid-state imaging device of Embodiment 19.

[0120] Fig.83A 、 83B And 83C are diagrams showing examples of reading and driving in the imaging element block of Embodiment 19.

[0121] Fig.84 It is a schematic plan view of the first electrode and the charge storage electrode section of the solid-state imaging device of Embodiment 20.

[0122] Fig.85 It is a schematic plan view of the first electrode and the charge storage electrode section in a modified example of the solid-state imaging device of Embodiment 20.

[0123] Fig.86 It is a schematic plan view of the first electrode and the charge storage electrode section in a modified example of the solid-state imaging device of Embodiment 20.

[0124] Fig.87 It is a schematic plan view of the first electrode and the charge storage electrode section in a modified example of the solid-state imaging device of Embodiment 20.

[0125] Fig.88 It is a schematic partial cross-sectional view of another modified example of the imaging element and the stacked imaging element of Embodiment 1.

[0126] Fig.89 It is a schematic partial cross-sectional view of yet another modified example of the imaging element and the stacked imaging element of Embodiment 1.

[0127] Fig.90A 、 90B And 90C are schematic partial enlarged cross-sectional views of respective parts such as the first electrode in yet another modified example of the imaging element and the stacked imaging element of Embodiment 1.

[0128] Fig.91It is a schematic partial cross-sectional view of another modified example of the imaging element and the stacked imaging element of Example 1.

[0129] Fig.92 It is a schematic partial cross-sectional view of another modified example of the imaging element and the stacked imaging element of Example 1.

[0130] Fig.93 It is a schematic partial cross-sectional view of another modified example of the imaging element and the stacked imaging element of Example 1.

[0131] Fig.94 It is a schematic partial cross-sectional view of another modified example of the imaging element and the stacked imaging element of Example 11.

[0132] Fig.95 It is a schematic partial cross-sectional view of another modified example of the imaging element and the stacked imaging element of Example 1.

[0133] Fig.96 It is a schematic partial cross-sectional view of another modified example of the imaging element and the stacked imaging element of Example 1.

[0134] Fig.97 It is a schematic partial enlarged cross-sectional view of a part where a charge storage electrode, a photoelectric conversion layer, and a second electrode are stacked in a modified example of the imaging element of Example 13.

[0135] Fig.98 It is a schematic partial enlarged cross-sectional view of a part where a charge storage electrode, a photoelectric conversion layer, and a second electrode are stacked in a modified example of the imaging element of Example 14.

[0136] Fig.99A and 99B It is an equivalent circuit diagram of a modified example of a transistor that drives a charge storage electrode.

[0137] Fig.100A and 100B It schematically illustrates driving Fig.99A and 99B The pulse waveform diagram of the transistor in the equivalent circuit shown in.

[0138] Fig.101 It is a conceptual diagram of an example of using a solid-state imaging device including the imaging element and the stacked imaging element of the present disclosure in an electronic device (camera).

[0139] Fig.102 It is a conceptual diagram of a conventional stacked imaging element (stacked solid-state imaging device).

[0140] Description of the embodiments

[0141] In the following, the present disclosure will be described based on embodiments with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments, and various values and materials in the embodiments are illustrative. Note that the present disclosure will be described in the following order.

[0142] 1. General description of the imaging element and the stacked imaging element according to the first to ninth aspects of the present disclosure and the solid-state imaging device according to the first and second aspects of the present disclosure

[0143] 2. Embodiment 1 (imaging element according to the first to third aspects of the present disclosure, stacked imaging element of the present disclosure, and solid-state imaging device according to the second aspect of the present disclosure)

[0144] 3. Embodiment 2 (imaging element according to the second aspect of the present disclosure)

[0145] 4. Embodiment 3 (imaging element according to the fourth aspect of the present disclosure)

[0146] 5. Embodiment 4 (imaging element according to the fifth aspect of the present disclosure)

[0147] 6. Embodiment 5 (imaging element according to the sixth aspect of the present disclosure)

[0148] 7. Embodiment 6 (imaging element according to the seventh aspect of the present disclosure)

[0149] 8. Embodiment 7 (imaging element according to the eighth aspect of the present disclosure)

[0150] 9. Embodiment 8 (imaging element according to the ninth aspect of the present disclosure)

[0151] 10. Embodiment 9 (variation of the imaging elements of Embodiments 1 to 8)

[0152] 11. Embodiment 10 (variation of Embodiments 1 to 9, solid-state imaging device according to the first aspect of the present disclosure)

[0153] 12. Embodiment 11 (variation of Embodiments 1 to 10, imaging element including a transfer control electrode)

[0154] 13. Embodiment 12 (variation of Embodiments 1 to 11, imaging element including a plurality of charge storage electrode sections)

[0155] 14. Embodiment 13 (imaging element of the first structure and the sixth structure)

[0156] 15. Embodiment 14 (imaging element of the second structure and the sixth structure of the present disclosure)

[0157] 16. Embodiment 15 (imaging element of the third structure)

[0158] 17. Example 16 (Imaging Element of the Fourth Structure)

[0159] 18. Example 17 (Imaging Element of the Fifth Structure)

[0160] 19. Example 18 (Imaging Element of the Sixth Structure)

[0161] 20. Example 19 (Solid-State Imaging Device of the First and Second Structures)

[0162] 21. Example 20 (Variant of Example 19)

[0163] 22. Others Detailed Description

[0164] <General Description of the Imaging Element and Stacked Imaging Element of the First to Ninth Aspects of the Present Disclosure and the Solid-State Imaging Device of the First to Second Aspects of the Present Disclosure>

[0165] In the following description, for convenience, the "region of the photoelectric conversion layer located between the first electrode and the charge storage electrode" is referred to as "region A of the photoelectric conversion layer", and for convenience, the "region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element" is referred to as "region B of the photoelectric conversion layer". In addition, for convenience, the "region of the insulating layer located between the first electrode and the charge storage electrode" is referred to as "region A of the insulating layer", and for convenience, the "region of the insulating layer located between the imaging element and the adjacent imaging element" is referred to as "region B of the insulating layer". Region B of the photoelectric conversion layer corresponds to region B of the insulating layer. In addition, for convenience, the "region between the first electrode and the charge storage electrode" is referred to as "region a", and for convenience, the "region between the imaging element and the adjacent imaging element" is referred to as "region b". In region a, region A of the photoelectric conversion layer corresponds to region A of the insulating layer. In region b, region B of the photoelectric conversion layer corresponds to region B of the insulating layer.

[0166] In the imaging element and the like according to the first and second aspects of the present invention, in other words, region B of the photoelectric conversion layer represents the following part of the photoelectric conversion layer: the part that is positioned above the part (region B of the insulating layer) of the insulating layer located in the region (region b) between the charge storage electrode and the charge storage electrode included in the adjacent imaging element.

[0167] In an imaging element or the like according to the third aspect of the present invention, a charge movement control electrode is formed in a region B of a region facing the photoelectric conversion layer via an insulating layer. In other words, the charge movement control electrode is formed below a part (region B of the insulating layer) of a region (region b) of the insulating layer that is located between the charge storage electrode and the charge storage electrode included in an adjacent imaging element. The charge movement control electrode is provided at a distance from the charge storage electrode. Or, in other words, the charge movement control electrode is provided around and separated from the charge storage electrode, and the charge movement control electrode is arranged to face the region B of the photoelectric conversion layer via the insulating layer.

[0168] In an imaging element or the like according to the fourth aspect of the present invention, instead of the second electrode, a charge movement control electrode is formed in a region of the photoelectric conversion layer that is located between the imaging element and an adjacent imaging element. The charge movement control electrode is provided separately from the second electrode. In other words:

[0169] [A] A second electrode may be provided for each imaging element, and the charge movement control electrode may be provided to surround at least a part of the second electrode and be separated from the second electrode on the region B of the photoelectric conversion layer,

[0170] [B] A second electrode may be provided for each imaging element, the charge movement control electrode may be provided to surround at least a part of the second electrode and be separated from the second electrode, and a part of the charge storage electrode may exist on the lower side of the charge movement control electrode, or

[0171] [C] A second electrode may be provided for each imaging element, the charge movement control electrode may be provided to surround at least a part of the second electrode and be separated from the second electrode, a part of the charge storage electrode may exist on the lower side of the charge movement control electrode, and in addition, the charge movement control electrode in the imaging element or the like according to the third aspect may be formed on the lower side of the charge movement control electrode. The potential generated by the coupling of the charge movement control electrode and the second electrode is applied in some cases to the following region of the photoelectric conversion layer: the region located below the region between the charge movement control electrode and the second electrode.

[0172] In an imaging element or the like according to the fifth aspect of the present invention, the insulating material contained in region a (referred to as "insulating material A" for convenience) may fill all of region a on a plane, may fill a part of region a, may include the portion above the edge portion of region a up to the charge storage electrode (the edge portion facing region a), or may be formed on a part or all of the charge storage electrode. Alternatively, the insulating material may fill all of region a or may fill a part of region a along the thickness direction of the insulating layer. The insulating material contained in region B (region b) of the insulating layer (referred to as "insulating material B" for convenience) may fill all of region B of the insulating layer on a plane, may fill a part (region b) of region B of the insulating layer, or may include region B (region b) of the insulating layer up to the edge portion of the charge storage electrode (the edge portion facing region B (region b) of the insulating layer). Alternatively, the insulating material may fill all of region B (region b) of the insulating layer or may fill a part (region b) of region B of the insulating layer along the thickness direction of the insulating layer.

[0173] In an imaging element or the like according to the sixth aspect of the present invention, the thickness of region A of the insulating layer is thinner than the thickness of region B of the insulating layer. All regions of region A and region B of the insulating layer may meet the requirements, or a part of the regions may meet the requirements.

[0174] In an imaging element or the like according to the seventh aspect of the present invention, the thickness of region A of the photoelectric conversion layer is thicker than the thickness of region B of the photoelectric conversion layer. All regions of region A and region B of the photoelectric conversion layer can meet the requirements, or a part of the regions can meet the requirements. The thickness of region B of the photoelectric conversion layer may be "0". That is, depending on the situation, the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element may not exist.

[0175] In an imaging element or the like according to the eighth aspect of the present invention, the amount of fixed charge in the region of the interface between region A of the photoelectric conversion layer and region A of the insulating layer is less than the amount of fixed charge in the region of the interface between region B of the photoelectric conversion layer and region B of the insulating layer. All regions of the region of the interface between region A of the photoelectric conversion layer and region A of the insulating layer and the region of the interface between region B of the photoelectric conversion layer and region B of the insulating layer may meet the requirements, or a part of the regions may meet the requirements.

[0176] In an imaging element or the like according to the ninth aspect of the present invention, the value of the charge mobility in region A of the photoelectric conversion layer (referred to as "charge mobility A" for convenience) is greater than the value of the charge mobility in region B of the photoelectric conversion layer (referred to as "charge mobility B" for convenience). All regions of region A of the photoelectric conversion layer and region B of the photoelectric conversion layer may satisfy the above requirements, or a part of the regions may satisfy the above requirements. Alternatively, the region of the photoelectric conversion layer having charge mobility A may extend over a part or all of the charge storage electrode.

[0177] The imaging element or the like according to the third aspect of the present invention may further include a control unit provided on the semiconductor substrate and including a drive circuit, wherein

[0178] the first electrode, the second electrode, the charge storage electrode, and the charge movement control electrode are connected to the drive circuit,

[0179] during charge storage, the drive circuit applies a potential V 11 to the first electrode, applies a potential V 12 to the charge storage electrode, and applies a potential V 13 to the charge movement control electrode, and charges are stored in the photoelectric conversion layer, and

[0180] during charge transfer, the drive circuit applies a potential V 21 to the first electrode, applies a potential V 22 to the charge storage electrode, and applies a potential V 23 to the charge movement control electrode, and the charges stored in the photoelectric conversion layer are read out to the control unit through the first electrode, wherein

[0181] when the potential of the first electrode is higher than the potential of the second electrode,

[0182] V 12 ≥V 11 ,V 12 >V 13 and V 21 >V 22 >V 23 are maintained, and

[0183] when the potential of the first electrode is lower than the potential of the second electrode,

[0184] V 12 ≤V 11 ,V 12 <V 13 and V 21 <V 22 <V 23is maintained. The charge movement control electrode may be formed on the same level as the first electrode or the charge storage electrode, or may be formed on a different level.

[0185] The imaging element and the like according to the fourth aspect of the present invention may further include a control unit provided on the semiconductor substrate and including a drive circuit, wherein

[0186] the first electrode, the second electrode, the charge storage electrode, and the charge movement control electrode are connected to the drive circuit,

[0187] During charge storage, the drive circuit applies a potential V 2 ' to the second electrode and applies a potential V 13 ' to the charge movement control electrode, and charges are stored in the photoelectric conversion layer, and

[0188] During charge transfer, the drive circuit applies a potential V 2 ” to the second electrode and applies a potential V 23 ” to the charge movement control electrode, and the charges stored in the photoelectric conversion layer are read out to the control unit through the first electrode, wherein

[0189] In the case where the potential of the first electrode is higher than the potential of the second electrode

[0190] V 2 '≥V 13 ' and V 2 "≥V 23 " are maintained, and

[0191] In the case where the potential of the first electrode is lower than the potential of the second electrode

[0192] V 2 '≤V 13 ' and V 2 "≤V 23 " are maintained. The charge movement control electrode is formed on the same level as the second electrode.

[0193] Each of the imaging elements and the like of the present disclosure including the above preferred modes may further include a semiconductor substrate, wherein the photoelectric conversion unit is disposed on the upper side of the semiconductor substrate. Note that the first electrode, the charge storage electrode, the second electrode, and various electrodes are connected to the drive circuit described later.

[0194] In addition, each of the imaging elements and the like of the present disclosure including the various preferred modes described above may further include a transfer control electrode (charge transfer electrode) that is disposed between the first electrode and the charge storage electrode, is arranged to be separated from the first electrode and the charge storage electrode, and is arranged to face the photoelectric conversion layer via an insulating layer. Note that, for convenience, in some cases, the imaging elements and the like of the present disclosure in this mode are referred to as "imaging elements and the like of the present disclosure including a transfer control electrode". In addition, the imaging elements and the like of the present disclosure including a transfer control electrode may further include:

[0195] a control unit that is provided on a semiconductor substrate and includes a drive circuit, where

[0196] the first electrode, the charge storage electrode, and the transfer control electrode are connected to the drive circuit,

[0197] during charge storage, the drive circuit applies a potential V 11 to the first electrode, applies a potential V 12 to the charge storage electrode, and applies a potential V 14 to the transfer control electrode, charges are stored in the photoelectric conversion layer, and

[0198] during charge transfer, the drive circuit applies a potential V 21 to the first electrode, applies a potential V 22 to the charge storage electrode, and applies a potential V 24 to the transfer control electrode, the charges stored in the photoelectric conversion layer are read out to the control unit through the first electrode, where

[0199] in the case where the potential of the first electrode is higher than the potential of the second electrode

[0200] V 12 >V 14 and V 22 ≤V 24 ≤V 21 are maintained, and

[0201] in the case where the potential of the first electrode is lower than the potential of the second electrode

[0202] V 12 <V 14 and V 22 ≥V 24 ≥V 21 are maintained.

[0203] In addition, in each of the imaging elements of the present disclosure including the above-mentioned various preferred modes, the charge storage electrode may include a plurality of charge storage electrode segments. Note that for convenience, in some cases, the imaging element of the present disclosure in a mode is referred to as "the imaging element of the present disclosure including a plurality of charge storage electrode segments". The number of charge storage electrode segments may be equal to or greater than 2. In addition, in the case where different potentials are applied to each of the N charge storage electrode segments in the imaging element of the present disclosure including a plurality of charge storage electrode segments,

[0204] In the case where the potential of the first electrode is higher than the potential of the second electrode, during charge transfer, the potential applied to the charge storage electrode segment located closest to the first electrode (the first photoelectric conversion unit segment) may be higher than the potential applied to the charge storage electrode segment located farthest from the first electrode (the Nth photoelectric conversion unit segment), and

[0205] When the potential of the first electrode is lower than the potential of the second electrode, during charge transfer, the potential applied to the charge storage electrode segment (first photoelectric conversion unit segment) positioned closest to the first electrode can be lower than the potential applied to the charge storage electrode segment (Nth photoelectric conversion unit segment) positioned farthest from the first electrode.

[0206] Furthermore, in each of the imaging elements S and the like of the present disclosure including the above-mentioned various preferred modes, the size of the charge storage electrode may be larger than the size of the first electrode. Although not restrictive, it is preferred that

[0207] 4≤S 1 ' / S 1 ,

[0208] Where S 1 ' is the area of ​​the charge storage electrode, S 1 is the area of ​​the first electrode.

[0209] In the imaging element according to the second aspect of the present invention, the width W of the region A of the photoelectric conversion layer is A The width W of the region B of the photoelectric conversion layer is B Narrow, and (W A / W B Examples of values ​​for ) include

[0210] 1 / 2≤(W A / W B )<1.

[0211] In the imaging element according to the fifth aspect of the present invention, specific examples of the insulating material A include SiN, and specific examples of the insulating material B include SiO 2 .

[0212] In the imaging element according to the sixth aspect of the present invention, the thickness t of region A of the insulating layer In-A is thinner than the thickness t of region B of the insulating layer In-B , and examples of the value of (t In-A / t In-B ) include

[0213] 1 / 2 ≤ (t In-A / t In-B ) < 1.

[0214] In the imaging element according to the seventh aspect of the present invention, the thickness t of region A of the photoelectric conversion layer Pc-A is thicker than the thickness t of region B of the photoelectric conversion layer Pc-B , and examples of the value of (t Pc-A / t Pc-B ) include

[0215] 1 < (t Pc-A / t Pc-B ) ≤ 2.

[0216] In the imaging element according to the eighth aspect of the present invention, the fixed charge amount FC in the region of the interface between region A of the photoelectric conversion layer and region A of the insulating layer A is less than the fixed charge amount FC in the region of the interface between region B of the photoelectric conversion layer and region B of the insulating layer B .

[0217] 1 / 10 ≤ (FC A / FC B ) < 1.

[0218] Here, the fixed charge amount in the region of the interface between the photoelectric conversion layer and the insulating layer can be controlled based on, for example, the method of depositing a thin film having a fixed charge.

[0219] In the imaging element according to the ninth aspect of the present invention, the value CT of the charge mobility in region A of the photoelectric conversion layer A is greater than the value CT of the charge mobility in region B of the photoelectric conversion layer B .

[0220] 1 < (CT A / CT B ) ≤ 1 × 10 2 .

[0221] The materials included in region A of the photoelectric conversion layer and the materials included in region B of the photoelectric conversion layer can be appropriately selected from the materials included in the photoelectric conversion layer. Alternatively, a part of the photoelectric conversion layer can have a bilayer structure of an upper layer / lower layer. The upper layer of region A of the photoelectric conversion layer, the upper layer of region B of the photoelectric conversion layer, and the part of the photoelectric conversion layer positioned on the upper side of the charge storage electrode can include the same material (conveniently referred to as the "upper layer constituent material"). The lower layer of region A of the photoelectric conversion layer and the lower layer of the part of the photoelectric conversion layer positioned on the upper side of the charge storage electrode can include the same material (conveniently referred to as the "lower layer constituent material"). The upper layer constituent material and the lower layer constituent material can be different.

[0222] In this way, the lower layer of the photoelectric conversion layer (which will be referred to as the "lower semiconductor layer" in some cases) can be provided to prevent recombination, for example, during charge storage. This can also improve the charge transfer efficiency of the charges stored in the photoelectric conversion layer to the first electrode. In addition, the charges generated in the photoelectric conversion layer can be temporarily held to control the timing of transfer, etc. In addition, the generation of dark current can be suppressed. Note that in some cases, the upper layer of the photoelectric conversion layer is referred to as the "upper photoelectric conversion layer".

[0223] In addition to the imaging element and the like according to the fourth aspect of the present disclosure, the second electrode located on the light incident side can be shared by a plurality of imaging elements. That is, the second electrode can be a so-called solid electrode. In the imaging element and the like of the present disclosure, the photoelectric conversion layer is shared by a plurality of imaging elements. That is, one photoelectric conversion layer is formed in a plurality of imaging elements.

[0224] In addition, in the imaging element and the like of the present disclosure including the above various preferred modes, the first electrode can extend in the opening provided in the insulating layer and can be connected to the photoelectric conversion layer. Alternatively, the photoelectric conversion layer can extend in the opening provided in the insulating layer and can be connected to the first electrode. In this case,

[0225] The edge portion of the top surface of the first electrode can be covered by the insulating layer,

[0226] The first electrode can be exposed on the bottom surface of the opening, and

[0227] The side surface of the opening can be inclined to extend from the first surface to the second surface, where the first surface is the surface of the insulating layer in contact with the top surface of the first electrode, and the second surface is the surface of the insulating layer in contact with the part of the photoelectric conversion layer facing the charge storage electrode. In addition, the side surface of the opening that extends obliquely from the first surface to the second surface can be located on the charge storage electrode side. Note that another layer can also be formed between the photoelectric conversion layer and the first electrode (for example, a material layer suitable for charge storage can be formed between the photoelectric conversion layer and the first electrode).

[0228] In addition, in the imaging element of the present disclosure including the above various preferred modes, etc.,

[0229] At least the floating diffusion layer and the amplifying transistor included in the control unit can be provided on the semiconductor substrate, and

[0230] The first electrode can be connected to the floating diffusion layer and the gate portion of the amplifying transistor. In addition, in this case,

[0231] The reset transistor and the selection transistor included in the control unit can be further provided on the semiconductor substrate,

[0232] The floating diffusion layer can be connected to one source / drain region of the reset transistor

[0233] One source / drain region of the amplifying transistor can be connected to one source / drain region of the selection transistor, and the other source / drain region of the selection transistor can be connected to the signal line.

[0234] Alternatively, a modified example of the imaging element of the present disclosure including the above various preferred modes, etc. includes the imaging elements of the first to sixth configurations described below. That is, in each of the imaging elements of the first to sixth configurations in the imaging element of the present disclosure including the above various preferred modes, etc.,

[0235] The photoelectric conversion unit includes N (where N≥2) photoelectric conversion unit sections,

[0236] The photoelectric conversion layer includes N photoelectric conversion layer sections,

[0237] The insulating layer includes N insulating layer sections,

[0238] In each of the imaging elements of the first to third configurations, the charge storage electrode includes N charge storage electrode sections,

[0239] In each of the imaging elements of the fourth and fifth configurations, the charge storage electrode includes N charge storage electrode sections arranged separately from each other,

[0240] The nth (where n = 1, 2, 3, ··· N) photoelectric conversion unit section includes the nth charge storage electrode section, the nth insulating layer section, and the nth photoelectric conversion layer section, and

[0241] The larger the n value of the photoelectric conversion unit section, the farther the position of the photoelectric conversion unit section is from the first electrode.

[0242] In addition, in the imaging element of the first configuration, the thickness of the photoelectric conversion layer section gradually changes from the first photoelectric conversion unit section to the Nth photoelectric conversion unit section. In addition, in the imaging element of the second configuration, the thickness of the photoelectric conversion layer section gradually changes from the first photoelectric conversion unit section to the Nth photoelectric conversion unit section. In addition, in the imaging element of the third configuration, the material contained in the insulating layer section varies between adjacent photoelectric conversion unit sections. In addition, in the imaging element of the fourth configuration, the material contained in the charge storage electrode section varies between adjacent photoelectric conversion unit sections. In addition, in the imaging element of the fifth configuration, the area of the charge storage electrode section gradually decreases from the first photoelectric conversion unit section to the Nth photoelectric conversion unit section. Note that the area may decrease continuously or may decrease stepwise.

[0243] Alternatively, in the imaging element of the sixth configuration of the present disclosure including the above various preferred modes, the cross-sectional area of the stacked portion of the charge storage electrode, the insulating layer, and the photoelectric conversion layer (when the stacked portion is cut in the YZ virtual plane) varies with the distance from the first electrode, where the Z direction is the stacking direction of the charge storage electrode, the insulating layer, and the photoelectric conversion layer, and the X direction is the direction away from the first electrode. Note that the change in the cross-sectional area may be a continuous change or a stepwise change.

[0244] In each of the imaging elements of the first and second configurations, N photoelectric conversion layer sections are continuously provided, N insulating layer sections are also continuously provided, and N charge storage electrode sections are also continuously provided. In each of the imaging elements of the third to fifth configurations, N photoelectric conversion layer sections are continuously provided. In addition, in each of the imaging elements of the fourth and fifth configurations, N insulating layer sections are continuously provided. On the other hand, in the imaging element of the third configuration, N insulating layer sections are provided to correspond to the photoelectric conversion unit sections respectively. In addition, in each of the imaging elements of the fourth and fifth configurations and in the imaging element of the third configuration, as appropriate, N charge storage electrode sections are provided to correspond to the photoelectric conversion unit sections respectively. In addition, in each of the imaging elements of the first to sixth configurations, the same potential is applied to all the charge storage electrode sections. Alternatively, in each of the imaging elements of the fourth and fifth configurations and in the imaging element of the third configuration, as appropriate, different potentials may be applied to each of the N charge storage electrode sections.

[0245] In each of the imaging elements of the first to sixth configurations, and in the stacked imaging element and the solid-state imaging device of the present disclosure that employ the imaging element, the thickness of the insulating layer section is defined, the thickness of the photoelectric conversion layer section is defined, the materials included in each insulating layer section are different, the materials included in each charge storage electrode section are different, the area of the charge storage electrode section is defined, or the cross-sectional area of the stacked portion is defined. As a result, a charge transfer gradient is formed, and the charges generated by photoelectric conversion can be transferred to the first electrode more easily and more surely. In addition, as a result, the generation of afterimages or charge transfer leftovers can be prevented.

[0246] Modification examples of the stacked imaging element of the present disclosure include a stacked imaging element including at least one of the imaging elements of the first to sixth configurations. In addition, a modification example of the solid-state imaging device according to the first aspect of the present disclosure includes a solid-state imaging device including a plurality of imaging elements of the first to sixth configurations. A modification example of the solid-state imaging device according to the second aspect of the present disclosure includes a solid-state imaging device including a plurality of stacked imaging elements, each stacked imaging element including at least one of the imaging elements of the first to sixth configurations.

[0247] In each of the imaging elements of the first to fifth configurations, the larger the n value of the photoelectric conversion unit section, the farther the position of the photoelectric conversion unit section from the first electrode. It is determined whether the photoelectric conversion unit section is positioned away from the first electrode according to the X direction. In addition, in the imaging element of the sixth configuration, the direction away from the first electrode is the X direction, and the "X direction" is defined as follows. That is, a pixel region including a plurality of array imaging elements or stacked imaging elements includes a plurality of pixels arranged in a two-dimensional array (i.e., systematically arranged in the X direction and the Y direction). When the planar shape of the pixel is rectangular, the extending direction of the side closest to the first electrode is the Y direction, and the direction orthogonal to the Y direction is the X direction. Alternatively, when the planar shape of the pixel is an arbitrary shape, the overall direction including the straight line segment or curve closest to the first electrode is the Y direction, and the direction orthogonal to the Y direction is the X direction.

[0248] Hereinafter, the case where the potential of the first electrode is higher than the potential of the second electrode will be described for the imaging elements of the first to sixth configurations. When the potential of the first electrode is lower than the potential of the second electrode, it is only necessary to reverse the high and low of the potential.

[0249] In the imaging element of the first configuration, the thickness of the insulating layer section gradually changes from the first photoelectric conversion unit section to the Nth photoelectric conversion unit section. The thickness of the insulating layer section may gradually increase or gradually decrease. As a result, a charge transfer gradient is formed.

[0250] In the case where the charge to be stored is an electron, the thickness of the insulating layer section can be gradually increased. In the case where the charge to be stored is a hole, the thickness of the insulating layer section can be gradually decreased. Further, in these cases, when the state becomes |V 12 | ≥ |V 11 | during charge storage, the n-th photoelectric conversion unit section can store more charge than the (n + 1)-th photoelectric conversion unit section. A strong electric field is applied, which can of course prevent the charge from flowing from the first photoelectric conversion unit section to the first electrode. Further, when the state becomes |V 22 | < |V 21 | during the charge transfer period, the charge flow from the first photoelectric conversion unit section to the first electrode and the charge flow from the (n + 1)-th photoelectric conversion unit section to the n-th photoelectric conversion unit section can surely be ensured.

[0251] In the imaging element of the second configuration, the thickness of the photoelectric conversion layer section gradually changes from the first photoelectric conversion unit section to the N-th photoelectric conversion unit section. The thickness of the photoelectric conversion layer section can be gradually increased or gradually decreased. Thus, a charge transfer gradient is formed.

[0252] In the case where the charge to be stored is an electron, the thickness of the photoelectric conversion layer section can be gradually increased. In the case where the charge to be stored is a hole, the thickness of the photoelectric conversion layer section can be gradually decreased. Further, in the case where the thickness of the photoelectric conversion layer section is gradually increased, when the state becomes V 12 ≥ V 11 during charge storage, or in the case where the thickness of the photoelectric conversion layer section is gradually decreased, when the state becomes V 12 ≤ V 11 during charge storage, the electric field applied to the n-th photoelectric conversion unit section is stronger than the electric field applied to the (n + 1)-th photoelectric conversion unit section. This can surely prevent the charge from flowing from the first photoelectric conversion unit section to the first electrode. Further, in the case where the thickness of the photoelectric conversion layer section is gradually increased, when the state becomes V 22 < V 21 during charge storage, or in the case where the thickness of the photoelectric conversion layer section is gradually decreased, when the state becomes V 22 > V 21 during charge storage, the charge flow from the first photoelectric conversion unit section to the first electrode and the charge flow from the (n + 1)-th photoelectric conversion unit section to the n-th photoelectric conversion unit section can surely be ensured.

[0253] In the imaging element of the third structure, the material contained in the insulating layer section is different in adjacent photoelectric conversion unit sections, thereby forming a charge transfer gradient. Preferably, the dielectric constant value of the material contained in the insulating layer section gradually decreases from the first photoelectric conversion unit section to the Nth photoelectric conversion unit section. In addition, by adopting this structure, when the state becomes V during the charge storage period 12 ≥V 11 the nth photoelectric conversion unit section can store more charges than the (n + 1)th photoelectric conversion unit section. In addition, when the state becomes V during the charge transfer cycle 22 <V 21 the charge flow from the first photoelectric conversion unit section to the first electrode and the charge flow from the (n + 1)th photoelectric conversion unit section to the nth photoelectric conversion unit section can be surely guaranteed.

[0254] In the imaging element of the fourth structure, the material contained in the charge storage electrode section is different in adjacent photoelectric conversion unit sections. Thus, a charge transfer gradient is formed. Preferably, the work function value of the material contained in the insulating layer section gradually increases from the first photoelectric conversion unit section to the Nth photoelectric conversion unit section. In addition, by adopting this structure, regardless of whether the voltage is positive or negative, a potential gradient favorable for signal charge transfer can be formed.

[0255] In the imaging element of the fifth structure, the area of the charge storage electrode section gradually decreases from the first photoelectric conversion unit section to the Nth photoelectric conversion unit section. Thus, a charge transfer gradient is formed. Therefore, when the state becomes V during the charge storage cycle 12 ≥V 11 the nth photoelectric conversion unit section can store more charges than the (n + 1)th photoelectric conversion unit section. Additionally, when the state becomes V during the charge transfer period 22 <V 21 the charge flow from the first photoelectric conversion unit section to the first electrode and the charge flow from the (n + 1)th photoelectric conversion unit section to the nth photoelectric conversion unit section can be surely guaranteed.

[0256] In the imaging element of the sixth structure, the cross-sectional area of the stacked component varies according to the distance from the first electrode. Thus, a charge transfer gradient is formed. Specifically, the thickness of the cross-section of the stacked component can be constant, and as the distance from the first electrode increases, the width of the cross-section of the stacked component can decrease. By adopting this structure, as described in the imaging element of the fifth structure, when the state becomes V during the charge storage cycle 12 ≥V 11 the region closer to the first electrode can store more charges than the region farther from the first electrode. Therefore, when the state becomes V during the charge transfer cycle22 <V 21 When it is <V, it is certain to ensure the charge flow from the region close to the first electrode to the first electrode and the charge flow from the region far from the first electrode to the region close to the first electrode. On the other hand, the width of the cross-section of the stacked member can be constant, and the thickness of the cross-section of the stacked portion, especially the thickness of the insulating layer section, can gradually increase. By adopting this configuration, as described in the imaging element of the first configuration, when the state becomes <V during the charge storage period 12 ≥V 11 the region close to the first electrode stores more charges than the region far from the first electrode. By applying a strong electric field, it is certain to prevent the charge flow from the region close to the first electrode to the first electrode. In addition, when the state becomes <V during the charge transfer period 22 <V 21 it is certain to ensure the charge flow from the region close to the first electrode to the first electrode and the charge flow from the region far from the first electrode to the region close to the first electrode. In addition, the thickness of the photoelectric conversion layer section can gradually increase. By adopting this configuration, as described in the imaging element of the second configuration, when the state becomes <V during the charge storage period 12 ≥V 11 the electric field applied to the region close to the first electrode is stronger than the electric field applied to the region far from the first electrode. This can of course prevent the charge flow from the region close to the first electrode to the first electrode. In addition, when the state becomes <V during the charge transfer period 22 <V 21 it is certain to ensure the charge flow from the region close to the first electrode to the first electrode and the charge flow from the region far from the first electrode to the region close to the first electrode.

[0257] Another variant of the solid-state imaging device according to the first aspect of the present invention includes:

[0258] A solid-state imaging device including a plurality of imaging elements according to the first to ninth aspects of the present disclosure or imaging elements according to the first to sixth configurations, where

[0259] the plurality of imaging elements are included in an imaging element block, and

[0260] the first electrode is shared by the plurality of imaging elements included in the imaging element block. Note that for convenience, the solid-state imaging device configured in this way is referred to as a "solid-state imaging device of the first configuration". Alternatively, another variant of the solid-state imaging device according to the second aspect of the present disclosure includes:

[0261] A solid-state imaging device including a plurality of stacked imaging elements, each stacked imaging element including at least one imaging element according to the first to ninth aspects of the present disclosure or imaging elements according to the first to sixth configurations, where

[0262] A plurality of stacked imaging elements are included in an imaging element block, and

[0263] The first electrode is shared by the plurality of stacked imaging elements included in the imaging element block. Note that, for convenience, the solid-state imaging device constructed in this manner will be referred to as the "solid-state imaging device of the second configuration". Further, in this manner, the first electrode can be shared by the plurality of imaging elements included in the imaging element block to simplify and miniaturize the structure and construction of the pixel region including the plurality of array imaging elements.

[0264] In each of the solid-state imaging devices of the first and second configurations, one floating diffusion layer is provided for the plurality of imaging elements (one imaging element block). The plurality of imaging elements provided for one floating diffusion layer may include a plurality of imaging elements of the first type described later, or may include at least one imaging element of the first type and one or two or more imaging elements of the second type described later. Further, the timing of the charge transfer period can be appropriately controlled to allow the plurality of imaging elements to share one floating diffusion layer. The plurality of imaging elements operate together and are connected as an imaging element block to a drive circuit described later. That is, the plurality of imaging elements included in the imaging element block are connected to one drive circuit. However, the charge storage electrode is controlled for each imaging element. Additionally, the plurality of imaging elements may share one contact hole portion. Regarding the arrangement relationship between the first electrode shared by the plurality of imaging elements and the charge storage electrode of each imaging element, the first electrode may be arranged near the charge storage electrode of each imaging element. Alternatively, the first electrode may be arranged adjacent to the charge storage electrodes of a part of the plurality of imaging elements and not arranged adjacent to the charge storage electrodes of the remaining part of the plurality of imaging elements. In this case, the movement of charge from the remaining part of the plurality of imaging elements to the first electrode is through the movement of the part of the plurality of imaging elements. Preferably, the distance (referred to as "distance A" for convenience) between the charge storage electrodes included in the imaging element is longer than the distance (referred to as "distance B" for convenience) between the first electrode and the charge storage electrode in the imaging element adjacent to the first electrode to ensure the movement of charge from each imaging element to the first electrode. Further, preferably, the farther the imaging element is from the first electrode, the larger the value of distance A.

[0265] In addition, in each of the imaging elements and the like of the present disclosure including the above various preferred modes, light can be incident from the second electrode side, and a light-shielding layer can be formed on the light-incident side closer to the second electrode. Alternatively, light can be incident from the second electrode side, and the light may not be incident on the first electrode (the first electrode and the transfer control electrode, as the case may be). In addition, in this case, the light-shielding layer can be formed on the light-incident side closer to the second electrode and the upper side of the first electrode (the first electrode and the transfer control electrode, as the case may be). Alternatively, an on-chip microlens can be provided on the upper side of the charge storage electrode and the second electrode, and the light incident on the on-chip microlens can be collected by the charge storage electrode. Here, the light-shielding layer can be provided on the upper side of the surface of the light-incident side of the second electrode, or can be provided on the surface of the light-incident side of the second electrode. As the case may be, a light-shielding layer can be formed on the second electrode. Examples of the material included in the light-shielding layer include chromium (Cr), copper (Cu), aluminum (Al), tungsten (W), and a light-shielding resin (e.g., polyimide resin).

[0266] Specific examples of the imaging element of the present disclosure include: an imaging element sensitive to blue light (conveniently referred to as the "first type of blue light imaging element") including a photoelectric conversion layer that absorbs blue light (light with a wavelength of 425 to 495 nm) (conveniently referred to as the "first type of blue light photoelectric conversion layer"); an imaging element sensitive to green light (conveniently referred to as the "first type of green light imaging element") including a photoelectric conversion layer that absorbs green light (light with a wavelength of 495 to 570 nm) (conveniently referred to as the "first type of green light photoelectric conversion layer"); and an imaging element sensitive to red light (conveniently referred to as the "first type of red light imaging element") including a photoelectric conversion layer that absorbs red light (light with a wavelength of 620 to 750 nm) (conveniently referred to as the "first type of red light photoelectric conversion layer"). In addition, for convenience, an imaging element sensitive to blue light that is a conventional imaging element without a charge storage electrode is referred to as the "second type of blue light imaging element". For convenience, a conventional imaging element sensitive to green light is referred to as the "second type of green light imaging element". For convenience, a conventional imaging element sensitive to red light is referred to as the "second type of red light imaging element". For convenience, the photoelectric conversion layer included in the second type of blue light imaging element is referred to as the "second type of blue light photoelectric conversion layer". For convenience, the photoelectric conversion layer included in the second type of green light imaging element is referred to as the "second type of green light photoelectric conversion layer". For convenience, the photoelectric conversion layer included in the second type of red light imaging element is referred to as the "second type of red light photoelectric conversion layer".

[0267] The stacked imaging element of the present disclosure includes at least one imaging element (photoelectric conversion element) of the present disclosure, and specific examples of the structure and configuration include:

[0268] [A] The structure and configuration in which a first-type blue light photoelectric conversion unit, a first-type green light photoelectric conversion unit, and a first-type red light photoelectric conversion unit are stacked in the vertical direction, and

[0269] A control unit for a first-type blue light imaging element, a first-type green light imaging element, and a first-type red light imaging element is provided on the semiconductor substrate;

[0270] [B] The structure and configuration in which a first-type blue light photoelectric conversion unit and a first-type green light photoelectric conversion unit are stacked in the vertical direction,

[0271] A second-type red light photoelectric conversion unit is arranged on the lower side of these two first-type photoelectric conversion units, and

[0272] A control unit for a first-type blue light imaging element, a first-type green light imaging element, and a second-type red light imaging element is provided on the semiconductor substrate;

[0273] [C] The structure and configuration in which a second-type blue light photoelectric conversion unit and a second-type red light photoelectric conversion unit are arranged on the lower side of a first-type green light photoelectric conversion unit, and

[0274] A control unit for a first-type green light imaging element, a second-type blue light imaging element, and a second-type red light imaging element is provided on the semiconductor substrate;

[0275] [D] The structure and configuration in which a second-type green light photoelectric conversion unit and a second-type red light photoelectric conversion unit are arranged on the lower side of a first-type blue light photoelectric conversion unit, and

[0276] A control unit for a first-type blue light imaging element, a second-type green light imaging element, and a second-type red light imaging element is provided on the semiconductor substrate. Note that preferably, the arrangement order of the photoelectric conversion units of the imaging elements in the vertical direction is: from the light incident direction, the blue light photoelectric conversion unit, the green light photoelectric conversion unit, and the red light photoelectric conversion unit; or from the light incident direction, the green light photoelectric conversion unit, the blue light photoelectric conversion unit, and the red light photoelectric conversion unit. This is because light with a shorter wavelength is effectively absorbed on the incident surface side. Among the three colors, red has the longest wavelength, and preferably, from the light incident surface, the red light photoelectric conversion unit is located in the lowermost layer. The stacked structure of the imaging elements provides one pixel. In addition, a first-type infrared photoelectric conversion unit may also be included. Here, preferably, the photoelectric conversion layer of the first-type infrared photoelectric conversion unit includes, for example, an organic material and is arranged in the lowermost layer of the stacked structure of the first-type imaging elements and above the second-type imaging elements. Or, a second-type infrared photoelectric conversion unit may also be included on the lower side of the first-type photoelectric conversion units.

[0277] In a first type of imaging element, a first electrode is formed on, for example, an interlayer insulating layer provided on a semiconductor substrate. The imaging element formed on the semiconductor substrate may be a back-illumination type or a front-illumination type.

[0278] When the photoelectric conversion layer includes an organic material, the photoelectric conversion layer may be one of the following four modes.

[0279] (1) The photoelectric conversion layer includes a p-type organic semiconductor.

[0280] (2) The photoelectric conversion layer includes an n-type organic semiconductor.

[0281] (3) The photoelectric conversion layer includes a stacked structure of a p-type organic semiconductor layer / an n-type organic semiconductor layer. The photoelectric conversion layer includes a stacked structure of a p-type organic semiconductor layer / a mixed layer (bulk heterostructure) of a p-type organic semiconductor and an n-type organic semiconductor / an n-type organic semiconductor layer. The photoelectric conversion layer includes a stacked structure of a p-type organic semiconductor layer / a mixed layer (bulk heterostructure) of a p-type organic semiconductor and an n-type organic semiconductor. The photoelectric conversion layer includes a stacked structure of an n-type organic semiconductor layer / a mixed layer (bulk heterostructure) of a p-type organic semiconductor and an n-type organic semiconductor.

[0282] (4) The photoelectric conversion layer includes a mixture (bulk heterostructure) of a p-type organic semiconductor and an n-type organic semiconductor.

[0283] Here, the stacking order can be changed arbitrarily.

[0284] Examples of the p-type organic semiconductor include naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, pyrene derivatives, perylene derivatives, tetracene derivatives, pentacene derivatives, quinacridone derivatives, thiophene derivatives, thienothiophene derivatives, benzothiophene derivatives, benzothiophenobenzothiophene derivatives, triallylamine derivatives, carbazole derivatives, perylene derivatives, picene derivatives, Derivatives, fluoranthene derivatives, phthalocyanine derivatives, subphthalocyanine derivatives, subporphyrin derivatives, metal complexes including heterocyclic compounds as ligands, polythiophene derivatives, polybenzothiadiazole derivatives, and polyfluorene derivatives. Examples of n-type organic semiconductors include fullerenes and fullerene derivatives <e.g., fullerenes (higher fullerenes) such as C60, C70, and C74 or endohedral fullerenes, etc.) or fullerene derivatives (e.g., fullerene fluorides, PCBM fullerene compounds, or fullerene polymers, etc.)>, organic semiconductors having a larger (deeper) HOMO and LUMO than p-type organic semiconductors, and transparent inorganic metal oxides. Specific examples of n-type organic semiconductors include organic molecules containing a heterocyclic compound as part of the molecular framework, the heterocyclic compound containing nitrogen atoms, oxygen atoms, and sulfur atoms, such as pyridine derivatives, pyrazine derivatives, pyrimidine derivatives, triazine derivatives, quinoline derivatives, quinoxaline derivatives, isoquinoline derivatives, acridine derivatives, phenazine derivatives, phenanthroline derivatives, tetrazole derivatives, pyrazole derivatives, imidazole derivatives, thiazole derivatives, oxazole derivatives, imidazole derivatives, benzimidazole derivatives, benzotriazole derivatives, benzoxazole derivatives, benzoxazole derivatives, carbazole derivatives, benzofuran derivatives, dibenzofuran derivatives, subporphyrin derivatives, polyphenylene derivatives, polybenzothiazole derivatives, and polyfluorene derivatives, organometallic complexes, and subphthalocyanine derivatives. Examples of groups, etc. contained in fullerene derivatives include: halogen atoms; linear, branched, or cycloalkyl or phenyl groups; groups including linear or condensed aromatic compounds; groups including halides; partially fluorinated alkyl groups; perfluoroalkyl groups; silylalkyl groups; silylalkoxy groups; arylsilyl groups; arylsulfanyl groups; alkylsulfanyl groups; arylsulfonyl groups; alkylsulfonyl groups; arylthioether groups; alkylthioether groups; amino groups; alkylamino groups; arylamino groups; hydroxyl groups; alkoxy groups; acylamino groups; acyloxy groups; carbonyl groups; carboxyl groups; carboxamide groups; alkoxycarbonyl groups; acyl groups; sulfonyl groups; cyano groups; nitro groups; groups including chalcogen compounds; phosphine groups; phosphon groups; and their derivatives. Although the thickness of the photoelectric conversion layer (sometimes referred to as the "organic photoelectric conversion layer") including the organic material is not limited, the thickness can be, for example, 1×10 -8 m to 5×10 -7 m, preferably 2.5×10 -8 m to 3×10 -7 m, more preferably 2.5×10 -8 m to 2×10 -7 m, further preferably 1×10 -7 m to 1.8×10 -7m. Note that organic semiconductors are generally classified into p-type and n-type. The p-type indicates that holes are easily transported, and the n-type indicates that electrons are easily transported. The organic semiconductor is not limited to the following explanation: holes or electrons are included in inorganic semiconductors as thermally excited majority carriers.

[0285] Alternatively, examples of materials included in the organic photoelectric conversion layer for green light photoelectric conversion include rhodamine dyes, merocyanine dyes, quinacridone derivatives, and subphthalocyanine dyes (subphthalocyanine derivatives). Examples of materials included in the organic photoelectric conversion layer for blue light photoelectric conversion include coumaric acid dyes, tris(8-hydroxyquinoline)aluminum (Alq3), and merocyanine dyes. Examples of materials included in the organic photoelectric conversion layer for red light photoelectric conversion include phthalocyanine dyes and subphthalocyanine dyes (subphthalocyanine derivatives).

[0286] Alternatively, examples of inorganic materials included in the photoelectric conversion layer include crystalline silicon, amorphous silicon, microcrystalline silicon, crystalline selenium, amorphous selenium, chalcopyrite compounds such as CIGS (CuInGaSe), cis (CuInSe 2 ), CuInS 2 , CuAlS 2 , CuAlSe 2 , CuGaS 2 , CuGaSe 2 , AgAlS 2 , AgAlSe 2 , AgInS 2 and AgInSe 2 , III-V group compounds such as GaAs, InP, AlGaAs, InGaP, AlGaInP, and InGaAsP, and compound semiconductors such as CdSe, Cds, In 2 S e3 , In 2 S 3 , Bi 2 Se 3 , Bi 2 S 3 , ZnSe, ZnS, PbSe, and PbS and other compound semiconductors, etc. In addition, quantum dots containing these materials can also be used in the photoelectric conversion layer.

[0287] Alternatively, the photoelectric conversion layer may have a stacked structure of a lower semiconductor layer and an upper photoelectric conversion layer as described above. The lower semiconductor layer can be arranged in such a way as to prevent, for example, recombination during charge storage. In addition, the charge transfer efficiency of the charges stored in the photoelectric conversion layer to the first electrode can be improved. In addition, the charges generated in the photoelectric conversion layer can be temporarily held to control the transfer timing and the like. In addition, the generation of dark current can be suppressed. The material contained in the upper photoelectric conversion layer can be appropriately selected from various materials contained in the photoelectric conversion layer. On the other hand, preferably, the material for the lower semiconductor layer is a material having a large bandgap energy value (for example, a bandgap energy value equal to or greater than 3.0 eV) and having a higher mobility than the material contained in the photoelectric conversion layer. Specific examples of such materials include: oxide semiconductor materials such as IGZO; transition metal dichalcogenides; silicon carbide; diamond; graphene; carbon nanotubes; and organic semiconductor materials such as fused polycyclic hydrocarbon compounds and fused heterocyclic compounds. Alternatively, other examples of the materials included in the lower semiconductor layer include: a material having an ionization potential greater than that of the material contained in the photoelectric conversion layer when the charge to be stored is an electron; and a material having an electron affinity smaller than that of the material contained in the photoelectric conversion layer when the charge to be stored is a hole. Alternatively, preferably, the impurity concentration of the material contained in the lower semiconductor layer is equal to or less than 1×10 18 cm -3 . The lower semiconductor layer may have a single-layer structure or may have a multi-layer structure. In addition, the materials contained in the lower semiconductor layer on the upper side of the charge storage electrode and the materials contained in the lower semiconductor layer on the upper side of the first electrode may be different.

[0288] The solid-state imaging device according to the first and second aspects of the present disclosure and the solid-state imaging device having the first and second configurations can provide a single-board color solid-state imaging device.

[0289] In a solid-state imaging device according to a second aspect of the present disclosure or a solid-state imaging device having a second configuration including a stacked imaging element, different from a solid-state imaging device having an imaging element including a Bayer array (i.e., not using a color filter to separate blue, green, and red), imaging elements sensitive to multiple wavelength types of light are stacked in the same pixel in the light incident direction to provide one pixel. Therefore, sensitivity can be improved, and the pixel density per unit volume can be increased. In addition, the absorption coefficient of the organic material is high, and the film thickness of the organic photoelectric conversion layer can be thinner than that of a conventional Si-based photoelectric conversion layer. This reduces light leakage from adjacent pixels and alleviates the limitation on the light incident angle. Further, in a conventional Si-based imaging element, interpolation processing is performed on pixels of three colors to generate a color signal, and thus false colors are generated. In a solid-state imaging device according to a second aspect of the present disclosure or a solid-state imaging device having a second configuration including a stacked imaging element, generation of false colors is suppressed. The organic photoelectric conversion layer also functions as a color filter and can separate colors without arranging a color filter.

[0290] On the other hand, in a solid-state imaging device according to a first aspect of the present disclosure or a solid-state imaging device having a first configuration, a color filter can be used to alleviate the requirements for the spectral characteristics of blue, green, and red, and mass productivity is high. Examples of the array of imaging elements in a solid-state imaging device according to a first aspect of the present disclosure or a solid-state imaging device having a first configuration include a Bayer array, an interline array, a G-bar RB lattice array, a G-bar RB full lattice array, a lattice complementary color array, a stripe array, a diagonal stripe array, a principal chromatic aberration array, a field chromatic aberration sequence array, a frame chromatic aberration sequence array, a MOS array, an improved MOS array, a frame interleaved array, and a field interleaved array. Here, one imaging element provides one pixel (or sub-pixel).

[0291] A pixel region provided with a plurality of array imaging elements of the present disclosure or a plurality of array stacked imaging elements of the present disclosure includes a plurality of pixels systematically arranged in a two-dimensional array. The pixel region generally includes: an effective pixel region in which light is actually received, thereby generating signal charges through photoelectric conversion, and the signal charges are amplified and read out to a driving circuit; and a black reference pixel region for outputting optical black as a standard of the black level. The black reference pixel region is generally arranged at the periphery of the effective pixel region.

[0292] In the imaging element and the like of the present disclosure including the above various preferred modes and configurations, light is applied, and photoelectric conversion occurs in the photoelectric conversion layer. Carrier separation of electron-hole (hole) and electron is performed. In addition, the electrode from which holes are extracted is the anode, and the electrode from which electrons are extracted is the cathode. There is a mode in which the first electrode provides the anode and the second electrode provides the cathode. Conversely, there is also a mode in which the first electrode provides the cathode and the second electrode provides the anode.

[0293] In the case of providing a stacked imaging element, the first electrode, the charge storage electrode, the charge movement control electrode, the transmission control electrode, and the second electrode can include a transparent conductive material. Note that in some cases, the first electrode, the charge storage electrode, the charge movement control electrode, and the transmission control electrode are collectively referred to as "the first electrode etc.". Alternatively, in the case where the imaging element and the like of the present disclosure are arranged on a plane in, for example, a Bayer array, the second electrode can include a transparent conductive material, and the first electrode etc. can include a metal material. In this case, specifically, the second electrode located on the light incident side can include a transparent conductive material, and the first electrode etc. can include, for example, Al-Nd (an alloy of aluminum and neodymium) or ASC (an alloy of aluminum, samarium, and copper). Note that in some cases, an electrode including a transparent conductive material is referred to as a "transparent electrode". Here, it is desired that the band gap energy of the transparent conductive material is equal to or greater than 2.5 eV, preferably equal to or greater than 3.1 eV. Examples of the transparent conductive material included in the transparent electrode include conductive metal oxides. Specifically, examples of the transparent conductive material include indium oxide, indium tin oxide (including ITO, indium tin oxide, Sn-doped In 2 O 3 , crystalline ITO, and amorphous ITO), indium zinc oxide (IZO, indium zinc oxide) obtained by adding indium as a dopant to zinc oxide, indium gallium oxide (IGO) obtained by adding indium as a dopant to gallium oxide, indium-gallium-zinc oxide (IGZO, In-GaZnO 4 ) obtained by adding indium and gallium as dopants to zinc oxide, indium-tin-zinc oxide (ITZO) obtained by adding indium and tin as dopants to zinc oxide, IFO (fluorine-doped In 2 O 3 ), tin dioxide (SnO 2 ), ATO (antimony-doped SnO 2 ), FTO (fluorine-doped SnO 2 ), zinc oxide (including zinc oxide doped with other elements), aluminum zinc oxide (AZO) obtained by adding aluminum as a dopant to zinc oxide, gallium zinc oxide (GZO) obtained by adding gallium as a dopant to zinc oxide, titanium oxide (TiO 2) Niobium titanium oxide (TNO) obtained by adding niobium as a dopant to titanium oxide, antimony oxide, spinel oxide, and oxide having a YbFe 2 O 4 structure. Alternatively, the transparent electrode may include gallium oxide, titanium oxide, niobium oxide, nickel oxide, etc. as a mother layer. Examples of the thickness of the transparent electrode include 2×10 -8 m to 2×10 -7 m, preferably 3×10 -8 m to 1×10 -7 m. When the first electrode needs to be transparent, from the perspective of simplifying the manufacturing process, it is preferred that the other electrodes also include a transparent conductive material.

[0294] Alternatively, when transparency is not required, it is preferred to use a conductive material having a high work function (e.g., to 5.5 eV) as the conductive material included in the anode having the function of extracting holes. Specifically, examples of the conductive material include gold (Au), silver (Ag), chromium (Cr), nickel (Ni), palladium (Pd), platinum (Pt), iron (Fe), iridium (Ir), germanium (Ge), osmium (Os), rhenium (Re), and tellurium (Te). On the other hand, it is preferred to use a conductive material having a low work function (e.g., A conductive material with a work function of 4.0 to 4.5 eV is used as the conductive material included in the cathode having the function of an electrode for extracting electrons. Specifically, examples of the conductive material include alkali metals (such as Li, Na, K, etc.) and fluorides or oxides of alkali metals, alkaline earth metals (such as Mg, Ca, etc.) and fluorides or oxides of alkaline earth metals, aluminum (Al), zinc (Zn), tin (Sn), thallium (Tl), sodium-potassium alloy, aluminum-lithium alloy, magnesium-silver alloy, indium, rare earth metals (such as ytterbium), and their alloys. Alternatively, examples of the materials included in the anode or cathode include metals such as platinum (Pt), gold (Au), palladium (Pd), chromium (Cr), nickel (Ni), aluminum (Al), silver (Ag), tantalum (Ta), tungsten (W), copper (Cu), titanium (Ti), indium (In), tin (Sn), iron (Fe), cobalt (Co), and molybdenum (Mo), alloys containing these metal elements, conductive particles including these metals, conductive particles of alloys containing these metals, polycrystalline silicon containing impurities, carbon materials, oxide semiconductor materials, carbon nanotubes, and conductive materials such as graphene. The anode or cathode may also have a multi-layer stacked structure containing these elements. In addition, examples of the materials included in the anode or cathode also include organic materials (conductive polymers) such as poly(3,4-ethylenedioxythiophene-poly(styrenesulfonate)) [PEDOT / PSS]. Furthermore, these conductive materials can be mixed with a binder (polymer) to obtain a paste or ink, and the paste or ink can be cured and used as an electrode.

[0295] A dry method or a wet method can be used as the deposition method for the first electrode, etc. or the second electrode (cathode or anode). Examples of the dry method include physical vapor deposition (PVD method) and chemical vapor deposition (CVD method). Examples of the deposition methods using the PVD method principle include vacuum evaporation using resistance heating or radio frequency heating, EB (electron beam) evaporation method, various sputtering methods (magnetron sputtering method, RF-DC coupled bias sputtering method, ECR sputtering method, facing target sputtering method, and RF sputtering method), ion plating method, laser ablation method, molecular beam epitaxy method, and laser transfer method. In addition, examples of the CVD method include plasma CVD method, thermal CVD method, metalorganic (MO) CVD method, and optical CVD method. On the other hand, examples of the wet method include various methods such as electroplating method, electroless plating method, spin coating method, inkjet method, spraying method, imprinting method, microcontact printing method, flexographic printing method, offset printing method, gravure printing method, and dipping method. Examples of the patterning method include chemical etching such as shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet light or laser, etc. Examples of the planarization method for the first electrode, etc. and the second electrode include laser planarization method, reflow method, and CMP (chemical mechanical polishing) method.

[0296] In addition to the insulating layer and the like in the imaging element according to the fifth aspect of the present disclosure, examples of the materials included in the insulating layer include not only inorganic insulating materials such as metal oxide high-dielectric insulating materials, such as silicon oxide materials, silicon nitride (SiN y ), and aluminum oxide (Al 2 O 3 ), but also organic insulating materials (organic polymers), such as: polymethyl methacrylate (PMMA); polyvinyl phenol (PVP); polyvinyl alcohol (PVA); polyimide; polycarbonate (PC); polyethylene terephthalate (PET); polystyrene; silanol derivatives (silane coupling agents), such as N-(2-aminoethyl)-3-aminopropyltrimethoxysilane (AEAPTMS), 3-mercaptopropyltrimethoxysilane (MPTMS), and octadecyltrichlorosilane (OTS), novolac phenolic resin; fluororesins, and straight-chain hydrocarbons, such as octadecyl mercaptan and dodecyl isocyanate, including a functional group capable of binding to the control electrode at one end. Note that examples of the silicon oxide material include silicon oxide (SiOx), BPSG, PSG, BSG, AsSG, PbSG, silicon oxynitride (SiON), SOG (spin-on glass), and low-dielectric insulating materials (e.g., polyarylether, fluorinated carbon polymer, benzocyclobutene, fluorinated epoxy resin, polytetrafluoroethylene, fluorinated aryl ether, fluorinated polyimide, amorphous carbon, and organic SOG). These materials can also be appropriately selected for the materials included in various interlayer insulating layers and insulating films.

[0297] The structure and construction of the floating diffusion layer, amplifier transistor, reset transistor, and selection transistor included in the control unit can be similar to the structure and construction of the conventional floating diffusion layer, amplifier transistor, reset transistor, and selection transistor. The drive circuit can also have a known structure and construction.

[0298] The first electrode is connected to the floating diffusion layer and the gate portion of the amplifier transistor, and a contact hole portion can be formed for connecting the first electrode to the floating diffusion layer and the gate portion of the amplifier transistor. Examples of the materials included in the contact hole portion include doped polysilicon, high-melting-point metals, and metal silicides, such as tungsten, Ti, Pt, Pd, Cu, TiW, TiN, TiNW, WSi 2 and MoSi 2 and a stacked structure including these materials (e.g., Ti / TiN / W).

[0299] A first carrier blocking layer may be provided between the organic optoelectronic conversion layer and the first electrode, and a second carrier blocking layer may be provided between the organic optoelectronic conversion layer and the second electrode. In addition, a first charge injection layer may be provided between the first carrier blocking layer and the first electrode, and a second charge injection layer may be provided between the second carrier blocking layer and the second electrode. For example, examples of materials included in the electron injection layer include alkali metals such as lithium (Li), sodium (Na), and potassium (K), fluorides or oxides of alkali metals, alkaline earth metals such as magnesium (Mg) and calcium (Ca), and fluorides or oxides of alkaline earth metals.

[0300] Examples of deposition methods for various organic layers include dry deposition methods and wet deposition methods. Examples of dry deposition methods include vacuum evaporation methods using resistance heating, radio frequency heating, or electron beam heating, flash evaporation methods, plasma deposition methods, EB evaporation methods, various sputtering methods (bipolar sputtering method, DC sputtering method, DC magnetron sputtering method, RF sputtering method, magnetron sputtering method, RF-DC coupled bias sputtering method, ECR sputtering method, facing target sputtering method, RF sputtering method, and ion beam sputtering method), DC (direct current) method, RF method, multi-cathode method, activated reaction method, electric field evaporation method, various ion plating methods (such as RF ion plating method and reactive ion plating method), laser ablation method, molecular beam epitaxy method, laser transfer method, and molecular beam epitaxy method (MBE method). In addition, examples of CVD methods include plasma CVD method, thermal CVD method, MOCVD method, and optical CVD method. On the other hand, specific examples of wet methods include: spin coating method; dipping method; casting method; microcontact printing method; drop casting method; various printing methods such as screen printing method, inkjet printing method, offset printing method, gravure printing method, flexographic printing method, stamping method, spraying method; and various coating methods such as air knife coating method, blade coating method, rod coating method, knife coating method, extrusion coating method, reverse roll coating method, transfer roll coating method, gravure coating method, kiss coating method, cast coating method, spray coating method, slot die coating method, and calendar coater method. Note that in coating methods, examples of solvents include non-polar or low-polar organic solvents such as toluene, chloroform, hexane, and ethanol. Examples of patterning methods include chemical etching such as shadow masking, laser transfer, and photolithography, and physical etching using ultraviolet light, laser, etc. Laser planarization method, reflow method, etc. can be used as planarization techniques for various organic layers.

[0301] Two or more types of imaging elements, etc. according to the first to ninth aspects of the present disclosure and imaging elements including the first to sixth configurations of the above preferred modes and structures can be appropriately combined as needed.

[0302] As described above, an on-chip microlens and a light-shielding layer can be provided on the imaging element or the solid-state imaging device as needed, and a driving circuit and wirings for driving the imaging element can be provided. A shutter for controlling light incident on the imaging element can be arranged as needed, and an optical cut-off filter can be provided according to the purpose of the solid-state imaging device.

[0303] In addition, the solid-state imaging devices of the first and second configurations can be in a mode where one on-chip microlens is arranged on the upper side of one imaging element. Alternatively, two imaging elements can be included in an imaging element block, and one on-chip microlens can be arranged on the upper side of the imaging element block.

[0304] For example, in the case of stacking a solid-state imaging device and a readout integrated circuit (ROIC), a driving substrate having a readout integrated circuit and a connection portion containing copper (Cu) and an imaging element provided with a connection portion can be stacked on top of each other such that the connection portions are in contact with each other. The connection portions can be combined to laminate the solid-state imaging device and the readout integrated circuit, or solder bumps or the like can be used to join the connection portions.

[0305] In addition, a driving method for driving the solid-state imaging devices according to the first and second aspects of the present disclosure can be a driving method for a solid-state imaging device that repeats the following steps:

[0306] In all the imaging elements, charges are stored in the photoelectric conversion layer, and all the charges in the first electrode are discharged to the outside of the system at once; subsequently,

[0307] In all the imaging elements, all the charges stored in the photoelectric conversion layer are transferred to the first electrode at once, and after the transfer is completed, the charges transferred to the first electrode in each imaging element are read sequentially.

[0308] In the driving method of the solid-state imaging device, in each imaging element, light incident from the second electrode side does not enter the first electrode. In all the imaging elements, charges are stored in the photoelectric conversion layer in all the imaging elements, and all the charges in the first electrode are released to the outside of the system at once. Therefore, in all the imaging elements, the first electrode can surely be reset simultaneously. In addition, subsequently, in all the imaging elements, all the charges stored in the photoelectric conversion layer are transferred to the first electrode at once. After the transfer is completed, the imaging elements read the charges transferred to the first electrode sequentially. Therefore, it is possible to easily achieve a so-called global shutter function.

[0309] Example 1

[0310] Example 1 relates to an imaging element or the like according to the first aspect of the present disclosure, an imaging element or the like according to the third aspect of the present disclosure, a stacked imaging element of the present disclosure, and a solid-state imaging device according to the second aspect of the present disclosure.

[0311] Figure 1A Shows a schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 1. Note that the Figure 1A or Figure 1B The schematic cross-sectional view is similar to, for example, the schematic cross-sectional view taken along the Fig.15A Single-dot chain line A-A. In addition, Figure 2 Shows a schematic partial cross-sectional view of the imaging element and the stacked imaging element of Example 1. Figure 3 And Figure 4 Show the equivalent circuit diagrams of the imaging element and the stacked imaging element of Example 1. Figure 5 Shows a schematic layout diagram of the transistors of the first electrode, the charge storage electrode, and the control unit included in the imaging element of Example 1. In addition, Figure 6 And Figure 7 Show the schematic layout diagrams of the first electrode and the charge storage electrode included in the imaging element of Example 1. Figure 8 Schematically illustrates the state of the electric potential in each part during the operation of the imaging element of Example 1. Fig. 9A Shows the equivalent circuit diagrams of the imaging element and the stacked imaging element of Example 1 for describing the Figure 8 Each part. Fig.10 Shows a conceptual diagram of the solid-state imaging device of Example 1. Note that, for convenience, various constituent elements of the imaging element located on the lower side of the interlayer insulating layer 81 may be collectively denoted by reference numeral 91 to simplify the drawing.

[0312] Each of the imaging element of Example 1 (for example, the green light imaging element described later) and the imaging elements of Examples 2 to 8 described later includes a photoelectric conversion unit, which includes a stacked first electrode 11, a photoelectric conversion layer 13, and a second electrode 12. The photoelectric conversion unit further includes a charge storage electrode 14 that is disposed away from the first electrode 11 and is disposed to face the photoelectric conversion layer 13 through an insulating layer 82.

[0313] Note that, in the Figure 6 Shown example, one imaging element is provided with one charge storage electrode 14 corresponding to one first electrode 11. On the other hand, in the Figure 7 Shown example (Variant Example 1 of Example 1), two imaging elements are provided with one common first electrode 11 corresponding to two charge storage electrodes 14. Figure 1A The schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 1 shown corresponds to Figure 7 .

[0314] Except for the imaging element of Example 3 and the like described later, the second electrode 12 located on the light incident side is shared by a plurality of imaging elements, that is, the second electrode 12 is a so-called solid electrode. The photoelectric conversion layer 13 is shared by a plurality of imaging elements. That is, one photoelectric conversion layer 13 is formed in a plurality of imaging elements.

[0315] The stacked imaging element of Example 1 includes at least one of the imaging element of Example 1 and the imaging elements of Examples 2 to 8 described later. In Example 1, the stacked imaging element includes one of the imaging element of Example 1 and the imaging elements of Examples 2 to 8 described later.

[0316] In addition, the solid-state imaging device of Example 1 includes a plurality of stacked imaging elements of the imaging elements of Example 1 and Examples 2 to 8 described later.

[0317] In addition, when light is incident on the photoelectric conversion layer 13 and photoelectric conversion occurs in the photoelectric conversion layer 13 in the imaging element of Example 1, the absolute value of the electric potential applied to the portion 13 of the photoelectric conversion layer 13 facing the charge storage electrode 14 C is greater than the absolute value of the electric potential applied to the region 13 of the photoelectric conversion layer 13 located between the imaging element and the adjacent imaging element B (region B of the photoelectric conversion layer).

[0318] Alternatively, in the imaging element of Example 1, the charge movement control electrode 21 is formed in the region 13 of the photoelectric conversion layer located between the imaging element and the adjacent imaging element and facing the photoelectric conversion layer 13 via the insulating layer 82 B (region B of the photoelectric conversion layer). In other words, the charge movement control electrode 21 is formed in the region (region b) between the charge storage electrode 14 and the charge storage electrode 14 of the adjacent imaging element below the portion 82 of the insulating layer 82 B (region B of the insulating layer 82). The charge movement control electrode 21 is provided to be separated from the charge storage electrode 14. Or, in other words, the charge movement control electrode 21 is provided around the charge storage electrode 14 and separated from the charge storage electrode 14, and the charge movement control electrode 21 is provided to face the region B of the photoelectric conversion layer via the insulating layer 82 (13 B ). Note that although the charge movement control electrode 21 is not shown in Figure 2 , the charge movement control electrode 21 is formed in the direction of arrow "A". The charge movement control electrode 21 is shared by the imaging elements arranged in the Figure 5 left-right direction and is shared by a pair of imaging elements arranged in the Figure 5 up-down direction.

[0319] For convenience, the charge movement control electrode 21 (not shown), connection holes 23, pad portions 22, and wiring V (described later) 0B of the imaging element are referred to as "imaging elements having the basic structure of the present disclosure." Figure 2 FIG. 4 is a schematic partial cross-sectional view of an imaging element having the basic structure of the present disclosure. Fig.42 , 43 , 44, 45, 46, 47, 54, 61, 62, 64, 65, 66, 71, 88, 89, 91, 92, 93, 94, 95, 96, 97, and 98 are schematic partial cross-sectional views of various modified examples of the imaging element having the basic structure of the present disclosure as shown in Figure 2 FIG. 10, and the charge movement control electrode 21 and the like are not shown.

[0320] Further, a semiconductor substrate (more specifically, a silicon semiconductor layer) is included, and a photoelectric conversion unit is provided on the upper side of the semiconductor substrate 70. Further, a control unit is included, and the control unit is provided on the semiconductor substrate 70 and includes a drive circuit connected to the first electrode 11 and the second electrode 12. Here, the light incident surface of the semiconductor substrate 70 is the upper side, and the opposite side of the semiconductor substrate 70 is the lower side. A wiring layer 62 including a plurality of wirings is provided on the lower side of the semiconductor substrate 70.

[0321] The semiconductor substrate 70 is provided with at least one floating diffusion layer FD 1 and an amplification transistor TR1 amp included in the control unit, and the first electrode 11 is connected to the floating diffusion layer FD 1 and the gate portion of the amplification transistor TR1 amp . The semiconductor substrate 70 is further provided with a reset transistor TR1 rst and a selection transistor TR1 set included in the control unit. The floating diffusion layer FD 1 is connected to one source / drain region of the reset transistor TR1 rst . The other source / drain region of the amplification transistor TR1 amp is connected to one source / drain region of the selection transistor TR1 set . The other source / drain region of the selection transistor TR1 set is connected to the signal line VSL 1 . The amplification transistor TR1 amp , the reset transistor TR1 rst , and the selection transistor TR1 set are included in the drive circuit.

[0322] Specifically, the imaging element and the stacked imaging element of Embodiment 1 are back-illuminated imaging elements and back-illuminated stacked imaging elements. The imaging element and the stacked imaging element have a stacked structure of three imaging elements, including: a first type of green light imaging element (hereinafter, referred to as "first imaging element") in Embodiment 1 that is sensitive to green light, and the green light imaging element includes a first type of green light photoelectric conversion layer for absorbing green light; a conventional second type of blue light imaging element (hereinafter, referred to as "second imaging element") that is sensitive to blue light, and the blue light imaging element includes a second type of blue light photoelectric conversion layer for absorbing blue light; and a conventional second type of red light imaging element (hereinafter, referred to as "third imaging element") that is sensitive to red light, and the red light imaging element includes a second type of red light photoelectric conversion layer for absorbing red light. Here, the red light imaging element (third imaging element) and the blue light imaging element (second imaging element) are provided in the semiconductor substrate 70, and the second imaging element is located on the light incident side with respect to the third imaging element. In addition, the green light imaging element (first imaging element) is provided on the upper side of the blue light imaging element (second imaging element). The stacked structure of the first imaging element, the second imaging element, and the third imaging element is included in one pixel. A color filter is not provided.

[0323] In the first imaging element, a first electrode 11 and a charge storage electrode 14 are formed separately from each other on the interlayer insulating layer 81. In addition, a charge movement control electrode 21 is formed on the interlayer insulating layer 81 separately from the charge storage electrode 14. The interlayer insulating layer 81, the charge storage electrode 14, and the charge movement control electrode 21 are covered by an insulating layer 82. A photoelectric conversion layer 13 is formed on the insulating layer 82, and a second electrode 12 is formed on the photoelectric conversion layer 13. A protective layer 83 is formed on the entire surface including the second electrode 12, and an on-chip microlens 90 is provided on the protective layer 83. For example, the first electrode 11, the charge storage electrode 14, the charge movement control electrode 21, and the second electrode 12 include a transparent electrode containing ITO (work function: about 4.4 ev). The photoelectric conversion layer 13 includes a layer containing a known organic photoelectric conversion material that is at least sensitive to green light (for example, organic substances such as rhodamine dyes, phthalocyanine dyes, and quinacridone). In addition, the photoelectric conversion layer 13 may further include a material layer suitable for charge storage. That is, a material layer suitable for charge storage may be further formed between the photoelectric conversion layer 13 and the first electrode 11 (for example, in the connection portion 67). The interlayer insulating layer 81, the insulating layer 82, and the protective layer 83 include known insulating materials (for example, SiO 2 or SiN). The photoelectric conversion layer 13 and the first electrode 11 are connected by a connection portion 67 provided on the insulating layer 82. The photoelectric conversion layer 13 extends in the connection portion 67. That is, the photoelectric conversion layer 13 extends in the opening 84 provided in the insulating layer 82 and is connected to the first electrode 11.

[0324] The charge storage electrode 14 is connected to the driving circuit. Specifically, the charge storage electrode 14 is connected to the vertical driving circuit 112 included in the driving circuit through the connection hole 66, the pad portion 64, and the wire V provided in the interlayer insulating layer 81. 0A It is connected to the vertical driving circuit 112 included in the driving circuit.

[0325] The charge movement control electrode 21 is also connected to the driving circuit. Specifically, the charge movement control electrode 21 is connected to the vertical driving circuit 112 included in the driving circuit through the connection hole 23, the pad portion 22, and the wiring V provided in the interlayer insulating layer 81. 0B More specifically, the charge movement control electrode 21 is formed in the region B (13 B ) that faces the photoelectric conversion layer 13 via the insulating layer 82 (the region B (82 B ) of the insulating layer). In other words, the charge movement control electrode 21 is formed in the region (region b) between the charge storage electrode 14 and the charge storage electrode 14 included in the adjacent imaging element below a part 82 of the insulating layer 82. The charge movement control electrode 21 is provided separately from the charge storage electrode 14. Or, in other words, the charge movement control electrode 21 is provided around the charge storage electrode 14 and separated from the charge storage electrode 14, and the charge movement control electrode 21 is arranged to face the region B (13 B ) of the photoelectric conversion layer 13 via the insulating layer 82. B )

[0326] The size of the charge storage electrode 14 is larger than that of the first electrode 11. Although not limited, it is preferably satisfied that

[0327] 4 ≤ S 1 ′ / S 1

[0328] where S 1 ′ is the area of the charge storage electrode 14, and S 1 is the area of the first electrode 11. Although not limited, for example, in the imaging elements of Embodiment 1 and Embodiments 2 to 8 described later,

[0329] S 1 ′ / S 1 = 8

[0330] Note that in Embodiments 13 to 16 described later, the three photoelectric conversion unit sections (10 1 , 10 2 and 10 3 ) have the same size and the same planar shape.

[0331] The element separation region 71 is formed on the side of the first surface (front surface) 70A of the semiconductor substrate 70, and the oxide film 72 is formed on the first surface 70A of the semiconductor substrate 70. In addition, a reset transistor TR1 included in the control unit of the first imaging element rst , an amplification transistor TR1 amp , and a selection transistor TR1 sel are provided on the first surface side of the semiconductor substrate 70, and a first floating diffusion layer FD 1 is further provided.

[0332] The reset transistor TR1 rst includes a gate portion 51, a channel formation region 51A, source / drain regions 51B and 51C. The gate portion 51 of the reset transistor TR1 rst is connected to the reset line RST 1 , and the source / drain region 51C of the reset transistor TR1 rst also serves as the first floating diffusion layer FD 1 , and the other source / drain region 51B is connected to the power supply V DD .

[0333] The first electrode 11 is connected to the source / drain region 51C (the first floating diffusion layer FD rst ) of the reset transistor TR1 through a connection hole 65 provided in the interlayer insulating layer 81 and a pad portion 63, through a contact hole portion 61 formed on the semiconductor substrate 70 and the interlayer insulating layer 76, and through a wiring layer 62 formed on the interlayer insulating layer 76 1 .

[0334] The amplification transistor TR1 amp includes a gate portion 52, a channel formation region 52A, and source / drain regions 52B and 52C. The gate portion 52 is connected to the first electrode 11 and the source / drain region 51C (the first floating diffusion layer FD rst ) of the reset transistor TR1 through the wiring layer 62. In addition, one source / drain region 52B is connected to the power supply V 1 DD .

[0335] The selection transistor TR1 sel includes a gate portion 53, a channel formation region 53A, source / drain regions 53B and 53C. The gate portion 53 is connected to the selection line SEL 1 . In addition, one source / drain region 53B shares the region with the other source / drain region 52C included in the amplification transistor TR1 amp , and the other source / drain region 53C is connected to a signal line (data output line) VSL 1 (117).

[0336] The second imaging element includes an n-type semiconductor region 41 as a photoelectric conversion layer provided on a semiconductor substrate 70. The transfer transistor TR2 including a vertical transistor trs has a gate portion 45 extending to the n-type semiconductor region 41 and connected to a transfer gate line TG 2 . Further, a second floating diffusion layer FD 2 is provided in a region 45C of the semiconductor substrate 70, the region being close to the gate portion 45 of the transfer transistor TR2 trs . The charge stored in the n-type semiconductor region 41 is read out to the second floating diffusion layer FD through a transfer channel formed along the gate portion 45 2 .

[0337] On the first surface side of the semiconductor substrate 70, the second imaging element is further provided with a reset transistor TR2, an amplification transistor TR2 rst , and a selection transistor TR2 amp included in the control unit of the second imaging element sel .

[0338] The reset transistor TR2 rst includes a gate portion, a channel formation region, and source / drain regions. The gate portion of the reset transistor TR2 rst is connected to a reset line RST 2 , and one source / drain region of the reset transistor TR2 rst is connected to a power supply V DD . The other source / drain region also serves as the second floating diffusion layer FD 2 .

[0339] The amplification transistor TR2 amp includes a gate portion, a channel formation region, and source / drain regions. The gate portion is connected to the other source / drain region (the second floating diffusion layer FD rst ) of the reset transistor TR2. Further, one source / drain region is connected to the power supply V 2 . DD .

[0340] The selection transistor TR2 sel includes a gate portion, a channel formation region, and source / drain regions. The gate portion is connected to a selection line SEL 2 . Additionally, one source / drain region shares the region with the other source / drain region included in the amplification transistor TR2 amp , and the other source / drain region is connected to a signal line (data output line) VSL 2 .

[0341] The third imaging element includes an n-type semiconductor region 43, which is provided on a semiconductor substrate 70 and serves as a photoelectric conversion layer. The transfer transistor TR3 trs has a gate portion 46 connected to a transfer gate line TG 3 . Further, a third floating diffusion layer FD 3 is provided in a region 46C of the semiconductor substrate 70, which is close to the gate portion 46 of the transfer transistor TR3 trs . The charge stored in the n-type semiconductor region 43 is read out to the third floating diffusion layer FD through a transfer channel 46A formed along the gate portion 46 3 .

[0342] In the third imaging element, a reset transistor TR3, an amplification transistor TR3, and a selection transistor TR3, which are included in the control unit of the third imaging element, are further provided on the first surface side of the semiconductor substrate 70 rst 、an amplification transistor TR3 amp and a selection transistor TR3 sel .

[0343] The reset transistor TR3 rst includes a gate portion, a channel formation region, and source / drain regions. The gate portion of the reset transistor TR3 rst is connected to a reset line RST 3 . One source / drain region of the reset transistor TR3 rst is connected to a power supply V DD . The other source / drain region also serves as the third floating diffusion layer FD 3 .

[0344] The amplification transistor TR3 amp includes a gate portion, a channel formation region, and source / drain regions. The gate portion is connected to the other source / drain region (the third floating diffusion layer FD rst ) of the reset transistor TR3. In addition, one source / drain region is connected to the power supply V 3 ). DD ).

[0345] The selection transistor TR3 sel includes a gate portion, a channel formation region, and source / drain regions. The gate portion is connected to a selection line SEL 3 . Further, one source / drain region shares the region with the other source / drain region included in the amplification transistor TR3 amp , while the other source / drain region is connected to a signal line (data output line) VSL 3 .

[0346] Reset lines RST 1 、RST 2 and RST 3, selection line SEL 1 , SEL 2 and SEL 3 , and transfer gate line TG 2 and TG 3 are connected to the vertical drive circuit 112 included in the drive circuit. Signal lines (data output lines) VSL 1 , VSL 2 and VSL 3 are connected to the column signal processing circuit 113 included in the drive circuit.

[0347] A p + layer 44 is provided between the n-type semiconductor region 43 and the front surface 70A of the semiconductor substrate 70 to suppress the generation of dark current. A p + layer 42 is formed between the n-type semiconductor region 41 and the n-type semiconductor region 43. In addition, a part of the side surface of the n-type semiconductor region 43 is surrounded by the p + layer 42. A p + layer 73 is formed on the back surface 70B side of the semiconductor substrate 70, and an HfO + film 74 and an insulating film 75 are formed at a portion where the contact hole portion 61 should be formed from the p 2 layer 73 to the inside of the semiconductor substrate 70. In the interlayer insulating layer 76, wirings are formed in multiple layers, but the wirings are not shown.

[0348] The HfO 2 film 74 is a film having a negative fixed charge, and this film can be provided to suppress the generation of dark current. Note that, as an alternative to the HfO 2 film, an alumina (Al 2 O 3 ) film, a zirconia (ZrO 2 ) film, a tantalum oxide (Ta 2 O 5 ) film, a titanium dioxide (TiO 2 ) film, a lanthanum oxide (La 2 O 3 ) film, a praseodymium oxide (Pr 2 O 3 ) film, a cerium oxide (CeO 2 ) film, a neodymium oxide (Nd 2 O 3 ) film, a promethium oxide (Pm 2 O 3 ) film, a samarium oxide (Sm 2 O 3 ) film, a europium oxide (Eu 2 O 3 ) film, a gadolinium oxide (Gd 2 O 3) film, terbium oxide (Tb 2 O 3 ) film, dysprosium oxide (Dy 2 O 3 ) film, holmium oxide (Ho 2 O 3 ) film, thulium oxide (Tm 2 O 3 ) thin film, ytterbium oxide (Yb 2 O 3 ) thin film, lutetium oxide (Lu 2 O 3 ) film, yttrium oxide (Y 2 O 3 ) film, hafnium nitride film, aluminum nitride film, hafnium oxynitride film, or aluminum oxynitride film. Examples of deposition methods for these films include CVD method, PVD method, and ALD method.

[0349] Hereinafter, reference will be made to Figure 8 and 9A to describe the operation of the imaging element (first imaging element) of Example 1. The imaging element of Example 1 further includes a control unit provided on a semiconductor substrate 70 and including a drive circuit, and the first electrode 11, the second electrode 12, the charge storage electrode 14, and the charge movement control electrode 21 are connected to the drive circuit. Here, the potential of the first electrode 11 is higher than the potential of the second electrode 12. That is, for example, the first electrode 11 is set to a positive potential, while the second electrode 12 is set to a negative potential. Electrons generated by photoelectric conversion in the photoelectric conversion layer 13 are read out to the floating diffusion layer. This also applies to other embodiments. Note that in the mode where the first electrode 11 is set to a negative potential, the second electrode is set to a positive potential, and electron holes generated based on photoelectric conversion in the photoelectric conversion layer 13 are read out to the floating diffusion layer, it is only necessary to reverse the high and low of the potentials described below.

[0350] In Figure 8 , Example 11 described later Fig.51 and 52 as well as Example 12 Fig.58 and 59 the markings used are as follows. Note that Fig. 9A , 9B and 9C are used to describe Figure 8 (Example 1), Fig.51 (Example 11) and Fig.58 (Example 12) the equivalent circuit diagrams of the imaging elements and stacked imaging elements of Example 1, Example 11, and Example 12 for each part.

[0351] P A·····The potential at point P in the region of the photoelectric conversion layer 13 that is opposite to the region located between the charge storage electrode 14 and the first electrode 11 or between the transfer control electrode (charge transfer electrode) 15 and the first electrode 11 A at the potential

[0352] P B ·····The potential at point P in the region of the photoelectric conversion layer 13 facing the charge movement control electrode 21 B at the potential

[0353] P C ·····The potential at point P in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 C at the potential

[0354] P C1 ·····The potential at point P in the region of the photoelectric conversion layer 13 facing the charge storage electrode section 14A C1 at the potential

[0355] P C2 ·····The potential at point P in the region of the photoelectric conversion layer 13 facing the charge storage electrode section 14B C2 at the potential

[0356] P C3 ·····The potential at point P in the region of the photoelectric conversion layer 13 facing the charge storage electrode section 14C C3 at the potential

[0357] P D ·····The potential at point P in the region of the photoelectric conversion layer 13 facing the transfer control electrode (charge transfer electrode) 15 D at the potential

[0358] FD ···· The potential of the first floating diffusion layer FD 1 at the potential

[0359] V 0A ·····The potential of the charge storage electrode 14

[0360] V 0A-A ·····The potential of the charge storage electrode section 14A

[0361] V 0A-B ·····The potential of the charge storage electrode section 14B

[0362] V 0A-C ·····The potential of the charge storage electrode section 14C

[0363] V 0T ·····The potential of the transfer control electrode (charge transfer electrode) 15

[0364] RST ····· Reset transistor TR1 rst The potential of the gate portion 51

[0365] V DD ····· The potential of the power supply

[0366] VSL 1 ····· Signal line (data output line) VSL 1

[0367] TR1 rst ····· Reset transistor TR1 rst

[0368] TR1 amp ····· Amplification transistor TR1 amp

[0369] TR1 sel ····· Selection transistor TR1 sel

[0370] During the charge storage period, the drive circuit applies the potential V 11 to the first electrode 11, applies the potential V 12 to the charge storage electrode 14, and applies the potential V 13 to the charge movement control electrode 21. Light incident on the photoelectric conversion layer 13 causes photoelectric conversion in the photoelectric conversion layer 13. The electron - hole pairs generated by the photoelectric conversion are sent from the second electrode 12 to the drive circuit through the wiring V 0U . On the other hand, the potential of the first electrode 11 is higher than the potential of the second electrode 12. That is, for example, a positive potential is applied to the first electrode 11, and a negative potential is applied to the second electrode 12. Therefore, the potential is set such that V 12 ≥V 11 , preferably, V 12 >V 11 is maintained, and V 12 >V 13 is maintained. Therefore, the electrons generated by the photoelectric conversion are attracted to the charge storage electrode 14, and the electrons stop in the region 13 C of the photoelectric conversion layer 13 facing the charge storage electrode 14. That is, charges are stored in the photoelectric conversion layer 13. V 12 is greater than V 11 , so the electrons generated within the photoelectric conversion layer 13 do not move toward the first electrode 11. In addition, V 12 is greater than V 13, therefore, the electrons generated within the photoelectric conversion layer 13 also do not move towards the charge movement control electrode 21. That is to say, this can prevent the charges generated by photoelectric conversion from flowing into adjacent imaging elements. During the time course of photoelectric conversion, the electric potential in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 becomes a larger negative value.

[0371] Subsequently, a reset operation is performed during the charge storage period. This resets the electric potential of the first floating diffusion layer FD 1 , and the electric potential of the first floating diffusion layer FD 1 becomes the electric potential V of the power supply DD .

[0372] After the reset operation is completed, the charges are read out. That is, during the charge transfer period, the drive circuit applies the electric potential V 21 to the first electrode 11, applies the electric potential V 22 to the charge storage electrode 14, and applies the electric potential V 23 to the charge movement control electrode 21. Here, the electric potentials are set such that V 21 > V 22 > V 23 is maintained. Therefore, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 are read out to the first electrode 11 and further read out to the first floating diffusion layer FD 1 . That is to say, the charges stored in the photoelectric conversion layer 13 are read out to the control unit. In addition, V 22 is greater than V 23 , therefore, the electrons generated within the photoelectric conversion layer 13 do not move towards the charge movement control electrode 21. That is to say, this can prevent the charges generated by photoelectric conversion from flowing into adjacent imaging elements.

[0373] This completes a series of operations including charge storage, reset operation, and charge transfer.

[0374] After the electrons are read out to the first floating diffusion layer FD 1 , the operations of the amplification transistor TR1 amp and the selection transistor TR1 sel are the same as those of a conventional transistor. In addition, a series of operations including charge storage, reset operation, and charge transfer for the second imaging element and the third imaging element are similar to the conventional series of operations including charge storage, reset operation, and charge transfer. In addition, as in the conventional technology, the reset noise of the first floating diffusion layer FD 1 can be removed during the correlated double sampling (CDS) process.

[0375] As described above, a charge storage electrode that is disposed separately from the first electrode and is disposed to face the photoelectric conversion layer via an insulating layer is provided in the imaging element of Embodiment 1 or Embodiments 2 to 8 described later. Therefore, in the photoelectric conversion in the photoelectric conversion unit after light is applied to the photoelectric conversion unit, the photoelectric conversion layer, the insulating layer, and the charge storage electrode constitute a kind of capacitor. Charge can be stored in the photoelectric conversion layer. Therefore, the charge storage portion can be completely depleted to remove charge at the start of exposure. This can suppress the phenomenon of deterioration of imaging quality caused by the degradation of random noise due to an increase in KTC noise. In addition, all pixels can be reset at once, realizing a so-called global shutter function.

[0376] In addition, when light enters the photoelectric conversion layer in the imaging element of Embodiment 1 and photoelectric conversion occurs in the photoelectric conversion layer, the absolute value of the electric potential applied to the portion of the photoelectric conversion layer facing the charge storage electrode is greater than the absolute value of the electric potential applied to Region B of the photoelectric conversion layer. Therefore, the charge generated by photoelectric conversion is strongly attracted to the portion of the photoelectric conversion layer facing the charge storage electrode. This can prevent the charge generated by photoelectric conversion from flowing into adjacent imaging elements, and the quality of the captured video (image) is not degraded. Alternatively, a charge movement control electrode is formed in the region of Region B of the photoelectric conversion layer that faces the photoelectric conversion layer via an insulating layer, and the electric field and electric potential of Region B of the photoelectric conversion layer located above the charge movement control electrode can be controlled. Therefore, the charge movement control electrode can prevent the charge generated by photoelectric conversion from flowing into adjacent imaging elements, and the quality of the captured video (image) is not degraded.

[0377] Fig.10 A conceptual diagram of the solid-state imaging device of Embodiment 1 is shown. Embodiment 1 of the solid-state imaging device 100 includes an imaging region 111 that includes stacked imaging elements 101 arranged in a two-dimensional array, a vertical drive circuit 112 as a drive circuit (peripheral circuit) of the stacked imaging elements 101, a column signal processing circuit 113, a horizontal drive circuit 114, an output circuit 115, a drive control circuit 116, and so on. Note that the circuit may include known circuits or other circuit configurations (for example, various circuits used in conventional CCD solid-state imaging devices or CMOS solid-state imaging devices). Note that in Fig.10 only the reference numeral "101" is shown in one row of stacked imaging elements 101.

[0378] The drive control circuit 116 generates a clock signal and a control signal that serve as a reference for the operations of the vertical drive circuit 112, the column signal processing circuit 113, and the horizontal drive circuit 114 based on a vertical synchronization signal, a horizontal synchronization signal, and a main clock. In addition, the generated clock signal and control signal are input to the vertical drive circuit 112, the column signal processing circuit 113, and the horizontal drive circuit 114.

[0379] The vertical drive circuit 112 includes, for example, a shift register, and sequentially selects and scans the stacked imaging elements 101 of the imaging region 111 row by row in the vertical direction. In addition, pixel signals (image signals) based on currents (signals) generated according to the amount of light received in each stacked imaging element 101 are sent to the column signal processing circuit 113 through signal lines (data output lines) 117, VSL.

[0380] For example, the column signal processing circuit 113 is arranged for each column of the stacked imaging elements 101, for example, and is configured to use signals from black reference pixels (although not shown, formed around the effective pixel region) to perform signal processing, such as noise removal and signal amplification, on the image signals output from one row of stacked imaging elements 101 for each imaging element. A horizontal selection switch (not shown) is connected and provided between the output stage of the column signal processing circuit 113 and the horizontal signal line 118.

[0381] The horizontal drive circuit 114 includes, for example, a shift register, and sequentially outputs horizontal scan pulses to sequentially select the column signal processing circuits 113. The horizontal drive circuit 114 outputs the signals from each column signal processing circuit 113 to the horizontal signal line 118.

[0382] The output circuit 115 performs signal processing on the signals sequentially provided from the column signal processing circuit 113 through the horizontal signal line 118 and outputs the signals.

[0383] Fig.11 An equivalent circuit diagram of a modified example of the imaging element and the stacked imaging element of Example 1 (Modified Example 2 of Example 1) is shown. Fig.12 A schematic layout diagram of the transistors of the first electrode, the charge storage electrode, and the control unit included in the modified example of the imaging element of Example 1 (Modified Example 2 of Example 1) is shown. Thus, the other source / drain region 51B of the reset transistor TR1 rst can be grounded instead of connecting the other source / drain region 51B to the power supply V DD .

[0384] For example, the imaging element and the stacked imaging element of Example 1 can be produced by the following method. That is, first, an SOI substrate is prepared. Then, a first silicon layer is formed on the surface of the SOI substrate based on the epitaxial growth method, and a p + layer 73 and an n-type semiconductor region 41 are formed on the first silicon layer. Next, a second silicon layer is formed on the first silicon layer based on the epitaxial growth method, and an element isolation region 71, an oxide film 72, a p + layer 42, an n-type semiconductor region 43, and a p +Layer 44. Additionally, various transistors and the like included in the control unit of the imaging element are formed on the second silicon layer, and a wiring layer 62, an interlayer insulating layer 76, and various wirings are further formed on top of it. Then, the interlayer insulating layer 76 and a support substrate (not shown) are bonded together. Subsequently, the SOI substrate is removed to expose the first silicon layer. Note that the surface of the second silicon layer corresponds to the front surface 70A of the semiconductor substrate 70, and the surface of the first silicon layer corresponds to the back surface 70B of the semiconductor substrate 70. Additionally, the first silicon layer and the second silicon layer are collectively referred to as the semiconductor substrate 70. Next, an opening for forming the contact hole portion 61 is formed on the back surface 70B side of the semiconductor substrate 70, and HfO 2 film 74, insulating film 75, and contact hole portion 61 are formed. Additionally, pad portions 63, 64, and 22, interlayer insulating layer 81, connection holes 65, 66, and 23, first electrode 11, charge storage electrode 14, charge movement control electrode 21, and insulating layer 82 are formed. Next, the connection portion 67 is opened, and a photoelectric conversion layer 13, second electrode 12, protective layer 83, and on-chip microlens 90 are formed. In this way, the imaging element and the stacked imaging element of Example 1 can be obtained.

[0385] Fig.13 (Variant Example 3 of Example 1) Fig.14A (Variant Example 4 of Example 1) Fig. 14B , Fig.15A (Variant Example 5 of Example 1) and Fig. 15B shows a schematic layout diagram of other variant examples of the first electrode and the charge storage electrode included in the imaging element of Example 1. In the examples shown in these figures, one common first electrode 11 is provided to correspond to four charge storage electrodes 14 in four imaging elements. Additionally, in Fig.13 the example shown, the charge movement control electrode 21 is formed below a portion 82 of the insulating layer 82 in the region (region b) located between the charge storage electrode 14 and the charge storage electrode 14 B . On the other hand, in Fig.14A the example shown, the charge movement control electrode 21 is formed below a portion of the insulating layer 82 in the region surrounded by four charge storage electrodes 14. Fig.15A The example shown in Fig.13 and Fig.14A is a combination of the examples shown in Fig. 15B The example shown in Fig. 14B and Fig.15A is a combination of the examples shown in Fig.13 , 14A , 14B, 15A, and 15B also represent solid-state imaging devices of the first structure and the second structure.

[0386] In Fig. 14B In the example shown, a common first electrode 11 is provided to correspond to four charge storage electrodes 14 among four imaging elements, and a charge movement control electrode 21 is formed below a portion of the insulating layer 82 in a region surrounded by the four charge storage electrodes 14. Further, a discharge electrode 25 is formed below a portion of the insulating layer 82 in a region surrounded by the four charge storage electrodes 14. The discharge electrode 25 can be used as, for example, a floating diffusion region or an overflow port of the photoelectric conversion layer 13. The discharge electrode 25 and the photoelectric conversion layer 13 are connected through an opening provided in the insulating layer 82. That is, similar to the relationship between the photoelectric conversion layer 13 and the first electrode 11, the photoelectric conversion layer 13 extends in the opening provided in the insulating layer 82, and an extended portion of the photoelectric conversion layer 13 contacts the discharge electrode 25. The discharge electrode 25 is connected to a vertical drive circuit 112 included in a drive circuit through a connection hole 25A, a pad portion 25B, and a wiring (not shown) provided in an interlayer insulating layer 81. The discharge electrode 25 can also be applied to other embodiments. Note that, for reference, Fig. 16B shows a Fig.15A schematic cross-sectional view taken along the single dotted line A - A in the case where the discharge electrode 25 in the fifth modification of the first embodiment shown in Fig.15A is substituted for the charge movement control electrode 21.

[0387] Alternatively, in Fig. 15B the example shown, a common first electrode 11 is provided to correspond to four charge storage electrodes 14 among four imaging elements, and a charge movement control electrode 21 is formed below a portion of the insulating layer located in a region between the charge storage electrodes 14. Further, a discharge electrode 25 is formed below a portion of the insulating layer 82 in a region surrounded by the four charge storage electrodes 14. The discharge electrode 25 and the photoelectric conversion layer 13 are connected through an opening provided in the insulating layer 82. That is, similar to the relationship between the photoelectric conversion layer 13 and the first electrode 11, the photoelectric conversion layer 13 extends in the opening provided in the insulating layer 82, and an extended portion of the photoelectric conversion layer 13 contacts the discharge electrode 25. Fig.16A shows a Fig. 15B schematic cross-sectional view taken along the single dotted line B - B in the fifth modification of the first embodiment shown in Fig. 15B the figure.

[0388] Alternatively, Figure 1B shows a schematic cross-sectional view of a part of a modified example (the sixth modified example of the first embodiment) of the imaging element (two imaging elements arranged side by side) of the first embodiment, and the photoelectric conversion layer can have a stacked structure of a lower semiconductor layer 13 DN and an upper photoelectric conversion layer 13 UP . The upper photoelectric conversion layer 13 UP and the lower semiconductor layer 13DN Shared by multiple imaging elements. That is, an upper photoelectric conversion layer 13 is formed among the multiple imaging elements UP and a lower semiconductor layer 13 DN . In this way, the lower semiconductor layer 13 can be provided DN , thereby preventing recombination, for example, during charge storage. This can also improve the charge transfer efficiency of the charge stored in the photoelectric conversion layer 13 to the first electrode 11. In addition, the charge generated in the photoelectric conversion layer 13 can be temporarily held to control the timing of transfer, etc. In addition, the generation of dark current can be suppressed. The material contained in the upper photoelectric conversion layer 13 UP can be appropriately selected from various materials contained in the photoelectric conversion layer 13. On the other hand, preferably, the material contained in the lower semiconductor layer 13 DN is a material having a large bandgap energy value (for example, a bandgap energy value equal to or greater than 3.0 eV) and having higher mobility than the material contained in the photoelectric conversion layer. Specifically, an example of such a material includes an oxide semiconductor material such as IGZO. Alternatively, another example of the material contained in the lower semiconductor layer 13 DN includes a material having an ionization potential larger than that of the material contained in the photoelectric conversion layer when the charge to be stored is an electron. Alternatively, preferably, the impurity concentration of the material contained in the lower semiconductor layer is preferably equal to or less than 1×10 18 cm -3 . Note that the configurations and structures of Variant Example 6 of Embodiment 1 can be applied to other embodiments.

[0389] Embodiment 2

[0390] Embodiment 2 relates to an imaging element and the like according to the second aspect of the present invention. Fig.17A A schematic cross-sectional view showing a part of the imaging element (two imaging elements arranged side by side) of Embodiment 2 is shown. In the imaging element of Embodiment 2, the width W A of the region 13 A (region A of the photoelectric conversion layer) of the photoelectric conversion layer 13 located between the first electrode 11 and the charge storage electrode 14 B is narrower than the width W B of the region 13 A (region B of the photoelectric conversion layer) of the photoelectric conversion layer 13 located between the imaging element and the adjacent imaging element B . An example of the (W

[0391] / W A / W B ) value includes

[0392] Specifically, in Embodiment 2, this value is

[0393] (W A / W B ) = 2 / 3

[0394] In addition, the structures in the imaging element of Example 2 may be similar to those of the imaging element having the basic structure of the present disclosure, and details will not be described again.

[0395] Thus, in the imaging element of Example 2, the width of the region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is narrower than the width W of the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element. This can prevent the charge generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) will not be degraded. B Narrow. This can prevent the charge generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) will not be degraded.

[0396] Example 3

[0397] Example 3 relates to an imaging element and the like according to the fourth aspect of the present invention. Fig. 17B FIG. shows a schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 3, Fig.19 and Fig. 20 FIG. shows a schematic plan view of a part of the imaging element (2×2 imaging elements arranged side by side) of Example 3. In the imaging element of Example 3, instead of the second electrode 12, a charge movement control electrode 24 is formed on the region 13 of the photoelectric conversion layer located between the imaging element and the adjacent imaging element. The charge movement control electrode 24 is provided separately from the second electrode 12. In other words, the second electrode 12 is provided for each imaging element, and the charge movement control electrode 24 is provided around at least a part of the second electrode 12 separately from the second electrode 12 on the region B of the photoelectric conversion layer 13. The charge movement control electrode 24 is formed at the same level as the second electrode 12. B In addition, as shown in FIG., which shows a schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 3, the second electrode 12 can be divided into a plurality of second electrodes 12, and different potentials can be applied to the divided second electrodes 12 separately. In addition, as shown in 18B, the charge movement control electrode 24 can be provided between the divided second electrodes 12 and the second electrode 12.

[0398] In addition, as Fig.18A shown, which shows a schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 3, the second electrode 12 can be divided into a plurality of second electrodes 12, and different potentials can be applied to the divided second electrodes 12 separately. In addition, as shown in 18B, the charge movement control electrode 24 can be provided between the divided second electrodes 12 and the second electrode 12.

[0399] Note that in Fig.19 the example shown, one charge storage electrode 14 is provided corresponding to one first electrode 11 in one imaging element. On the other hand, in Fig. 20In the example shown in (Variant Example 1 of Embodiment 3), a common first electrode 11 is provided corresponding to two charge storage electrodes 14 in two imaging elements. Fig. 17B A schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Embodiment 3 shown corresponds to Fig. 20 .

[0400] In Embodiment 3, the second electrode 12 located on the light incident side is shared by the imaging elements arranged in the Fig.19 left - right direction, and is shared by a pair of imaging elements arranged in the Fig.19 up - down direction. Further, the charge movement control electrode 24 is also shared by the imaging elements arranged in the Fig.19 left - right direction, and is shared by a pair of imaging elements arranged in the Fig.19 up - down direction. The second electrode 12 and the charge movement control electrode 24 can be obtained by depositing the material layers of the second electrode 12 and the charge movement control electrode 24 on the photoelectric conversion layer 13 and then patterning the material layers. The second electrode 12 and the charge movement control electrode 24 are respectively connected to wirings (not shown), and the wirings are connected to a drive circuit. The wiring connected to the second electrode 12 is shared by a plurality of imaging elements. The wiring connected to the charge movement control electrode 24 is also shared by a plurality of imaging elements.

[0401] In the imaging element of Embodiment 3, the drive circuit applies a potential V 2 ' to the second electrode 12 and applies a potential V 13 ' to the charge movement control electrode 24, and charges are stored in the photoelectric conversion layer 13 during charge storage. During charge transfer, the drive circuit applies a potential V 2 ” to the second electrode 12 and applies a potential V 23 ” to the charge movement control electrode 24, and the charges stored in the photoelectric conversion layer 13 are read out to the control unit through the first electrode 11. Here, the potential of the first electrode 11 is higher than the potential of the second electrode 12, and thus,

[0402] V 2 '≥V 13 ' and V 2 ”≥V 23 ” are maintained.

[0403] Meanwhile, the following problem may occur in the configuration where the charge movement control electrode 21 is provided adjacent to the first electrode 11 as shown in FIG. 1. That is, during charge storage, the drive circuit applies a potential V 11 to the first electrode 11, applies a potential V 12 to the charge storage electrode 14, applies a potential V 13 to the charge movement control electrode 21, and applies a potential V2 is applied to the second electrode 12. For example, here, V 12 > V 11 > V 2 and V 12 > V 13 > V 2 is maintained. Fig.21A and Fig. 21B the "A" in indicates the electric potential in the photoelectric conversion layer 13 located on the upper side of the first electrode 11. On the other hand, in the case where the electric potential V 13 is applied to the charge movement control electrode 21 and the electric potential is not applied to the charge storage electrode 14, the electric potential in the photoelectric conversion layer 13 located on the upper side of the charge movement control electrode 21 will be as Fig.21A the "B" in indicates simply changes. However, the electric potential V 12 is applied to the charge storage electrode 14, and due to the influence of the charge storage electrode 14, the electric potential changes as Fig.21A the "C" in indicates. That is, in the insulating layer 82, the electric potential decreases toward the charge movement control electrode 21. Therefore, during charge storage, electron holes are stored in the region of the insulating layer 82 located on the upper side of the charge storage electrode 14, and the charges generated by photoelectric conversion can be weakly attracted to the portion of the photoelectric conversion layer facing the charge storage electrode.

[0404] On the other hand, in Embodiment 3, the charge movement control electrode 24 is formed at the same level as the second electrode 12, and the electric potential V 13 ' is applied to the charge movement control electrode 24. Therefore, the electric potential in the photoelectric conversion layer 13 located on the lower side of the charge movement control electrode 24 simply increases as Fig. 21B the "B" in indicates. In addition, there is no charge movement control electrode 21 on the lower side of the photoelectric conversion layer 13 located on the lower side of the charge movement control electrode 24, and the electric potential further simply increases in the insulating layer 82. Therefore, during charge storage, electron holes are not stored in the region of the insulating layer 82 located on the lower side of the charge movement control electrode 24, and this can prevent the phenomenon that the charges generated by photoelectric conversion are weakly attracted to the portion of the photoelectric conversion layer facing the charge storage electrode. This can more surely prevent the quality of the captured video (image) from deteriorating.

[0405] In this way, in the imaging element of Embodiment 3, instead of the second electrode, a charge movement control electrode is formed on the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element. Therefore, the charge movement control electrode can prevent the charges generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) will not deteriorate.

[0406] Fig.22A and 22B shows a schematic plan view of a part of a modified example (modified example 2 of Example 3) of the imaging element of Example 3. Note that Fig.22A 、 23A 、25A, 26A, 27A, and 28A show an example in which one common first electrode 11 is provided corresponding to four charge storage electrodes 14 among four imaging elements. In addition, as Fig. 22B shown, the second electrode 12 is provided on the upper side of the charge storage electrode 14 with substantially the same size as the charge storage electrode 14. The second electrode 12 is surrounded by the charge movement control electrode 24. The charge movement control electrode 24 is shared by the imaging elements. An insulating film (not shown) is formed on the photoelectric conversion layer 13 including the second electrode 12 and the charge movement control electrode 24, and a contact hole (not shown) connected to the second electrode 12 is formed in the insulating film on the upper side of the second electrode 12. A wiring V 0U (not shown) is provided on the insulating film. Note that the structures and configurations of the second electrode 12, the insulating film, the contact hole, and the wiring V 0U are similar in the following modified examples. In addition, Fig.22A 、 22B 、23A, 23B, 23C, 25A, 25B, 26A, 26B, 27A, 27B, 28A, and 28B also represent solid-state imaging devices of the first and second configurations.

[0407] Fig.23A 、 23B and 23C show a schematic plan view of a part of a modified example 3 of Example 3. As Fig. 23B and 23C shown, the second electrode 12 is provided on the upper side of the charge storage electrode 14 with substantially the same size as the charge storage electrode 14. The second electrode 12 is surrounded by the charge movement control electrode 24. The charge movement control electrode 24 is shared by four imaging elements. The shared part is formed on the photoelectric conversion layer 13. Note that in the example shown in Fig.23C , the second electrode 12 extends to the second electrodes of adjacent imaging elements.

[0408] Fig.24A shows a schematic cross-sectional view of a part of a modified example (modified example 4A of Example 3) of the imaging element (two imaging elements arranged side by side) of Example 3, Fig.25A and 25BA schematic plan view of this part is shown. In Variant Example 4A of Embodiment 3, a second electrode 12 is provided for each imaging element, and a charge movement control electrode 24 is disposed around at least a part of the second electrode 12 and separated from the second electrode 12. A part of the charge storage electrode 14 exists on the lower side of the charge movement control electrode 24. The second electrode 12 is disposed on the upper side of the charge storage electrode 14 with a size smaller than that of the charge storage electrode 14.

[0409] Fig. 24B A schematic cross-sectional view of a part of a variant example (Variant Example 4B of Embodiment 3) of the imaging elements (two imaging elements arranged side by side) of Embodiment 3 is shown, Fig.26A and 26B a schematic plan view of this part is shown. In Variant Example 4B, a second electrode 12 is provided for each imaging element, and the charge movement control electrode 24 surrounds at least a part of the second electrode 12 and is separated from the second electrode 12. A part of the charge storage electrode 14 exists on the lower side of the charge movement control electrode 24, and in addition, a charge movement control electrode (lower charge movement control electrode) 21 is disposed on the lower side of the charge movement control electrode (upper charge movement control electrode 24). The size of the second electrode 12 is smaller than that in Variant Example 4A. That is, compared with the region of the second electrode 12 facing the charge movement control electrode 24 in Variant Example 4A, the region of the second electrode 12 facing the charge movement control electrode 24 is closer to the first electrode 11. The charge storage electrode 14 is surrounded by the charge movement control electrode 21.

[0410] Fig.27A and Fig.27B A schematic plan view of a part of a variant example (Variant Example 4C of Embodiment 3) of the imaging elements of Embodiment 3 is shown. In Variant Example 4C, as in Variant Example 4B of Embodiment 3, a part of the charge storage electrode 14 exists on the lower side of the charge movement control electrode 24. The size of the second electrode 12 is smaller than that in Variant Example 4A. That is, compared with the region of the second electrode 12 facing the charge movement control electrode 24 in Variant Example 4A, the region of the second electrode 12 facing the charge movement control electrode 24 is closer to the first electrode 11. In addition, the charge movement control electrode 24 includes an external charge movement control electrode 24 1 and an internal charge movement control electrode 24 disposed between the external charge movement control electrode 24 1 and the second electrode 12 2 . The charge storage electrode 14 is surrounded by the charge movement control electrode 21. During charge transfer, the relationship (the potential applied to the external charge movement control electrode 24 1 ) < (the potential applied to the internal charge movement control electrode 24 2The electric potential of <(the electric potential applied to the second electrode 12)> is used to more effectively transfer charges.

[0411] Fig.28A and Fig.28B FIG. shows a schematic plan view of a part of a modified example (modified example 4D of Example 3) of the imaging element of Example 3. In Example 4D, as in modified example 4B of Example 3, a charge movement control electrode (lower charge movement control electrode) 21 is provided on the lower side of a charge movement control electrode (upper charge movement control electrode) 24. The size of the second electrode 12 is smaller than that in modified example 4B. That is, the region of the second electrode 12 facing the charge movement control electrode 24 is closer to the first electrode 11 than the region of the second electrode 12 facing the charge movement control electrode 24 in modified example 4B. In addition, the interval between the charge movement control electrode 24 and the second electrode 12 is wider than that in modified example 4B. The charge storage electrode 14 is surrounded by the charge movement control electrode 21. The electric potential generated by the coupling of the charge movement control electrode 24 and the second electrode 12 is applied to the following region of the photoelectric conversion layer 13: the region located below the region between the charge movement control electrode 24 and the second electrode 12.

[0412] Fig.29A 、 29B and 29C schematically illustrate the electric potential states in each part (during charge transfer) of modified example 4B of Example 3, modified example 4C of Example 3, and modified example 4D of Example 3, respectively.

[0413] Example 4

[0414] Example 4 relates to an imaging element and the like according to the fifth aspect of the present disclosure. Fig.30 FIG. shows a schematic cross-sectional view of a part of the imaging element of Example 4 (two imaging elements arranged side by side). In the imaging element of Example 4, the region (region a) 82 located between the first electrode 11 and the charge storage electrode 14 A (Specifically, the region 82 of the insulating layer 82 located between the first electrode 11 and the charge storage electrode 14 A ) contains an insulating material (insulating material A) 82 A ′ with a dielectric constant value ε A higher than the region (region b) 82 located between the imaging element and the adjacent imaging element B (Specifically, the region 82 of the insulating layer 82 located between the imaging element and the adjacent imaging element B ) contains an insulating material (insulating material B) 82 B ′ with a dielectric constant value ε B . The insulating material A (82 A ′) and the insulating material B (82B ′) is formed in the level of the insulating layer 82 covering the charge storage electrode 14. That is, when the insulating layer 82 is represented by two layers including a lower insulating layer filling the gap between the charge storage electrode 14 and the charge storage electrode 14 and an upper insulating layer covering the charge storage electrode 14 and formed on the lower insulating layer, the insulating material A (82 A ′) and the insulating material B (82 B ′) fill a part of the upper insulating layer (specifically, a part of the upper insulating layer in the region 82 of the insulating layer 82 located between the first electrode 11 and the charge storage electrode 14 A and a part of the upper insulating layer in the region (region b) 82 between the imaging element and the adjacent imaging element B ).

[0415] The imaging element and the stacked imaging element of Example 4 can also be obtained by forming a region 82 of the insulating layer 82 containing the insulating material A (82 A ′) and the insulating material B (82 B ′) when forming the insulating layer 82 in the manufacturing process of the imaging element and the stacked imaging element of Example 1 A and 82 B .

[0416] In the imaging element of Example 4, the value of the dielectric constant of the insulating material contained in the region between the first electrode and the charge storage electrode is higher than the value of the dielectric constant of the insulating material contained in the region between the imaging element and the adjacent imaging element. Therefore, the capacitance of capacitor A is larger than the capacitance of capacitor B, and compared with the region between the imaging element and the adjacent imaging element, more charges are attracted to the region between the first electrode and the charge storage electrode. This can prevent the charges generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) is not reduced.

[0417] Fig.31 FIG. shows a schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 4, and Fig.32 and 33 show schematic cross-sectional views of a part of other modified examples. Note that Fig.30 , 31 , the formation positions of the insulating material A (82 A ′) and the insulating material B (82 B ′) shown in 32 and 33 can be appropriately combined.

[0418] In Fig.31 the example shown, the insulating material A (82 A ′) extends from the region 82 of the insulating layer 82 located between the first electrode 11 and the charge storage electrode 14A Begin to fill a part of the insulating layer on the charge storage electrode 14, and the insulating material B (82 B ′) fills a part of the insulating layer in the region (region b) 82 between the imaging element and the adjacent imaging element B .

[0419] In Fig.32 the example shown, the insulating material A (82 A ′) fills a part of the lower insulating layer in the region 82 of the insulating layer 82 located between the first electrode 11 and the charge storage electrode 14, and the insulating material B (82 A ′) fills a part of the lower insulating layer in the region (region b) 82 between the imaging element and the adjacent imaging element B . B

[0420] In Fig.33 the example shown, the insulating material A (82 A ′) fills a part of the interlayer insulating layer 81 located below the region 82 of the insulating layer 82, the region 82 A is located between the first electrode 11 and the charge storage electrode 14, and the insulating material B (82 A ′) fills a part of the interlayer insulating layer 81 located below the region (region b) 82 between the imaging element and the adjacent imaging element B . B

[0421] Example 5

[0422] Example 5 relates to an imaging element and the like according to the sixth aspect of the present disclosure Fig.34 Fig. shows a schematic cross-sectional view of a part of the imaging element (two imaging elements arranged side by side) of Example 5. In the imaging element of Example 5, the thickness t A of the region 82 of the insulating layer 82 located between the first electrode 11 and the charge storage electrode 14 In-A (region A of the insulating layer) is thinner than the thickness t B of the region 82 of the insulating layer 82 located between the imaging element and the adjacent imaging element In-B (region B of the insulating layer). Examples of the (t In-A / t In-B ) value include

[0423] 1 / 2 ≤ (t In-A / t In-B ) < 1,

[0424] Specifically, the value is

[0425] (t In-A / t​​In-B ) = 0.9.

[0426] The imaging element and the stacked imaging element of Example 5 can be obtained by controlling the thickness in regions 82 and 82 of the insulating layer 82 when forming the insulating layer 82 in the manufacturing process of the imaging element and the stacked imaging element of Example 1 A and 82 B (e.g., controlling the thickness based on etching).

[0427] In the imaging element of Example 5, the thickness of the region of the insulating layer located between the first electrode and the charge storage electrode is thinner than the thickness of the region of the insulating layer located between the imaging element and an adjacent imaging element. Accordingly, the capacitance of capacitor A is greater than the capacitance of capacitor B, and more charge is attracted to the region of the insulating layer located between the first electrode and the charge storage electrode than to the region of the insulating layer located between the imaging element and an adjacent imaging element. This can prevent the charge generated by photoelectric conversion from flowing into an adjacent imaging element, and the quality of the captured video (image) is not degraded.

[0428] Fig.35 FIG. shows a schematic cross-sectional view of a part of a modified example of the imaging element of Example 5 (two imaging elements arranged side by side), and Fig.36 FIG. shows a schematic cross-sectional view of a part of another modified example.

[0429] In Fig.35 the shown modified example, the thickness t of region 82 of the insulating layer 82 located between the first electrode 11 and the charge storage electrode 14 A (region A of the insulating layer) In-A is thinner than the thickness t of region 82 of the insulating layer 82 located between the imaging element and an adjacent imaging element B (region B of the insulating layer). In-B However, the level of the top surface of the insulating layer 82 above the charge storage electrode 14 is the same as the level of the top surface of the insulating layer 82 in region B of the insulating layer.

[0430] In Fig.36 the shown modified example, the level of the top surface of the insulating layer 82 in region B of the insulating layer is the same as the level of the top surface of the insulating layer 82 above the charge storage electrode 14 included in one imaging element (the imaging element on the right side included in Fig.36 ). However, this top surface is at a level higher than the top surface of the insulating layer 82 above the charge storage electrode 14 included in the other imaging element (the imaging element on the left side included in Fig.36in a higher level than the top surface of the insulating layer 82 above the charge storage electrode 14 in the left imaging element in ). Further, the level of the top surface of the insulating layer 82 in the region A of the insulating layer is the same as the level of the top surface of the insulating layer 82 located above the charge storage electrode 14 included in another imaging element. However, this top surface is in a level lower than the level of the top surface of the insulating layer 82 located above the charge storage electrode 14 included in one imaging element.

[0431] Example 6

[0432] Example 6 relates to an imaging element and the like according to the seventh aspect of the present disclosure. Fig.37 A schematic cross-sectional view showing a part of the imaging element (two imaging elements arranged side by side) of Example 6 is shown. In the imaging element of Example 6, the region 13 of the photoelectric conversion layer 13 located between the first electrode 11 and the charge storage electrode 14 A (region A of the photoelectric conversion layer 13) has a thickness t Pc-A is thicker than the region 13 of the photoelectric conversion layer 13 located between the imaging element and the adjacent imaging element B (region B of the photoelectric conversion layer 13). Pc-B (t Pc-A / t Pc-B ) value examples include

[0433] 1 < (t Pc-A / t Pc-B ) ≤ 2

[0434] Specifically, the value is

[0435] (t Pc-A / t Pc-B ) = 1.25.

[0436] The imaging element and the stacked imaging element of Example 6 can be obtained by controlling the thickness of the region 13 of the photoelectric conversion layer 13 when forming the photoelectric conversion layer 13 in the manufacturing process of the imaging element and the stacked imaging element of Example 1 A and 13 B (for example, controlling the thickness based on etching).

[0437] In the imaging element of Example 6, the thickness of the region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is thicker than the thickness of the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element. This can prevent the charge generated by the photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) will not be reduced.

[0438] Fig.38Schematic cross-sectional view showing a part of a modified example of the imaging element (two imaging elements arranged side by side) of Example 6, and depending on the situation, t Pc-B The value of can be 0. That is, depending on the situation, the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element may not exist.

[0439] Example 7

[0440] Example 7 relates to an imaging element and the like according to the eighth aspect of the present disclosure. Fig.39 Schematic cross-sectional view showing a part of the imaging element (two imaging elements arranged side by side) of Example 7. In the imaging element of Example 7, in the photoelectric conversion layer 13 located between the first electrode 11 and the charge storage electrode 14 A (Region A of the photoelectric conversion layer 13) and the insulating layer 82 A The fixed charge amount FC in the region of the interface between (region A of the insulating layer 82) A is less than that in the photoelectric conversion layer 13 located between the imaging element and the adjacent imaging element B (Region B of the photoelectric conversion layer 13) and the insulating layer 82 B (Region B of the insulating layer 82) The fixed charge amount FC in the region of the interface between B . (FC A / FC B ) Examples of the value include

[0441] 1 / 10 ≤ (FC A / FC B ) < 1.

[0442] In Fig.39 , the black circles represent the charges (electron holes) generated at the interface of the insulating layer. The fixed charge amount in the region of the interface between the photoelectric conversion layer 13 and the insulating layer 82 can be controlled, for example, based on the method of depositing a thin film having a fixed charge.

[0443] In the imaging element of Example 7, the fixed charge amount in the region of the interface between the photoelectric conversion layer and the insulating layer located between the first electrode and the charge storage electrode is less than that in the region of the interface between the photoelectric conversion layer and the insulating layer located between the imaging element and the adjacent imaging. This can prevent the charges generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) is not reduced.

[0444] Example 8

[0445] Example 8 relates to an imaging element and the like according to the ninth aspect of the present invention. Fig.40Schematic cross-sectional view showing a part of the imaging element of Example 8 (two imaging elements arranged side by side). In the imaging element of Example 8, the charge mobility CT in the region 13 of the photoelectric conversion layer located between the first electrode 11 and the charge storage electrode 14 A (region A of the photoelectric conversion layer 13) A is greater than the charge mobility CT of the region 13 of the photoelectric conversion layer 13 located between the imaging element and the adjacent imaging element B (region B of the photoelectric conversion layer 13). B (CT A / CT B ) value examples include

[0446] 1 < (CT A / CT B ) ≤ 1 × 10 2 .

[0447] Specifically, the value is

[0448] (CT A / CT B ) = 2.

[0449] The imaging element of Example 8 and the stacked imaging element can be obtained by forming the regions 13 and 13 of the photoelectric conversion layer 13 using materials having the following relationship A and 13 B , which is the same relationship of the charge mobility CT and the charge mobility CT as described above for the materials included in the regions 13 and 13 of the photoelectric conversion layer 13 during the manufacturing process of the imaging element and the stacked imaging element of Example 1 when forming the photoelectric conversion layer 13 A and 13 B . A and the charge mobility CT B .

[0450] In the imaging element of Example 8, the value of the charge mobility in the region of the photoelectric conversion layer located between the first electrode and the charge storage electrode is greater than the value of the charge mobility in the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element. This can prevent the charge generated by photoelectric conversion from flowing into the adjacent imaging element, and the quality of the captured video (image) will not deteriorate.

[0451] Fig.41 Schematic cross-sectional view showing a part of a modified example of the imaging element of Example 8 (two imaging elements arranged side by side). In Fig.41 the modified example shown, a part of the photoelectric conversion layer 13 has an upper layer (upper photoelectric conversion layer) 13 UP ' / lower layer (lower semiconductor layer) 13 DNA two-layer structure of '. The upper layer of region A (13 A ) of the photoelectric conversion layer 13 and the upper layer of region B (13 B ) of the photoelectric conversion layer 13 UP ' and the portion of the photoelectric conversion layer 13 located above the charge storage electrode 14 contain the same material (upper layer composition material). In addition, the lower layer 13 A ) of region A (13 DN ' of the photoelectric conversion layer and the lower layer 13 DN ' of the portion of the photoelectric conversion layer 13 located above the charge storage electrode 14 contain the same material (lower layer composition material). However, the upper layer composition material and the lower layer composition material are different. The lower layer 13 DN ' can be provided in this way to prevent recombination, for example, during charge storage. This can also improve the charge transfer efficiency of the charges stored in the photoelectric conversion layer 13 to the first electrode 11. In addition, the charges generated in the photoelectric conversion layer 13 can be temporarily held to control the timing of transfer, etc. In addition, the generation of dark current can also be suppressed.

[0452] Example 9

[0453] Example 9 is a modification of Examples 1 to 8. In Fig.42 The imaging element and the stacked imaging element of Example 9 shown in the schematic partial cross-sectional view are a front-illumination type imaging element and a stacked imaging element. The imaging element and the stacked imaging element have a stacked structure of three imaging elements, including: a first type of green light imaging element (first imaging element) in Example 1 that is sensitive to green light, and this green light imaging element includes a first type of green light photoelectric conversion layer for absorbing green light; a second type of conventional blue light imaging element (second imaging element) that is sensitive to blue light, and this blue light imaging element includes a second type of blue light photoelectric conversion layer for absorbing blue light; and a second type of conventional red light imaging element (third imaging element) that is sensitive to red light, and this red light imaging element includes a second type of red light photoelectric conversion layer for absorbing red light. Here, the red light imaging element (third imaging element) and the blue light imaging element (second imaging element) are provided in the semiconductor substrate 70, and the second imaging element is located on the light incident side with respect to the third imaging element. In addition, the green light imaging element (first imaging element) is provided above the blue light imaging element (second imaging element).

[0454] As in Example 1, various transistors included in the control unit are provided on the front surface 70A side of the semiconductor substrate 70. Each transistor can have a structure and configuration that are basically similar to those of the transistors described in Example 1. In addition, the second imaging element and the third imaging element are provided in the semiconductor substrate 70, and the imaging element can also have a structure and configuration that are basically similar to those of the second imaging element and the third imaging element described in Example 1.

[0455] An interlayer insulating layer 77 and 78 are formed on the front surface 70A of the semiconductor substrate 70, and a photoelectric conversion unit (first electrode 11, photoelectric conversion layer 13, and second electrode 12) and a charge storage electrode 14 included in the imaging element of Embodiment 1 are provided on the interlayer insulating layer 78, and so on.

[0456] Thus, except that the imaging element and the stacked imaging element are front-illuminated imaging elements and stacked imaging elements, the configurations and structures of the imaging element and the stacked imaging element of Embodiment 9 may be similar to those of the imaging element and the stacked imaging element of Embodiment 1, and details will not be described again.

[0457] Embodiment 10

[0458] Embodiment 10 is a modification of Embodiments 1 to 9.

[0459] Fig.43 The imaging element and the stacked imaging element of Embodiment 10 shown in the schematic partial cross-sectional view of are back-illuminated imaging elements and stacked imaging elements. The imaging element and the stacked imaging element have a stacked structure including two imaging elements including a first imaging element of the first type and a second imaging element of the second type in Embodiment 1. In addition, Fig.44 A modified example of the imaging element and the stacked imaging element of Embodiment 10 shown in the schematic partial cross-sectional view of provides front-illuminated imaging elements and stacked imaging elements. The imaging element and the stacked imaging element have a stacked structure including two imaging elements including a first imaging element of the first type and a second imaging element of the second type in Embodiment 1. Here, the first imaging element absorbs primary color light, and the second imaging element absorbs complementary color light. Alternatively, the first imaging element absorbs white light, and the second imaging element absorbs infrared rays.

[0460] Fig.45 A modified example of the imaging element of Embodiment 10 shown in the schematic partial cross-sectional view of is a back-illuminated imaging element. The imaging element includes a first imaging element of the first type in Embodiment 1. In addition, Fig.46 A modified example of the imaging element of Embodiment 10 shown in the schematic partial cross-sectional view of is a front-illuminated imaging element. The imaging element includes a first imaging element of the first type in Embodiment 1. Here, the first imaging element includes three types of imaging elements, which include an imaging element that absorbs red light, an imaging element that absorbs green light, and an imaging element that absorbs blue light.

[0461] In addition, a solid-state imaging device according to the first aspect of the present disclosure includes a plurality of imaging elements. Examples of the arrangement of the plurality of imaging elements include a Bayer array. Color filters for separating blue, green, and red are arranged on the light incident side of the imaging element as needed.

[0462] Note that, as an alternative to providing one imaging element of the first type in Embodiment 1, two imaging elements may be stacked (i.e., two photoelectric conversion units are stacked, and control units for the two imaging elements are provided on a semiconductor substrate) or three imaging elements may be stacked (i.e., three photoelectric conversion units are stacked, and control units for the three imaging elements are provided on a semiconductor substrate). The following table illustrates an example of the stacked structure of the imaging elements of the first type and the second type.

[0463]

[0464]

[0465] Embodiment 11

[0466] Embodiment 11 is a modification of Embodiments 1 to 10, and Embodiment 11 relates to an imaging element of the present disclosure including a transfer control electrode (charge transfer electrode), etc. Fig.47 A schematic partial cross-sectional view showing a part of the imaging element of Embodiment 11 and the stacked imaging element is shown. Fig.48 and 49 An equivalent circuit diagram showing the imaging element of Embodiment 11 and the stacked imaging element is shown. Fig.50 A schematic layout diagram of transistors of a first electrode, a transfer control electrode, a charge storage electrode, and a control unit included in the imaging element of Embodiment 11 is shown. Fig.51 and 52 The potential states in each section during the operation of the imaging element of Embodiment 11 are schematically illustrated. Further, Fig.53 A schematic layout diagram of the first electrode, the transfer control electrode, and the charge storage electrode included in the imaging element of Embodiment 11 is shown. Fig. 9B Shown for describing Fig.51 and 52 An equivalent circuit diagram of the imaging element of Embodiment 11 and the stacked imaging element for each section.

[0467] The imaging element of Embodiment 11 and the stacked imaging element further include a transfer control electrode (charge transfer electrode) 15 disposed between the first electrode 11 and the charge storage electrode 14, separated from the first electrode 11 and the charge storage electrode 14, and disposed to face the photoelectric conversion layer 13 via an insulating layer 82. The transfer control electrode 15 is connected to a pixel drive circuit included in a drive circuit through a connection hole 68B provided in an interlayer insulating layer 81 and a pad portion 68A and through a wiring V 0T connected to the pixel drive circuit included in the drive circuit.

[0468] Hereinafter, with reference to Fig.51 and 52Describe the operation of the imaging element (first imaging element) of Example 11. Note that, in particular, the potential applied to the charge storage electrode 14 and the potential value at point P D vary between Fig.51 and 52 .

[0469] During charge storage, the drive circuit applies potential V 11 to the first electrode 11, applies potential V 12 to the charge storage electrode 14, and applies potential V 14 to the transfer control electrode 15. Light incident on the photoelectric conversion layer 13 causes photoelectric conversion in the photoelectric conversion layer 13. The electron-hole pairs generated by the photoelectric conversion are sent to the drive circuit from the second electrode 12 through the wiring V 0U . On the other hand, the potential of the first electrode 11 is higher than the potential of the second electrode 12. That is, for example, a positive potential is applied to the first electrode 11, and a negative potential is applied to the second electrode 12. Therefore, the potentials are set such that V 12 > V 14 (for example, V 12 > V 11 > V 14 or V 11 > V 12 > V 14 ) is maintained. Thus, the electrons generated by the photoelectric conversion are attracted to the charge storage electrode 14, and the electrons stop in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14. That is, charge is stored in the photoelectric conversion layer 13. V 12 is greater than V 14 , which of course prevents the electrons generated within the photoelectric conversion layer 13 from moving towards the first electrode 11. During the time course of the photoelectric conversion, the potential in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 becomes a larger negative value.

[0470] Subsequently, a reset operation is performed during charge storage. This resets the potential of the first floating diffusion layer FD 1 , and the potential of the first floating diffusion layer FD 1 becomes the potential V DD of the power supply.

[0471] After the reset operation is completed, the charge is read out. That is, during charge transfer, the drive circuit applies potential V 21 to the first electrode 11, applies potential V 22 to the charge storage electrode 14, and applies potential V 24 to the transfer control electrode 15. Here, the potentials are set such that V 22 ≤V 24 ≤V 21is maintained. Therefore, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 must be read out to the first electrode 11 and further read out to the first floating diffusion layer FD 1 . That is, the charges stored in the photoelectric conversion layer 13 are read out to the control unit.

[0472] This completes a series of operations including charge storage, reset operation, and charge transfer.

[0473] Read out the electrons to the first floating diffusion layer FD 1 After that, the amplification transistor TR1 amp and the selection transistor TR1 sel operate in the same manner as a conventional transistor. In addition, for example, a series of operations including charge storage, reset operation, and charge transfer of the second imaging element and the third imaging element are similar to a series of conventional operations including charge storage, reset operation, and charge transfer.

[0474] As Fig.53 shown in the schematic layout diagram of the transistors of the first electrode, charge storage electrode, and control unit included in the modified example of the imaging element of Embodiment 11, the other source / drain region 51B of the reset transistor TR1 rst can be grounded instead of connecting the other source / drain region 51B to the power supply V DD .

[0475] Embodiment 12

[0476] Embodiment 12 is a modification of Embodiments 1 to 11, and Embodiment 12 relates to an imaging element of the present disclosure including a plurality of charge storage electrode sections, etc.

[0477] Fig.54 Shows a schematic partial cross-sectional view of a part of the imaging element of Embodiment 12.

[0478] Fig.55 And 56 shows the equivalent circuit diagrams of the imaging element of Embodiment 12 and the stacked imaging element. Fig.57 Shows the schematic layout diagram of the transistors of the first electrode, charge storage electrode, and control unit included in the imaging element of Embodiment 12. Fig.58 And 59 schematically illustrates the potential states in each part during the operation of the imaging element of Embodiment 12. In addition, Fig. 9C shows Fig.58 the equivalent circuit diagrams of the imaging element of Embodiment 12 and the stacked imaging element for describing each part in

[0479] In Embodiment 12, the charge storage electrode 14 includes a plurality of charge storage electrode segments 14A, 14B, and 14C. The number of charge storage electrode segments may be equal to or greater than 2, and in Embodiment 12, the number is "3". Further, different electric potentials are applied to each of the N charge storage electrode segments in the imaging element and the stacked imaging element of Embodiment 12. The electric potential of the first electrode 11 is higher than the electric potential of the second electrode 12. That is, for example, a positive electric potential is applied to the first electrode 11, and a negative electric potential is applied to the second electrode 12. Therefore, during charge transfer, the electric potential applied to the charge storage electrode segment (first photoelectric conversion unit segment) 14A located at the position closest to the first electrode 11 is higher than the electric potential applied to the charge storage electrode segment (Nth photoelectric conversion unit segment) 14C located at the position farthest from the first electrode 11. In this way, an electric potential gradient is provided to the charge storage electrode 14. Therefore, electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 are more surely read out to the first electrode 11 and further read out to the first floating diffusion layer FD 1 . That is, the charges stored in the photoelectric conversion layer 13 are read out to the control unit.

[0480] In Fig.58 the example shown, during charge transfer, the electric potential of the charge storage electrode segment 14C < the electric potential of the charge storage electrode segment 14B < the electric potential of the charge storage electrode segment 14A is maintained. In this way, electrons stopped in the region of the photoelectric conversion layer 13 are simultaneously read out to the first floating diffusion layer FD 1 . On the other hand, in Fig.59 the example shown, during charge transfer, the electric potential of the charge storage electrode segment 14C, the electric potential of the charge storage electrode segment 14B, and the electric potential of the charge storage electrode segment 14A are gradually changed (i.e., changed stepwise or in an inclined shape). In this way, electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode segment 14C move to the region of the photoelectric conversion layer 13 facing the charge storage electrode segment 14B. Next, electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode segment 14B move to the region of the photoelectric conversion layer 13 facing the charge storage electrode segment 14A. Next, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode segment 14A are surely read out to the first floating diffusion layer FD 1 .

[0481] As Fig.60 shows a schematic layout diagram of the transistors of the first electrode, the charge storage electrode, and the control unit included in a modified example of the imaging element of Embodiment 12, the reset transistor TR1 rstAnother source / drain region 51B may be grounded instead of connecting another source / drain region 51B to the power supply V DD .

[0482] Example 13

[0483] Example 13 is a modification of Examples 1 to 12 and relates to the first configuration and the sixth configuration of the imaging element.

[0484] Fig.61 Schematic partial cross-sectional views of the imaging element and the stacked imaging element of Example 13 are shown. Fig.62 An enlarged schematic partial cross-sectional view showing a portion where the charge storage electrode, the photoelectric conversion layer, and the second electrode are stacked. The equivalent circuit diagrams of the imaging element and the stacked imaging element of Example 13 are similar to Figure 3 and 4 the equivalent circuit diagram of the imaging element of Example 1 described in. The schematic layout diagrams of the transistors of the first electrode, the charge storage electrode, and the control unit included in the imaging element of Example 13 are similar to Figure 5 the imaging element of Example 1 described in. In addition, the operation of the imaging element (the first imaging element) of Example 13 is substantially similar to the operation of the imaging element of Example 1.

[0485] Here, in the imaging element of Example 13 or the imaging elements of Examples 14 to 18 described later,

[0486] the photoelectric conversion unit includes N (where N≥2) photoelectric conversion unit sections (specifically, three photoelectric conversion unit sections 10 1 、10 2 、10 3 ).

[0487] The photoelectric conversion layer 13 includes N photoelectric conversion layer sections (specifically, three photoelectric conversion layer sections 13 1 、13 2 and 13 3 ), and

[0488] the insulating layer 82 includes N insulating layer sections (specifically, three insulating layer sections 82 1 、82 2 and 82 3 ).

[0489] In Examples 13 to 15, the charge storage electrode 14 includes N charge storage electrode sections (specifically, three charge storage electrode sections 14 in each example 1 、14 2 and 14 3 ).

[0490] In Embodiments 16 and 17 and, as the case may be, in Embodiment 15, the charge storage electrode 14 includes N charge storage electrode segments (specifically, three charge storage electrode segments 14 1 、14 2 and 14 3 ) arranged separately from each other,

[0491] The nth (where n = 1, 2, 3 ··· N) photoelectric conversion unit segment 10 n includes the nth charge storage electrode segment 14 n 、the nth insulating layer segment 82 n and the nth photoelectric conversion layer segment 13 n , and

[0492] The larger the n value of the photoelectric conversion unit segment, the farther the position of the photoelectric conversion unit segment is from the first electrode 11.

[0493] Alternatively, the imaging element of Embodiment 13 or the imaging elements of Embodiments 14 and 17 described later include

[0494] a photoelectric conversion unit including a stacked first electrode 11, a photoelectric conversion layer 13, and a second electrode 12, where

[0495] the photoelectric conversion unit further includes a charge storage electrode 14 arranged separately from the first electrode 11 and arranged to face the photoelectric conversion layer 13 via an insulating layer 82, and

[0496] the cross-sectional area when the stacked portions of the charge storage electrode 14, the insulating layer 82, and the photoelectric conversion layer 13 are cut in the YZ virtual plane varies according to the distance from the first electrode, where the Z direction is the stacking direction of the charge storage electrode 14, the insulating layer 82, and the photoelectric conversion layer 13, and the X direction is the direction away from the first electrode 11.

[0497] In addition, in the imaging element of Embodiment 13, the thickness of the insulating layer segment gradually changes from the first photoelectric conversion unit segment 10 1 to the Nth photoelectric conversion unit segment 10 N . Specifically, the thickness of the insulating layer segment gradually increases. Alternatively, in the imaging element of Embodiment 13, the width of the cross-section of the stacked portion is constant, and the thickness of the cross-section of the stacked portion, specifically, the thickness of the insulating layer segment, gradually increases according to the distance from the first electrode 11. Note that the thickness of the insulating layer segment increases stepwise. The thickness of the insulating layer segment 82 n in the nth photoelectric conversion unit segment 10 n is constant. Assuming the nth insulating layer segment 82 n in the nth photoelectric conversion unit segment 10 nIf the thickness of is "1", then the (n + 1)-th photoelectric conversion unit section 10 (n+1) the insulating layer section 82 in (n+1) can have a thickness of 2 to 10. However, the values are not limited to these. In Embodiment 13, the charge storage electrode sections 14 1 、14 2 and 14 3 have gradually decreasing thicknesses so that the insulating layer sections 82 1 、82 2 and 82 3 have gradually increasing thicknesses. The photoelectric conversion layer sections 13 1 、13 2 and 13 3 have a constant thickness.

[0498] Hereinafter, the operation of the imaging element of Embodiment 13 will be described.

[0499] During charge storage, the drive circuit applies a potential V 11 to the first electrode 11 and applies a potential V 12 to the charge storage electrode 14. Light incident on the photoelectric conversion layer 13 causes photoelectric conversion in the photoelectric conversion layer 13. The electron-hole pairs generated by the photoelectric conversion are sent from the second electrode 12 to the drive circuit through the wiring V 0U . On the other hand, the potential of the first electrode 11 is higher than the potential of the second electrode 12. That is, for example, a positive potential is applied to the first electrode 11 and a negative potential is applied to the second electrode 12. Therefore, the potential is set such that V 12 ≥V 11 , preferably, V 12 >V 11 is maintained. Thus, the electrons generated by the photoelectric conversion are attracted to the charge storage electrode 14, and the electrons stop in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14. That is, charges are stored in the photoelectric conversion layer 13. V 12 is greater than V 11 , so the electrons generated within the photoelectric conversion layer 13 do not move towards the first electrode 11. During the time course of the photoelectric conversion, the potential in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 becomes a larger negative value.

[0500] In the structure adopted by the imaging element of Embodiment 13, the thickness of the insulating layer section gradually increases. Therefore, when the state becomes V 12 ≥V 11 during charge storage, the n-th photoelectric conversion unit section 10 n can store more charges than the (n + 1)-th photoelectric conversion unit section 10 (n+1)More charges. A strong electric field is applied, and it is certain to prevent the charges from flowing from the first photoelectric conversion unit section 10 1 to the first electrode 11.

[0501] Subsequently, a reset operation is performed during the charge storage period. This resets the potential of the first floating diffusion layer FD 1 , and the potential of the first floating diffusion layer FD 1 becomes the potential V of the power supply DD .

[0502] After the reset operation is completed, the charges are read out. That is, during the charge transfer period, the driving circuit applies the potential V 21 to the first electrode 11 and applies the potential V 22 to the charge storage electrode 14. Here, the potentials are set such that V 21 > V 22 is maintained. Therefore, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 are read out to the first electrode 11 and further read out to the first floating diffusion layer FD 1 . That is to say, the charges stored in the photoelectric conversion layer 13 are read out to the control unit.

[0503] More specifically, when the state during the charge transfer period becomes V 21 > V 22 , it is certain to ensure the charge flow from the first photoelectric conversion unit section 10 1 to the first electrode 11 and the charge flow from the (n + 1)th photoelectric conversion unit section 10 (n+1) to the nth photoelectric conversion unit section 10 n .

[0504] This completes a series of operations including charge storage, reset operation, and charge transfer.

[0505] In the imaging element of Embodiment 13, the thickness of the insulating layer section gradually changes from the first photoelectric conversion unit section to the Nth photoelectric conversion unit section. Alternatively, the cross-sectional area of the stacked portion of the charge storage electrode, insulating layer, and photoelectric conversion layer when the stacked portion is cut in the YZ virtual plane changes according to the distance from the first electrode. Thus, a charge transfer gradient is formed, and the charges generated by photoelectric conversion can be transferred more easily and more surely.

[0506] The imaging element of Embodiment 13 and the stacked imaging element can be produced by a method substantially similar to that of the imaging element of Embodiment 1, and the details will not be described again.

[0507] Note that when forming the first electrode 11, charge storage electrode 14, and insulating layer 82 in the imaging element of Example 13, first, a conductive material layer for forming the charge storage electrode 14 is deposited on the interlayer insulating layer 81. The conductive material layer is patterned and left in the regions where the photoelectric conversion unit sections 10 3 are to be formed, 1 10 2 and 3 10 3 and the first electrode 11. In this way, a part of the first electrode 11 and the charge storage electrode 14 3 can be obtained. Next, an insulating layer for forming the insulating layer section 82 3 is deposited on the entire surface. The insulating layer is patterned and planarized. In this way, the insulating layer section 82 2 can be obtained. Then, a conductive material layer for forming the charge storage electrode 14 1 is deposited on the entire surface, and the conductive material layer is patterned. The conductive material layer is left in the regions where the photoelectric conversion unit sections 10 2 and 2 10 2 and the first electrode 11 are to be formed. In this way, a part of the first electrode 11 and the charge storage electrode 14 2 can be obtained. Then, an insulating layer for forming the insulating layer section 82 1 is deposited on the entire surface. The insulating layer is patterned and planarized. In this way, the insulating layer section 82 1 can be obtained. Then, a conductive material layer for forming the charge storage electrode 14 1 is deposited on the entire surface. The conductive material layer is patterned and left in the regions where the photoelectric conversion unit section 10 1 (insulating layer 82). In addition, a photoelectric conversion layer 13 is formed on the insulating layer 82. In this way, the photoelectric conversion unit sections 10 1 10 2 and 3 10

[0508] As Fig.63 shown, which shows a schematic layout diagram of the transistors of the first electrode, charge storage electrode, and control unit included in a modified example of the imaging element of Example 13, the reset transistor TR1 rstAnother source / drain region 51B may be grounded instead of connecting the said another source / drain region 51B to the power supply V DD .

[0509] Example 14

[0510] The imaging element of Example 14 relates to the imaging elements of the second configuration and the sixth configuration of the present disclosure. As shown in the enlarged schematic partial cross-sectional view of the portion of the stacked charge storage electrode, the photoelectric conversion layer, and the second electrode, in the imaging element of Example 14, the thickness of the photoelectric conversion layer section gradually changes from the first photoelectric conversion unit section 10 Fig.64 to the Nth photoelectric conversion unit section 10 1 . N Alternatively, in the imaging element of Example 14, the width of the cross-section of the stacked member is constant, and the thickness of the cross-section of the stacked portion, particularly the thickness of the photoelectric conversion layer section, gradually increases according to the distance from the first electrode 11. Specifically, the thickness of the photoelectric conversion layer section gradually increases. Note that the thickness of the photoelectric conversion layer section increases stepwise. The thickness of the photoelectric conversion layer section 13 n in the nth photoelectric conversion unit section 10 n is constant. Assuming that the thickness of the photoelectric conversion layer section 13 n in the nth photoelectric conversion unit section 10 n is "1", then the thickness of the photoelectric conversion layer section 13 (n+1) in the (n + 1)th photoelectric conversion unit section 10 (n+1) can be 2 to 10. However, the values are not limited to these. In Example 14, the thicknesses of the charge storage electrode sections 14 1 , 14 2 and 14 3 gradually decrease so that the thicknesses of the photoelectric conversion layer sections 13 1 , 13 2 and 13 3 gradually increase. The thicknesses of the insulating layer sections 82 1 , 82 2 and 82 3 are constant.

[0511] In the imaging element of Example 14, the thickness of the photoelectric conversion layer section gradually increases. Therefore, when the state becomes V during the charge storage period 12 ≥V 11 , the electric field applied to the nth photoelectric conversion unit section 10 n is stronger than the electric field applied to the (n + 1)th photoelectric conversion unit section 10 (n+1) . This surely can prevent charges from the first photoelectric conversion unit section 10 1flows to the first electrode 11. Further, when the state during charge transfer becomes V 22 <V 21 it is always possible to ensure the charge flow from the first photoelectric conversion unit section 10 1 to the first electrode 11 and the charge flow from the (n + 1)-th photoelectric conversion unit section 10 (n+1) to the n-th photoelectric conversion unit section 10 n .

[0512] In this way, in the imaging element of Embodiment 14, the thickness of the photoelectric conversion layer section gradually changes from the first photoelectric conversion unit section to the N-th photoelectric conversion unit section. Alternatively, the cross-sectional area of the stacked portion of the charge storage electrode, the insulating layer, and the photoelectric conversion layer when the stacked portion is cut in the YZ virtual plane varies according to the distance from the first electrode. Thus, a charge transfer gradient is formed, and the charges generated by photoelectric conversion can be transferred more easily and more surely.

[0513] When forming the first electrode 11, the charge storage electrode 14, the insulating layer 82, and the photoelectric conversion layer 13 in the imaging element of Embodiment 14, first, a conductive material layer for forming the charge storage electrode 14 is deposited on the interlayer insulating layer 81 3 . The conductive material layer is patterned, and the conductive material layer is left in the regions where the photoelectric conversion unit sections 10 1 、10 2 and 10 3 as well as the first electrode 11 will be formed. In this way, a part of the first electrode 11 and the charge storage electrode 14 3 can be obtained. Next, a conductive material layer for forming the charge storage electrode 14 is deposited on the entire surface, and the conductive material layer is patterned. The conductive material layer is left in the regions where the photoelectric conversion unit sections 10 2 and 10 1 and 10 2 as well as the first electrode 11 will be formed. In this way, a part of the first electrode 11 and the charge storage electrode 14 2 can be obtained. Next, a conductive material layer for forming the charge storage electrode 14 is deposited on the entire surface, and the conductive material layer is patterned. The conductive material layer is left in the regions where the photoelectric conversion unit section 10 1 and the first electrode 11 will be formed. In this way, the first electrode 11 and the charge storage electrode 14 1 can be obtained. Next, the insulating layer 82 is conformally deposited on the entire surface. Further, the photoelectric conversion layer 13 is formed on the insulating layer 82, and a planarization process is applied to the photoelectric conversion layer 13. In this way, the photoelectric conversion unit sections 10 1 、10 1 、102 and 10 3 。

[0514] Example 15

[0515] Example 15 relates to an imaging element of the third structure. Fig.65 FIG. shows a schematic partial cross-sectional view of the imaging element of Example 15 and the stacked imaging element. In the imaging element of Example 15, the material contained in the insulating layer section varies between adjacent photoelectric conversion unit sections. Here, the dielectric constant value of the material contained in the insulating layer section ranges from the first photoelectric conversion unit section 10 1 to the nth photoelectric conversion unit section 10 n gradually decreases. In the imaging element of Example 15, the same potential can be applied to all N charge storage electrode sections, or different potentials can be applied to each of the N charge storage electrode sections. In the latter case, as described in Example 16, the charge storage electrode sections 14 1 、14 2 and 14 3 can be connected to the vertical drive circuit 112 included in the drive circuit through the pad portions 64 1 、64 2 and 64 3 connected to the vertical drive circuit 112 included in the drive circuit.

[0516] In addition, by adopting this structure, a charge transfer gradient is formed. When the state becomes V during the charge storage period 12 ≥V 11 , the nth photoelectric conversion unit section can store more charges than the (n + 1)th photoelectric conversion unit section. In addition, when the state becomes V during the charge transfer period 22 <V 21 , it is certain to ensure the charge flow from the first photoelectric conversion unit section to the first electrode and the charge flow from the (n + 1)th photoelectric conversion unit section to the nth photoelectric conversion unit section.

[0517] Example 16

[0518] Example 16 relates to an imaging element of the fourth structure, Fig.66 FIG. shows a schematic partial cross-sectional view of the imaging element of Example 16 and the stacked imaging element. In the imaging element of Example 16, the material contained in the charge storage electrode section varies between adjacent photoelectric conversion unit sections. Here, the work function value of the material contained in the insulating layer section ranges from the first photoelectric conversion unit section 10 1 to the Nth photoelectric conversion unit section 10 NGradually increase. In the imaging element of Embodiment 16, the same potential can be applied to all N charge storage electrode segments, or different potentials can be applied to each of the N charge storage electrode segments. In the latter case, the charge storage electrode segments 14 1 、14 2 and 14 3 are connected to the vertical drive circuit 112 included in the drive circuit through the pad portions 64 1 、64 2 and 64 3 .

[0519] Embodiment 17

[0520] The imaging element of Embodiment 17 relates to an imaging element of the fifth structure. Fig.67A 、 67B 、68A and 68B show schematic plan views of the charge storage electrode segments in Embodiment 17. Fig.69 A schematic layout diagram of the transistors of the first electrode, charge storage electrode, and control unit included in the imaging element of Embodiment 17 is shown. The schematic partial cross-sectional views of the imaging element of Embodiment 17 and the stacked imaging element are similar to Fig.66 or the schematic partial cross-sectional view shown in 71. In the imaging element of Embodiment 17, the area of the charge storage electrode segments gradually decreases from the first photoelectric conversion unit segment 10 1 to the Nth photoelectric conversion unit segment 10 N . In the imaging element of Embodiment 17, the same potential can be applied to all N charge storage electrode segments, or different potentials can be applied to each of the N charge storage electrode segments. Specifically, as described in Embodiment 16, the charge storage electrode segments 14 1 、14 2 and 14 3 can be connected to the vertical drive circuit 112 included in the drive circuit through the pad portions 64 1 、64 2 and 64 3 .

[0521] In Embodiment 17, the charge storage electrode 14 includes a plurality of charge storage electrode segments 14 1 、14 2 and 14 3. The number of charge storage electrode segments may be equal to or greater than 2, and in Embodiment 17, the number is "3". Further, in the imaging element and the stacked imaging element of Embodiment 17, the potential of the first electrode 11 is higher than the potential of the second electrode 12. That is, for example, a positive potential is applied to the first electrode 11, and a negative potential is applied to the second electrode 12. Therefore, during charge transfer, the potential applied to the charge storage electrode segment 14 located closest to the first electrode 11 1 is higher than the potential applied to the charge storage electrode segment 14 located farthest from the first electrode 11 3 . In this way, a potential gradient is provided to the charge storage electrode 14. Therefore, electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 are more surely read out to the first electrode 11 and further read out to the first floating diffusion layer FD 1 . That is, the charge stored in the photoelectric conversion layer 13 is read out to the control unit.

[0522] Further, during charge transfer, the potential of the charge storage electrode segment 14 3 < the potential of the charge storage electrode segment 14 2 < the potential of the charge storage electrode segment 14 1 is maintained. In this way, electrons stopped in the region of the photoelectric conversion layer 13 can be simultaneously read out to the first floating diffusion layer FD 1 . Alternatively, during charge transfer, the potential of the charge storage electrode segment 14 3 , the potential of the charge storage electrode segment 14 2 , and the potential of the charge storage electrode segment 14 1 gradually change (i.e., change stepwise or in an inclined shape). In this way, electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode segment 14 3 move to the region of the photoelectric conversion layer 13 facing the charge storage electrode segment 14 2 . Then, electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode segment 14 2 move to the region of the photoelectric conversion layer 13 facing the charge storage electrode segment 14 1 . Then, electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode segment 14 1 can surely be read out to the first floating diffusion layer FD 1 .

[0523] As Fig.70 shows a schematic layout diagram of the transistors of the first electrode, the charge storage electrode, and the control unit included in a modified example of the imaging element of Embodiment 17, the reset transistor TR3 rstAnother source / drain region 51B may be grounded instead of connecting another source / drain region 51B to the power supply V DD .

[0524] In the imaging element of Embodiment 17, a charge transfer gradient is also formed by adopting this configuration. That is, the area of the charge storage electrode section gradually decreases from the first photoelectric conversion unit section 10 1 to the Nth photoelectric conversion unit section 10 N . Therefore, when the state becomes V 12 ≥V 11 during the charge storage period, the nth photoelectric conversion unit section can store more charges than the (n + 1)th photoelectric conversion unit section. In addition, when the state becomes V 22 <V 21 during the charge transfer period, the charge flow from the first photoelectric conversion unit section to the first electrode and the charge flow from the (n + 1)th photoelectric conversion unit section to the nth photoelectric conversion unit section can be surely ensured.

[0525] Embodiment 18

[0526] Embodiment 18 relates to an imaging element of the sixth configuration. Fig.71 FIG. shows a schematic partial cross-sectional view of the imaging element of Embodiment 18 and a stacked imaging element. Fig.72A and 72B FIG. shows a schematic plan view of the charge storage electrode section in Embodiment 18. The imaging element of Embodiment 18 includes a photoelectric conversion unit, which includes a stacked first electrode 11, a photoelectric conversion layer 13, and a second electrode 12. The photoelectric conversion unit further includes a charge storage electrode 14 that is separately arranged from the first electrode 11 and is arranged to face the photoelectric conversion layer 13 via an insulating layer 82. In addition, the cross-sectional area of the stacked portion of the charge storage electrode 14, the insulating layer 82, and the photoelectric conversion layer 13 when the stacked portion is cut in the YZ virtual plane varies according to the distance from the first electrode 11, where the Z direction is the stacking direction of the charge storage electrode 14, the insulating layer 82, and the photoelectric conversion layer 13, and the X direction is the direction away from the first electrode 11.

[0527] Specifically, in the imaging element of Embodiment 18, the thickness of the cross-section of the stacked portion is constant, and the width of the cross-section of the stacked portion decreases as the distance from the first electrode 11 increases. Note that the width can decrease continuously (see Fig.72A ) or can decrease stepwise (see Fig.72B ).

[0528] Thus, in the imaging element of Example 18, the cross-sectional area of the stacked portion of the charge storage electrode 14, the insulating layer 82, and the photoelectric conversion layer 13 changes according to the distance from the first electrode. Accordingly, a charge transfer gradient is formed, and the charges generated by photoelectric conversion can be transferred more easily and more surely.

[0529] Example 19

[0530] Example 19 relates to a solid-state imaging device having a first configuration and a second configuration.

[0531] The solid-state imaging device of Example 19 includes

[0532] a photoelectric conversion unit including a stacked first electrode 11, a photoelectric conversion layer 13, and a second electrode 12, wherein

[0533] the photoelectric conversion unit further includes a plurality of imaging elements, each imaging element including a charge storage electrode 14 disposed separately from the first electrode 11 and disposed to face the photoelectric conversion layer 13 via an insulating layer 82,

[0534] the plurality of imaging elements are included in an imaging element block, and

[0535] the first electrode 11 is shared by the plurality of imaging elements included in the imaging element block.

[0536] Alternatively, the solid-state imaging device of Example 19 includes the plurality of imaging elements described in Examples 1 to 18.

[0537] In Example 19, one floating diffusion layer is provided for the plurality of imaging elements. Additionally, the timing of the charge transfer period can be appropriately controlled to allow the plurality of imaging elements to share one floating diffusion layer. Further, in this case, the plurality of imaging elements can share one contact hole portion.

[0538] Note that, except that the first electrode 11 is shared by the plurality of solid-state imaging devices included in the example block, the solid-state imaging device of Example 19 has a configuration and structure substantially similar to those of the solid-state imaging devices described in Examples 1 to 18.

[0539] Fig.73 (Example 19), Fig.74 (First modification of Example 19), Fig.75 (Second modification of Example 19), Modification 76 (Third modification of Example 19) and Example 77 (Fourth modification of Example 19) schematically illustrate the arrangement states of the first electrode 11 and the charge storage electrode 14 in the solid-state imaging device of Example 19. Fig.73 、 74 、77 and 78 show 16 imaging elements, Fig.75 and 76 shows 12 imaging elements. In addition, two imaging elements are included in an imaging element block. The imaging element block is surrounded by a dashed line and shown. Subscripts attached to the first electrode 11 and the charge storage electrode 14 are used to distinguish the first electrode 11 and the charge storage electrode 14. The same applies to the following description. In addition, an on-chip microlens ( Figures 73 to 82 not shown in the figure) is arranged on the upper side of one imaging element. In addition, in one imaging element block, two charge storage electrodes 14 are arranged on both sides of the first electrode 11 (see Fig.73 and 74 ). Alternatively, one first electrode 11 is arranged to face two charge storage electrodes 14 arranged side by side (see Fig.77 and 78 ). That is, the first electrode is arranged adjacent to the charge storage electrodes of each imaging element. Alternatively, the first electrode is arranged adjacent to the charge storage electrodes of a part of the plurality of imaging elements and not arranged adjacent to the charge storage electrodes of the remaining part of the plurality of imaging elements (see Fig.75 and 76 ). In this case, the movement of charge from the remaining part of the plurality of imaging elements to the first electrode is through the movement of the said part of the plurality of imaging elements. Preferably, the distance A between the charge storage electrodes included in the imaging elements and the charge storage electrodes included in the imaging elements is longer than the distance B between the first electrode and the charge storage electrodes in the imaging element adjacent to the first electrode, so as to surely move the charge from each imaging element to the first electrode. In addition, preferably, the farther the position of the imaging element is from the first electrode, the larger the value of the distance A is. In addition, in the examples shown in Fig.74 , 76 and 78, the charge movement control electrode 21 is arranged between a plurality of imaging elements included in the imaging element block. Arranging the charge movement control electrode 21 can surely suppress the movement of charge in the imaging element block located on both sides of the charge movement control electrode 21. Note that the potential can be set such that V 12 >V 13 (for example, V 12-2 >V 13 ) is maintained, where V 13 is the potential applied to the charge movement control electrode 21.

[0540] The charge movement control electrode 21 may be formed on the same level as the first electrode 11 or the charge storage electrode 14, or may be formed on a different level on the first electrode side (specifically, a level below the first electrode 11 or the charge storage electrode 14). In the former case, the distance between the charge movement control electrode 21 and the photoelectric conversion layer can be reduced, and the electric potential can be easily controlled. On the other hand, in the latter case, the distance between the charge movement control electrode 21 and the charge storage electrode 14 can be reduced, which is advantageous for miniaturization.

[0541] Hereinafter, the operation of the imaging element block including the first electrode 11 2 and two charge storage electrodes 14 21 and 14 22 will be described.

[0542] During charge storage, the drive circuit applies the electric potential V a to the first electrode 11 2 , and applies the electric potential V A to the charge storage electrodes 14 21 and 14 22 . The light incident on the photoelectric conversion layer 13 causes photoelectric conversion in the photoelectric conversion layer 13. The electron-hole pairs generated by the photoelectric conversion are sent from the second electrode 22 to the drive circuit through the wiring V 0U . On the other hand, the electric potential of the first electrode 11 2 is higher than the electric potential of the second electrode 12. That is, for example, a positive electric potential is applied to the first electrode 11 2 , while a negative electric potential is applied to the second electrode 12. Therefore, the electric potential is set so that V A ≥V a is maintained. Thus, the electrons generated by the photoelectric conversion are attracted to the charge storage electrodes 14 21 and 14 22 , and the electrons stop in the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 21 and 14 22 . That is, charges are stored in the photoelectric conversion layer 13. V A is equal to or greater than V a , so the electrons generated within the photoelectric conversion layer 13 do not move toward the first electrode 11 2 . During the time course of the photoelectric conversion, the electric potential in the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 21 and 14 22 becomes a larger negative value.

[0543] Subsequently, a reset operation is performed during charge storage. This resets the electric potential of the first floating diffusion layer, and the electric potential of the first floating diffusion layer becomes the electric potential V DD of the power supply.

[0544] After the reset operation is completed, the charge is read out. That is, during the charge transfer, the drive circuit applies the potential V b to the first electrode 11 2 and applies the potential V 21-B to the charge storage electrode 14 21 and applies the potential V 22-B to the charge storage electrode 14 22 . Here, the potential is set such that V 21-B < V b < V 22-B is maintained. Accordingly, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 are read out to the first electrode 11 2 and further read out to the first floating diffusion layer FD 1 . That is, the charge stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 is read out to the control unit. Once the reading is completed, the potential is set such that V 22-B ≤ V 21-B < V b is maintained. Note that in the examples illustrated in Fig.77 and Fig.78 , the potential can be set such that V 22-B < V b < V 21-B is maintained. Accordingly, the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 22 are read out to the first electrode 11 2 and further read out to the first floating diffusion layer FD 1 . In addition, in the examples illustrated in Fig.75 and 76 , the electrons stopped in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 22 can be read out to the first floating diffusion layer FD 22 through the first electrode 11 3 adjacent to the charge storage electrode 14 1 . In this way, the charge stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 22 is read out to the control unit. Note that when the charge stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 is read out to the control unit, the potential of the first floating diffusion layer can be reset.

[0545] Fig.83A Shows an example of reading and driving in the imaging element block of Example 19.

[0546] [Step A]

[0547] Input the auto zero signal to the comparator

[0548] [Step B]

[0549] Reset operation of a common floating diffusion layer

[0550] [Step C]

[0551] Read the P-phase corresponding to the charge storage electrode 14 in the imaging element 21 and move the charge to the first electrode 11 2

[0552] [Step D]

[0553] Read the D-phase corresponding to the charge storage electrode 14 in the imaging element 21 and move the charge to the first electrode 112

[0554] [Step E]

[0555] Reset operation of a common floating diffusion layer

[0556] [Step F]

[0557] Input the auto zero signal to the comparator

[0558] [Step G]

[0559] Read the P-phase corresponding to the charge storage electrode 14 in the imaging element 22 and move the charge to the first electrode 11 2

[0560] [Step H]

[0561] Read the D-phase corresponding to the charge storage electrode 14 in the imaging element 22 and move the charge to the first electrode 11 2

[0562] In this process, signals from two imaging elements corresponding to the charge storage electrode 14 21 and the charge storage electrode 14 22 are read. Based on the correlated double sampling (CDS) process, the difference between the P-phase read in [Step C] and the D-phase read in [Step D] is the signal from the imaging element corresponding to the charge storage electrode 14 21 . The difference between the P-phase read in [Step G] and the D-phase read in [Step H] is the signal from the imaging element corresponding to the charge storage electrode 14 22 . ​​​

[0563] Note that the operation of [Step E] can be skipped (see Fig.83B ). In addition, the operation of [Step F] can be skipped, and in this case, the operation of [Step G] can be further skipped (see Fig.83C ). The difference between the reading of the P-phase in [Step C] and the reading of the D-phase in [Step D] is the signal from the imaging element corresponding to the charge storage electrode 14 21 . The difference between the reading of the D-phase in [Step D] and the reading of the D-phase in [Step H] is the signal from the imaging element corresponding to the charge storage electrode 14 22 .

[0564] In a modified example (the sixth modified example of Embodiment 19) schematically showing the arrangement state of the first electrode 11 and the charge storage electrode 14 and Fig.79 (the seventh modified example of Embodiment 19), four imaging elements are included in the imaging element block. The operation of the solid-state imaging device can be substantially similar to that of the solid-state imaging device shown in Fig.80 . Figures 73 to 78

[0565] In the eighth modified example and the ninth modified example schematically illustrating the arrangement state of the first electrode 11 and the charge storage electrode 14 Fig.81 and 82 , 16 imaging elements are included in the imaging element block. As shown in Fig.81 and 82 , the charge movement control electrodes 21A 1 , 21A 2 and 21A 3 are arranged between the charge storage electrode 14 11 and the charge storage electrode 14 12 , between the charge storage electrode 14 12 and the charge storage electrode 14 13 , and between the charge storage electrode 14 13 and the charge storage electrode 14 14 . In addition, as shown in Fig.82 , the charge movement control electrodes 21B 1 , 21B 2 and 21B 3 are arranged between the charge storage electrodes 14 21 , 14 31 and 14 41 and the charge storage electrodes 14 22 , 14 32 and 14 42 , between the charge storage electrodes 14 22 , 14 32 and 14 42 and the charge storage electrode 14​23 and 14 33 and 14 43 between years and the charge storage electrodes 14 23 and 14 33 and 14 43 and the charge storage electrodes 14 24 and 14 34 and 14 44 In addition, the charge movement control electrode 21C is provided between the imaging element blocks. Further, in each solid-state imaging device, sixteen charge storage electrodes 14 can be controlled to read the charges stored in the photoelectric conversion layer 13 from the first electrode 11.

[0566] [Step 10]

[0567] Specifically, first, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 are read from the first electrode 11. 11 of the region. Next, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 are read from the first electrode 11 through the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 11 of the region. Next, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 are read from the first electrode 11 through the regions of the photoelectric conversion layer 13 facing the charge storage electrodes 14 12 and the charge storage electrodes 14 12 of the region. 11 of the region. 13 of the region.

[0568] [Step 20]

[0569] Subsequently, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14. 21 of the region. The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 11 of the region. The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 22 of the region. The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 12 of the region. The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 23 of the region. The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 13 of the region. The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 24 of the region. The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrodes 14 14 of the region.

[0570] [Step 21]

[0571] Move the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 31 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 32 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 22 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 33 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 23 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 34 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 24 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14

[0572] [Step 22]

[0573] Move the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 41 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 31 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 42 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 32 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 43 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 33 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 44 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 34 to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14

[0574] [Step 30]

[0575] In addition, step 10 can be executed again to read the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 from the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 22 from the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 23 from the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 24 from the region of the photoelectric conversion layer 13 facing the charge storage electrode 14

[0576] [Step 40]

[0577] Subsequently, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 11 The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 22 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 12 The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 23 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 13 The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 24 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 14 The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14

[0578] [Step 41]

[0579] The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 31 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 32 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 22 The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 33 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 23 The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 34 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 24 The charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14

[0580] [Step 50]

[0581] In addition, step 10 can be executed again to read the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 31 the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 32 the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 33 the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 34 through the first electrode 11

[0582] [Step 60]

[0583] Subsequently, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 21 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 11 Subsequently, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 22 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 12 Subsequently, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 23 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 13 Subsequently, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 24 are moved to the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 14 Subsequently, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14

[0584] [Step 70]

[0585] In addition, step 10 can be executed again to read the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 41 by the first electrode 11, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 42 by the first electrode 11, the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 43 by the first electrode 11, and the charges stored in the region of the photoelectric conversion layer 13 facing the charge storage electrode 14 44 by the first electrode 11.

[0586] In the solid-state imaging device according to Embodiment 19, the first electrode is shared by a plurality of imaging elements included in the imaging element block. This can simplify and miniaturize the structure and configuration in the pixel region where a plurality of imaging elements are arranged. Note that the plurality of imaging elements provided for one floating diffusion layer may include a plurality of imaging elements of the first type, or may include at least one imaging element of the first type or one or two or more imaging elements of the second type.

[0587] Embodiment 20

[0588] Embodiment 20 is a modification of Embodiment 19. In the solid-state imaging device according to Embodiment 20 shown schematically in Fig.84 , 85 , 86, and 87, two imaging elements are included in the imaging element block. In addition, an on-chip microlens 90 is provided on the upper side of the imaging element block. Note that in Fig.85and Fig.87 In the example shown in Fig.87 , the charge movement control electrode 21 is arranged between a plurality of imaging elements included in the imaging element block.

[0589] For example, the photoelectric conversion layer corresponding to the charge storage electrodes 14 11 , 14 21 , 14 31 and 14 41 included in the imaging element block is highly sensitive to incident light from the upper right in the drawing. In addition, the photoelectric conversion layer corresponding to the charge storage electrodes 14 12 , 14 22 , 14 32 and 14 42 included in the imaging element block is highly sensitive to incident light from the upper left in the drawing. Therefore, for example, imaging elements including the charge storage electrode 14 11 and imaging elements including the charge storage electrode 14 12 can be combined to obtain an image plane phase difference signal. Additionally, the signals from the imaging elements including the charge storage electrode 14 11 and the signals from the imaging elements including the charge storage electrode 14 12 can be added, and the combination of the imaging elements can provide one imaging element. Although in the example shown in Fig.84 , the first electrode 11 Fig.84 is arranged between the charge storage electrode 14 1 and the charge storage electrode 14 11 , one first electrode 11 12 can be arranged to face two charge storage electrodes 14 1 arranged side by side 11 and 14 12 , as in the example shown in Fig.86 , thereby further improving the sensitivity. Fig.86

[0590] Although the present disclosure has been described based on preferred embodiments, the present disclosure is not limited to these embodiments. The structures, configurations, manufacturing conditions, manufacturing methods, and materials used for the imaging elements, stacked imaging elements, and solid-state imaging devices described in the embodiments are illustrative and can be appropriately changed. The imaging elements of the embodiments can be appropriately combined. For example, the imaging elements of Embodiment 13, the imaging elements of Embodiment 14, the imaging elements of Embodiment 15, the imaging elements of Embodiment 16, and the imaging elements of Embodiment 17 can be arbitrarily combined, and the imaging elements of Embodiment 13, the imaging elements of Embodiment 14, the imaging elements of Embodiment 15, the imaging elements of Embodiment 16, and the imaging elements of Embodiment 18 can be arbitrarily combined.

[0591] Floating diffusion layer FD 1 , FD 21 , FD​3 51C, 45C, and 46C can also be shared as appropriate.

[0592] For example, in the variant of the imaging element and the stacked imaging element described in Example 1 shown in Fig.88 the first electrode 11 may extend in the opening 84A provided in the insulating layer 82, and the first electrode 11 may be connected to the stacked photoelectric conversion layer 13.

[0593] Alternatively, for example, in the variant of the imaging element and the stacked imaging element described in Example 1 shown in Fig.89 and as shown in the enlarged schematic partial cross-sectional view of a part of the first electrode etc. shown in Fig.90A the edge portion of the top surface of the first electrode 11 is covered by the insulating layer 82, and the first electrode 11 is exposed on the bottom surface of the opening 84B. The side surface of the opening 84B has a slope extending from the first surface 82a to the second surface 82b, where the first surface 82a is the surface of the insulating layer 82 that contacts the top surface of the first electrode 11, and the second surface 82b is the surface of the insulating layer 82 that contacts the portion of the photoelectric conversion layer 13 facing the charge storage electrode 14. Thus, the side surface of the opening 84B is inclined, and charges move more smoothly from the photoelectric conversion layer 13 to the first electrode 11. Note that although in the example shown in Fig.90A the side surface of the opening 84B has rotational symmetry with respect to the axis of the opening 84B, as shown in Fig.90B the opening 84C may be provided such that the side surface of the opening 84C that extends inclined from the first surface 82a to the second surface 82b is closer to the charge storage electrode 14. This makes it difficult for charges to move from the portion of the photoelectric conversion layer 13 that is on the opposite side of the charge storage electrode 14 with respect to the opening 84C. Further, although the side surface of the opening 84B extends inclined from the first surface 82a to the second surface 82b, the edge portion of the side surface of the opening 84B in the second surface 82b may be located outside the edge portion of the first electrode 11 as shown in Fig.90A or may be located inside the edge portion of the first electrode 11 as shown in Fig.90C The former configuration can be adopted to more easily transfer charges, and the latter configuration can be adopted to reduce shape changes during the opening formation process.

[0594] The reflux of the etching mask including the resist material formed for forming an opening in the insulating layer based on an etching method can cause the side surface of the opening of the etching mask to form a slope, and the etching mask can be used to etch the insulating layer 82 to form the openings 84B and 84C.

[0595] In addition, for example, in Fig.91In the modification examples of the imaging element and the stacked imaging element described in Example 1 shown, light may be incident from the second electrode 12 side, and a light-shielding layer 92 may be formed closer to the light-incident side of the second electrode 12. Note that various wirings provided on the light-incident side with respect to the photoelectric conversion layer may also be used as the light-shielding layer.

[0596] Note that although in Fig.91 the example shown the light-shielding layer 92 is formed on the upper side of the second electrode 12, that is, although the light-shielding layer 92 is formed closer to the light-incident side of the second electrode 12 and on the upper side of the first electrode 11, the light-shielding layer 92 may be arranged as Fig.92 shown on the surface of the light-incident side of the second electrode 12. Further, as Fig.93 shown, depending on the situation, the light-shielding layer 92 may be formed on the second electrode 12.

[0597] Alternatively, light may be incident from the second electrode 12 side, and the light may not be incident on the first electrode 11. Specifically, as Fig.91 shown, the light-shielding layer 92 is formed closer to the light-incident side of the second electrode 12 and on the upper side of the first electrode 11. Alternatively, as Fig.95 shown, the on-chip microlens 90 may be provided on the upper sides of the charge storage electrode 14 and the second electrode 12. The light incident on the on-chip microlens 90 may be collected by the charge storage electrode 14, and the light may not reach the first electrode 11. Note that in the case where the transfer control electrode 15 is provided as described in Example 11, the light may not be incident on the first electrode 11 and the transfer control electrode 15. Specifically, as Fig.94 shown, the light-shielding layer 92 may be formed on the upper sides of the first electrode 11 and the transfer control electrode 15. Alternatively, the light incident on the on-chip microlens 90 may not reach the first electrode 11, or may not reach the first electrode 11 and the transfer control electrode 15.

[0598] These configurations and structures may be adopted. Alternatively, the light-shielding layer 92 may be provided such that light is only incident on the portion of the photoelectric conversion layer 13 located above the charge storage electrode 14. Alternatively, the on-chip microlens 90 may be designed. In this way, the portion of the photoelectric conversion layer 13 located above the first electrode 11 (or above the first electrode 11 and the transfer control electrode 15) does not contribute to photoelectric conversion. Therefore, all pixels can be more surely reset simultaneously in their entirety, and the global shutter function can be more easily achieved. That is, in a driving method of a solid-state imaging device including a plurality of imaging elements having the configurations and structures, the following steps are repeated:

[0599] In all the imaging elements, all the charges in the first electrode 11 are simultaneously released to the outside of the system, and charges are stored in the photoelectric conversion layer 13; subsequently,

[0600] In all imaging elements, the charges stored in the photoelectric conversion layer 13 are simultaneously and entirely transferred to the first electrode 11, and after the transfer is completed, the imaging elements sequentially read the charges transferred to the first electrode 11.

[0601] In the driving method of the solid-state imaging device, in each imaging element, light from the second electrode side does not impinge on the first electrode. In all imaging elements, the charges in the first electrode are simultaneously and entirely released to the outside of the system, and the charges are stored in the photoelectric conversion layer. Therefore, the first electrode can surely be reset simultaneously in all imaging elements. Furthermore, subsequently, in all imaging elements, the charges stored in the photoelectric conversion layer are simultaneously and entirely transferred to the first electrode. After the transfer is completed, the imaging elements sequentially read the charges transferred to the first electrode. Therefore, the so-called global shutter function can be easily achieved.

[0602] In addition, in a modification of Embodiment 11, as Fig.95 shown, a plurality of transfer control electrodes can be provided from the position closest to the first electrode 11 toward the charge storage electrode 14. Note that Figure 96 an example in which two transfer control electrodes 15A and 15B are provided is shown. In addition, an on-chip microlens 90 can be provided on the upper side of the charge storage electrode 14 and the second electrode 12. The light incident on the on-chip microlens 90 can be collected by the charge storage electrode 14, and the light does not reach the first electrode 11 and the transfer control electrodes 15A and 15B.

[0603] In Figure 61 and 62 the Embodiment 13 shown, the thicknesses of the charge storage electrode sections 14 1 , 14 2 and 14 3 gradually decrease so that the thicknesses of the insulating layer sections 82 1 , 82 2 and 82 3 gradually increase. On the other hand, as shown in a magnified schematic partial cross-sectional view of a stacked portion of the charge storage electrode, the photoelectric conversion layer, and the second electrode in a modification of Embodiment 13 in Figure 97 , the thicknesses of the charge storage electrode sections 14 1 , 14 2 and 14 3 can be constant, and the thicknesses of the insulating layer sections 82 1 , 82 2 and 82 3 can gradually increase. Note that the thicknesses of the photoelectric conversion layer sections 13 1 , 13 2 and 13 3 are constant.

[0604] In addition, in Figure 64 Example 14 shown, the thickness of the charge storage electrode sections 14 1 , 14 2 and 14 3 gradually decreases so that the thickness of the photoelectric conversion layer sections 13 1 , 13 2 and 13 3 gradually increases. On the other hand, as shown in Figure 98 is a magnified schematic partial cross-sectional view of the stacked portion of the charge storage electrode, the photoelectric conversion layer, and the second electrode in a modified example of Example 14, the thickness of the charge storage electrode sections 14 1 , 14 2 and 14 3 can be constant, and the thickness of the insulating layer sections 82 1 , 82 2 and 82 3 can gradually decrease so that the thickness of the photoelectric conversion layer sections 13 1 , 13 2 and 13 3 gradually increases.

[0605] Obviously, the above various modified examples can also be applied to examples other than Example 1.

[0606] Although electrons are signal charges and the conductivity type of the photoelectric conversion layer formed on the semiconductor substrate in the example is n-type, the example can also be applied to a solid-state imaging device in which holes are signal charges. In this case, each semiconductor region can be a semiconductor region of the opposite conductivity type, and the conductivity type of the photoelectric conversion layer formed on the semiconductor substrate can be p-type.

[0607] In addition, in the above example, the example is applied to a CMOS solid-state imaging device, in which unit pixels for detecting signal charges as physical quantities according to the incident light amount are arranged in a matrix. However, the example is not limited to being applied to a CMOS solid-state imaging device, and the example can also be applied to a CCD solid-state imaging device. In the latter case, the vertical transfer register of the CCD structure transfers signal charges in the vertical direction, and the horizontal transfer register transfers signal charges in the horizontal direction. The charges are amplified and pixel signals (image signals) are output. In addition, the example is not limited to a general column-type solid-state imaging device in which pixels are formed in a two-dimensional matrix and a column signal processing circuit is provided for each pixel column. In addition, depending on the specific situation, the selection transistor may not be included.

[0608] In addition, the imaging element and the stacked imaging element of the present disclosure are not limited to solid-state imaging devices that detect the distribution of the incident light amount of visible light to obtain an image of the distribution. The imaging element and the stacked imaging element can also be applied to solid-state imaging devices that capture images of the distribution of the incident amounts of infrared rays, X-rays, particles, etc. In addition, in a broad sense, the imaging element and the stacked imaging element can generally be applied to solid-state imaging devices (physical quantity distribution detection devices) such as fingerprint detection sensors, which detect the distribution of other physical quantities (such as pressure and capacitance) to obtain an image of the distribution.

[0609] In addition, the imaging element and the stacked imaging element are not limited to solid-state imaging devices that sequentially scan the unit pixels of the imaging area line by line to read pixel signals from the unit pixels. The imaging element and the stacked imaging element can also be applied to X-Y address type solid-state imaging devices, which select arbitrary pixels one by one and read pixel signals one by one from the selected pixels. The solid-state imaging device can be formed as a single chip, or can be in the form of a module having an imaging function, in which the imaging area and the drive circuit or optical system are encapsulated together.

[0610] In addition, the imaging element and the stacked imaging element are not limited to being applied to solid-state imaging devices, and the imaging element and the stacked imaging element can also be applied to imaging devices. Here, the imaging device represents a camera system, such as a digital camera and a video camera, or an electronic device having an imaging function such as a mobile phone. In some cases, the imaging device is in the form of a module mounted on an electronic device, that is, a camera module.

[0611] Figure 99A and 99B An equivalent circuit diagram illustrating a modified example of a transistor that drives a charge storage electrode is shown. Figure 100A and 100B Schematically illustrates for driving in Figure 99A and 99B the pulse waveforms of the transistors in the equivalent circuit shown in. Figure 100A and Figure 100B The horizontal axis of represents time, and the vertical axis represents the potential of the charge storage electrode 14. A transistor generally applies a potential to the charge storage electrode 14. Note that the operation of the transistor that applies a potential to the charge storage electrode 14 will be expressed as "the charge storage electrode 14 is driven by the transistor". On the other hand, in Figure 99A and 100AIn the example shown, two transistors (FET-1, FET-2) drive the charge storage electrode 14. Further, at the initial stage during charge transfer, the charge storage electrode 14 is driven by one transistor (FET-1), and at the later stage during charge transfer, the charge storage electrode 14 is driven by two transistors (FET-1, FET-2) simultaneously. Note that the reference numeral "FET-0" denotes a transistor for control. In Figure 99B and Figure 100B In the example shown, the charge storage electrode 14 is driven by a transistor (FET-5) with a large driving ability and a transistor (FET-3) with a small driving ability. Specifically, at the initial stage during charge transfer, the charge storage electrode 14 is driven by the transistor (FET-3) with a small driving ability, and at the later stage during charge transfer, the charge storage electrode 14 is driven by the transistor (FET-5) with a large driving ability. Note that the reference numeral "FET-4" denotes a MOS diode. The magnitude of the driving ability of a transistor is defined by, for example, the channel width of the transistor. Based on the configuration, when there is a large amount of charge to be transferred, the charge storage electrode 14 can be driven by one transistor or by a transistor with a small driving ability. This can suppress the occurrence of blooming. When the occurrence of blooming is no longer a concern, the charge storage electrode 14 can be driven by two transistors or by a transistor with a large driving ability (or by a transistor with a large driving ability and a transistor with a small driving ability). This can increase the charge transfer speed (reduce the charge transfer time).

[0612] Figure 101A conceptual diagram showing an example of using a solid-state imaging device 201 including the imaging element and the stacked imaging element of the present disclosure in an electronic device (camera) 200. The electronic device 200 includes a solid-state imaging device 201, an optical lens 210, a shutter device 211, a driving circuit 212, and a signal processing circuit 213. The optical lens 210 forms an image of image light (incident light) from an object on the imaging surface of the solid-state imaging device 201. Accordingly, signal charges are stored in the solid-state imaging device 201 for a certain period of time. The shutter device 211 controls the light exposure period and the light shielding period of the solid-state imaging device 201. The driving circuit 212 provides driving signals for controlling the transfer operation and the like of the solid-state imaging device 201 and the shutter operation of the shutter device 211. Signals of the solid-state imaging device 201 are transferred based on the driving signals (timing signals) provided from the driving circuit 212. The signal processing circuit 213 performs various types of signal processing. The video signal after signal processing is stored in a storage medium such as a memory or output to a monitor. In the electronic device 200, the pixel size in the solid-state imaging device 201 can be miniaturized, and the transfer efficiency can be improved. Accordingly, the pixel characteristics in the electronic device 200 can be improved. The electronic device 200 to which the solid-state imaging device 201 can be applied is not limited to a camera. The solid-state imaging device 201 can be applied to a digital camera, a camera module for a mobile device (e.g., a mobile phone), and other imaging devices.

[0613] Note that the present disclosure can also be configured as follows.

[0614] [A01] <<Imaging element: First aspect>>

[0615] An imaging element, comprising:

[0616] A photoelectric conversion unit including a stacked first electrode, a photoelectric conversion layer, and a second electrode, wherein

[0617] The photoelectric conversion unit further includes a charge storage electrode which is arranged separately from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer, and

[0618] When light undergoes photoelectric conversion in the photoelectric conversion layer after entering the photoelectric conversion layer, the absolute value of the potential applied to a part of the photoelectric conversion layer facing the charge storage electrode is greater than the absolute value of the potential applied to the region of the photoelectric conversion layer located between the imaging element and the adjacent imaging element.

[0619] [A02] <<Imaging element: Second aspect>>

[0620] An imaging element, comprising:

[0621] A photoelectric conversion unit including a stacked first electrode, a photoelectric conversion layer, and a second electrode, wherein

[0622] The photoelectric conversion unit further includes a charge storage electrode, which is disposed separately from the first electrode and is disposed to face the photoelectric conversion layer via an insulating layer, and

[0623] the width of the region of the photoelectric conversion layer between the first electrode and the charge storage electrode is narrower than the width of the region of the photoelectric conversion layer between the imaging element and the adjacent imaging element.

[0624] [A03] <<Imaging element: Third aspect>>

[0625] An imaging element, comprising:

[0626] a photoelectric conversion unit including a stacked first electrode, a photoelectric conversion layer, and a second electrode, wherein

[0627] the photoelectric conversion unit further includes a charge storage electrode, which is disposed separately from the first electrode and is disposed to face the photoelectric conversion layer via an insulating layer, and

[0628] a charge movement control electrode is formed in a region that faces, via an insulating layer, the region of the photoelectric conversion layer between the imaging element and the adjacent imaging element.

[0629] [A04] <<Imaging element: Fourth aspect>>

[0630] An imaging element, comprising:

[0631] a photoelectric conversion unit including a stacked first electrode, a photoelectric conversion layer, and a second electrode, wherein

[0632] the photoelectric conversion unit further includes a charge storage electrode, which is disposed separately from the first electrode and is disposed to face the photoelectric conversion layer via an insulating layer, and

[0633] As an alternative to the second electrode, a charge movement control electrode is formed in the region of the photoelectric conversion layer between the imaging element and the adjacent imaging element.

[0634] [A05] <<Imaging element: Fifth aspect>>

[0635] An imaging element, comprising:

[0636] a photoelectric conversion unit including a stacked first electrode, a photoelectric conversion layer, and a second electrode, wherein

[0637] the photoelectric conversion unit further includes a charge storage electrode, which is disposed separately from the first electrode and is disposed to face the photoelectric conversion layer via an insulating layer, and

[0638] The value of the dielectric constant of the insulating material contained in the region between the first electrode and the charge storage electrode is higher than the value of the dielectric constant of the insulating material contained in the region between the imaging element and the adjacent imaging element.

[0639] [A06] <<Imaging element: Sixth aspect>>

[0640] An imaging element, comprising:

[0641] A photoelectric conversion unit, including a stacked first electrode, a photoelectric conversion layer, and a second electrode, wherein

[0642] The photoelectric conversion unit further includes a charge storage electrode, which is arranged separately from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer, and

[0643] The thickness of the region of the insulating layer between the first electrode and the charge storage electrode is thinner than the thickness of the region of the insulating layer between the imaging element and the adjacent imaging element.

[0644] [A07] <<Imaging element: Seventh aspect>>

[0645] An imaging element, comprising:

[0646] A photoelectric conversion unit, including a stacked first electrode, a photoelectric conversion layer, and a second electrode, wherein

[0647] The photoelectric conversion unit further includes a charge storage electrode, which is arranged separately from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer, and

[0648] The thickness of the region of the photoelectric conversion layer between the first electrode and the charge storage electrode is thicker than the thickness of the region of the photoelectric conversion layer between the imaging element and the adjacent imaging element.

[0649] [A08] <<Imaging element: Eighth aspect>>

[0650] An imaging element includes:

[0651] A photoelectric conversion unit, including a stacked first electrode, a photoelectric conversion layer, and a second electrode, wherein

[0652] The photoelectric conversion unit further includes a charge storage electrode, which is arranged separately from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer, and

[0653] The amount of fixed charge in the region of the interface between the photoelectric conversion layer and the insulating layer between the first electrode and the charge storage electrode is less than the amount of fixed charge in the region of the interface between the photoelectric conversion layer and the insulating layer between the imaging element and the adjacent imaging element.

[0654] [A09]<<Imaging Element: Ninth Aspect>>

[0655] An imaging element includes:

[0656] A photoelectric conversion unit including a stacked first electrode, a photoelectric conversion layer, and a second electrode, wherein

[0657] The photoelectric conversion unit further includes a charge storage electrode that is disposed separately from the first electrode and is disposed to face the photoelectric conversion layer via an insulating layer, and

[0658] The value of the charge mobility in the region of the photoelectric conversion layer between the first electrode and the charge storage electrode is greater than the value of the charge mobility in the region of the photoelectric conversion layer between the imaging element and an adjacent imaging element.

[0659] [A10]

[0660] The imaging element according to [A03] further includes:

[0661] A control unit disposed on a semiconductor substrate and including a drive circuit, wherein

[0662] The first electrode, the second electrode, the charge storage electrode, and the charge movement control electrode are connected to the drive circuit,

[0663] During charge storage, the drive circuit applies a potential V 11 to the first electrode, applies a potential V 12 to the charge storage electrode, and applies a potential V 13 to the charge movement control electrode, and charges are stored in the photoelectric conversion layer, and

[0664] During charge transfer, the drive circuit applies a potential V 21 to the first electrode, applies a potential V 22 to the charge storage electrode, and applies a potential V 23 to the charge movement control electrode, and the charges stored in the photoelectric conversion layer are read out to the control unit through the first electrode, wherein

[0665] When the potential of the first electrode is higher than the potential of the second electrode

[0666] maintain V 12 ≥V 11 、V 12 >V 13 and V 21 >V 22 >V 23 , and

[0667] When the potential of the first electrode is lower than the potential of the second electrode

[0668] Maintain V 12 ≤V 11 、V 12 <V 13 and V 21 <V 22 <V 23 。

[0669] [A11]

[0670] The imaging element according to [A04] further includes:

[0671] A control unit disposed on a semiconductor substrate and including a driving circuit, wherein

[0672] A first electrode, a second electrode, a charge storage electrode, and a charge movement control electrode are connected to the driving circuit,

[0673] During charge storage, the driving circuit applies a potential V 2 ' to the second electrode and applies a potential V 13 ' to the charge movement control electrode, and charges are stored in the photoelectric conversion layer, and

[0674] During charge transfer, the driving circuit applies a potential V 2 ” to the second electrode and applies a potential V 23 ” to the charge movement control ...

Claims

1. An imaging element, wherein it comprises: a photoelectric conversion unit, the photoelectric conversion unit including a stacked first electrode, a photoelectric conversion layer, and a second electrode, wherein, the photoelectric conversion unit further includes a charge storage electrode, the charge storage electrode being arranged to be separated from the first electrode and arranged to face the photoelectric conversion layer via an insulating layer, and the value of the dielectric constant of the insulating material included in the region between the first electrode and the charge storage electrode is higher than the value of the dielectric constant of the insulating material included in the region between the imaging element and an adjacent imaging element.

2. The imaging element according to claim 1, further comprising: a semiconductor substrate, wherein the photoelectric conversion unit is provided on the upper side of the semiconductor substrate.

3. The imaging element according to claim 1, further comprising: a transfer control electrode, the transfer control electrode being arranged between the first electrode and the charge storage electrode, arranged separately from the first electrode and the charge storage electrode, and arranged to face the photoelectric conversion layer via the insulating layer.

4. The imaging element according to claim 1, wherein the charge storage electrode includes a plurality of charge storage electrode segments.

5. The imaging element according to claim 1, wherein the size of the charge storage electrode is larger than that of the first electrode.

6. A stacked imaging element, comprising at least one imaging element according to any one of claims 1 to 5.

7. A solid-state imaging device, comprising a plurality of imaging elements according to any one of claims 1 to 5.

8. A solid-state imaging device, comprising a plurality of stacked imaging elements according to claim 6.

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