Semiconductor device

Abstract

A semiconductor device includes a substrate, a first gallium nitride type high electron mobility transistor, a second gallium nitride type high electron mobility transistor, a first inner connector, and a second inner connector. The substrate includes a first type doped semiconductor region and a second type doped semiconductor region. The first gallium nitride type high electron mobility transistor covers a first region on the first type doped semiconductor region and the second type doped semiconductor region. The second gallium nitride type high electron mobility transistor covers a second region on the first type doped semiconductor region and the second type doped semiconductor region. The first region and the second region are separated from each other. The first inner connector connects the first region, and a width of the first inner connector is greater than a source-drain pitch of the first gallium nitride type high electron mobility transistor. The second inner connector connects the second region, and a width of the second inner connector is greater than a source-drain pitch of the second gallium nitride type high electron mobility transistor.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202080003405.4, entitled "Semiconductor Device and Method of Manufacturing Semiconductor Device", filed on October 20, 2020. Technical Field

[0002] This invention generally relates to semiconductor devices. More specifically, this invention relates to semiconductor devices with high electron mobility transistors having a doped substrate to achieve good voltage distribution. Background Technology

[0003] In recent years, in-depth research on high electron mobility transistors (HEMTs) has become increasingly prevalent in semiconductor devices, such as high-power switches and high-frequency applications. HEMTs utilize heterojunctions between two materials with different band gaps to form a quantum well-like structure, which houses a two-dimensional electron gas (2DEG) region to meet the requirements of high-power / high-frequency devices. Besides HEMTs, other examples of devices with heterojunction structures include heterojunction bipolar transistors (HBTs), heterojunction field-effect transistors (HFETs), and modulation-doped field-effect transistors (MODFETs). Currently, there is a demand for increased production capacity of HEMTs to meet the requirements of mass production. Summary of the Invention

[0004] One aspect of this disclosure provides a semiconductor device characterized by comprising a substrate, a first gallium nitride high electron mobility transistor (GaN high electron mobility transistor), a second GaN high electron mobility transistor, a first internal connector, and a second internal connector. The substrate includes a plurality of first-type doped semiconductor regions and a plurality of second-type doped semiconductor regions extending along a first direction and alternately arranged along a second direction, wherein the first direction and the second direction are different. The first GaN high electron mobility transistor is disposed above the substrate and covers a first region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions. The second GaN high electron mobility transistor is disposed above the substrate and covers a second region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions, wherein the first region and the second region are spaced apart from each other. The first internal connector is disposed above the substrate and connects the first regions on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions, and the width of the first internal connector is greater than the source-drain spacing of the first GaN high electron mobility transistor. The second internal connector is disposed above the substrate and connects the second region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions, and the width of the second internal connector is greater than the source-drain spacing of the second gallium nitride high electron mobility transistor.

[0005] According to another aspect of this disclosure, a semiconductor device is provided, characterized in that it includes a substrate, a first gallium nitride high electron mobility transistor (GaN high electron mobility transistor), a second gallium nitride high electron mobility transistor (GaN high electron mobility transistor), a first internal connector, and a second internal connector. The substrate includes a plurality of first-type doped semiconductor regions and a plurality of second-type doped semiconductor regions, the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions extending along a first direction and alternately arranged along a second direction, wherein the first direction and the second direction are different. The first gallium nitride high electron mobility transistor is disposed above the substrate and covers a first region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions. The second gallium nitride high electron mobility transistor is disposed above the substrate and covers a second region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions, wherein the first region and the second region are arranged along the second direction. The first internal connector is disposed above the substrate and connects the first region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions, and the first internal connector and the first gallium nitride high electron mobility transistor are arranged along the first direction. The second internal connector is disposed above the substrate and connects the second region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions, and the second internal connector and the second gallium nitride high electron mobility transistor are arranged along the first direction.

[0006] By applying the above configuration, the voltage and current of the semiconductor device can be improved due to the alternating arrangement of first-type and second-type doped semiconductor regions on the substrate. In the semiconductor device, the voltage and current of the second gallium nitride high-electron-mobility transistor can be protected from the influence of the first gallium nitride high-electron-mobility transistor. In other words, when there is a voltage change in the substrate below the second gate electrode, the voltage change in the substrate below the first gate electrode can be reduced. Simultaneously, the first internal connector and the second internal connector can be protected from mutual interference, and each can control the substrate voltage via the first interface and the second interface. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, various aspects of this disclosure can be readily understood from the following detailed description. It should be noted that the features are not drawn to scale. In fact, for ease of explanation, the dimensions of various features can be arbitrarily increased or decreased.

[0008] The accompanying drawings, which are referred to below, provide a more detailed description of embodiments of the present invention, wherein:

[0009] Figure 1 A top view illustrating some embodiments according to this disclosure;

[0010] Figure 2 Draw along Figure 1 A sectional view of the section symbol I1;

[0011] Figure 3 Draw along Figure 1 A sectional view of the section symbol I2;

[0012] Figure 4 Cross-sectional views illustrating some embodiments according to this disclosure;

[0013] Figures 5 to 11 A cross-sectional view of a semiconductor device in a manufacturing method according to some embodiments of this disclosure;

[0014] Figure 12 A top view illustrating some embodiments according to this disclosure;

[0015] Figure 13 A top view illustrating some embodiments according to this disclosure;

[0016] Figure 14 A top view illustrating some embodiments according to this disclosure;

[0017] Figure 15 A top view illustrating some embodiments according to this disclosure;

[0018] Figure 16 A top view illustrating some embodiments according to this disclosure;

[0019] Figure 17 A top view illustrating some embodiments according to this disclosure;

[0020] Figure 18 A top view illustrating some embodiments according to this disclosure;

[0021] Figure 19 A top view illustrating some embodiments according to this disclosure;

[0022] Figure 20 A top view illustrating some embodiments according to this disclosure;

[0023] Figure 21 A top view illustrating some embodiments according to this disclosure;

[0024] Figure 22 Top view illustrating some embodiments according to this disclosure; and

[0025] Figure 23 A top view illustrating some embodiments according to this disclosure. Detailed Implementation

[0026] Throughout the accompanying drawings and detailed description, the same reference numerals will be used to denote the same or similar parts. The embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0027] In spatial descriptions, terms such as "up," "down," "above," "left," "right," "below," "top," "bottom," "vertical," "horizontal," "one side," "higher," "lower," "above," "above," and "below" are defined for a specific plane of a component or a group of components. The orientation of a component can be shown in its corresponding diagram. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and the structures described herein can be arranged in space in any orientation or manner in practice, provided that the advantages of the embodiments disclosed herein are not deviated from by such arrangement.

[0028] In the following description, semiconductor devices and methods of manufacturing thereof are listed as preferred examples. Those skilled in the art will understand that modifications, including additions and / or substitutions, can be made without departing from the scope and spirit of the invention. Specific details may be omitted to avoid obscuring the invention; however, this disclosure is intended to enable those skilled in the art to implement the teachings herein without undue experimentation.

[0029] Figure 1 This is a top view illustrating a semiconductor device 100A according to some embodiments of the present disclosure. To clearly illustrate the features of the present disclosure, some components and material layers of the semiconductor device 100A are omitted in the drawing. In this embodiment, the semiconductor device 100A includes a substrate 110A, gallium nitride high electron mobility transistors 120A and 130A, an internal connector 140A, and an internal connector 150A.

[0030] The substrate 110A has a plurality of first-type doped semiconductor regions 111A and a plurality of second-type doped semiconductor regions 112A. These first-type doped semiconductor regions 111A and second-type doped semiconductor regions 112A extend longitudinally along a first direction d1. These first-type doped semiconductor regions 111A and second-type doped semiconductor regions 112A are arranged alternately along a second direction d2. The second direction d2 is different from the first direction d1. For example, in this embodiment, the first direction d1 and the second direction d2 are perpendicular to each other.

[0031] In semiconductor device 100A, gallium nitride high electron mobility transistors 120A and 130A are disposed above substrate 110A. In one aspect, gallium nitride high electron mobility transistor 120A covers region 101A on the first type-doped semiconductor regions 111A and the second type-doped semiconductor regions 112A in substrate 110A. Gallium nitride high electron mobility transistor 130A covers region 102A on the first type-doped semiconductor regions 111A and the second type-doped semiconductor regions 112A in substrate 110A. Regions 101A and 102A are different. Spacing g1 is located between regions 101A and 102A in a second direction d2.

[0032] In this embodiment, the first-type doped semiconductor regions 111A and the second-type doped semiconductor regions 112A form a plurality of interfaces 113A. The interval g1 between regions 101A and 102A spans at least two interfaces 113A. For example, in this embodiment, the interval g1 spans four interfaces 113A.

[0033] Figure 2 It is based on Figure 1 The diagram shows a side cross-sectional view of the semiconductor device 100A, as indicated by cut line I1. The gallium nitride high electron mobility transistor 120A of this embodiment has a heterojunction region 125A between two nitride semiconductor layers 103A and 104A. The gallium nitride high electron mobility transistor 120A has a two-dimensional electron gas region 126A adjacent to the heterojunction region 125A. In other words, the heterojunction region 125A is a heterojunction located in region 101A between the two nitride semiconductor layers 103A and 104A.

[0034] The gallium nitride high electron mobility transistor 130A has a heterojunction region 135A between two nitride semiconductor layers 103A and 104A. The gallium nitride high electron mobility transistor 130A has a two-dimensional electron gas region 136A adjacent to the heterojunction region 135A. The heterojunction region 135A is a heterojunction located in region 102A between the two nitride semiconductor layers 103A and 104A.

[0035] In this embodiment, a nitride semiconductor layer 104A is disposed on a nitride semiconductor layer 103A. The band gap of the nitride semiconductor layer 104A is larger than that of the nitride semiconductor layer 103A. Therefore, a two-dimensional electron gas region 126A and a two-dimensional electron gas region 136A are respectively formed in regions 101A and 102A.

[0036] In this embodiment, the four interfaces 113A are located between regions 101A and 102A. Therefore, on the substrate 110A, the voltage of region 101A is not affected by the voltage change of region 102A.

[0037] Furthermore, a pair of source / drain electrodes 121A and 122A are disposed on the nitride semiconductor layer 104A. A gate electrode 123A is disposed on the nitride semiconductor layer 104A. The gate electrode 123A is disposed between these source / drain electrodes 121A and 122A. A pair of source / drain electrodes 131A and 132A are disposed on the nitride semiconductor layer 104A. A gate electrode 133A is disposed on the nitride semiconductor layer 104A. The gate electrode 133A is disposed between these source / drain electrodes 131A and 132A. These source / drain electrodes 121A and 122A, and the gate electrode 123A, are located in region 101A. These source / drain electrodes 131A, 132A and gate electrode 133A are located in region 102A. When the voltage of substrate 110A in region 102A is changed by the source / drain electrodes 131A, 132A and gate electrode 133A, the voltage of substrate 110A in region 101A is not affected.

[0038] For example, each source / drain electrode 121A, 122A, 131A, 132A includes one or more common conductive layers. In some embodiments, these source / drain electrodes 121A, 122A, 131A, 132A may comprise, for example, metals, alloys, doped semiconductor materials (such as doped crystalline silicon), other conductive materials, or combinations thereof, but this disclosure is not limited thereto. For example, the materials of the source / drain electrodes 121A, 122A, 131A, 132A may comprise, for example, titanium (Ti), aluminum-silicon alloy (AlSi), titanium nitride (TiN), or combinations thereof, but this disclosure is not limited thereto. In some disclosed embodiments, these source / drain electrodes 121A, 122A, 131A, 132A each form an ohmic contact with the nitride semiconductor layer 104. These source / drain electrodes 121A, 122A, 131A, 132A can achieve these ohmic contacts using titanium (Ti), aluminum (Al), or other suitable materials. In some embodiments, a dielectric layer such as silicon nitride (SiN) (not shown) can be disposed between the nitride semiconductor layer 104 and these source / drain electrodes 121A, 122A, 131A, 132A.

[0039] Reference Figure 1Internal connector 140A is disposed above substrate 110A. Internal connector 150A is disposed above substrate 110A. Depending on one aspect, internal connector 140A and region 101A may have the same length in the second direction d2. Internal connector 150A and region 102A may also have the same length in the second direction d2. Depending on the application of the device, these lengths may also be chosen to be different from each other.

[0040] Figure 3 It is based on Figure 1 A side cross-sectional view illustrated by section symbol I2. An internal connector 140A is disposed above a substrate 110A. A portion of a first-type doped semiconductor region 111A and a second-type doped semiconductor region 112A are located below the internal connector 140A. The internal connector 140A passes through two nitride semiconductor layers 103A and 104A. The internal connector 140A is electrically connected to the substrate 110A. A portion of region 101A and the internal connector 140A form an interface 141A. In other words, the internal connector 140A is connected to the substrate 110A through interface 141A.

[0041] An internal connector 150A is disposed above a substrate 110A. Some type-1 doped semiconductor regions 111A and type-2 doped semiconductor regions 112A are located below the internal connector 150A. The internal connector 150A also passes through two nitride semiconductor layers 103A and 104A. The internal connector 150A is electrically connected to the substrate 110A. A portion of region 102A and the internal connector 150A form an interface 151A. In other words, the internal connector 150A is connected to the substrate 110A through interface 151A.

[0042] Therefore, the voltage of substrate 110A in regions 101A and 102A can be independently controlled by internal connectors 140A and 150A, respectively. By providing an electrical signal to internal connector 140A, the voltage of substrate 110A in region 101A can be maintained within a selected range. By providing an electrical signal to internal connector 150A, the voltage of substrate 110A in region 102A can be maintained within a selected range. These voltages can be the same or different from each other.

[0043] Conversely, when two gallium nitride (GaN) high electron mobility transistors (HEMTs) are disposed on a substrate lacking the aforementioned type-1 and type-2 doped semiconductor regions, it becomes difficult to operate these GaNHs individually. Substrate effects occur even without these doped semiconductor regions, causing the two GaNHs to interfere with each other. These substrate effects refer to the sharing of substrate voltages between the two GaNHs. Therefore, it becomes very difficult to operate these two GaNHs individually.

[0044] like Figure 3 As shown, at least two interfaces 113A separate interfaces 141A and 151A. A portion of the nitride semiconductor layer 103A, projected vertically onto the substrate 110A, lies between interfaces 141A and 151A. This portion of the nitride semiconductor layer 103A spans at least two complete doped semiconductor regions 111A and 112A. For example, four interfaces 113A separate interfaces 141A and 151A. This portion of the nitride semiconductor layer 103A spans two complete first-type doped semiconductor regions 111A and one complete second-type doped semiconductor region 112A between interfaces 141A and 151A. The voltage of the substrate 110A in region 101A is not affected by the voltage in region 102A.

[0045] The first type-doped semiconductor region 111A may include a P-type dopant in one aspect. The second type-doped semiconductor region 112A may include an N-type dopant in one aspect. These interfaces 113A include at least two PN junctions. These interfaces 113A may also include PNP structures. In other words, the PNP structure between region 101A and region 102A forms two PN junctions. For example, in the semiconductor device 100A of this embodiment, there are four PN junctions between region 101A and region 102A. In other words, the spacing g1 spans four PN junctions 113A. A portion of the nitride semiconductor layer 103A's vertical projection onto the substrate 110B spans one PNP structure.

[0046] For example, the P-type dopant described above may include beryllium (Be), magnesium (Mg), zinc (Zn), or cadmium (Cd), but this disclosure is not limited to these. The N-type dopant described above may include silicon (Si), but this disclosure is not limited to these.

[0047] Reference Figure 1 A pair of source / drain electrodes 121A and 122A have a source-drain spacing g2 and are arranged along a second direction d2. Interface 141A has a length L1 in the second direction d2 that is longer than the source-drain spacing g2. A pair of source / drain electrodes 131A and 132A have a source-drain spacing g3 and are arranged along the second direction d2. Interface 151A may optionally have a length L2 in the second direction d2 that is longer than the source-drain spacing g3. Depending on the application of the device, these spacings may also have the same length in other configurations.

[0048] In the above configuration, the internal connector 140A can control the voltage under the source / drain electrodes 121A and 122A. The internal connector 150A can control the voltage under the source / drain electrodes 131A and 132A.

[0049] Furthermore, the shortest distance (i.e., the interval g1) from the inner connector 140A to the inner connector 150A can be shorter than the shortest distance L3 from the source / drain electrodes 121A, 122A to the source / drain electrodes 131A, 132A.

[0050] Reference Figure 2 In this embodiment, the substrate 110A includes a base layer 115A and a dielectric layer 114A. The base layer 115A may be made of silicon. Alternatively, the base layer may be germanium, silicon carbide, sapphire, or other known substrate materials. The dielectric layer 114A is disposed on the base layer 115A and may be silicon dioxide, silicon nitride, a mixture thereof, other known nitrides, oxides, or dielectrics. Type-1 doped semiconductor regions 111A and Type-2 doped semiconductor regions 112A are disposed on the dielectric layer 114A. The dielectric layer 114A can block current between the base layer 115A, the Type-1 doped semiconductor regions 111A, and the Type-2 doped semiconductor regions 112A. For example, the dielectric layer 114A may be formed from a single dielectric material layer or multiple dielectric material layers. The dielectric material may include, for example, one or more oxide layers, silicon oxide (SiO2), etc. x ) layer, silicon nitride (SiN) x The material layer may be a layer with a high dielectric constant (such as hafnium oxide (HfO2), aluminum oxide (Al2O3), titanium dioxide (TiO2), zirconium hafnium oxide (HfZrO), tantalum trioxide (Ta2O3), silicon hafnium oxide (HfSiO4), zirconium dioxide (ZrO2), silicon zirconium oxide (ZrSiO2), etc.) or a combination thereof.

[0051] In some embodiments, a nucleation layer may be disposed on the dielectric layer 114A. The first-type doped semiconductor regions 111A and the second-type doped semiconductor regions 112A may be formed on the nucleation layer. In some embodiments, a buffer layer may be disposed on the first-type doped semiconductor regions 111A and the second-type doped semiconductor regions 112A. A nitride semiconductor layer 103A may be formed on the buffer layer.

[0052] The materials of these first-type doped semiconductor regions 111A and second-type doped semiconductor regions 112A include gallium nitride (GaN). In some embodiments, these first-type doped semiconductor regions 111A and second-type doped semiconductor regions 112A may comprise nitrides or group III-V compounds, such as gallium nitride (GaN), gallium arsenide (GaAs), indium nitride (InN), aluminum nitride (AlN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (InAlGaN), or combinations thereof.

[0053] The material of the nitride semiconductor layer 103A may include gallium nitride. The material of the nitride semiconductor layer 104A may include aluminum gallium nitride. The band gap of the nitride semiconductor layer 104A is larger than that of the nitride semiconductor layer 103A, thus allowing the formation of two-dimensional electron gas regions 126A and 136A. In some embodiments, these nitride semiconductor layers 103A and 104A may, for example, include nitrides or group III-V compounds, such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and aluminum indium gallium nitride (In). x Al y Ga (1-x-y) N, where x+y≤1), aluminum gallium nitride (Al) y Ga (1-y) N, where y≤1), wherein the band gap of the nitride semiconductor layer 104A is greater than that of the nitride semiconductor layer 103A, thereby forming a two-dimensional electron gas. Alternatively, other devices can also use other binary, ternary, or quaternary group III-V semiconductor compound materials with band gap differences to form heterojunctions and two-dimensional electron gas regions respectively.

[0054] Semiconductor device 100A also includes a passivation layer 180A and multiple connection pads 161A, 162A, 163A, 171A, 172A, and 173A. Connection pads 161A and 162A pass through the passivation layer 180 in region 101A and are electrically connected to source / drain electrodes 121A and 122A, respectively. Connection pad 163A passes through the passivation layer 180 in region 101A and is electrically connected to gate electrode 120A. Connection pads 171A and 172A pass through the passivation layer 180 in region 102A and are electrically connected to source / drain electrodes 131A and 132A, respectively. Connection pad 173A passes through the passivation layer 180 in region 102A and is electrically connected to gate electrode 133A.

[0055] For protection purposes, passivation layer 180A covers source / drain electrodes 121A, 122A, 131A, 132A and gate electrodes 123A, 133A. The material of passivation layer 180A may include, for example, silicon nitride (SiN). x ), silicon dioxide (SiO)x The passivation layer 180A comprises silicon oxynitride (SiON), silicon carbide (SiC), silicon boron nitride (SiBN), silicon boron carbonitride (SiCBN), oxides, nitrides, or combinations thereof. In some embodiments, the passivation layer 180A is a multilayer structure, such as a composite dielectric layer of aluminum oxide / silicon nitride (Al2O3 / SiN), aluminum oxide / silicon oxide (Al2O3 / SiO2), aluminum nitride / silicon nitride (AlN / SiN), aluminum nitride / silicon oxide (AlN / SiO2), or combinations thereof, but this disclosure is not limited thereto.

[0056] Semiconductor device 100A includes a first-type doped gate layer 124A and a first-type doped gate layer 134A. The first-type doped gate layer 124A is disposed between a gate electrode 123A and a nitride semiconductor layer 104A. The first-type doped gate layer 134A is disposed between a gate electrode 133A and a nitride semiconductor layer 104A. For example, these first-type doped gate layers 124A and 134A are doped with a P-type dopant. Therefore, gallium nitride high electron mobility transistor 120A and gallium nitride high electron mobility transistor 130A can operate in a normally off state, generally referred to as enhancement-mode. P-type dopant may include, for example, beryllium (Be), magnesium (Mg), zinc (Zn), and cadmium (Cd), but this disclosure is not limited to these.

[0057] In some embodiments, the first-type doped gate layers 124A and 134A may be omitted from the semiconductor device. Therefore, the semiconductor devices in these embodiments can operate in a normally-on state, generally referred to as depletion-mode. Alternatively, one device may be configured with a doped layer and operate as an enhancement-mode device, while the other operates as a depletion-mode device.

[0058] Reference Figure 3 Semiconductor device 100A includes connection pads 191A and 192A. Connection pad 191A passes through passivation layer 180A and is electrically connected to inner connector 140A. Connection pad 192A passes through passivation layer 180A and is electrically connected to inner connector 150A. In some embodiments, these connection pads 191A and 192A may each include a via and a metal wire. The via may pass through passivation layer 180A and be electrically connected to inner connector 140A. The metal wire is disposed on passivation layer 180A and contacts the via. The via and the metal wire may include metal or metal compound. The metal or metal compound may include, for example, tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), alloys formed from the above materials, or other metal compounds.

[0059] Internal connector 140A extends along the sidewalls of nitrogen-type semiconductor layers 103A and 104A and passes through nitride semiconductor layers 103A and 104A. The bottommost portion 142A of internal connector 140A forms interface 141A. The bottommost portion 152A of internal connector 150A forms interface 151A. These internal connectors 140A and 150A can each be electrically connected to external connection pads through these connection pads 191A and 192A. For example, these connection pads 191A and 192A can be electrically connected to power supplies of different voltages.

[0060] Figure 4 This is a side cross-sectional view illustrating a semiconductor device according to some embodiments of this disclosure. In some embodiments, the internal connectors 140A, 150A may pass through the passivation layer 180A, the nitride semiconductor layer 104A, and the nitride semiconductor layer 103A. In some embodiments, a portion of the internal connectors 140A, 150A may be located above the passivation layer 180A.

[0061] Figures 5 to 11 This is a cross-sectional view of the semiconductor device 100B in a manufacturing method according to some embodiments of this disclosure. (Refer to...) Figure 5 The fabrication method of this embodiment includes providing an undoped substrate 1101B. The undoped substrate 110B has a base layer 115B, a dielectric layer 114B, and an undoped layer 116B. The dielectric layer 114B is disposed on the base layer 115B. The undoped layer 116B is disposed on the dielectric layer 114B. In some embodiments of this disclosure, a nucleation layer is disposed on the dielectric layer. The undoped layer 116B is disposed on the nucleation layer. In some embodiments, the undoped layer 116B comprises a nitride or a III-V compound. In some embodiments, the undoped layer 116B may, for example, comprise gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), or aluminum indium gallium nitride (In). x Al y Ga (1-x-y) N, where x+y≤1), aluminum gallium nitride (Al) y Ga (1-y) N, where y≤1). For example, the undoped layer 116B is an undoped gallium nitride layer. In some embodiments, the formation of the undoped layer 116B may include forming a buffer layer to reduce differences in thermal conductivity or lattice number.

[0062] Reference Figure 6The fabrication method of this embodiment includes forming a plurality of first-type doped semiconductor regions 111B and a plurality of second-type doped semiconductor regions 112B having a plurality of interfaces 113B in a substrate 110B. In some embodiments, the formation of these first-type doped semiconductor regions 111B and second-type doped semiconductor regions 112B is achieved through at least one doping process. On one hand, an initial undoped layer 116B may be doped with a first-type dopant to these first-type doped semiconductor regions 111B and then with a second-type dopant, and vice versa. These first-type doped semiconductor regions 111B and these second-type doped semiconductor regions 112B are arranged alternately along a second direction d2. The interfaces 113B are formed between these first-type doped semiconductor regions 111B and second-type doped semiconductor regions 112B. For example, these first-type doped semiconductor regions 111B may be formed by doping with a P-type dopant. These second-type doped semiconductor regions 112B may be formed by doping with an N-type dopant.

[0063] Reference Figure 7 The fabrication method of this embodiment includes forming a nitride semiconductor layer 103B over a substrate 111B; and forming a nitride semiconductor layer 104B on the nitride semiconductor layer 103B. The band gap of the nitride semiconductor layer 104B is larger than that of the nitride semiconductor layer 103B.

[0064] For example, the material of the nitride semiconductor layer 103B may include gallium nitride. The material of the nitride semiconductor layer 104B may include aluminum gallium nitride. A heterojunction is formed between the nitride semiconductor layers 103B and 104B, and a two-dimensional electron gas is formed. In some embodiments, the fabrication method may also form a nucleation layer or a buffer layer before forming the nitride semiconductor layer 103B to reduce differences in thermal conductivity or lattice number. The material of the nucleation layer or buffer layer may be selected based on the properties of the substrate 110B and the nitride semiconductor layer 103B.

[0065] The fabrication method of this embodiment further includes forming a pair of source / drain electrodes 121B and 122B and a pair of source / drain electrodes 131B and 132B on the nitride semiconductor layer 104B; and forming a gate electrode 123B and a gate electrode 133B on the nitride semiconductor layer 104B. The gate electrode 123B is located between the source / drain electrodes 121B and 122B. The gate electrode 133B appears between the source / drain electrodes 131B and 132B.

[0066] Source / drain electrodes 121B and 122B, and gate electrode 123B are disposed on region 101B of substrate 110B. Heterojunction region 125B is a heterojunction located in region 101B. Two-dimensional electron gas region 126B is a two-dimensional electron gas in region 101B. Two-dimensional electron gas region 126B is adjacent to heterojunction region 125B.

[0067] Source / drain electrodes 131B and 132B, and gate electrode 133B are disposed on region 102B of substrate 110B. Heterojunction region 135B is a heterojunction located in region 102B. Two-dimensional electron gas region 136B is a two-dimensional electron gas in region 102B. Two-dimensional electron gas region 136B is adjacent to heterojunction region 135B.

[0068] Reference Figure 8 The fabrication method of this embodiment includes configuring a passivation layer 180B having a plurality of connection pads 161B, 162B, 163B, 171B, 172B, and 173B. These connection pads 161B, 162B, 163B, 171B, 172B, and 173B electrically connect source / drain electrodes 121B and 122B, gate electrode 123B, source / drain electrodes 131B and 132B, and gate electrode 133B. A high electron mobility transistor region of the semiconductor device 100B is thus formed.

[0069] Semiconductor device 100B includes a first-type doped gate layer 124B and a first-type doped gate layer 134B. The first-type doped gate layer 124B is disposed between a gate electrode 123B and a nitride semiconductor layer 104B. The first-type doped gate layer 134B is disposed between a gate electrode 133B and a nitride semiconductor layer 104B.

[0070] Reference Figure 9 On another portion of the substrate 110B, the fabrication method of this embodiment includes removing portions of the nitride semiconductor layer 103B and the nitride semiconductor layer 104B to form trenches 105B and 106B that are separated from each other, thereby exposing the top of the substrate 110B. In the second direction d2, trenches 105B and 106B are separated by two interfaces 103B of the substrate 110B.

[0071] Reference Figure 10 as well as Figure 11 The fabrication method of this embodiment includes forming internal connectors 140B and 150B in trenches 105B and 106B, respectively. These internal connectors 140B and 150B contact the top of the substrate 110B and each form an interface 141B and an interface 151B. The vertical projections of these interfaces 141B and 151B onto the substrate 110B are separated by at least two interfaces 113B.

[0072] Reference Figure 10 The steps of forming these internal connectors 140B and 150B include forming a conductive capping layer 107B over the nitride semiconductor layer 104B. A portion of the conductive capping layer 107B appears in these trenches 105B and 106B.

[0073] Reference Figure 11 The steps of forming these internal connectors 140B and 150B include patterning a conductive overlay layer 107B, thereby forming internal connectors 140B and 150B that are separated from each other. Furthermore, a passivation layer 180B having these connection pads 191B and 192B is disposed on these internal connectors 140B and 150B. Thus, an internal connection portion of the semiconductor device 100B is formed.

[0074] For example, refer to Figure 8 In this embodiment, the interfaces 113B of the substrate 110B are PN junctions. A portion of the vertical projection of the nitride semiconductor layer 103B onto the substrate 110B spans the two PN junctions (i.e., the interfaces 113B). Figure 12 This is a top view of a semiconductor device 100B according to an embodiment of the present disclosure. Regions 101B and 102B are separated by two PN junctions 113B. A gallium nitride high electron mobility transistor 120B and an internal connector 140B are disposed on region 101B. A gallium nitride high electron mobility transistor 130B and an internal connector 150B are disposed on region 102B.

[0075] Figure 13 This is a top view of a semiconductor device 100C drawn according to some embodiments of the present disclosure. In another embodiment, gallium nitride high electron mobility transistors 120C and 130C are similar to gallium nitride high electron mobility transistors 120A and 130A. On substrate 110C, internal connector 140C, source / drain electrodes 121C, 122C, and gate electrode 123C are disposed in region 101C, and internal connector 150C, source / drain electrodes 131C, 132C, and gate electrode 133C are disposed in region 102C.

[0076] In this embodiment, the first type-doped semiconductor regions 111C are doped with N-type dopant. The second type-doped semiconductor regions 112C are doped with P-type dopant. A plurality of interfaces 113C are formed between the first type-doped semiconductor regions 111C and the second type-doped semiconductor regions 112C.

[0077] Figure 14This is a top view of a semiconductor device 100D drawn according to some embodiments of the present disclosure. In this embodiment, a gallium nitride high electron mobility transistor 120D includes a pair of source / drain electrodes 121D and 122D arranged along a first direction d1. The interface 141D of the internal connector 140D and the source / drain electrodes 121D and 122D are arranged along the first direction d1 in their vertical projection onto the substrate 110D. These first-type doped semiconductor regions 111D, second-type doped semiconductor regions 112D, and interfaces 113D extend along the first direction d1.

[0078] The gallium nitride high electron mobility transistor 130D includes a pair of source / drain electrodes 131D and 132D arranged along a first direction d1. The interface 151D of the internal connector 150D and the source / drain electrodes 131D and 132D are arranged along the first direction d1 in their vertical projection on the substrate 110D.

[0079] Figure 15 This is a top view of a semiconductor device 100E drawn according to some embodiments of the present disclosure. In this embodiment, a gallium nitride high electron mobility transistor 120E includes a pair of source / drain electrodes 121E, 122E and a gate electrode 123E arranged along a first direction d1. The vertical projection of the interface 141E of the internal connector 140E and the source / drain electrodes 121E, 122E onto the substrate 111E falls on one of these first-type doped semiconductor regions 111E and second-type doped semiconductor regions 112E. In other words, the vertical projection of the interface 141E and the source / drain electrodes 121E, 122E onto the substrate 110E falls between two interfaces 113E.

[0080] The gallium nitride high electron mobility transistor 130E includes a pair of source / drain electrodes 131E and 132E arranged along a first direction d1, and a gate electrode 133E. The vertical projection of the interface 151E of the internal connector 150E and the source / drain electrodes 131E and 132E onto the substrate 111E falls on one of the first-type doped semiconductor regions 111E and the second-type doped semiconductor region 112E. In other words, the vertical projection of the interface 151E and the source / drain electrodes 131E and 132E onto the substrate 110E falls between two interfaces 113E.

[0081] Figure 16This is a top view of a semiconductor device 100F drawn according to some embodiments of the present disclosure. In this embodiment, a gallium nitride high electron mobility transistor 120F includes a pair of source / drain electrodes 121F, 122F and a gate electrode 123 arranged along a first direction d1. The source / drain electrodes 121F, 122F and the gate electrode 123F are similar to the source / drain electrodes 121E, 122E and the gate electrode 123E. The interface 141F of the internal connector 140F spans two interfaces 113F. The source / drain electrodes 121F, 122F and the gate electrode 123F are disposed in one of the first type doped semiconductor regions 111F and the second type doped semiconductor regions 112F, and are located between the two interfaces 113F.

[0082] The gallium nitride high electron mobility transistor 130F includes a pair of source / drain electrodes 131F and 132F and a gate electrode 133F arranged along a first direction d1. The source / drain electrodes 131F, 132F, and gate electrode 133F are similar to source / drain electrodes 131E, 132E, and gate electrode 133E. An interface 151F of the internal connector 150F spans two interfaces 113F. The source / drain electrodes 131F, 132F, and gate electrode 133F are disposed on one of the first-type doped semiconductor regions 111F and the second-type doped semiconductor regions 112F, and are located between the two interfaces 113F.

[0083] Figure 17 This is a top view of a semiconductor device 100G drawn according to some embodiments of the present disclosure. In this embodiment, a gallium nitride high electron mobility transistor 120G includes a pair of source / drain electrodes 121G and 122G and a gate electrode 123G arranged along a first direction d1. The source / drain electrodes 121G, 122G and the gate electrode 123G are disposed on one of a plurality of interfaces 113G formed between the first type doped semiconductor regions 111G and the second type doped semiconductor regions 112G formed on the substrate 110G.

[0084] Figure 18 This is a top view of a semiconductor device 100H drawn according to some embodiments of the present disclosure. In this embodiment, a gallium nitride high electron mobility transistor 120H includes a pair of source / drain electrodes 121H and 122H and a gate electrode 123H arranged along a second direction d2. The gallium nitride high electron mobility transistor 120H is disposed between inner connectors 140H and 141H in a first direction d1. The inner connectors 140H and 141H are arranged along the first direction d1.

[0085] The gallium nitride high electron mobility transistor 130H includes a pair of source / drain electrodes 131H and 132H arranged along a second direction, and a gate electrode 133H. In a first direction d1, the gallium nitride high electron mobility transistor 130H is disposed between inner connectors 150H and 151H. The inner connectors 150H and 151H are arranged along the first direction d1.

[0086] In this embodiment, the vertical projection of each source / drain electrode 121H, 122H on the inner connector 141H is located directly above the interface, which is formed between the inner connector 141H and the substrate 110H.

[0087] Figure 19 This is a top view of a semiconductor device 100I drawn according to some embodiments of the present disclosure. In this embodiment, the substrate 110I has region A and region B. In region A, the first-type doped semiconductor regions 111I and the second-type doped semiconductor regions 112I extend along a third direction d3. In region B, the first-type doped semiconductor regions 111I and the second-type doped semiconductor regions 112I extend along a first direction d1. The first direction d1 and the third direction d3 are different. A gallium nitride high electron mobility transistor 120I includes a pair of source / drain electrodes 121I, 122I and a gate electrode 123I arranged along a second direction d2. A gallium nitride high electron mobility transistor 130I includes a pair of source / drain electrodes 131I, 132I and a gate electrode 133I arranged along a second direction d2.

[0088] Gallium nitride high electron mobility transistor 120I is disposed in region B. Gallium nitride high electron mobility transistor 130I is disposed in region B. Internal connectors 140I and 150I are disposed in region A. Gallium nitride high electron mobility transistor 120I and internal connector 140I cross the same interface 113I. Gallium nitride high electron mobility transistor 130I and internal connector 150I cross the same interface 113I.

[0089] Figure 20 This is a top view of a semiconductor device 100J drawn according to some embodiments of the present disclosure. In this embodiment, the vertical projection of the internal connector 140J onto the substrate 110J has at least an L-shaped profile. The vertical projection of the internal connector 150J onto the substrate 110J also has at least an L-shaped profile. The internal connector 140J is adjacent to the source / drain electrodes 121J, 122J and the gate electrode 123J of the gallium nitride high electron mobility transistor 120J. The internal connector 150J is adjacent to the source / drain electrodes 131J, 132J and the gate electrode 133J of the gallium nitride high electron mobility transistor 130J.

[0090] Figure 21 This is a top view of a semiconductor device 100K drawn according to some embodiments of the present disclosure. In this embodiment, the vertical projection of the inner connector 140K onto the substrate 110K has an annular shape, and the vertical projection of the gallium nitride high electron mobility transistor 120K onto the substrate 110K is within the annular vertical projection of the inner connector 140K. The vertical projection of the inner connector 150K onto the substrate 110K has an annular shape, and the vertical projection of the gallium nitride high electron mobility transistor 130K onto the substrate 110K is within the annular vertical projection of the inner connector 150K. The gallium nitride high electron mobility transistor 120K includes a pair of source / drain electrodes 121K, 122K and a gate electrode 123K arranged along a second direction d2. The gallium nitride high electron mobility transistor 130K includes a pair of source / drain electrodes 131K, 132K and a gate electrode 133K arranged along a second direction d2.

[0091] Figure 22 This is a top view of a semiconductor device 100J drawn according to some embodiments of the present disclosure. In this embodiment, the vertical projection of the internal connector 140J onto the substrate 110J is located directly above the gallium nitride high electron mobility transistor 120J in the first direction d1. The vertical projection of the internal connector 150J onto the substrate 110J is located directly below the gallium nitride high electron mobility transistor 130J in the first direction d1. The gallium nitride high electron mobility transistor 120J includes source / drain electrodes 121J and 122J arranged along the second direction d2, and a gate electrode 123J. The gallium nitride high electron mobility transistor 130J includes source / drain electrodes 131J and 132J arranged along the second direction d2, and a gate electrode 133J.

[0092] Figure 23 This is a top view of a semiconductor device 100K drawn according to some embodiments of the present disclosure. In this embodiment, a gallium nitride high electron mobility transistor 200K is disposed on a substrate 110K, which covers a region 101K on a plurality of first-type doped semiconductor regions 111K and a plurality of second-type doped semiconductor regions 112K in the substrate 110K. The gallium nitride high electron mobility transistor 200K has a heterojunction region disposed between two nitride semiconductor layers and another adjacent two-dimensional electron gas region.

[0093] Gallium nitride high electron mobility transistor 200K has source / drain electrodes 201K and 203K arranged along a second direction d2, and a gate electrode 202K. Gallium nitride high electron mobility transistor 120K has source / drain electrodes 121K and 122K arranged along a second direction d2, and a gate electrode 123K. Gallium nitride high electron mobility transistor 130K has source / drain electrodes 131K and 132K arranged along a second direction d2, and a gate electrode 133K. Gallium nitride high electron mobility transistors 120K and 200K cover a region 101K. Interfaces 113K between these first-type doped semiconductor regions 111K and second-type doped semiconductor regions 112K separate gallium nitride high electron mobility transistors 200K and 130K.

[0094] Although not shown in the figures, it should be understood that additional gallium nitride high electron mobility transistors can be integrated onto a single substrate using the devices described above, allowing any number to be combined in this manner. Furthermore, the above embodiments provide different semiconductor device configurations, which improve adaptability. For example, different semiconductor device configurations can be selected based on the process environment, device size, and device function (e.g., low-voltage, high-voltage, or radio frequency applications). Although not shown in the figures, the semiconductor devices with the different configurations described above should be understood as being able to be integrated into a single chip or circuit.

[0095] The above description of this disclosure is provided for illustrative purposes only and is not intended to exhaustively or limit the scope of this disclosure to these detailed descriptions. Many obvious modifications and improvements can be made to it by those skilled in the art.

[0096] The embodiments selected and described above are intended to most clearly illustrate the principles and practical applications of this disclosure, enabling other skilled in the art to understand the various embodiments of this disclosure and various modifications suitable for specific purposes.

[0097] As used herein, “about,” “approximately,” or “substantially” includes the value and the average of the values ​​within an acceptable range of deviation from a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and a particular number of errors associated with the measurement (i.e., limitations of the measurement system). When these terms are used together with an event or situation, they include both embodiments in which the event or situation occurs precisely and embodiments in which the event or situation occurs similarly. For example, when these terms are used together with numerical values, the term may include a range of values ​​equal to ±10% or less of the value, such as ±5% or less, ±4% or less, ±3% or less, ±2% or less, ±1% or less, ±0.5% or less, ±0.1% or less, or ±0.05% or less. "Substantially coplanar" means that the two surfaces are within a few thousand decimeters or on the same plane, such as within 40, 30, 20, 10, 1000 decimeters or on the same plane.

[0098] For example, “about” can mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the terms “about,” “approximately,” or “substantially” used herein can be chosen to select a more acceptable range of deviations or standard deviations depending on the optical, etched, or other properties, rather than applying a single standard deviation to all properties.

[0099] As used herein, unless the context clearly specifies otherwise, the singular terms “single,” “an,” and “the single” may include plural references. In the description of some embodiments, a component provided “above” or “on top of” another component may include a situation where the preceding component is directly on the following component (e.g., in physical contact with the following component), and a situation where one or more intervening components are located between the preceding and following components.

[0100] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not intended to be limiting. Those skilled in the art will understand that various modifications and substitutions can be made to equivalents without departing from the true spirit and scope of this disclosure as defined in the appended claims. The drawings are not necessarily drawn to scale. Due to manufacturing processes and tolerances, the processes presented in this disclosure may differ from actual apparatus. Other embodiments of this disclosure may not be specifically described. The specification and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the purpose, spirit, and scope of this disclosure. All such modifications will fall within the scope of the appended claims. Although the methods disclosed herein are described by performing specific operations in a specific order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of these operations are not limited.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes a plurality of first-type doped semiconductor regions and a plurality of second-type doped semiconductor regions, the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions extending along a first direction and alternating along a second direction, the first direction and the second direction being different; adjacent first-type doped semiconductor regions and second-type doped semiconductor regions form a PN junction; A first gallium nitride high electron mobility transistor is disposed above the substrate and covers a first region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions; A second gallium nitride high electron mobility transistor is disposed above the substrate and covers a second region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions, wherein the first region and the second region are separated from each other; A first internal connector is disposed above the substrate and connects the first region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions, and the width of the first internal connector is greater than the source-drain spacing of the first gallium nitride high electron mobility transistor. as well as A second internal connector is disposed above the substrate and connects the plurality of first-type doped semiconductor regions and the second region on the plurality of second-type doped semiconductor regions, and the width of the second internal connector is greater than the source-drain spacing of the second gallium nitride high electron mobility transistor. The first inner connector and the second inner connector are electrically connected to an external power supply of different voltages via connecting pads.

2. The semiconductor device as claimed in claim 1, characterized in that, The first region and the second region are separated by at least one of the plurality of first-type doped semiconductor regions or the plurality of second-type doped semiconductor regions.

3. The semiconductor device as described in claim 1, characterized in that, The first internal connector covers and traverses multiple, the multiple first-type doped semiconductor regions and the multiple second-type doped semiconductor regions.

4. The semiconductor device as claimed in claim 1, characterized in that, The second inner connector covers and traverses multiple, the multiple first-type doped semiconductor regions and the multiple second-type doped semiconductor regions.

5. The semiconductor device as claimed in claim 1, characterized in that, The distance between the first inner connector and the second inner connector is shorter than the distance between the first gallium nitride high electron mobility transistor and the second gallium nitride high electron mobility transistor.

6. The semiconductor device as claimed in claim 1, characterized in that, Multiple adjacent first-type doped semiconductor regions and second-type doped semiconductor regions form a PNP structure.

7. The semiconductor device as claimed in claim 1, characterized in that, The number of first-type doped semiconductor regions and second-type doped semiconductor regions that the first internal connector traverses or spans is greater than the number of first-type doped semiconductor regions and second-type doped semiconductor regions that the first gallium nitride high electron mobility transistor traverses or spans.

8. The semiconductor device as claimed in claim 1, characterized in that, The number of the first-type doped semiconductor regions and the second-type doped semiconductor regions that the second internal connector traverses or spans is greater than the number of the first-type doped semiconductor regions and the second-type doped semiconductor regions that the second gallium nitride high electron mobility transistor traverses or spans.

9. The semiconductor device as claimed in claim 1, characterized in that, The first internal connector and the second internal connector are located on the same side of the first gallium nitride high electron mobility transistor and the second gallium nitride high electron mobility transistor.

10. A semiconductor device, characterized in that, include: The substrate includes a plurality of first-type doped semiconductor regions and a plurality of second-type doped semiconductor regions, the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions extending along a first direction and alternating along a second direction, the first direction and the second direction being different; adjacent first-type doped semiconductor regions and second-type doped semiconductor regions form a PN junction; A first gallium nitride high electron mobility transistor is disposed above the substrate and covers a first region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions; A second gallium nitride high electron mobility transistor is disposed above the substrate and covers a second region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions, wherein the first region and the second region are arranged along the second direction; A first internal connector is disposed above the substrate and connects the first region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions, and the first internal connector and the first gallium nitride high electron mobility transistor are arranged along the first direction; as well as A second internal connector is disposed above the substrate and connects the second region on the plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions, and the second internal connector and the second gallium nitride high electron mobility transistor are arranged along the first direction; The first inner connector and the second inner connector are electrically connected to an external power supply of different voltages via connecting pads.

11. The semiconductor device as claimed in claim 10, characterized in that, The first region and the second region are separated by at least one of the plurality of first-type doped semiconductor regions or the plurality of second-type doped semiconductor regions.

12. The semiconductor device as claimed in claim 10, characterized in that, The first internal connector covers and traverses a plurality of first-type doped semiconductor regions and the plurality of second-type doped semiconductor regions along the second direction.

13. The semiconductor device as claimed in claim 10, characterized in that, The second inner connector covers and traverses a plurality of first-type doped semiconductor regions and a plurality of second-type doped semiconductor regions along the second direction.

14. The semiconductor device as claimed in claim 10, characterized in that, The distance between the first inner connector and the second inner connector is shorter than the distance between the first gallium nitride high electron mobility transistor and the second gallium nitride high electron mobility transistor.

15. The semiconductor device as claimed in claim 10, characterized in that, Multiple adjacent first-type doped semiconductor regions and second-type doped semiconductor regions form a PNP structure.

16. The semiconductor device as claimed in claim 10, characterized in that, The number of first-type doped semiconductor regions and second-type doped semiconductor regions that the first internal connector traverses or spans is greater than the number of first-type doped semiconductor regions and second-type doped semiconductor regions that the first gallium nitride high electron mobility transistor traverses or spans.

17. The semiconductor device as claimed in claim 10, characterized in that, The number of the first-type doped semiconductor regions and the second-type doped semiconductor regions that the second internal connector traverses or spans is greater than the number of the first-type doped semiconductor regions and the second-type doped semiconductor regions that the second gallium nitride high electron mobility transistor traverses or spans.

18. The semiconductor device as claimed in claim 10, characterized in that, The first internal connector and the second internal connector are located on the same side of the first gallium nitride high electron mobility transistor and the second gallium nitride high electron mobility transistor.

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