A trench gate DMOS device

Abstract

The present application belongs to the technical field of power semiconductor, and relates to a trench gate MOSFET structure, which comprises a metallized drain, a heavily doped first-conductivity-type semiconductor substrate located above the metallized drain, a lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer located above the first-conductivity-type semiconductor substrate; a second-conductivity-type semiconductor body region located above the lightly doped first-conductivity-type semiconductor lightly doped epitaxial layer. The present application divides the channel into two parts with different doping concentrations, which increases the length of the channel, increases the influence of the mobility on the temperature coefficient of the drain current, makes the device enter the current negative temperature characteristic interval earlier, reduces the zero temperature point of the drain current of the device, makes the device enter the current negative temperature characteristic region earlier, improves the stability of the low-voltage DMOS under small current, and reduces the resistance of the channel as much as possible.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and specifically to a trench gate DMOS device. Background Technology

[0002] Power semiconductor devices are semiconductor devices used for power processing. They combine microelectronics and power electronics technologies, forming the foundation and core of power electronics technology. Power DMOS devices play a crucial role in power conversion due to their advantages such as fast switching speed, high input impedance, low loss, simple driving, and good frequency characteristics. Their development has been a process of continuously improving voltage withstand and reducing losses while maintaining their inherent advantages. Traditional DMOS devices are planar structures using a double-diffusion process. This was the first commercially successful power DMOS, playing a key role in its development. However, the presence of the internal JFET region resulted in a relatively high on-resistance, which was undesirable for power device development. This provided an opportunity for the development of trench-gate power devices. Trench-gate DMOS devices employ a U-shaped trench structure with a longitudinal conductive channel, high cell density, and large current handling capacity. Because their structure eliminates the JFET region, resulting in lower on-resistance, they have been widely adopted in low-voltage applications.

[0003] In low-voltage and ultra-low-voltage applications, with the continuous development and optimization of processes in recent years, the problems caused by the low-current temperature instability of power DMOS have gradually become apparent. DMOS devices exhibit a negative temperature characteristic (TTC) under high current conditions and a positive TTC under low current conditions. This is because the temperature characteristic of mobility dominates under high current, while the temperature characteristic of threshold voltage dominates under low current. When the temperature characteristics of mobility and threshold voltage have opposite effects on the current, their effects cancel each other out, reaching a point where the current reaches zero temperature, i.e., the device's zero-temperature point. The DMOS exhibits a positive TTC when the drain current is below zero temperature and a negative TTC when it is above zero temperature. Since the positive TTC of the drain current can cause device failure or even burnout, it is desirable to minimize the zero-temperature point of the device to improve its thermal stability. Summary of the Invention

[0004] To address the aforementioned issues, this invention provides a trench-gate DMOS device that improves stability under low current conditions, achieving a lower zero-temperature point and enabling the device to enter the negative temperature characteristic region of current earlier, thereby improving the stability of low-voltage DMOS under low current conditions.

[0005] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0006] A trench gate DMOS device includes a metallized drain 1, a heavily doped first conductivity type semiconductor substrate 2 located on the metallized drain 1, a lightly doped first conductivity type semiconductor epitaxial layer 3 located on the first conductivity type semiconductor substrate 2, and a second conductivity type semiconductor body region 4 located on the lightly doped first conductivity type semiconductor epitaxial layer 3.

[0007] The top of the lightly doped epitaxial layer 3 of the first conductivity type semiconductor has a trench, and the lower surface of the trench is lower than the lower surface of the second conductivity type semiconductor body region 4. A polysilicon gate electrode 9 is provided in the trench and on part of the upper surface of the second conductivity type semiconductor body region 4. The polysilicon gate electrode 9 includes a horizontal section and a vertical section. The vertical section of the polysilicon gate electrode 9 is isolated from the second conductivity type semiconductor body region 4 by a sidewall gate oxide layer 14, and the horizontal section of the polysilicon gate electrode 9 is isolated from the second conductivity type semiconductor body region 4 by a lateral gate oxide layer 10. The area located at the top of the second conductivity type semiconductor body region 4 and in contact with the lateral gate oxide layer 10 is a lateral channel region 6. The area located on the side of the second conductivity type semiconductor body region 4 and in contact with the sidewall gate oxide layer 14 is a longitudinal channel region 5.

[0008] The top of the second type of conductivity semiconductor body region 4 has a first type of conductivity semiconductor heavily doped source region 7 and a second type of conductivity semiconductor heavily doped contact region 8; the side of the first type of conductivity semiconductor heavily doped source region 7 is in direct contact with the lateral channel region 6; the second type of conductivity semiconductor heavily doped contact region 8 and the first type of conductivity semiconductor heavily doped source region 7 are in contact with the metallized source electrode 13 located on the upper surface of the device through a metal via 12; the polysilicon gate electrode 9 is isolated from the metallized source electrode 13 and the metal via 12 through an oxide layer 11, and is isolated from the first type of conductivity semiconductor heavily doped source region 7 and the lightly doped first type of conductivity semiconductor lightly doped epitaxial layer 3 through a sidewall gate oxide layer 14; the lateral channel region 6 and the longitudinal channel region 5 have different doping concentrations and different threshold voltages.

[0009] As a preferred method, the heavy doping concentration is 1E18cm. -3 -1E19cm -3 The lightly doped concentration is 1E15cm. -3 -1E16cm -3 .

[0010] As a preferred approach, the silicon material in the device is replaced with silicon carbide, gallium arsenide, indium phosphide, or germanium silicon semiconductor material.

[0011] The beneficial effects of this invention are as follows: Extending the channel laterally from the longitudinal channel region 5 of a conventional trench-gate DMOS to the lateral channel region 6 increases the channel length, significantly increasing the influence of mobility on drain current and significantly reducing the drain current I at the zero-temperature point of the device. D * ,like Figure 2 and Figure 3 As shown, this allows the device to enter the negative temperature characteristic region of current earlier, improving device reliability. Simultaneously, the lateral channel region 6 and the longitudinal channel region 5 have different doping concentrations and form a series current flow path. Therefore, while reducing the doping concentration of one channel region to lower the channel resistance, the other channel region can maintain a higher doping concentration to keep the threshold voltage within a reasonable range. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the structure of Embodiment 1 of the present invention;

[0013] Figure 2 The transfer characteristic curves of this invention at different temperatures and the drain current I corresponding to the zero temperature point are... D * Indication;

[0014] Figure 3 The channel length of this invention is 1 / I D * The relationship.

[0015] 1 is a metallized drain, 2 is a heavily doped first conductivity type semiconductor substrate, 3 is a lightly doped first conductivity type semiconductor lightly doped epitaxial layer, 4 is a second conductivity type semiconductor body region, 5 is a vertical channel region, 6 is a lateral channel region, 7 is a heavily doped first conductivity type semiconductor source region, 8 is a heavily doped second conductivity type semiconductor contact region, 9 is a polysilicon gate electrode, 10 is a lateral gate oxide layer, 11 is an oxide layer, 12 is a metal via, 13 is a metallized source, and 14 is a sidewall gate oxide layer. Detailed Implementation

[0016] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0017] Example 1

[0018] like Figure 1As shown, this embodiment provides a trench gate DMOS device, including a metallized drain 1, a heavily doped first conductivity type semiconductor substrate 2 located on the metallized drain 1, a lightly doped first conductivity type semiconductor lightly doped epitaxial layer 3 located on the first conductivity type semiconductor substrate 2, and a second conductivity type semiconductor body region 4 located on the lightly doped first conductivity type semiconductor lightly doped epitaxial layer 3.

[0019] The top of the lightly doped epitaxial layer 3 of the first conductivity type semiconductor has a trench, and the lower surface of the trench is lower than the lower surface of the second conductivity type semiconductor body region 4. A polysilicon gate electrode 9 is provided in the trench and on part of the upper surface of the second conductivity type semiconductor body region 4. The polysilicon gate electrode 9 includes a horizontal section and a vertical section. The vertical section of the polysilicon gate electrode 9 is isolated from the second conductivity type semiconductor body region 4 by a sidewall gate oxide layer 14, and the horizontal section of the polysilicon gate electrode 9 is isolated from the second conductivity type semiconductor body region 4 by a lateral gate oxide layer 10. The area located at the top of the second conductivity type semiconductor body region 4 and in contact with the lateral gate oxide layer 10 is a lateral channel region 6. The area located on the side of the second conductivity type semiconductor body region 4 and in contact with the sidewall gate oxide layer 14 is a longitudinal channel region 5.

[0020] The top of the second type of conductivity semiconductor body region 4 has a first type of conductivity semiconductor heavily doped source region 7 and a second type of conductivity semiconductor heavily doped contact region 8; the side of the first type of conductivity semiconductor heavily doped source region 7 is in direct contact with the lateral channel region 6; the second type of conductivity semiconductor heavily doped contact region 8 and the first type of conductivity semiconductor heavily doped source region 7 are in contact with the metallized source electrode 13 located on the upper surface of the device through a metal via 12; the polysilicon gate electrode 9 is isolated from the metallized source electrode 13 and the metal via 12 through an oxide layer 11, and is isolated from the first type of conductivity semiconductor heavily doped source region 7 and the lightly doped first type of conductivity semiconductor lightly doped epitaxial layer 3 through a sidewall gate oxide layer 14; the lateral channel region 6 and the longitudinal channel region 5 have different doping concentrations and different threshold voltages.

[0021] The heavy doping concentration is 1E18cm. -3 -1E19cm -3 The lightly doped concentration is 1E15cm. -3 -1E16cm -3 .

[0022] The working principle of the present invention will be explained using Example 1 as an example:

[0023] DMOS devices exhibit a negative temperature characteristic (TTC) under high current conditions and a positive TTC under low current conditions. This is because the temperature characteristic of mobility dominates at high currents, while the temperature characteristic of the threshold voltage dominates at low currents. When the temperature characteristics of mobility and threshold voltage have opposite effects on the current, their effects cancel each other out, reaching a point where the current reaches zero temperature, i.e., the device's zero-temperature point. A DMOS device exhibits a positive TTC when the drain current is below zero temperature and a negative TTC when it is above zero temperature. Figure 2 As shown. Since the positive temperature characteristic of drain current can cause device failure or even burnout, a smaller zero-temperature point is desirable for improving device thermal stability. Increasing the channel length significantly increases the influence of mobility on drain current, thus significantly reducing the drain current I corresponding to the zero-temperature point of the device. D * ,like Figure 3 As shown. However, increasing the channel length by increasing the Pbody depth requires a deeper junction depth and a deeper trench depth, which increases the difficulty of the process and also increases the on-resistance.

[0024] Taking an N-type semiconductor as an example, in this invention, when the polysilicon gate electrode 9 is at a high potential, the longitudinal channel region 5 is formed. The charge carriers flow not only through the longitudinal channel region 5 but also through the lateral channel region 6, resulting in a longer flow area. Therefore, the influence of mobility on the drain current will significantly increase, thereby lowering the zero-temperature point and allowing the device to enter the negative current temperature characteristic region earlier, improving the stability of the DMOS under low current. Simultaneously, the lateral channel region 6 has a lower doping concentration and a lower threshold voltage, thus also a lower resistance. This allows for minimizing channel resistance while increasing channel length. Since the lateral channel region 6 and the longitudinal channel region 5 form a series structure, the threshold voltage will not decrease due to the reduced doping concentration in the lateral channel region.

[0025] The present invention proposes a trench gate DMOS device in which the silicon material can be replaced with silicon carbide, gallium arsenide, indium phosphide or germanium silicon semiconductor material.

[0026] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A trench-gate DMOS device, characterized in that: It includes a metallized drain (1), a heavily doped first conductivity type semiconductor substrate (2) located on the metallized drain (1), a lightly doped first conductivity type semiconductor lightly doped epitaxial layer (3) located on the first conductivity type semiconductor substrate (2); and a second conductivity type semiconductor body region (4) located on the lightly doped first conductivity type semiconductor lightly doped epitaxial layer (3). The top of the lightly doped epitaxial layer (3) of the first conductivity type semiconductor has a trench, and the lower surface of the trench is lower than the lower surface of the second conductivity type semiconductor body region (4); a polysilicon gate electrode (9) is provided in the trench and on part of the upper surface of the second conductivity type semiconductor body region (4); the polysilicon gate electrode (9) includes a horizontal section and a vertical section, the vertical section of the polysilicon gate electrode (9) is isolated from the second conductivity type semiconductor body region (4) by a sidewall gate oxide layer (14), the horizontal section of the polysilicon gate electrode (9) is isolated from the second conductivity type semiconductor body region (4) by a lateral gate oxide layer (10), the area located at the top of the second conductivity type semiconductor body region (4) and in contact with the lateral gate oxide layer (10) is a lateral channel region (6); the area located on the side of the second conductivity type semiconductor body region (4) and in contact with the sidewall gate oxide layer (14) is a longitudinal channel region (5). The top of the second type of semiconductor body region (4) has a first type of semiconductor heavily doped source region (7) and a second type of semiconductor heavily doped contact region (8); the side of the first type of semiconductor heavily doped source region (7) and the lateral channel region (6) are in direct contact; the second type of semiconductor heavily doped contact region (8) and the first type of semiconductor heavily doped source region (7) are in contact with the metallized source electrode (13) located on the upper surface of the device through a metal via (12); the polysilicon gate electrode (9) is isolated from the metallized source electrode (13) and the metal via (12) through an oxide layer (11), and is isolated from the first type of semiconductor heavily doped source region (7) and the lightly doped first type of semiconductor lightly doped epitaxial layer (3) through a sidewall gate oxide layer (14); the lateral channel region (6) and the longitudinal channel region (5) have different doping concentrations and different threshold voltages; The heavy doping concentration is 1E18cm. -3 -1E19cm -3 The lightly doped concentration is 1E15cm. -3 -1E16cm -3 ; Extending the channel laterally to the lateral channel region (6) increases the channel length, thereby increasing the influence of mobility on drain current and reducing the drain current I corresponding to the zero temperature point of the device. D * To improve device reliability, the doping concentrations of the lateral channel region (6) and the longitudinal channel region (5) are different and form a series current flow path. When the polysilicon gate electrode (9) is at a high potential, the longitudinal channel region (5) is formed. The charge carriers not only flow through the longitudinal channel region (5) but also through the lateral channel region (6), and the flow area is longer. Therefore, the influence of mobility on drain current increases, thereby lowering the zero temperature point. The device can enter the negative temperature characteristic region of current earlier. At the same time, the lateral channel region (6) has a lower doping concentration and a lower threshold voltage, so the resistance is also lower. Thus, while increasing the channel length, the channel resistance is reduced as much as possible. Since the lateral channel region (6) and the longitudinal channel region (5) form a series structure, the threshold voltage will not decrease due to the decrease in the doping concentration of the lateral channel region.

2. The trench-gate DMOS device according to claim 1, characterized in that: The silicon material in the device is replaced with silicon carbide, gallium arsenide, indium phosphide, or germanium silicon semiconductor materials.

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