A method for preparing a bottom electrode excited surface acoustic wave device

Abstract

The application relates to a bottom electrode excitation type surface acoustic wave device preparation method, which comprises the following steps: S1. Preprocessing a piezoelectric wafer, and defining the position of a through hole for electrode lead-out on the piezoelectric wafer through photoetching; S2. Preparing the through hole on the piezoelectric wafer, and performing seed layer sputtering in the through hole and then performing electroplating filling in the through hole; S3. Polishing the surface of the piezoelectric wafer and performing surface flattening; S4. Overlaying a pattern on the piezoelectric wafer, so that the pattern is coincident with the through hole, and the pattern comprises an electrode structure and an interdigital transducer structure; S5. Depositing an insulating layer on the surface of the piezoelectric wafer; and S6. Preprocessing the surface of the piezoelectric wafer and the substrate wafer, bonding them by using a normal-temperature wafer direct bonding method after increasing the activity. The application is used for preparing a surface acoustic wave device, reducing the influence of an external environment on the surface acoustic wave device, and improving the high integration requirement of the surface acoustic wave device.

Description

Technical Field

[0001] The present invention relates to the technical field of surface acoustic wave filters, in particular to a method for preparing a bottom electrode excitation type surface acoustic wave device. Background Art

[0002] A surface acoustic wave (SAW) filter is an acoustic device used in communications, radio, radar and other related RF front-end fields.

[0003] Currently, SAW devices primarily include traditional SAW, TC-SAW, and IHP-SAW, with various structures. TC-SAW is an acoustic device that suppresses temperature drift by coating the base SAW structure with a SiO2 temperature-compensating film. It is widely used in communication terminals. IHP-SAW, also known as TF-SAW, is a new acoustic device that achieves higher performance by optimizing and modifying the piezoelectric substrate through a multilayer film structure. Regardless of the structure, the operating principle of SAW devices is essentially the same: a comb-shaped interdigital transducer is fabricated on the surface of a piezoelectric material or a substrate with a piezoelectric material layer through semiconductor processing. The piezoelectric and inverse piezoelectric effects of the piezoelectric layer enable electrical-acoustic-electrical signal propagation, thereby filtering communication signals. Commonly used piezoelectric materials include lithium tantalate (LiTaO3, LT), lithium niobate (LiNbO3, LN), aluminum nitride (AlN), and zinc oxide (ZnO), with LT and LN being the most common. LT and LN are mostly synthetic materials with high plasticity and strong corrosion resistance. Therefore, these materials are difficult to process in a refined manner. For example, when using a through-hole process to drill holes in LT and LN, the conventional processing depth can only be maintained between hundreds of nanometers and 1 micron, making it difficult to achieve micron-level processing. In addition, key material parameters such as the thermal expansion coefficient of these materials are also incompatible with silicon-based materials. Therefore, piezoelectric materials are difficult to integrate with mainstream silicon-based semiconductor processes, which leads to a natural disadvantage in the integration and miniaturization of related devices. In addition, for most SAW devices, the comb-tooth structure of their active functional area is located on the very surface of the chip. Not only is the propagation of sound waves easily affected by changes in the external environment, but the unprotected comb-tooth structure is also extremely susceptible to damage from external debris, which in turn affects the overall performance of the device. Therefore, there are almost no bare chip solutions for these devices available for use in the communications field. This further limits the application of these devices in miniaturization and integration.

[0004] Therefore, those skilled in the art are committed to developing a method for preparing a bottom electrode excited surface acoustic wave device, which is used to prepare the surface acoustic wave device, reduce the influence of the surface acoustic wave device on the external environment, and improve the high integration demand of the surface acoustic wave device. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for preparing a bottom electrode excited surface acoustic wave device, which is used to prepare the surface acoustic wave device, reduce the influence of the surface acoustic wave device on the external environment, and improve the high integration requirement of the surface acoustic wave device.

[0006] The present invention solves the above-mentioned technical problem with the following technical solution: A method for preparing a bottom electrode excited surface acoustic wave device comprises the following steps:

[0007] S1. Pre-processing the piezoelectric wafer by photolithographically defining the positions of the electrode lead-out holes on the piezoelectric wafer;

[0008] S2. preparing the via holes on the piezoelectric wafer, and performing electroplating filling in the via holes after sputtering a seed layer in the via holes;

[0009] S3. Polishing the surface of the piezoelectric wafer and smoothing the surface;

[0010] S4. Overlaying a pattern on the piezoelectric wafer so that the pattern coincides with the via hole, the pattern including an electrode structure and an IDT structure;

[0011] S5. Depositing an insulating layer on the surface of the piezoelectric wafer;

[0012] S6. The piezoelectric wafer and the substrate wafer are surface pretreated to increase their activity and then bonded by direct wafer bonding at room temperature;

[0013] S7 thinning the piezoelectric layer structure of the substrate wafer, and polishing and smoothing the surface;

[0014] S8. Prepare an under-bump metallization layer at the electrode structure, and prepare solder joints on the surface of the wafer with the under-bump metallization layer.

[0015] The beneficial effects of the present invention are: through the relevant process technologies and process steps such as wafer thin film deposition, direct wafer bonding at room temperature, etching and opening, electroplating filling, wafer thinning and CMP, a bottom comb-shaped transducer structure is realized by wrapping the piezoelectric material above the device and the insulating layer below, which solves the disadvantage that the surface acoustic wave device is easily affected by the external environment. At the same time, it can also achieve a temperature compensation effect to control the temperature drift of the device within an acceptable range. The device also meets the needs of subsequent integration in a bare chip manner.

[0016] On the basis of the above technical solution, the present invention can also be improved as follows.

[0017] Furthermore, step S5 also includes preparing a functional layer, depositing the functional layer on the surface of the insulating layer, and performing polishing and surface smoothing.

[0018] The beneficial effect of adopting the above further solution is that the functional layer is provided with corresponding functional layers according to different applications of the product, thereby improving the versatility of the surface acoustic wave device.

[0019] Furthermore, the insulating layer is a SiO2 insulating layer, and the functional layer is a SiO2 functional layer.

[0020] The beneficial effect of adopting the above further solution is that both the insulating layer and the functional layer are made of SiO2, which is conducive to etching processing.

[0021] Furthermore, in step S5, the thickness of the insulating layer and the functional layer after surface smoothing is within 5 nm of the design indicator, and the uniformity within the chip is required to be within ±2 nm.

[0022] The beneficial effect of adopting the above further solution is that the film thickness of the insulating layer and the functional layer has an error within the design index of 5 nm, which is conducive to subsequent polishing and surface smoothing.

[0023] Furthermore, in step S1, the position of the via is determined by a photolithography process, and the piezoelectric wafer is made of one of LN and LT materials with different cut types.

[0024] The beneficial effect of adopting the above further solution is to select the corresponding wafer material according to the function of the product.

[0025] Furthermore, in step S2, when the via hole is formed, the depth of the via hole is 20 nm to 50 nm greater than the design requirement.

[0026] The beneficial effect of adopting the above further solution is that it facilitates the subsequent thickness and consistency control of the via hole.

[0027] Furthermore, in step S3 and step S7, chemical mechanical polishing is used when polishing the wafer.

[0028] The beneficial effect of adopting the above further solution is to use chemical mechanical polishing to improve the flatness of the polished surface.

[0029] Furthermore, in step S6, the substrate wafer after bonding is thinned so that the thickness of the substrate wafer is 20 nm greater than the design requirement.

[0030] The beneficial effect of adopting the above further solution is that it facilitates the subsequent film uniformity control.

[0031] Furthermore, in step S8, the solder joint preparation method includes BGA ball planting, flip chip ball planting and microbump electroplating.

[0032] The beneficial effect of adopting the above further solution is that the solder joint is used to connect with external devices.

[0033] Furthermore, in step S1, before photolithography is performed on the piezoelectric wafer to define the positions of the electrode lead-out via holes, a photoresist is coated on the surface of the piezoelectric wafer.

[0034] The beneficial effect of adopting the above further solution is that the surface of the piezoelectric wafer is coated with photoresist, which facilitates rapid photolithography to define the position of the conductive hole for electrode extraction. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a flow chart of a specific embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of the device assembly structure of a specific embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of a structure for photolithographically defining via hole positions in a specific embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of the structure after etching of the via hole according to a specific embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of the structure of a through hole after planarization according to a specific embodiment of the present invention;

[0040] Figure 6 This is a schematic structural diagram of a piezoelectric material of a via hole after secondary photolithography in a specific embodiment of the present invention;

[0041] Figure 7 This is a schematic structural diagram of an IDT and an electrode structure after preparation according to a specific embodiment of the present invention;

[0042] Figure 8 This is a schematic diagram of the structure after the insulating layer is deposited according to a specific embodiment of the present invention;

[0043] Figure 9 This is a schematic structural diagram of a specific embodiment of the present invention after the insulating layer is planarized;

[0044] Figure 10 This is a schematic diagram of the structure after depositing a functional layer and planarizing according to a specific embodiment of the present invention;

[0045] Figure 11 This is a schematic diagram of the structure of a piezoelectric material after direct bonding in a specific embodiment of the present invention;

[0046] Figure 12 This is a schematic diagram of the structure of a substrate material wafer after thinning according to a specific embodiment of the present invention;

[0047] Figure 13 This is a schematic diagram of the structure of the piezoelectric layer after wafer thinning and subsequent planarization in a specific embodiment of the present invention;

[0048] Figure 14 This is a schematic diagram of the structure after solder joint preparation according to a specific embodiment of the present invention.

[0049] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0050] 10. Substrate wafer; 20. Functional layer; 30. Insulation layer; 40. Piezoelectric wafer; 50. IDT structure; 51. Electrode structure; 60. Via filling material; 62. Via; 70. UBM pad; 80. Solder joint; 90. Photoresist. DETAILED DESCRIPTION

[0051] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0052] In the description of the present invention, it should be understood that the terms "center", "length", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "inside", "outside", "peripheral", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred system or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0053] In the description of the present invention, “a plurality of” means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0054] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0055] like Figures 1 to 14 As shown, a method for preparing a bottom electrode excited surface acoustic wave device includes the following steps:

[0056] S1. Pre-process the piezoelectric wafer 40 and apply photoresist 90 to the surface of the piezoelectric wafer 40 to facilitate the rapid photolithography of the locations of the electrode lead-out vias 62 on the piezoelectric wafer 40. Specifically, the locations of the vias 62 are determined by photolithography, and the piezoelectric wafer 40 is made of one of LN and LT materials with different cuts.

[0057] S2. Etching is performed on the piezoelectric wafer 40 to form via holes 62. The depth of via holes 62 is 20 nm to 50 nm greater than the design requirement, facilitating subsequent thickness and consistency control. A seed layer is sputtered within via holes 62, and then electroplating is performed to fill the via holes 62, forming a via-hole filling material 60.

[0058] S3. Polish the surface of the piezoelectric wafer 40 by chemical mechanical polishing (CMP). After polishing, the surface is leveled to maintain consistency and uniformity of the wafer surface.

[0059] S4. Overlaying a pattern on the piezoelectric wafer 40 so that the pattern coincides with the via 62, the pattern including the electrode structure 51 and the IDT structure 50. Specifically, the piezoelectric wafer 40 is overprinted, requiring the electrode structure 51 to coincide with the via 62. The overprinted structure is then patterned using semiconductor processing techniques, including the electrode structure 51 and the IDT structure 50.

[0060] S5. An insulating layer 30 is deposited on the surface of the piezoelectric wafer 40, wherein the insulating layer 30 is a SiO2 insulating layer. The thickness of the insulating layer 30 is increased by 50 nm according to the design indicators to control the film thickness and uniformity. Subsequently, the insulating layer 30 is subjected to chemical mechanical polishing (CMP) and surface smoothing. The thickness of the film layer after smoothing is required to be basically consistent with the design indicators, with an error within 5 nm, and the uniformity within the chip is required to be within ±2 nm.

[0061] To make the surface acoustic wave device suitable for a variety of components, a functional layer 20 can be formed on the insulating layer 30. Specifically, the functional layer 20 is a SiO2 functional layer. The functional layer 20 is deposited on the surface of the insulating layer 30, and chemical mechanical polishing (CMP) and surface smoothing of the functional layer 20 are performed. The thickness of the functional layer 20 after surface smoothing is within 5nm of the design specification, and the uniformity within the wafer is required to be within ±2nm.

[0062] S6. Perform surface pretreatment on the piezoelectric wafer 40 and the substrate wafer 10 to increase their activity, and then bond them using room temperature wafer direct bonding. Thin the bonded substrate wafer 10 to a thickness that meets the requirements of the structural design. Thin the piezoelectric layer structure of the wafer after thinning the substrate material in the previous step, so that the thickness of the substrate wafer 10 is 20 nm thicker than the design requirement, to facilitate subsequent film uniformity control.

[0063] S7. Thinning the piezoelectric layer structure of the substrate wafer 10, and polishing and smoothing the surface. Chemical mechanical polishing (CMP) is used for wafer polishing.

[0064] S8. Prepare an under-bump metallization layer (UBM layer) at the electrode structure 51, and prepare solder joints 80 on the surface of the wafer with the under-bump metallization layer (UBM layer). Specifically, the preparation of the under-bump metallization layer (UBM layer) at the electrode structure 51 is consistent with the conventional method of preparing the under-bump metallization layer (UBM layer), and then the UBM pad 70 is prepared on the wafer with the under-bump metallization layer (UBM layer), and then the solder joints 80 are prepared on the UBM pad 70. The preparation methods of the solder joints 80 include BGA ball planting, flip chip ball planting and microbump electroplating.

[0065] In the present invention, by using relevant process technologies and process steps such as wafer thin film deposition, direct wafer bonding at room temperature, etching and opening, electroplating filling, wafer thinning and CMP, a bottom comb-shaped transducer structure is achieved by wrapping the piezoelectric material above the device and the insulating layer 30 below, thereby solving the disadvantage that the surface acoustic wave device is easily affected by the external environment. At the same time, a temperature compensation effect can also be achieved to control the temperature drift of the device within an acceptable range. The device also meets the requirements of subsequent integration in a bare chip manner.

[0066] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0067] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a bottom electrode excited surface acoustic wave device, characterized in that: The following steps are involved: S1. Pre-processing the piezoelectric wafer by photolithographically defining the positions of the electrode lead-out holes on the piezoelectric wafer; S2. preparing the via holes on the piezoelectric wafer, and performing electroplating filling in the via holes after sputtering a seed layer in the via holes; S3. Polishing the surface of the piezoelectric wafer and smoothing the surface; S4. Overlaying a pattern on the piezoelectric wafer so that the pattern coincides with the via hole, the pattern including an electrode structure and an IDT structure; S5. Depositing an insulating layer on the surface of the piezoelectric wafer; S6. The piezoelectric wafer and the substrate wafer are surface pretreated to increase their activity and then bonded by direct wafer bonding at room temperature; S7 thinning the piezoelectric layer structure of the substrate wafer, and polishing and smoothing the surface; S8. Prepare an under-bump metallization layer at the electrode structure, and prepare solder joints on the surface of the wafer with the under-bump metallization layer.

2. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 1, wherein: Step S5 also includes preparing a functional layer, depositing the functional layer on the surface of the insulating layer, and performing polishing and surface smoothing.

3. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 2, wherein: The insulating layer is a SiO2 insulating layer, and the functional layer is a SiO2 functional layer.

4. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 2, wherein: In step S5, the thickness of the insulating layer and the functional layer after surface smoothing is within 5 nm of the design indicator, and the uniformity within the chip is required to be within ±2 nm.

5. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 1, wherein: In step S1 , the position of the via hole is determined by a photolithography process, and the piezoelectric wafer is made of one of LN and LT materials with different cut types.

6. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 1, wherein: In step S2 , when the via hole is formed, the depth of the via hole is 20 nm to 50 nm greater than the design requirement.

7. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 1, wherein: In step S3 and step S7, chemical mechanical polishing is used when polishing the wafer.

8. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 1, wherein: In step S6, the bonded substrate wafer is thinned so that the thickness of the substrate wafer is 20 nm greater than the design requirement.

9. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 1, wherein: In step S8 , the solder joint preparation methods include BGA ball planting, flip chip ball planting and microbump electroplating.

10. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 1, wherein: In step S1, before photolithography is performed on the piezoelectric wafer to define the positions of the electrode lead-out via holes, a photoresist is coated on the surface of the piezoelectric wafer.

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