A method for improving the temperature immunity of digital circuits and an electronic device

Abstract

The present invention discloses a method for improving the temperature immunity of digital circuits and an electronic device. The method includes: selecting standard cells for transient simulation; tracking the device current trajectory and voltage trajectory and selecting voltage sampling points; calculating the effective drive current and the temperature dependence of the device; determining the zero-temperature delay operating point; establishing a zero-temperature delay operating point database for the standard cell library and determining the zero-temperature delay operating point from the device level to the standard cell level; using the statistical average of the zero-temperature coefficient points of the standard cell library as the initial power supply voltage to complete the logic synthesis process; generating the gate-level netlist of the circuit according to the timing analysis result of the logic synthesis; performing physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining the optimal zero-temperature delay operating point for large-scale digital circuits. The present invention can alleviate the thermal effect in digital circuits and reduce the temperature dependence of electrical characteristics, and can be widely applied to the field of integrated circuit technology.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a method for improving the temperature immunity of digital circuits and an electronic device. Background Art

[0002] In recent years, with the progress of manufacturing processes, the miniaturization process of integrated circuits has been further promoted. The size of transistors in circuits has been continuously reduced, and the transistor structure has changed from traditional planar devices to three-dimensional devices, or even gate-all-around structure devices. The integration density has been greatly improved. At the same time, the thermal effects in chips have become more obvious. In addition, temperature changes brought about by the external environment and working conditions are also one of the important factors leading to fluctuations in device and circuit characteristics. From the device perspective, the thermal effect reduces the carrier mobility, resulting in the degradation of device performance. From the circuit perspective, the thermal effect causes the increase of the on-chip temperature, leading to the degradation of the circuit driving ability, the increase of delay, and the sharp increase of leakage current. Therefore, the working temperature of the chip itself and the external temperature changes it withstands pose a serious threat to the performance stability of the entire circuit and the system reliability.

[0003] The thermal effect is one of the key factors leading to circuit aging and further restricting the performance of integrated circuits. Exploring an optimization design method with the thermal effect as a breakthrough is expected to enhance circuit performance and reliability. Therefore, how to make the best use of the advantages brought about by process progress while meeting the expected performance and reliability requirements of circuit design is a key problem that needs to be solved urgently.

[0004] Currently, in the technology of alleviating or avoiding the negative impacts brought about by the thermal effect in chip design, there are the following problems:

[0005] A thermal-related timing guard band is introduced in the design stage, that is, when designing, a delay margin against temperature influence is added on the basis of the delay of the critical path of the circuit to overcome the influence of the thermal effect. However, this design strategy cannot eliminate the negative impacts brought about by the thermal effect at the root, and will inevitably reduce the circuit frequency, resulting in the sacrifice of some performance.

[0006] Designing a dedicated temperature and performance monitoring module or a real-time dynamic voltage adjustment circuit module can adjust the working frequency of the chip according to the real-time monitored temperature change inside the chip to prevent the accelerated aging of the chip caused by the too high chip temperature. This solution is a compensation measure for temperature changes, introducing a large design overhead, including increasing the chip area and power consumption.

[0007] Optimizing the design of heat dissipation at the chip packaging level to improve the heat dissipation environment of the circuit and thus reduce the chip temperature rise. However, this solution essentially cannot change or reduce the temperature dependence of circuit characteristics such as delay. Therefore, the sensitivity of the circuit system to temperature still exists, resulting in differences in the performance of the circuit system at different temperatures.

[0008] Existing technologies for improving the temperature fluctuation resistance of circuits based on the zero temperature coefficient point for analog circuits have a core of biasing the circuit at a fixed static operating point, that is, at a certain gate voltage, the drain current does not change with temperature. However, this technology is not applicable to digital circuits because the gate voltage cannot be maintained constant during the switching operation of digital circuits, and digital circuits mainly concern delay information. Therefore, the current zero temperature coefficient point technology applicable to analog circuits cannot be used to enhance the temperature immunity characteristics of digital circuits. Summary of the Invention

[0009] In view of this, embodiments of the present invention provide a method for improving the temperature immunity of digital circuits and an electronic device to alleviate the thermal effect in digital circuits and reduce the temperature dependence of electrical characteristics.

[0010] One aspect of the embodiments of the present invention provides a method for improving the temperature immunity of digital circuits, including:

[0011] Determining the zero temperature delay operating point from the device level to the standard cell level; and determining the optimal zero temperature delay operating point for large-scale digital circuits;

[0012] Among them, the determination of the zero temperature delay operating point from the device level to the standard cell level includes:

[0013] Selecting a standard cell for transient simulation;

[0014] Tracking the device current trajectory and voltage trajectory, and selecting voltage sampling points;

[0015] Calculating the effective drive current of the device and the temperature dependence of the device;

[0016] Determining the zero temperature delay operating point of each standard cell;

[0017] Establishing a zero temperature delay operating point database for the standard cell library, and determining the zero temperature delay operating point from the device level to the standard cell level;

[0018] The determination of the optimal zero temperature delay operating point for large-scale digital circuits includes:

[0019] Taking the statistical average value of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to complete the process of logic synthesis;

[0020] Generating a gate-level netlist of the circuit according to the timing analysis result of the logic synthesis;

[0021] Performing physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining the optimal zero temperature delay operating point for large-scale digital circuits.

[0022] Optionally, the transient simulation of the selected standard cell includes:

[0023] Obtain the transient voltage and current curves of the standard cell;

[0024] Obtain a first time interval between when the output voltage reaches 50% of the supply voltage at the rising edge and when the input voltage reaches 50% of the supply voltage at the falling edge;

[0025] Obtain a second time interval between when the output voltage reaches 50% of the operating voltage at the falling edge and when the input voltage reaches 50% of the operating voltage at the rising edge;

[0026] Calculate the propagation delay based on the first time interval and the second time interval.

[0027] Optionally, the tracking of the device current trajectory and voltage trajectory and the selection of voltage sampling points include:

[0028] Determine the dominant device affecting the delay of the standard cell from the current transient response;

[0029] Obtain the operating voltage trajectory of the dominant device;

[0030] Select appropriate sampling points on the voltage trajectory according to the operating voltage trajectory of the dominant device.

[0031] Optionally, the calculation of the effective drive current of the device and the temperature dependence of the device includes:

[0032] After obtaining the voltage sampling points, integrate and average the current of the device operating under the voltage combination of VGS and VDS to obtain the effective drive current;

[0033] Perform TCAD device mixed-mode simulation of the device at different temperatures or SPICE circuit simulation at different temperatures to obtain the effective current and effective current curve of the device at different temperatures, and calculate the effective current corresponding to the propagation delay at different temperatures;

[0034] Find the point where the effective current in the effective current curve does not change with temperature as the zero-temperature delay operating point of the standard cell.

[0035] Optionally, the determination of the zero-temperature delay operating point of each standard cell includes:

[0036] Change different combinations of circuit load and signal transition rate, statistically determine the zero-temperature delay operating points determined by the delay of each standard cell, and establish a zero-temperature delay operating point database that can be retrieved through the standard cell type and operating conditions.

[0037] Optionally, taking the statistical average value of the zero temperature coefficient point of the standard cell library as the initial power supply voltage, the process of completing logic synthesis includes:

[0038] Prepare a behavioral description file describing the expected logic function of the circuit;

[0039] According to the behavioral description file and the timing constraint file, use a logic synthesis tool to perform logic synthesis on the netlist to generate a gate-level netlist that meets the requirements of the timing constraint file.

[0040] Optionally, performing physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining the optimal zero temperature delay operating point for large-scale digital circuits, including:

[0041] Use a floorplanning tool to perform floorplanning to partition the gate-level netlist;

[0042] Use an automatic placement and routing tool to electrically connect the partitioned netlist according to the positions and relationships of circuit units or modules. After performing two steps of design rule verification and comparison between the layout and the schematic diagram on the generated layout, enter the parasitic parameter extraction process, obtain the parasitic parameters of the layout, and then perform timing simulation;

[0043] Among them, the tool for the timing simulation is the PrimeTime timing analysis tool.

[0044] Another aspect of the embodiments of the present invention also provides a device for improving the temperature immunity of digital circuits, including a first module and a second module;

[0045] The first module is used to determine the zero temperature delay operating point from the device level to the standard cell level;

[0046] The second module is used to determine the optimal zero temperature delay operating point for large-scale digital circuits;

[0047] Among them, the first module is specifically used for:

[0048] Select standard cells for transient simulation;

[0049] Track the device current trajectory and voltage trajectory, and select voltage sampling points;

[0050] Calculate the effective drive current of the device and the temperature dependence of the device;

[0051] Determine the zero temperature delay operating point of each standard cell;

[0052] Establish a zero temperature delay operating point database for the standard cell library, and determine the zero temperature delay operating point from the device level to the standard cell level;

[0053] The second module is specifically used for:

[0054] Taking the statistical average of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to complete the process of logic synthesis;

[0055] Generating a gate-level netlist of the circuit according to the timing analysis result of the logic synthesis;

[0056] Performing physical design according to the gate-level netlist, transforming the gate-level netlist into a layout, and determining the optimal zero temperature delay operating point for large-scale digital circuits.

[0057] Another aspect of the embodiments of the present invention further provides an electronic device, including a processor and a memory;

[0058] The memory is used to store a program;

[0059] The processor executes the program to implement the method as described above.

[0060] Another aspect of the embodiments of the present invention further provides a computer-readable storage medium, where the storage medium stores a program, and the program is executed by a processor to implement the method as described above.

[0061] The embodiments of the present invention also disclose a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device can read the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to enable the computer device to execute the method as described above.

[0062] The method of the embodiments of the present invention includes: determining the zero temperature delay operating point from the device level to the standard cell level; and determining the optimal zero temperature delay operating point for large-scale digital circuits; wherein, the determination of the zero temperature delay operating point from the device level to the standard cell level includes: selecting standard cells for transient simulation; tracking the device current trajectory and voltage trajectory, and selecting voltage sampling points; calculating the effective drive current of the device and the temperature dependence of the device; determining the zero temperature delay operating point of each standard cell; establishing a zero temperature delay operating point database of the standard cell library to determine the zero temperature delay operating point from the device level to the standard cell level; the determination of the optimal zero temperature delay operating point for large-scale digital circuits includes: taking the statistical average of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to complete the process of logic synthesis; generating a gate-level netlist of the circuit according to the timing analysis result of the logic synthesis; performing physical design according to the gate-level netlist, transforming the gate-level netlist into a layout, and determining the optimal zero temperature delay operating point for large-scale digital circuits. The present invention can alleviate the thermal effect in digital circuits and reduce the temperature dependence of electrical characteristics. Description of the Drawings

[0063] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0064] Figure 1 It is the determination process of the zero-temperature delay operating point of each unit in the standard cell library provided by the embodiments of the present invention;

[0065] Figure 2 It is a schematic diagram of the transient response simulation result of the standard cell;

[0066] Figure 3 It is a schematic diagram of the relationship between the effective current and the power supply voltage of the device at different temperatures;

[0067] Figure 4 It is a schematic diagram of the influence of temperature on the circuit operating frequency. Specific embodiments

[0068] In order to make the purpose, technical solutions and advantages of the present application clearer, the following further details the present application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0069] In view of the problems existing in the prior art, one aspect of the embodiments of the present invention provides a method for improving the temperature immunity of digital circuits, including:

[0070] Determination of the zero-temperature delay operating point from the device level to the standard cell level; and determination of the optimal zero-temperature delay operating point for large-scale digital circuits;

[0071] Among them, the determination of the zero-temperature delay operating point from the device level to the standard cell level includes:

[0072] Select standard cells for transient simulation;

[0073] Track the device current trajectory and voltage trajectory, and select voltage sampling points;

[0074] Calculate the effective drive current of the device and the temperature dependence of the device;

[0075] Determine the zero-temperature delay operating point of each standard cell;

[0076] Establish a zero-temperature delay operating point database for the standard cell library, and determine the zero-temperature delay operating point from the device level to the standard cell level;

[0077] The determination of the optimal zero-temperature delay operating point for large-scale digital circuits includes:

[0078] Taking the statistical average of the zero-temperature coefficient points of the standard cell library as the initial supply voltage to complete the process of logic synthesis;

[0079] Generating a gate-level netlist of the circuit according to the timing analysis result of the logic synthesis;

[0080] Performing physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining the optimal zero-temperature delay operating point for large-scale digital circuits.

[0081] Optionally, the selection of standard cells for transient simulation includes:

[0082] Obtaining the transient voltage and current curves of the standard cells;

[0083] Obtaining a first time interval between when the output voltage reaches 50% of the supply voltage at the rising edge and when the input voltage reaches 50% of the supply voltage at the falling edge;

[0084] Obtaining a second time interval between when the output voltage reaches 50% of the operating voltage at the falling edge and when the input voltage reaches 50% of the operating voltage at the rising edge;

[0085] Calculating the propagation delay according to the first time interval and the second time interval.

[0086] Optionally, the tracking of the device current trajectory and voltage trajectory and the selection of voltage sampling points include:

[0087] Determining the dominant device affecting the delay of the standard cell from the current transient response;

[0088] Obtaining the operating voltage trajectory of the dominant device;

[0089] Selecting appropriate sampling points on the voltage trajectory according to the operating voltage trajectory of the dominant device.

[0090] Optionally, the calculation of the effective drive current of the device and the temperature dependence of the device includes:

[0091] After obtaining the voltage sampling points, integrating and averaging the current of the device operating under the voltage combination of VGS and VDS to obtain the effective drive current;

[0092] Performing TCAD device mixed-mode simulation of the device at different temperatures or SPICE circuit simulation at different temperatures to obtain the effective current and effective current curve of the device at different temperatures, and calculating the effective current corresponding to the propagation delay at different temperatures;

[0093] Find the point where the effective current in the effective current curve does not change with temperature, and use it as the zero-temperature delay operating point of the standard cell.

[0094] Optionally, determining the zero-temperature delay operating point of each standard cell includes:

[0095] Vary different combinations of circuit loads and signal transition rates, statistically determine the zero-temperature delay operating points determined by the delays of each standard cell, and establish a zero-temperature delay operating point database that can be retrieved by standard cell type and operating conditions.

[0096] Optionally, using the statistical average value of the zero-temperature coefficient points of the standard cell library as the initial power supply voltage to complete the process of logic synthesis includes:

[0097] Prepare a behavioral description file describing the expected logical function of the circuit;

[0098] According to the behavioral description file and the timing constraint file, use a logic synthesis tool to perform logic synthesis on the netlist to generate a gate-level netlist that meets the requirements of the timing constraint file.

[0099] Optionally, performing physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining the optimal zero-temperature delay operating point for large-scale digital circuits includes:

[0100] Use a floorplanning tool for floorplanning to partition the gate-level netlist;

[0101] Use an automatic placement and routing tool to electrically connect the partitioned netlist according to the positions and relationships of circuit units or modules. After performing two steps of design rule verification and comparison between the layout and the schematic diagram on the generated layout, enter the parasitic parameter extraction process, obtain the parasitic parameters of the layout, and then perform timing simulation;

[0102] Among them, the tool for the timing simulation is the PrimeTime timing analysis tool.

[0103] Another aspect of the embodiments of the present invention also provides a device for improving the temperature immunity of a digital circuit, including a first module and a second module;

[0104] The first module is used for determining the zero-temperature delay operating point from the device level to the standard cell level;

[0105] The second module is used for determining the optimal zero-temperature delay operating point for large-scale digital circuits;

[0106] Among them, the first module is specifically used for:

[0107] Select a standard cell for transient simulation;

[0108] Track the current and voltage trajectories of the device and select voltage sampling points;

[0109] Calculate the effective drive current of the device and its temperature dependence;

[0110] Determine the zero-temperature delay operating points of each standard cell;

[0111] Establish a database of zero-temperature delay operating points for the standard cell library and determine the zero-temperature delay operating points from the device level to the standard cell level;

[0112] The second module is specifically used for:

[0113] Use the statistical average of the zero-temperature coefficient points of the standard cell library as the initial power supply voltage to complete the process of logic synthesis;

[0114] Generate a gate-level netlist of the circuit according to the timing analysis result of the logic synthesis;

[0115] Perform physical design according to the gate-level netlist, convert the gate-level netlist into a layout, and determine the optimal zero-temperature delay operating point for large-scale digital circuits.

[0116] Another aspect of the embodiments of the present invention also provides an electronic device, including a processor and a memory;

[0117] The memory is used to store programs;

[0118] The processor executes the program to implement the method as described above.

[0119] Another aspect of the embodiments of the present invention also provides a computer-readable storage medium, where the storage medium stores a program, and the program is executed by a processor to implement the method as described above.

[0120] The embodiments of the present invention also disclose a computer program product or a computer program, which includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device can read the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method as described above.

[0121] The following will describe the specific implementation process of the present invention in detail with reference to the accompanying drawings of the specification:

[0122] Thermal effects are one of the key factors leading to circuit aging and further restricting the performance of integrated circuits. Exploring optimization design methods with thermal effects as a breakthrough is expected to enhance circuit performance and reliability. Therefore, how to make the best use of the advantages brought by technological progress while meeting the expected performance and reliability requirements of circuit design is a key issue that urgently needs to be solved. The core of solving this problem lies in reducing the negative impact of thermal effects from the physical root. The starting point of this invention is to alleviate the thermal effects in digital circuits and reduce the temperature dependence of electrical characteristics. The specific idea is as follows: Starting from the physical essence affecting thermal effects and combining the available factors in design, effectively alleviate the performance degradation caused by the enhanced thermal effects at as low an implementation cost as possible. Based on the zero-temperature coefficient point of the device and considering that digital circuits mainly focus on delay information, this invention introduces a design strategy of zero-temperature delay (the influence of circuit delay on temperature change is close to zero), provides a method for quickly determining the zero-temperature delay operating point of standard cells at the device level, and formulates a corresponding implementation process for determining the optimal zero-temperature delay operating point at the large-scale digital circuit level. By providing an accurate zero-temperature delay operating point range and corresponding design schemes for chip design, the temperature immunity of digital circuits is enhanced.

[0123] This invention proposes a method, system, device, and medium that can be used to improve the temperature immunity of digital circuits, aiming to enhance the temperature immunity of digital circuit delay based on the proposed zero-temperature delay operating point design strategy, further alleviate the thermal effects under advanced processes, and improve the reliability of digital circuits and systems on the premise of balancing performance and power consumption, especially serving the digital circuit design based on standard cells under advanced processes.

[0124] The operation steps of this invention consist of two parts, and the core content and purpose of each part are summarized as follows:

[0125] The first part is the determination of the zero-temperature delay operating point from the device level to the standard cell level, and the output information is the distribution range of the zero-temperature delay operating points of each standard cell in the standard cell library, as Figure 1 shown; The second part is to use the zero-temperature delay operating point database at the standard cell level to determine the optimal zero-temperature delay operating point of the large-scale digital circuit, and the output information is the critical path of the circuit and its optimal zero-temperature delay operating point.

[0126] It should be noted that the present invention involves two levels of zero-temperature delay operating points, namely the zero-temperature delay operating point of the standard cell and the zero-temperature delay operating point of the digital circuit. The two are different but closely related. Among them, the power supply voltage when the delay of the standard cell is least affected by temperature change is defined as the zero-temperature delay operating point of the standard cell. Generally, since the digital circuit design is composed of a large number of standard cells combined according to their logic functions, and the zero-temperature delay operating points of different standard cells are different due to the differences in their circuit structures and operating waveforms, the zero-temperature delay operating point of the digital circuit refers to the power supply voltage when the temperature dependence of the delay of the critical path of the digital circuit is the smallest, and the zero-temperature delay operating point of the digital circuit is determined by the standard cells on its critical path. The zero-temperature coefficient point mentioned in the invention is for the device, and it represents the operating voltage value corresponding to the device when the effective drain current of the device changes least with temperature.

[0127] The first part is the determination of the zero-temperature delay operating point from the device level to the standard cell level. The specific operation steps are as follows:

[0128] Step 1: Standard cell transient simulation. First, select a standard cell for transient response simulation. Refer to Figure 2 , taking the inverter as an example, available tools include TCAD (Technology Computer Aided Design) and SPICE (Simulation Program with Integrated Circuit Emphasis), and the transient voltage and current curves of the standard cell can be obtained. In the transient response, the definition of delay is that the time interval between the output voltage (V OUT ) reaching 50% of the power supply voltage at the rising edge and the input voltage (V IN ) reaching 50% of the power supply voltage at the falling edge is defined as t pLH , and the time interval between the output voltage reaching 50% of the operating voltage at the falling edge and the input voltage reaching 50% of the operating voltage at the rising edge is defined as t pHL . The average value of t pLH and t pLH is defined as the propagation delay t p . Figure 2 In (a) is the transient response waveform of the input and output voltages of the inverter standard cell, (b) is the transient current response of the NFET and PFET in the inverter, and (c) is the schematic diagram of the voltage waveform experienced by the NFET in the inverter;

[0129] The calculation of each delay at different temperatures is shown in the following formula:

[0130]

[0131]

[0132]

[0133] Among them, t pHL (T), t pLH (T), t p (T) represents the delay of the standard cell circuit at different temperatures, C L is the load capacitance of the standard cell, V DD is the power supply voltage of the standard cell, V GS is the voltage between the gate node and the source node of the transistor in the standard cell, V DS is the voltage between the drain node and the source node of the transistor in the standard cell, I DS is the current between the drain node and the source node of the transistor in the standard cell, I DS is related to V GS , V DS and temperature, I DS is the sum of I DS of all transistors in the standard cell.

[0134] Step 2: Device current, voltage trajectory tracking and voltage sampling point selection. This step includes: determining the dominant device affecting the delay of the standard cell from the current transient response, obtaining the operating voltage trajectory of the device, and then selecting appropriate sampling points on the voltage trajectory. As can be seen from formulas (1) and (2), the delay of the standard cell at different temperatures is determined by the effective drive current of the device within the corresponding delay interval, as shown in Figure 2 (b). Through the simulation results of Step 1, the time interval of each delay can be obtained according to the input and output voltage response waveforms of the standard cell, and the delay parameters t pHL , t pLH can be determined by which device(s) (N-type field effect transistor NFET / P-type field effect transistor PFET) play a dominant role. Secondly, in order to conveniently and quickly determine the effective current of the device when it operates in the standard cell at the device level, the values of the inter-node voltages V GS and V DS are extracted from the obtained delay time interval to form the operating voltage trajectory of the device, as shown in Figure 2 (c). As can be seen from Figure 2 (c), as the power supply voltage decreases, the shape of the voltage trajectory also shrinks approximately proportionally. Therefore, the selection of sampling points in the voltage trajectory is referenced by the power supply voltage, and the recommended selection principle is that the horizontal and vertical distances between adjacent two voltage sampling points should both be in the range of 0.1 - 0.25V DD . This selection principle can achieve a good balance between the computational complexity and accuracy. Taking the inverter as an example, according to this principle, it is recommended to select a total of three voltage sampling points, which are (V GS= ±0.5V DD , V DS = ±V DD ), (V GS = ±V DD , V DS = ±0.5V DD ), and (V GS = ±0.75V DD , V DS = ±0.75V DD ), where taking “+” represents the voltage sampling point for calculating the delay time t pHL , and taking “-” represents the voltage sampling point for calculating the delay time t pLH . The specific number of sampling points in the voltage trajectory depends on the voltage waveform experienced by the devices in the standard cell and the voltage sampling point selection principle.

[0135] Step 3: Calculation of the effective drive current of the devices affecting the delay of the standard cell. After obtaining the voltage sampling points in Step 2, the current of the device operating under the voltage combinations of V GS and V DS can be integrated and averaged, as shown in Formulas (1) and (2), and the obtained value is the effective drive current I eff . Then, perform TCAD device mixed-mode simulation of the device at different temperatures or SPICE circuit simulation at different temperatures, and further obtain the I effLH (T) and I effHL (T) curves of the device at different temperatures, as shown in Figure 3 , where (a) is I effLH (b) I effHL (c) I eff , where the V ZTC values from left to right in the figure respectively correspond to the zero-temperature delay operating points of t pHL , t pLH and t p , as shown in Figure 3 (a) and 3(b). Then, calculate the effective current I p corresponding to t eff (T) at different temperatures through Formula (4), as shown in the following formula:

[0136]

[0137] where, I effHL (T) is the effective current corresponding to t pHL at different temperatures, and I effLH (T) is the effective current corresponding to t pLH at different temperatures. Plot the effective current I p corresponding to t eff(T) Variation curves with respect to operating voltage and temperature, as shown in Figure 3 (c). Locate the point on the curve where the effective current does not change with temperature. The voltage value corresponding to this point is the zero-temperature delay operating point of the standard cell. In this way, the problem of the standard cell delay being immune to temperature is transformed into the problem of the effective current of the device being immune to temperature. The zero-temperature coefficient point of the effective current of the device in the figure can be regarded as the zero-temperature delay operating point of the standard cell. Specifically, take the average propagation delay t p That is, dI eff (T) / dT = 0 and use the corresponding zero-temperature delay operating point as the zero-temperature delay operating point of the standard cell.

[0138] Step 4: Statistics of the zero-temperature delay operating points of the standard cell library. First, considering that there are multiple types of standard cells used in circuit design; second, since different operating conditions such as circuit load and the slope of the input signal have a certain impact on the zero-temperature delay operating point. Therefore, repeat Steps 1 to 3 for other standard cells in the standard cell library, while changing different combinations of circuit load and signal transition rate. The typical value settings can refer to Table 1, and automatically statistically calculate the zero-temperature delay operating points determined by the delay t p That is, I eff of each standard cell in the form of a script, so as to establish a zero-temperature delay operating point database that can be retrieved by standard cell type and operating conditions, which is convenient for the use of the second part later.

[0139] Table 1 Typical value ranges for the load capacitance and input slope parameter settings of standard cells. For example, C L = 10 fF, T SL = 10 ns

[0140]

[0141] The second part is to determine the optimal zero-temperature delay operating points for large-scale digital circuits. The specific operation steps are as follows:

[0142] Step 1: Use the statistical average of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to complete the logic synthesis process. The files required for this step include behavioral description files such as Verilog or Verilog HDL files that describe the expected logic function of the circuit, in the format of.v files. Then, perform logic synthesis on the netlist. This process uses logic synthesis tools such as Design Compiler and Encounter RTL Compiler. The specific operation is to import the netlist into the logic synthesis tool, input the timing constraint file in the.sdc format, and set the initial power supply voltage value to the statistical average of the zero temperature delay operating points of all standard cells obtained in the first part. The synthesis tool performs logic synthesis on the netlist according to the timing constraint file and power supply voltage settings, that is, optimizes the area and power consumption of the circuit. The gate-level netlist generated after logic synthesis is the gate-level netlist that meets the requirements of the timing constraint file, which contains various standard cells that meet the process conditions.

[0143] Step 2: According to the timing analysis results after logic synthesis in Step 1, use the logic synthesis tool to screen out the critical path, output all the standard cells on this path, count the types of standard cells that appear on this path, and based on the zero temperature delay operating point data of each standard cell obtained in the first part, perform a weighted average according to the proportion of each standard cell that appears to obtain the zero temperature delay operating point under this critical path. Compare it with the initial power supply voltage value. If the zero temperature delay operating point under this critical path is different from the initial power supply voltage value in Step 1, then use this as the new power supply voltage value of the circuit, and re-execute the logic synthesis in Step 1 and the extraction and comparison operations of the zero temperature delay operating point of the critical path in Step 2, and iterate until the power supply voltage value is consistent with the zero temperature delay operating point under the critical path or the difference is less than 0.01V.

[0144] Step 3: Perform subsequent physical design on the gate-level netlist generated in Step 2. Physical design is the process of converting the circuit gate-level netlist into a layout. The specific process includes: First, perform floorplanning, using a floorplanning tool such as ICCompiler to partition the gate-level netlist; then perform placement and routing. In this step, use an automatic placement and routing tool to electrically connect the partitioned netlist according to the positions and relationships of circuit units or modules. After performing two steps of design rule verification and comparison between the layout and the schematic diagram on the generated layout, enter the parasitic parameter extraction process, obtain the parasitic parameters of the layout and then perform timing simulation. The difference from the timing simulation in Steps 1 and 2 is that the timing simulation at this time is a timing simulation that has considered the layout parasitic information. The tools that can be used are timing analysis tools such as PrimeTime. After the timing meets the requirements, the timing verification of the digital circuit based on the zero temperature delay operating point is completed. Finally, the physical layout is delivered to the chip foundry in the GDSII format. Figure 4It is shown that the operating frequency of the circuit designed based on the zero-temperature delay operating point is greatly reduced by the influence of temperature, while the thermal effect is alleviated. The temperature is reduced by 1.9 times compared with that at 0.9V. At the same time, the power-delay product reaches the minimum value at the zero-temperature delay operating point, achieving a good trade-off among performance, power consumption, and reliability. From Figure 4 As can be seen from (a) in Figure 4 it, the fluctuation of the circuit frequency based on the zero-temperature delay operating point is greatly reduced by the influence of temperature; as can be seen from (b) in

[0145] it, the self-heating effect mitigation and the trade-off effect between power consumption and performance brought by selecting the zero-temperature delay operating point as the power supply voltage.

[0146] In summary, the present invention can determine the zero-temperature delay operating point for improving the temperature immunity according to the digital circuit design, and use this operating point as the power supply voltage of the circuit, so as to achieve the purpose of alleviating the self-heating effect and reducing the temperature dependence of the circuit delay, suppressing the adverse effects of temperature fluctuations on the circuit performance at the lowest possible design cost, realizing the trade-off among performance, power consumption, and reliability, and being beneficial to the development of digital circuits in the fields of low-power and high-reliability design requirements.

[0147] 1. Design strategy based on the zero-temperature delay operating point: Utilize the competitive relationship between the temperature dependencies of mobility and threshold voltage, which results in the temperature dependence of circuit delay approaching zero at a certain power supply voltage. In the digital circuit design, use this zero-temperature delay operating point as the power supply voltage to reduce the influence of performance degradation caused by the thermal effect as much as possible from the physical root, and enhance the reliability of digital circuits under advanced processes.

[0148] 2. Determination method of the zero-temperature delay operating point from the device level to the standard cell level: Trace the key devices contributing to the standard cell delay through the current waveform, sample the voltage waveform during their operation, and integrate and average the current corresponding to the voltage sampling points to obtain the effective drive current. Use the power supply voltage at which the temperature dependence of the device effective drive current is the smallest as the zero-temperature delay operating point of the standard cell.

[0149] 3. Large-scale circuit design method based on the zero-temperature delay operating point: Based on the data of the zero-temperature delay operating points of the standard cell library, determine the standard cells affecting the digital circuit delay according to the critical paths determined by the timing analysis, and determine the optimal zero-temperature delay point by the statistical method of weighted average. Based on this principle, the trade-off among performance, power consumption, and reliability of digital circuits is realized.

[0150] Compared with the prior art, the present invention has the following advantages:

[0151] 1. By using the zero-temperature-delay operating point as the operating voltage, the dependence of the key delay metric of digital circuits on temperature is fundamentally reduced, thereby avoiding the introduction of a thermal-related timing guard band during design. As a result, the performance loss caused by the thermal timing guard band can be reduced.

[0152] 2. There is no need to introduce additional design overheads, such as increasing the chip area. Since the zero-temperature-delay operating point only makes corresponding adjustments to the power supply voltage, it is simple to implement. While reducing power consumption and alleviating the thermal effect, it improves the reliability of the chip, achieving a better trade-off among power consumption, performance, and reliability, and is particularly suitable for application scenarios with low power consumption and high reliability requirements.

[0153] 3. Different from the application of the zero-temperature coefficient point in analog circuits, the zero-temperature-delay operating point design strategy proposed in the present invention is a customized solution for digital circuit design, providing an efficient and fast determination method from devices to standard cells and to large-scale circuits, facilitating users to determine the operating point that provides circuit temperature immunity according to their own circuit designs.

[0154] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order mentioned in the operating diagrams. For example, depending on the functions / operations involved, two consecutive blocks shown may actually be executed substantially simultaneously or the blocks can sometimes be executed in the reverse order. In addition, the embodiments presented and described in the flowcharts of the present invention are provided by way of example for a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logical flows presented herein. Alternative embodiments are contemplated, where the order of various operations is changed and where sub-operations described as part of a larger operation are executed independently.

[0155] Furthermore, although the present invention has been described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the functions and / or features described may be integrated in a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present invention. Rather, considering the attributes, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the modules will be understood within the ordinary skills of an engineer. Therefore, those skilled in the art can implement the present invention as set forth in the claims without undue experimentation. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0156] When the above-mentioned functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs.

[0157] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definite sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch instructions from the instruction execution system, apparatus, or device and execute the instructions), or in combination with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

[0158] More specific examples (non-exhaustive list) of computer-readable media include the following: electrical connection parts with one or more wirings (electronic devices), portable computer disk cartridges (magnetic devices), random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memories), optical fiber devices, and portable compact disc read-only memories (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, then editing, interpreting, or otherwise processing it as appropriate, and then storing it in a computer memory.

[0159] It should be understood that each part of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), and the like.

[0160] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0161] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the claims and their equivalents.

[0162] The above has specifically described the preferred embodiments of the present invention, but the present invention is not limited to the described embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A method for improving the temperature immunity of digital circuits, characterized in that, it includes: Determination of the zero-temperature delay operating point from the device level to the standard cell level; And determination of the optimal zero-temperature delay operating point for large-scale digital circuits; Among them, the determination of the zero-temperature delay operating point from the device level to the standard cell level includes: Select standard cells for transient simulation; Track the device current trajectory and voltage trajectory, and select voltage sampling points; Calculate the effective drive current of the device and the temperature dependence of the device; Determine the zero-temperature delay operating point of each standard cell; Establish a zero-temperature delay operating point database for the standard cell library, and determine the zero-temperature delay operating point from the device level to the standard cell level; The determination of the optimal zero-temperature delay operating point for large-scale digital circuits includes: Taking the statistical average value of the zero-temperature coefficient points of the standard cell library as the initial power supply voltage to complete the process of logic synthesis; Generate the gate-level netlist of the circuit according to the timing analysis result of the logic synthesis; Conduct physical design according to the gate-level netlist, transform the gate-level netlist into a layout, and determine the optimal zero-temperature delay operating point for large-scale digital circuits; The selection of standard cells for transient simulation includes: Obtain the transient voltage and current curves of the standard cells; Obtain the first time interval between when the output voltage reaches 50% of the power supply voltage at the rising edge and when the input voltage reaches 50% of the power supply voltage at the falling edge; Obtain the second time interval between when the output voltage reaches 50% of the operating voltage at the falling edge and when the input voltage reaches 50% of the operating voltage at the rising edge; Calculate the propagation delay according to the first time interval and the second time interval; The calculation of the effective drive current of the device and the temperature dependence of the device includes: After obtaining the voltage sampling points, integrate and average the current of the device under the voltage combination of VGS and VDS to obtain the effective drive current; Perform TCAD device mixed-mode simulation on the device at different temperatures or SPICE circuit simulation at different temperatures to obtain the effective current and effective current curve of the device at different temperatures, and calculate the effective current corresponding to the propagation delay at different temperatures; Find the point where the effective current in the effective current curve does not change with temperature as the zero-temperature delay operating point of the standard cell.

2. The method for improving the temperature immunity of digital circuits according to claim 1, characterized in that, The tracking of the device current trajectory and voltage trajectory and the selection of voltage sampling points include: Determine the dominant device affecting the delay of the standard cell from the current transient response; Obtain the operating voltage trajectory of the dominant device; Select appropriate sampling points on the voltage trajectory according to the operating voltage trajectory of the dominant device.

3. The method for improving the temperature immunity of digital circuits according to claim 1, characterized in that, The determination of the zero-temperature delay operating point of each standard cell includes: Change different combinations of circuit load and signal transition rate, statistically determine the zero-temperature delay operating point determined by the delay of each standard cell, and establish a zero-temperature delay operating point database that can be retrieved by standard cell type and working conditions.

4. A method for improving the temperature immunity of a digital circuit according to claim 1, characterized in that, using the statistical average of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to complete the process of logic synthesis, including: Preparing a behavioral description file describing the expected logic function of the circuit; According to the behavioral description file and the timing constraint file, using a logic synthesis tool to perform logic synthesis on the netlist to generate a gate-level netlist that meets the requirements of the timing constraint file.

5. A method for improving the temperature immunity of a digital circuit according to claim 1, characterized in that, performing physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining the optimal zero temperature delay operating point for large-scale digital circuits, including: Using a floorplanning tool for floorplanning to partition the gate-level netlist; Using an automatic placement and routing tool to electrically connect the partitioned netlist according to the positions and relationships of circuit units or modules. After performing two steps of design rule verification and comparison between the layout and the schematic diagram on the generated layout, entering the parasitic parameter extraction process, obtaining the parasitic parameters of the layout and then performing timing simulation; Among them, the tool for the timing simulation is the PrimeTime timing analysis tool.

6. An apparatus for implementing the method for improving the temperature immunity of a digital circuit as described in any one of claims 1-5, characterized in that, including a first module and a second module; The first module is used for determining the zero temperature delay operating point from the device level to the standard cell level; The second module is used for determining the optimal zero temperature delay operating point for large-scale digital circuits; Among them, the first module is specifically used for: Selecting standard cells for transient simulation; Tracking the device current trajectory and voltage trajectory, and selecting voltage sampling points; Calculating the effective drive current of the device and the temperature dependence of the device; Determining the zero temperature delay operating point of each standard cell; Establishing a zero temperature delay operating point database of the standard cell library to determine the zero temperature delay operating point from the device level to the standard cell level; The second module is specifically used for: Using the statistical average of the zero temperature coefficient points of the standard cell library as the initial power supply voltage to complete the process of logic synthesis; Generating a gate-level netlist of the circuit according to the timing analysis result of the logic synthesis; Performing physical design according to the gate-level netlist, converting the gate-level netlist into a layout, and determining the optimal zero temperature delay operating point for large-scale digital circuits.

7. An electronic device, characterized in that, including a processor and a memory; The memory is used for storing programs; The processor executes the program to implement the method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, the storage medium stores a program, and the program is executed by a processor to implement the method as described in any one of claims 1 to 5.

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